| /* |
| * Copyright (C) 2013 Freescale Semiconductor, Inc. |
| * |
| * Author: Fabio Estevam <fabio.estevam@freescale.com> |
| * |
| * SPDX-License-Identifier: GPL-2.0+ |
| */ |
| |
| #include <asm/arch/clock.h> |
| #include <asm/arch/imx-regs.h> |
| #include <asm/arch/iomux.h> |
| #include <asm/arch/mx6-pins.h> |
| #include <asm/errno.h> |
| #include <asm/gpio.h> |
| #include <asm/imx-common/iomux-v3.h> |
| #include <mmc.h> |
| #include <fsl_esdhc.h> |
| #include <asm/arch/crm_regs.h> |
| #include <asm/io.h> |
| #include <asm/arch/sys_proto.h> |
| |
| DECLARE_GLOBAL_DATA_PTR; |
| |
| #define UART_PAD_CTRL (PAD_CTL_PUS_100K_UP | \ |
| PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | \ |
| PAD_CTL_SRE_FAST | PAD_CTL_HYS) |
| |
| #define USDHC_PAD_CTRL (PAD_CTL_PUS_47K_UP | \ |
| PAD_CTL_SPEED_LOW | PAD_CTL_DSE_80ohm | \ |
| PAD_CTL_SRE_FAST | PAD_CTL_HYS) |
| |
| #define WDT_EN IMX_GPIO_NR(5, 4) |
| #define WDT_TRG IMX_GPIO_NR(3, 19) |
| |
| int dram_init(void) |
| { |
| gd->ram_size = (phys_size_t)CONFIG_DDR_MB * 1024 * 1024; |
| |
| return 0; |
| } |
| |
| static iomux_v3_cfg_t const uart2_pads[] = { |
| MX6_PAD_EIM_D26__UART2_TXD | MUX_PAD_CTRL(UART_PAD_CTRL), |
| MX6_PAD_EIM_D27__UART2_RXD | MUX_PAD_CTRL(UART_PAD_CTRL), |
| }; |
| |
| static iomux_v3_cfg_t const usdhc3_pads[] = { |
| MX6_PAD_SD3_CLK__USDHC3_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL), |
| MX6_PAD_SD3_CMD__USDHC3_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL), |
| MX6_PAD_SD3_DAT0__USDHC3_DAT0 | MUX_PAD_CTRL(USDHC_PAD_CTRL), |
| MX6_PAD_SD3_DAT1__USDHC3_DAT1 | MUX_PAD_CTRL(USDHC_PAD_CTRL), |
| MX6_PAD_SD3_DAT2__USDHC3_DAT2 | MUX_PAD_CTRL(USDHC_PAD_CTRL), |
| MX6_PAD_SD3_DAT3__USDHC3_DAT3 | MUX_PAD_CTRL(USDHC_PAD_CTRL), |
| }; |
| |
| static iomux_v3_cfg_t const wdog_pads[] = { |
| MX6_PAD_EIM_A24__GPIO_5_4 | MUX_PAD_CTRL(NO_PAD_CTRL), |
| MX6_PAD_EIM_D19__GPIO_3_19, |
| }; |
| |
| static void setup_iomux_uart(void) |
| { |
| imx_iomux_v3_setup_multiple_pads(uart2_pads, ARRAY_SIZE(uart2_pads)); |
| } |
| |
| static void setup_iomux_wdog(void) |
| { |
| imx_iomux_v3_setup_multiple_pads(wdog_pads, ARRAY_SIZE(wdog_pads)); |
| gpio_direction_output(WDT_TRG, 0); |
| gpio_direction_output(WDT_EN, 1); |
| } |
| |
| static struct fsl_esdhc_cfg usdhc_cfg = { USDHC3_BASE_ADDR }; |
| |
| int board_mmc_getcd(struct mmc *mmc) |
| { |
| return 1; /* Always present */ |
| } |
| |
| int board_mmc_init(bd_t *bis) |
| { |
| imx_iomux_v3_setup_multiple_pads(usdhc3_pads, ARRAY_SIZE(usdhc3_pads)); |
| usdhc_cfg.sdhc_clk = mxc_get_clock(MXC_ESDHC3_CLK); |
| usdhc_cfg.max_bus_width = 4; |
| |
| return fsl_esdhc_initialize(bis, &usdhc_cfg); |
| } |
| |
| int board_early_init_f(void) |
| { |
| setup_iomux_wdog(); |
| setup_iomux_uart(); |
| |
| return 0; |
| } |
| |
| int board_init(void) |
| { |
| /* address of boot parameters */ |
| gd->bd->bi_boot_params = PHYS_SDRAM + 0x100; |
| |
| return 0; |
| } |
| |
| int checkboard(void) |
| { |
| puts("Board: Udoo\n"); |
| |
| return 0; |
| } |