Merge branch 'hs@denx.de' of git://git.denx.de/u-boot-staging
* 'hs@denx.de' of git://git.denx.de/u-boot-staging:
drivers/net/dnet.c: Fix GCC 4.6 warnings
board/xaeniax/flash.c: Fix GCC 4.6 warnings
net/bootp.c: Fix GCC 4.6 warning
common/cmd_bootm.c: Fix GCC 4.6 warnings
board/mx1ads/mx1ads.c: Fix GCC 4.6 warning
board/mx1ads/syncflash.c: Fix GCC 4.6 warnings
board/lubbock/flash.c: Fix GCC 4.6 warnings
drivers/net/cs8900.c: Fix GCC 4.6 warning
arch/arm/cpu/arm926ejs/omap/cpuinfo.c: Fix GCC 4.6 warnings
drivers/net/lan91c96.c: Fix GCC 4.6 warning
board/ronetix/pm9263/pm9263.c: Fix GCC 4.6 warning
drivers/mtd/onenand/samsung.c: Fix GCC 4.6 warning
drivers/usb/musb/musb_hcd.c: Fix GCC 4.6 warning
diff --git a/.checkpatch.conf b/.checkpatch.conf
new file mode 100644
index 0000000..977db9e
--- /dev/null
+++ b/.checkpatch.conf
@@ -0,0 +1,14 @@
+# Not Linux, so don't expect a Linux tree.
+--no-tree
+
+# Temporary for false positive in checkpatch
+--ignore COMPLEX_MACRO
+
+# For CONFIG_SYS_I2C_NOPROBES
+--ignore MULTISTATEMENT_MACRO_USE_DO_WHILE
+
+# For simple_strtoul
+--ignore CONSIDER_KSTRTO
+
+# For min/max
+--ignore MINMAX
diff --git a/.gitignore b/.gitignore
index 70a11f7..ff4bae0 100644
--- a/.gitignore
+++ b/.gitignore
@@ -36,6 +36,7 @@
/u-boot.lds
/u-boot.ubl
/u-boot.dtb
+/u-boot.sb
#
# Generated files
diff --git a/MAINTAINERS b/MAINTAINERS
index 030fe4a..f6f6b72 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -305,10 +305,6 @@
snapper9260 ARM926EJS (AT91SAM9260 SoC)
snapper9g20 ARM926EJS (AT91SAM9G20 SoC)
-Eran Man <eran@nbase.co.il>
-
- EVB64260_750CX MPC750CX
-
Andrea "llandre" Marson <andrea.marson@dave-tech.it>
PPChameleonEVB PPC405EP
@@ -543,10 +539,10 @@
rsdproto MPC8260
EVB64260 MPC7xx_74xx
+ EVB64260_750CX MPC750CX [Eran Man <eran@nbase.co.il>]
versatile ARM926EJ-S
-
#########################################################################
# ARM Systems: #
# #
@@ -775,10 +771,6 @@
omap730p2 ARM926EJS
-Manikandan Pillai <mani.pillai@ti.com>
-
- omap3_evm ARM ARMV7 (OMAP3xx SoC)
-
Stelian Pop <stelian.pop@leadtechdesign.com>
at91sam9260ek ARM926EJS (AT91SAM9260 SoC)
@@ -786,6 +778,10 @@
at91sam9263ek ARM926EJS (AT91SAM9263 SoC)
at91sam9rlek ARM926EJS (AT91SAM9RL SoC)
+Tom Rini <trini@ti.com>
+
+ omap3_evm ARM ARMV7 (OMAP3xx SoC)
+
Tom Rix <Tom.Rix@windriver.com>
omap3_zoom2 ARM ARMV7 (OMAP3xx SoC)
@@ -817,11 +813,6 @@
magnesium i.MX27
mgcoge3un ARM926EJS (Kirkwood SoC)
-Robert Schwebel <r.schwebel@pengutronix.de>
-
- csb226 xscale/pxa
- innokom xscale/pxa
-
Michael Schwingen <michael@schwingen.org>
actux1 xscale/ixp
@@ -850,6 +841,7 @@
omap4_panda ARM ARMV7 (OMAP4xx SoC)
omap4_sdp4430 ARM ARMV7 (OMAP4xx SoC)
+ omap5_evm ARM ARMV7 (OMAP5xx Soc)
Marek Vasut <marek.vasut@gmail.com>
@@ -859,6 +851,7 @@
palmtc xscale/pxa
vpac270 xscale/pxa
zipitz2 xscale/pxa
+ m28evk i.MX28
efikamx i.MX51
efikasb i.MX51
@@ -1151,6 +1144,7 @@
Macpaul Lin <macpaul@andestech.com>
ADP-AG101 N1213 (AG101 SoC)
+ ADP-AG101P N1213 (AG101P XC5 FPGA)
#########################################################################
# End of MAINTAINERS list #
diff --git a/Makefile b/Makefile
index 294c762..d84b350 100644
--- a/Makefile
+++ b/Makefile
@@ -290,16 +290,9 @@
LIBS += api/libapi.o
LIBS += post/libpost.o
-ifeq ($(SOC),am33xx)
+ifneq ($(CONFIG_AM335X)$(CONFIG_OMAP34XX)$(CONFIG_OMAP44XX)$(CONFIG_OMAP54XX),)
LIBS += $(CPUDIR)/omap-common/libomap-common.o
endif
-ifeq ($(SOC),omap3)
-LIBS += $(CPUDIR)/omap-common/libomap-common.o
-endif
-ifeq ($(SOC),omap4)
-LIBS += $(CPUDIR)/omap-common/libomap-common.o
-endif
-
ifeq ($(SOC),s5pc1xx)
LIBS += $(CPUDIR)/s5p-common/libs5p-common.o
endif
@@ -424,6 +417,10 @@
rm $(obj)u-boot-ubl.bin
rm $(obj)spl/u-boot-spl-pad.bin
+$(obj)u-boot.sb: $(obj)u-boot.bin $(obj)spl/u-boot-spl.bin
+ elftosb -zdf imx28 -c $(TOPDIR)/board/$(BOARDDIR)/u-boot.bd \
+ -o $(obj)u-boot.sb
+
ifeq ($(CONFIG_SANDBOX),y)
GEN_UBOOT = \
cd $(LNDIR) && $(CC) $(SYMS) -T $(obj)u-boot.lds \
@@ -486,7 +483,7 @@
$(obj)mmc_spl/u-boot-mmc-spl.bin: mmc_spl
-$(obj)spl/u-boot-spl.bin: depend
+$(obj)spl/u-boot-spl.bin: $(SUBDIR_TOOLS) depend
$(MAKE) -C spl all
updater:
@@ -763,6 +760,7 @@
$(obj)arch/blackfin/cpu/bootrom-asm-offsets.[chs] \
$(obj)arch/blackfin/cpu/init.{lds,elf}
@rm -f $(obj)include/bmp_logo.h
+ @rm -f $(obj)include/bmp_logo_data.h
@rm -f $(obj)lib/asm-offsets.s
@rm -f $(obj)include/generated/asm-offsets.h
@rm -f $(obj)$(CPUDIR)/$(SOC)/asm-offsets.s
@@ -791,7 +789,8 @@
@rm -f $(obj)u-boot.imx
@rm -f $(obj)u-boot.ubl
@rm -f $(obj)u-boot.dtb
- @rm -f $(obj)tools/{env/crc32.c,inca-swap-bytes}
+ @rm -f $(obj)u-boot.sb
+ @rm -f $(obj)tools/inca-swap-bytes
@rm -f $(obj)arch/powerpc/cpu/mpc824x/bedbug_603e.c
@rm -fr $(obj)include/asm/proc $(obj)include/asm/arch $(obj)include/asm
@rm -fr $(obj)include/generated
diff --git a/README b/README
index 73ca042..07f1d11 100644
--- a/README
+++ b/README
@@ -1027,6 +1027,12 @@
Define this to use i/o functions instead of macros
(some hardware wont work with macros)
+ CONFIG_DRIVER_TI_EMAC
+ Support for davinci emac
+
+ CONFIG_SYS_DAVINCI_EMAC_PHY_COUNT
+ Define this if you have more then 3 PHYs.
+
CONFIG_FTGMAC100
Support for Faraday's FTGMAC100 Gigabit SoC Ethernet
diff --git a/api/Makefile b/api/Makefile
index 2a64c4d..0e99f74 100644
--- a/api/Makefile
+++ b/api/Makefile
@@ -24,7 +24,8 @@
LIB = $(obj)libapi.o
-COBJS-$(CONFIG_API) += api.o api_net.o api_storage.o api_platform-$(ARCH).o
+COBJS-$(CONFIG_API) += api.o api_display.o api_net.o api_storage.o \
+ api_platform-$(ARCH).o
COBJS := $(COBJS-y)
SRCS := $(COBJS:.o=.c)
diff --git a/api/api.c b/api/api.c
index 853f010..a3bf60a 100644
--- a/api/api.c
+++ b/api/api.c
@@ -553,6 +553,50 @@
return 0;
}
+/*
+ * pseudo signature:
+ *
+ * int API_display_get_info(int type, struct display_info *di)
+ */
+static int API_display_get_info(va_list ap)
+{
+ int type;
+ struct display_info *di;
+
+ type = va_arg(ap, int);
+ di = va_arg(ap, struct display_info *);
+
+ return display_get_info(type, di);
+}
+
+/*
+ * pseudo signature:
+ *
+ * int API_display_draw_bitmap(ulong bitmap, int x, int y)
+ */
+static int API_display_draw_bitmap(va_list ap)
+{
+ ulong bitmap;
+ int x, y;
+
+ bitmap = va_arg(ap, ulong);
+ x = va_arg(ap, int);
+ y = va_arg(ap, int);
+
+ return display_draw_bitmap(bitmap, x, y);
+}
+
+/*
+ * pseudo signature:
+ *
+ * void API_display_clear(void)
+ */
+static int API_display_clear(va_list ap)
+{
+ display_clear();
+ return 0;
+}
+
static cfp_t calls_table[API_MAXCALL] = { NULL, };
/*
@@ -616,6 +660,9 @@
calls_table[API_ENV_GET] = &API_env_get;
calls_table[API_ENV_SET] = &API_env_set;
calls_table[API_ENV_ENUM] = &API_env_enum;
+ calls_table[API_DISPLAY_GET_INFO] = &API_display_get_info;
+ calls_table[API_DISPLAY_DRAW_BITMAP] = &API_display_draw_bitmap;
+ calls_table[API_DISPLAY_CLEAR] = &API_display_clear;
calls_no = API_MAXCALL;
debugf("API initialized with %d calls\n", calls_no);
diff --git a/api/api_display.c b/api/api_display.c
new file mode 100644
index 0000000..6439170
--- /dev/null
+++ b/api/api_display.c
@@ -0,0 +1,74 @@
+/*
+ * Copyright (c) 2011 The Chromium OS Authors.
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <api_public.h>
+#include <lcd.h>
+#include <video_font.h> /* Get font width and height */
+
+/* lcd.h needs BMP_LOGO_HEIGHT to calculate CONSOLE_ROWS */
+#if defined(CONFIG_LCD_LOGO) && !defined(CONFIG_LCD_INFO_BELOW_LOGO)
+#include <bmp_logo.h>
+#endif
+
+/* TODO(clchiou): add support of video device */
+
+int display_get_info(int type, struct display_info *di)
+{
+ if (!di)
+ return API_EINVAL;
+
+ switch (type) {
+ default:
+ debug("%s: unsupport display device type: %d\n",
+ __FILE__, type);
+ return API_ENODEV;
+#ifdef CONFIG_LCD
+ case DISPLAY_TYPE_LCD:
+ di->pixel_width = panel_info.vl_col;
+ di->pixel_height = panel_info.vl_row;
+ di->screen_rows = CONSOLE_ROWS;
+ di->screen_cols = CONSOLE_COLS;
+ break;
+#endif
+ }
+
+ di->type = type;
+ return 0;
+}
+
+int display_draw_bitmap(ulong bitmap, int x, int y)
+{
+ if (!bitmap)
+ return API_EINVAL;
+#ifdef CONFIG_LCD
+ return lcd_display_bitmap(bitmap, x, y);
+#else
+ return API_ENODEV;
+#endif
+}
+
+void display_clear(void)
+{
+#ifdef CONFIG_LCD
+ lcd_clear();
+#endif
+}
diff --git a/api/api_private.h b/api/api_private.h
index 94a7fc5..988f702 100644
--- a/api/api_private.h
+++ b/api/api_private.h
@@ -45,4 +45,8 @@
void dev_stor_init(void);
+int display_get_info(int type, struct display_info *di);
+int display_draw_bitmap(ulong bitmap, int x, int y);
+void display_clear(void);
+
#endif /* _API_PRIVATE_H_ */
diff --git a/arch/arm/cpu/arm1136/mx31/generic.c b/arch/arm/cpu/arm1136/mx31/generic.c
index 4f27e25..f458281 100644
--- a/arch/arm/cpu/arm1136/mx31/generic.c
+++ b/arch/arm/cpu/arm1136/mx31/generic.c
@@ -27,8 +27,6 @@
#include <asm/io.h>
#include <asm/arch/sys_proto.h>
-#define IOMUXGPR (IOMUXC_BASE + 0x008)
-
static u32 mx31_decode_pll(u32 reg, u32 infreq)
{
u32 mfi = GET_PLL_MFI(reg);
@@ -89,7 +87,7 @@
void mx31_dump_clocks(void)
{
u32 cpufreq = mx31_get_mcu_main_clk();
- printf("mx31 cpu clock: %dMHz\n",cpufreq / 1000000);
+ printf("mx31 cpu clock: %dMHz\n", cpufreq / 1000000);
printf("ipg clock : %dHz\n", mx31_get_ipg_clk());
printf("hsp clock : %dHz\n", mx31_get_hsp_clk());
}
@@ -146,14 +144,15 @@
void mx31_set_gpr(enum iomux_gp_func gp, char en)
{
u32 l;
+ struct iomuxc_regs *iomuxc = (struct iomuxc_regs *)IOMUXC_BASE;
- l = readl(IOMUXGPR);
+ l = readl(&iomuxc->gpr);
if (en)
l |= gp;
else
l &= ~gp;
- writel(l, IOMUXGPR);
+ writel(l, &iomuxc->gpr);
}
void mxc_setup_weimcs(int cs, const struct mxc_weimcs *weimcs)
@@ -216,7 +215,7 @@
}
#if defined(CONFIG_DISPLAY_CPUINFO)
-int print_cpuinfo (void)
+int print_cpuinfo(void)
{
u32 srev = get_cpu_rev();
diff --git a/arch/arm/cpu/arm920t/a320/timer.c b/arch/arm/cpu/arm920t/a320/timer.c
index 443d31d..4bfcef2 100644
--- a/arch/arm/cpu/arm920t/a320/timer.c
+++ b/arch/arm/cpu/arm920t/a320/timer.c
@@ -18,20 +18,35 @@
*/
#include <common.h>
+#include <div64.h>
#include <asm/io.h>
#include <faraday/ftpmu010.h>
#include <faraday/fttmr010.h>
-static ulong timestamp;
-static ulong lastdec;
-
-static struct fttmr010 *tmr = (struct fttmr010 *)CONFIG_FTTMR010_BASE;
+DECLARE_GLOBAL_DATA_PTR;
#define TIMER_CLOCK 32768
#define TIMER_LOAD_VAL 0xffffffff
+static inline unsigned long long tick_to_time(unsigned long long tick)
+{
+ tick *= CONFIG_SYS_HZ;
+ do_div(tick, gd->timer_rate_hz);
+
+ return tick;
+}
+
+static inline unsigned long long usec_to_tick(unsigned long long usec)
+{
+ usec *= gd->timer_rate_hz;
+ do_div(usec, 1000000);
+
+ return usec;
+}
+
int timer_init(void)
{
+ struct fttmr010 *tmr = (struct fttmr010 *)CONFIG_FTTMR010_BASE;
unsigned int cr;
debug("%s()\n", __func__);
@@ -59,106 +74,57 @@
cr |= FTTMR010_TM3_ENABLE;
writel(cr, &tmr->cr);
- /* init the timestamp and lastdec value */
- reset_timer_masked();
+ gd->timer_rate_hz = TIMER_CLOCK;
+ gd->tbu = gd->tbl = 0;
return 0;
}
/*
- * timer without interrupts
- */
-
-/*
- * reset time
- */
-void reset_timer_masked(void)
-{
- /* capure current decrementer value time */
- lastdec = readl(&tmr->timer3_counter) / (TIMER_CLOCK / CONFIG_SYS_HZ);
- timestamp = 0; /* start "advancing" time stamp from 0 */
-
- debug("%s(): lastdec = %lx\n", __func__, lastdec);
-}
-
-/*
- * return timer ticks
- */
-ulong get_timer_masked(void)
-{
- /* current tick value */
- ulong now = readl(&tmr->timer3_counter) / (TIMER_CLOCK / CONFIG_SYS_HZ);
-
- debug("%s(): now = %lx, lastdec = %lx\n", __func__, now, lastdec);
-
- if (lastdec >= now) {
- /*
- * normal mode (non roll)
- * move stamp fordward with absoulte diff ticks
- */
- timestamp += lastdec - now;
- } else {
- /*
- * we have overflow of the count down timer
- *
- * nts = ts + ld + (TLV - now)
- * ts=old stamp, ld=time that passed before passing through -1
- * (TLV-now) amount of time after passing though -1
- * nts = new "advancing time stamp"...it could also roll and
- * cause problems.
- */
- timestamp += lastdec + TIMER_LOAD_VAL - now;
- }
-
- lastdec = now;
-
- debug("%s() returns %lx\n", __func__, timestamp);
-
- return timestamp;
-}
-
-/*
- * return difference between timer ticks and base
- */
-ulong get_timer(ulong base)
-{
- debug("%s(%lx)\n", __func__, base);
- return get_timer_masked() - base;
-}
-
-/* delay x useconds AND preserve advance timestamp value */
-void __udelay(unsigned long usec)
-{
- long tmo = usec * (TIMER_CLOCK / 1000) / 1000;
- unsigned long now, last = readl(&tmr->timer3_counter);
-
- debug("%s(%lu)\n", __func__, usec);
- while (tmo > 0) {
- now = readl(&tmr->timer3_counter);
- if (now > last) /* count down timer overflow */
- tmo -= TIMER_LOAD_VAL + last - now;
- else
- tmo -= last - now;
- last = now;
- }
-}
-
-/*
- * This function is derived from PowerPC code (read timebase as long long).
- * On ARM it just returns the timer value.
+ * Get the current 64 bit timer tick count
*/
unsigned long long get_ticks(void)
{
- debug("%s()\n", __func__);
- return get_timer(0);
+ struct fttmr010 *tmr = (struct fttmr010 *)CONFIG_FTTMR010_BASE;
+ ulong now = TIMER_LOAD_VAL - readl(&tmr->timer3_counter);
+
+ /* increment tbu if tbl has rolled over */
+ if (now < gd->tbl)
+ gd->tbu++;
+ gd->tbl = now;
+ return (((unsigned long long)gd->tbu) << 32) | gd->tbl;
+}
+
+void __udelay(unsigned long usec)
+{
+ unsigned long long start;
+ ulong tmo;
+
+ start = get_ticks(); /* get current timestamp */
+ tmo = usec_to_tick(usec); /* convert usecs to ticks */
+ while ((get_ticks() - start) < tmo)
+ ; /* loop till time has passed */
}
/*
- * This function is derived from PowerPC code (timebase clock frequency).
- * On ARM it returns the number of timer ticks per second.
+ * get_timer(base) can be used to check for timeouts or
+ * to measure elasped time relative to an event:
+ *
+ * ulong start_time = get_timer(0) sets start_time to the current
+ * time value.
+ * get_timer(start_time) returns the time elapsed since then.
+ *
+ * The time is used in CONFIG_SYS_HZ units!
+ */
+ulong get_timer(ulong base)
+{
+ return tick_to_time(get_ticks()) - base;
+}
+
+/*
+ * Return the number of timer ticks per second.
*/
ulong get_tbclk(void)
{
- debug("%s()\n", __func__);
- return CONFIG_SYS_HZ;
+ return gd->timer_rate_hz;
}
diff --git a/arch/arm/cpu/arm926ejs/Makefile b/arch/arm/cpu/arm926ejs/Makefile
index 930e0d1..a56ff08 100644
--- a/arch/arm/cpu/arm926ejs/Makefile
+++ b/arch/arm/cpu/arm926ejs/Makefile
@@ -28,6 +28,12 @@
START = start.o
COBJS = cpu.o
+ifdef CONFIG_SPL_BUILD
+ifdef CONFIG_SPL_NO_CPU_SUPPORT_CODE
+START :=
+endif
+endif
+
SRCS := $(START:.o=.S) $(SOBJS:.o=.S) $(COBJS:.o=.c)
OBJS := $(addprefix $(obj),$(COBJS) $(SOBJS))
START := $(addprefix $(obj),$(START))
diff --git a/arch/arm/cpu/arm926ejs/davinci/Makefile b/arch/arm/cpu/arm926ejs/davinci/Makefile
index 98c7e55..aeb058a 100644
--- a/arch/arm/cpu/arm926ejs/davinci/Makefile
+++ b/arch/arm/cpu/arm926ejs/davinci/Makefile
@@ -28,7 +28,7 @@
LIB = $(obj)lib$(SOC).o
COBJS-y += cpu.o timer.o psc.o
-COBJS-$(CONFIG_AM18018_LOWLEVEL) += am1808_lowlevel.o
+COBJS-$(CONFIG_DA850_LOWLEVEL) += da850_lowlevel.o
COBJS-$(CONFIG_SOC_DM355) += dm355.o
COBJS-$(CONFIG_SOC_DM365) += dm365.o
COBJS-$(CONFIG_SOC_DM644X) += dm644x.o
diff --git a/arch/arm/cpu/arm926ejs/davinci/am1808_lowlevel.c b/arch/arm/cpu/arm926ejs/davinci/am1808_lowlevel.c
deleted file mode 100644
index 1ea4a9f..0000000
--- a/arch/arm/cpu/arm926ejs/davinci/am1808_lowlevel.c
+++ /dev/null
@@ -1,428 +0,0 @@
-/*
- * SoC-specific lowlevel code for AM1808 and similar chips
- *
- * Copyright (C) 2011
- * Heiko Schocher, DENX Software Engineering, hs@denx.de.
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
- */
-#include <common.h>
-#include <nand.h>
-#include <ns16550.h>
-#include <post.h>
-#include <asm/arch/am1808_lowlevel.h>
-#include <asm/arch/hardware.h>
-#include <asm/arch/ddr2_defs.h>
-#include <asm/arch/emif_defs.h>
-
-void am1808_waitloop(unsigned long loopcnt)
-{
- unsigned long i;
-
- for (i = 0; i < loopcnt; i++)
- asm(" NOP");
-}
-
-int am1808_pll_init(struct davinci_pllc_regs *reg, unsigned long pllmult)
-{
- if (reg == davinci_pllc0_regs)
- /* Unlock PLL registers. */
- clrbits_le32(&davinci_syscfg_regs->cfgchip0, 0x00000010);
-
- /*
- * Set PLLENSRC '0',bit 5, PLL Enable(PLLEN) selection is controlled
- * through MMR
- */
- clrbits_le32(®->pllctl, 0x00000020);
- /* PLLCTL.EXTCLKSRC bit 9 should be left at 0 for Freon */
- clrbits_le32(®->pllctl, 0x00000200);
-
- /* Set PLLEN=0 => PLL BYPASS MODE */
- clrbits_le32(®->pllctl, 0x00000001);
-
- am1808_waitloop(150);
-
- if (reg == davinci_pllc0_regs) {
- /*
- * Select the Clock Mode bit 8 as External Clock or On Chip
- * Oscilator
- */
- dv_maskbits(®->pllctl, 0xFFFFFEFF);
- setbits_le32(®->pllctl, (CONFIG_SYS_DV_CLKMODE << 8));
- }
-
- /* Clear PLLRST bit to reset the PLL */
- clrbits_le32(®->pllctl, 0x00000008);
-
- /* Disable the PLL output */
- setbits_le32(®->pllctl, 0x00000010);
-
- /* PLL initialization sequence */
- /*
- * Power up the PLL- PWRDN bit set to 0 to bring the PLL out of
- * power down bit
- */
- clrbits_le32(®->pllctl, 0x00000002);
-
- /* Enable the PLL from Disable Mode PLLDIS bit to 0 */
- clrbits_le32(®->pllctl, 0x00000010);
-
- /* Program the required multiplier value in PLLM */
- writel(pllmult, ®->pllm);
-
- /* program the postdiv */
- if (reg == davinci_pllc0_regs)
- writel((0x8000 | CONFIG_SYS_AM1808_PLL0_POSTDIV),
- ®->postdiv);
- else
- writel((0x8000 | CONFIG_SYS_AM1808_PLL1_POSTDIV),
- ®->postdiv);
-
- /*
- * Check for the GOSTAT bit in PLLSTAT to clear to 0 to indicate that
- * no GO operation is currently in progress
- */
- while ((readl(®->pllstat) & 0x1) == 1)
- ;
-
- if (reg == davinci_pllc0_regs) {
- writel(CONFIG_SYS_AM1808_PLL0_PLLDIV1, ®->plldiv1);
- writel(CONFIG_SYS_AM1808_PLL0_PLLDIV2, ®->plldiv2);
- writel(CONFIG_SYS_AM1808_PLL0_PLLDIV3, ®->plldiv3);
- writel(CONFIG_SYS_AM1808_PLL0_PLLDIV4, ®->plldiv4);
- writel(CONFIG_SYS_AM1808_PLL0_PLLDIV5, ®->plldiv5);
- writel(CONFIG_SYS_AM1808_PLL0_PLLDIV6, ®->plldiv6);
- writel(CONFIG_SYS_AM1808_PLL0_PLLDIV7, ®->plldiv7);
- } else {
- writel(CONFIG_SYS_AM1808_PLL1_PLLDIV1, ®->plldiv1);
- writel(CONFIG_SYS_AM1808_PLL1_PLLDIV2, ®->plldiv2);
- writel(CONFIG_SYS_AM1808_PLL1_PLLDIV3, ®->plldiv3);
- }
-
- /*
- * Set the GOSET bit in PLLCMD to 1 to initiate a new divider
- * transition.
- */
- setbits_le32(®->pllcmd, 0x01);
-
- /*
- * Wait for the GOSTAT bit in PLLSTAT to clear to 0
- * (completion of phase alignment).
- */
- while ((readl(®->pllstat) & 0x1) == 1)
- ;
-
- /* Wait for PLL to reset properly. See PLL spec for PLL reset time */
- am1808_waitloop(200);
-
- /* Set the PLLRST bit in PLLCTL to 1 to bring the PLL out of reset */
- setbits_le32(®->pllctl, 0x00000008);
-
- /* Wait for PLL to lock. See PLL spec for PLL lock time */
- am1808_waitloop(2400);
-
- /*
- * Set the PLLEN bit in PLLCTL to 1 to remove the PLL from bypass
- * mode
- */
- setbits_le32(®->pllctl, 0x00000001);
-
-
- /*
- * clear EMIFA and EMIFB clock source settings, let them
- * run off SYSCLK
- */
- if (reg == davinci_pllc0_regs)
- dv_maskbits(&davinci_syscfg_regs->cfgchip3, 0xFFFFFFF8);
-
- return 0;
-}
-
-void am1808_lpc_transition(unsigned char pscnum, unsigned char module,
- unsigned char domain, unsigned char state)
-{
- struct davinci_psc_regs *reg;
- dv_reg_p mdstat, mdctl;
-
- if (pscnum == 0) {
- reg = davinci_psc0_regs;
- mdstat = ®->psc0.mdstat[module];
- mdctl = ®->psc0.mdctl[module];
- } else {
- reg = davinci_psc1_regs;
- mdstat = ®->psc1.mdstat[module];
- mdctl = ®->psc1.mdctl[module];
- }
-
- /* Wait for any outstanding transition to complete */
- while ((readl(®->ptstat) & (0x00000001 << domain)))
- ;
-
- /* If we are already in that state, just return */
- if ((readl(mdstat) & 0x1F) == state)
- return;
-
- /* Perform transition */
- writel((readl(mdctl) & 0xFFFFFFE0) | state, mdctl);
- setbits_le32(®->ptcmd, (0x00000001 << domain));
-
- /* Wait for transition to complete */
- while (readl(®->ptstat) & (0x00000001 << domain))
- ;
-
- /* Wait and verify the state */
- while ((readl(mdstat) & 0x1F) != state)
- ;
-}
-
-int am1808_ddr_setup(unsigned int freq)
-{
- unsigned long tmp;
-
- /* Enable the Clock to DDR2/mDDR */
- am1808_lpc_transition(1, 6, 0, PSC_ENABLE);
-
- tmp = readl(&davinci_syscfg1_regs->vtpio_ctl);
- if ((tmp & VTP_POWERDWN) == VTP_POWERDWN) {
- /* Begin VTP Calibration */
- clrbits_le32(&davinci_syscfg1_regs->vtpio_ctl, VTP_POWERDWN);
- clrbits_le32(&davinci_syscfg1_regs->vtpio_ctl, VTP_LOCK);
- setbits_le32(&davinci_syscfg1_regs->vtpio_ctl, VTP_CLKRZ);
- clrbits_le32(&davinci_syscfg1_regs->vtpio_ctl, VTP_CLKRZ);
- setbits_le32(&davinci_syscfg1_regs->vtpio_ctl, VTP_CLKRZ);
-
- /* Polling READY bit to see when VTP calibration is done */
- tmp = readl(&davinci_syscfg1_regs->vtpio_ctl);
- while ((tmp & VTP_READY) != VTP_READY)
- tmp = readl(&davinci_syscfg1_regs->vtpio_ctl);
-
- setbits_le32(&davinci_syscfg1_regs->vtpio_ctl, VTP_LOCK);
- setbits_le32(&davinci_syscfg1_regs->vtpio_ctl, VTP_POWERDWN);
-
- setbits_le32(&davinci_syscfg1_regs->vtpio_ctl, VTP_IOPWRDWN);
- }
-
- writel(CONFIG_SYS_AM1808_DDR2_DDRPHYCR, &dv_ddr2_regs_ctrl->ddrphycr);
- clrbits_le32(&davinci_syscfg1_regs->ddr_slew,
- (1 << DDR_SLEW_CMOSEN_BIT));
-
- setbits_le32(&dv_ddr2_regs_ctrl->sdbcr, DV_DDR_BOOTUNLOCK);
-
- writel((CONFIG_SYS_AM1808_DDR2_SDBCR & ~0xf0000000) |
- (readl(&dv_ddr2_regs_ctrl->sdbcr) & 0xf0000000), /*rsv Bytes*/
- &dv_ddr2_regs_ctrl->sdbcr);
- writel(CONFIG_SYS_AM1808_DDR2_SDBCR2, &dv_ddr2_regs_ctrl->sdbcr2);
-
- writel(CONFIG_SYS_AM1808_DDR2_SDTIMR, &dv_ddr2_regs_ctrl->sdtimr);
- writel(CONFIG_SYS_AM1808_DDR2_SDTIMR2, &dv_ddr2_regs_ctrl->sdtimr2);
-
- clrbits_le32(&dv_ddr2_regs_ctrl->sdbcr,
- (1 << DV_DDR_SDCR_TIMUNLOCK_SHIFT));
-
- /*
- * LPMODEN and MCLKSTOPEN must be set!
- * Without this bits set, PSC don;t switch states !!
- */
- writel(CONFIG_SYS_AM1808_DDR2_SDRCR |
- (1 << DV_DDR_SRCR_LPMODEN_SHIFT) |
- (1 << DV_DDR_SRCR_MCLKSTOPEN_SHIFT),
- &dv_ddr2_regs_ctrl->sdrcr);
-
- /* SyncReset the Clock to EMIF3A SDRAM */
- am1808_lpc_transition(1, 6, 0, PSC_SYNCRESET);
- /* Enable the Clock to EMIF3A SDRAM */
- am1808_lpc_transition(1, 6, 0, PSC_ENABLE);
-
- /* disable self refresh */
- clrbits_le32(&dv_ddr2_regs_ctrl->sdrcr, 0xc0000000);
- writel(0x30, &dv_ddr2_regs_ctrl->pbbpr);
-
- return 0;
-}
-
-static void am1808_set_mdctl(dv_reg_p mdctl)
-{
- if ((readl(mdctl) & 0x1F) != PSC_ENABLE)
- writel(((readl(mdctl) & 0xFFFFFFE0) | PSC_ENABLE), mdctl);
-}
-
-void am1808_psc_init(void)
-{
- struct davinci_psc_regs *reg;
- int i;
-
- /* PSC 0 domain 0 init */
- reg = davinci_psc0_regs;
- while ((readl(®->ptstat) & 0x00000001))
- ;
-
- for (i = 3; i <= 4 ; i++)
- am1808_set_mdctl(®->psc0.mdctl[i]);
-
- for (i = 7; i <= 12 ; i++)
- am1808_set_mdctl(®->psc0.mdctl[i]);
-
- /* Do Always-On Power Domain Transitions */
- setbits_le32(®->ptcmd, 0x00000001);
- while (readl(®->ptstat) & 0x00000001)
- ;
-
- /* PSC1, domain 1 init */
- reg = davinci_psc1_regs;
- while ((readl(®->ptstat) & 0x00000001))
- ;
-
- am1808_set_mdctl(®->psc1.mdctl[3]);
- am1808_set_mdctl(®->psc1.mdctl[6]);
-
- /* UART1 + UART2 */
- for (i = 12 ; i <= 13 ; i++)
- am1808_set_mdctl(®->psc1.mdctl[i]);
-
- am1808_set_mdctl(®->psc1.mdctl[26]);
- am1808_set_mdctl(®->psc1.mdctl[31]);
-
- /* Do Always-On Power Domain Transitions */
- setbits_le32(®->ptcmd, 0x00000001);
- while (readl(®->ptstat) & 0x00000001)
- ;
-}
-
-void am1808_pinmux_ctl(unsigned long offset, unsigned long mask,
- unsigned long value)
-{
- clrbits_le32(&davinci_syscfg_regs->pinmux[offset], mask);
- setbits_le32(&davinci_syscfg_regs->pinmux[offset], (mask & value));
-}
-
-__attribute__((weak))
-void board_gpio_init(void)
-{
- return;
-}
-
-#if defined(CONFIG_NAND_SPL)
-void nand_boot(void)
-{
- __attribute__((noreturn)) void (*uboot)(void);
-
- /* copy image from NOR to RAM */
- memcpy((void *)CONFIG_SYS_NAND_U_BOOT_DST,
- (void *)CONFIG_SYS_NAND_U_BOOT_OFFS,
- CONFIG_SYS_NAND_U_BOOT_SIZE);
-
- /* and jump to it ... */
- uboot = (void *)CONFIG_SYS_NAND_U_BOOT_START;
- (*uboot)();
-}
-#endif
-
-#if defined(CONFIG_NAND_SPL)
-void board_init_f(ulong bootflag)
-#else
-int arch_cpu_init(void)
-#endif
-{
- /*
- * copied from arch/arm/cpu/arm926ejs/start.S
- *
- * flush v4 I/D caches
- */
- asm("mov r0, #0");
- asm("mcr p15, 0, r0, c7, c7, 0"); /* flush v3/v4 cache */
- asm("mcr p15, 0, r0, c8, c7, 0"); /* flush v4 TLB */
-
- /*
- * disable MMU stuff and caches
- */
- asm("mrc p15, 0, r0, c1, c0, 0");
- /* clear bits 13, 9:8 (--V- --RS) */
- asm("bic r0, r0, #0x00002300");
- /* clear bits 7, 2:0 (B--- -CAM) */
- asm("bic r0, r0, #0x00000087");
- /* set bit 2 (A) Align */
- asm("orr r0, r0, #0x00000002");
- /* set bit 12 (I) I-Cache */
- asm("orr r0, r0, #0x00001000");
- asm("mcr p15, 0, r0, c1, c0, 0");
-
- /* Unlock kick registers */
- writel(0x83e70b13, &davinci_syscfg_regs->kick0);
- writel(0x95a4f1e0, &davinci_syscfg_regs->kick1);
-
- dv_maskbits(&davinci_syscfg_regs->suspsrc,
- ((1 << 27) | (1 << 22) | (1 << 20) | (1 << 5) | (1 << 16)));
-
- /* System PSC setup - enable all */
- am1808_psc_init();
-
- /* Setup Pinmux */
- am1808_pinmux_ctl(0, 0xFFFFFFFF, CONFIG_SYS_AM1808_PINMUX0);
- am1808_pinmux_ctl(1, 0xFFFFFFFF, CONFIG_SYS_AM1808_PINMUX1);
- am1808_pinmux_ctl(2, 0xFFFFFFFF, CONFIG_SYS_AM1808_PINMUX2);
- am1808_pinmux_ctl(3, 0xFFFFFFFF, CONFIG_SYS_AM1808_PINMUX3);
- am1808_pinmux_ctl(4, 0xFFFFFFFF, CONFIG_SYS_AM1808_PINMUX4);
- am1808_pinmux_ctl(5, 0xFFFFFFFF, CONFIG_SYS_AM1808_PINMUX5);
- am1808_pinmux_ctl(6, 0xFFFFFFFF, CONFIG_SYS_AM1808_PINMUX6);
- am1808_pinmux_ctl(7, 0xFFFFFFFF, CONFIG_SYS_AM1808_PINMUX7);
- am1808_pinmux_ctl(8, 0xFFFFFFFF, CONFIG_SYS_AM1808_PINMUX8);
- am1808_pinmux_ctl(9, 0xFFFFFFFF, CONFIG_SYS_AM1808_PINMUX9);
- am1808_pinmux_ctl(10, 0xFFFFFFFF, CONFIG_SYS_AM1808_PINMUX10);
- am1808_pinmux_ctl(11, 0xFFFFFFFF, CONFIG_SYS_AM1808_PINMUX11);
- am1808_pinmux_ctl(12, 0xFFFFFFFF, CONFIG_SYS_AM1808_PINMUX12);
- am1808_pinmux_ctl(13, 0xFFFFFFFF, CONFIG_SYS_AM1808_PINMUX13);
- am1808_pinmux_ctl(14, 0xFFFFFFFF, CONFIG_SYS_AM1808_PINMUX14);
- am1808_pinmux_ctl(15, 0xFFFFFFFF, CONFIG_SYS_AM1808_PINMUX15);
- am1808_pinmux_ctl(16, 0xFFFFFFFF, CONFIG_SYS_AM1808_PINMUX16);
- am1808_pinmux_ctl(17, 0xFFFFFFFF, CONFIG_SYS_AM1808_PINMUX17);
- am1808_pinmux_ctl(18, 0xFFFFFFFF, CONFIG_SYS_AM1808_PINMUX18);
- am1808_pinmux_ctl(19, 0xFFFFFFFF, CONFIG_SYS_AM1808_PINMUX19);
-
- /* PLL setup */
- am1808_pll_init(davinci_pllc0_regs, CONFIG_SYS_AM1808_PLL0_PLLM);
- am1808_pll_init(davinci_pllc1_regs, CONFIG_SYS_AM1808_PLL1_PLLM);
-
- /* GPIO setup */
- board_gpio_init();
-
- /* setup CSn config */
- writel(CONFIG_SYS_AM1808_CS2CFG, &davinci_emif_regs->ab1cr);
- writel(CONFIG_SYS_AM1808_CS3CFG, &davinci_emif_regs->ab2cr);
-
- am1808_lpc_transition(1, 13, 0, PSC_ENABLE);
- NS16550_init((NS16550_t)(CONFIG_SYS_NS16550_COM1),
- CONFIG_SYS_NS16550_CLK / 16 / CONFIG_BAUDRATE);
-
- /*
- * Fix Power and Emulation Management Register
- * see sprufw3a.pdf page 37 Table 24
- */
- writel(readl((CONFIG_SYS_NS16550_COM1 + 0x30)) | 0x00006001,
- (CONFIG_SYS_NS16550_COM1 + 0x30));
-#if defined(CONFIG_NAND_SPL)
- puts("ddr init\n");
- am1808_ddr_setup(132);
-
- puts("boot u-boot ...\n");
-
- nand_boot();
-#else
- am1808_ddr_setup(132);
- return 0;
-#endif
-}
diff --git a/arch/arm/cpu/arm926ejs/davinci/da850_lowlevel.c b/arch/arm/cpu/arm926ejs/davinci/da850_lowlevel.c
new file mode 100644
index 0000000..c7ec70f
--- /dev/null
+++ b/arch/arm/cpu/arm926ejs/davinci/da850_lowlevel.c
@@ -0,0 +1,311 @@
+/*
+ * SoC-specific lowlevel code for DA850
+ *
+ * Copyright (C) 2011
+ * Heiko Schocher, DENX Software Engineering, hs@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
+ */
+#include <common.h>
+#include <nand.h>
+#include <ns16550.h>
+#include <post.h>
+#include <asm/arch/da850_lowlevel.h>
+#include <asm/arch/hardware.h>
+#include <asm/arch/ddr2_defs.h>
+#include <asm/arch/emif_defs.h>
+#include <asm/arch/pll_defs.h>
+
+void da850_waitloop(unsigned long loopcnt)
+{
+ unsigned long i;
+
+ for (i = 0; i < loopcnt; i++)
+ asm(" NOP");
+}
+
+int da850_pll_init(struct davinci_pllc_regs *reg, unsigned long pllmult)
+{
+ if (reg == davinci_pllc0_regs)
+ /* Unlock PLL registers. */
+ clrbits_le32(&davinci_syscfg_regs->cfgchip0, PLL_MASTER_LOCK);
+
+ /*
+ * Set PLLENSRC '0',bit 5, PLL Enable(PLLEN) selection is controlled
+ * through MMR
+ */
+ clrbits_le32(®->pllctl, PLLCTL_PLLENSRC);
+ /* PLLCTL.EXTCLKSRC bit 9 should be left at 0 for Freon */
+ clrbits_le32(®->pllctl, PLLCTL_EXTCLKSRC);
+
+ /* Set PLLEN=0 => PLL BYPASS MODE */
+ clrbits_le32(®->pllctl, PLLCTL_PLLEN);
+
+ da850_waitloop(150);
+
+ if (reg == davinci_pllc0_regs) {
+ /*
+ * Select the Clock Mode bit 8 as External Clock or On Chip
+ * Oscilator
+ */
+ dv_maskbits(®->pllctl, ~PLLCTL_RES_9);
+ setbits_le32(®->pllctl,
+ (CONFIG_SYS_DV_CLKMODE << PLLCTL_CLOCK_MODE_SHIFT));
+ }
+
+ /* Clear PLLRST bit to reset the PLL */
+ clrbits_le32(®->pllctl, PLLCTL_PLLRST);
+
+ /* Disable the PLL output */
+ setbits_le32(®->pllctl, PLLCTL_PLLDIS);
+
+ /* PLL initialization sequence */
+ /*
+ * Power up the PLL- PWRDN bit set to 0 to bring the PLL out of
+ * power down bit
+ */
+ clrbits_le32(®->pllctl, PLLCTL_PLLPWRDN);
+
+ /* Enable the PLL from Disable Mode PLLDIS bit to 0 */
+ clrbits_le32(®->pllctl, PLLCTL_PLLDIS);
+
+ /* Program the required multiplier value in PLLM */
+ writel(pllmult, ®->pllm);
+
+ /* program the postdiv */
+ if (reg == davinci_pllc0_regs)
+ writel((PLL_POSTDEN | CONFIG_SYS_DA850_PLL0_POSTDIV),
+ ®->postdiv);
+ else
+ writel((PLL_POSTDEN | CONFIG_SYS_DA850_PLL1_POSTDIV),
+ ®->postdiv);
+
+ /*
+ * Check for the GOSTAT bit in PLLSTAT to clear to 0 to indicate that
+ * no GO operation is currently in progress
+ */
+ while ((readl(®->pllstat) & PLLCMD_GOSTAT) == PLLCMD_GOSTAT)
+ ;
+
+ if (reg == davinci_pllc0_regs) {
+ writel(CONFIG_SYS_DA850_PLL0_PLLDIV1, ®->plldiv1);
+ writel(CONFIG_SYS_DA850_PLL0_PLLDIV2, ®->plldiv2);
+ writel(CONFIG_SYS_DA850_PLL0_PLLDIV3, ®->plldiv3);
+ writel(CONFIG_SYS_DA850_PLL0_PLLDIV4, ®->plldiv4);
+ writel(CONFIG_SYS_DA850_PLL0_PLLDIV5, ®->plldiv5);
+ writel(CONFIG_SYS_DA850_PLL0_PLLDIV6, ®->plldiv6);
+ writel(CONFIG_SYS_DA850_PLL0_PLLDIV7, ®->plldiv7);
+ } else {
+ writel(CONFIG_SYS_DA850_PLL1_PLLDIV1, ®->plldiv1);
+ writel(CONFIG_SYS_DA850_PLL1_PLLDIV2, ®->plldiv2);
+ writel(CONFIG_SYS_DA850_PLL1_PLLDIV3, ®->plldiv3);
+ }
+
+ /*
+ * Set the GOSET bit in PLLCMD to 1 to initiate a new divider
+ * transition.
+ */
+ setbits_le32(®->pllcmd, PLLCMD_GOSTAT);
+
+ /*
+ * Wait for the GOSTAT bit in PLLSTAT to clear to 0
+ * (completion of phase alignment).
+ */
+ while ((readl(®->pllstat) & PLLCMD_GOSTAT) == PLLCMD_GOSTAT)
+ ;
+
+ /* Wait for PLL to reset properly. See PLL spec for PLL reset time */
+ da850_waitloop(200);
+
+ /* Set the PLLRST bit in PLLCTL to 1 to bring the PLL out of reset */
+ setbits_le32(®->pllctl, PLLCTL_PLLRST);
+
+ /* Wait for PLL to lock. See PLL spec for PLL lock time */
+ da850_waitloop(2400);
+
+ /*
+ * Set the PLLEN bit in PLLCTL to 1 to remove the PLL from bypass
+ * mode
+ */
+ setbits_le32(®->pllctl, PLLCTL_PLLEN);
+
+
+ /*
+ * clear EMIFA and EMIFB clock source settings, let them
+ * run off SYSCLK
+ */
+ if (reg == davinci_pllc0_regs)
+ dv_maskbits(&davinci_syscfg_regs->cfgchip3,
+ ~(PLL_SCSCFG3_DIV45PENA | PLL_SCSCFG3_EMA_CLKSRC));
+
+ return 0;
+}
+
+int da850_ddr_setup(void)
+{
+ unsigned long tmp;
+
+ /* Enable the Clock to DDR2/mDDR */
+ lpsc_on(DAVINCI_LPSC_DDR_EMIF);
+
+ tmp = readl(&davinci_syscfg1_regs->vtpio_ctl);
+ if ((tmp & VTP_POWERDWN) == VTP_POWERDWN) {
+ /* Begin VTP Calibration */
+ clrbits_le32(&davinci_syscfg1_regs->vtpio_ctl, VTP_POWERDWN);
+ clrbits_le32(&davinci_syscfg1_regs->vtpio_ctl, VTP_LOCK);
+ setbits_le32(&davinci_syscfg1_regs->vtpio_ctl, VTP_CLKRZ);
+ clrbits_le32(&davinci_syscfg1_regs->vtpio_ctl, VTP_CLKRZ);
+ setbits_le32(&davinci_syscfg1_regs->vtpio_ctl, VTP_CLKRZ);
+
+ /* Polling READY bit to see when VTP calibration is done */
+ tmp = readl(&davinci_syscfg1_regs->vtpio_ctl);
+ while ((tmp & VTP_READY) != VTP_READY)
+ tmp = readl(&davinci_syscfg1_regs->vtpio_ctl);
+
+ setbits_le32(&davinci_syscfg1_regs->vtpio_ctl, VTP_LOCK);
+ setbits_le32(&davinci_syscfg1_regs->vtpio_ctl, VTP_POWERDWN);
+
+ setbits_le32(&davinci_syscfg1_regs->vtpio_ctl, VTP_IOPWRDWN);
+ }
+
+ writel(CONFIG_SYS_DA850_DDR2_DDRPHYCR, &dv_ddr2_regs_ctrl->ddrphycr);
+ clrbits_le32(&davinci_syscfg1_regs->ddr_slew,
+ (1 << DDR_SLEW_CMOSEN_BIT));
+
+ /*
+ * SDRAM Configuration Register (SDCR):
+ * First set the BOOTUNLOCK bit to make configuration bits
+ * writeable.
+ */
+ setbits_le32(&dv_ddr2_regs_ctrl->sdbcr, DV_DDR_BOOTUNLOCK);
+
+ /*
+ * Write the new value of these bits and clear BOOTUNLOCK.
+ * At the same time, set the TIMUNLOCK bit to allow changing
+ * the timing registers
+ */
+ tmp = CONFIG_SYS_DA850_DDR2_SDBCR;
+ tmp &= ~DV_DDR_BOOTUNLOCK;
+ tmp |= DV_DDR_TIMUNLOCK;
+ writel(tmp, &dv_ddr2_regs_ctrl->sdbcr);
+
+ /* write memory configuration and timing */
+ writel(CONFIG_SYS_DA850_DDR2_SDBCR2, &dv_ddr2_regs_ctrl->sdbcr2);
+ writel(CONFIG_SYS_DA850_DDR2_SDTIMR, &dv_ddr2_regs_ctrl->sdtimr);
+ writel(CONFIG_SYS_DA850_DDR2_SDTIMR2, &dv_ddr2_regs_ctrl->sdtimr2);
+
+ /* clear the TIMUNLOCK bit and write the value of the CL field */
+ tmp &= ~DV_DDR_TIMUNLOCK;
+ writel(tmp, &dv_ddr2_regs_ctrl->sdbcr);
+
+ /*
+ * LPMODEN and MCLKSTOPEN must be set!
+ * Without this bits set, PSC don;t switch states !!
+ */
+ writel(CONFIG_SYS_DA850_DDR2_SDRCR |
+ (1 << DV_DDR_SRCR_LPMODEN_SHIFT) |
+ (1 << DV_DDR_SRCR_MCLKSTOPEN_SHIFT),
+ &dv_ddr2_regs_ctrl->sdrcr);
+
+ /* SyncReset the Clock to EMIF3A SDRAM */
+ lpsc_syncreset(DAVINCI_LPSC_DDR_EMIF);
+ /* Enable the Clock to EMIF3A SDRAM */
+ lpsc_on(DAVINCI_LPSC_DDR_EMIF);
+
+ /* disable self refresh */
+ clrbits_le32(&dv_ddr2_regs_ctrl->sdrcr,
+ DV_DDR_SDRCR_LPMODEN | DV_DDR_SDRCR_LPMODEN);
+ writel(CONFIG_SYS_DA850_DDR2_PBBPR, &dv_ddr2_regs_ctrl->pbbpr);
+
+ return 0;
+}
+
+void da850_pinmux_ctl(unsigned long offset, unsigned long mask,
+ unsigned long value)
+{
+ clrbits_le32(&davinci_syscfg_regs->pinmux[offset], mask);
+ setbits_le32(&davinci_syscfg_regs->pinmux[offset], (mask & value));
+}
+
+__attribute__((weak))
+void board_gpio_init(void)
+{
+ return;
+}
+
+int arch_cpu_init(void)
+{
+ /* Unlock kick registers */
+ writel(DV_SYSCFG_KICK0_UNLOCK, &davinci_syscfg_regs->kick0);
+ writel(DV_SYSCFG_KICK1_UNLOCK, &davinci_syscfg_regs->kick1);
+
+ dv_maskbits(&davinci_syscfg_regs->suspsrc,
+ CONFIG_SYS_DA850_SYSCFG_SUSPSRC);
+
+ /* Setup Pinmux */
+ da850_pinmux_ctl(0, 0xFFFFFFFF, CONFIG_SYS_DA850_PINMUX0);
+ da850_pinmux_ctl(1, 0xFFFFFFFF, CONFIG_SYS_DA850_PINMUX1);
+ da850_pinmux_ctl(2, 0xFFFFFFFF, CONFIG_SYS_DA850_PINMUX2);
+ da850_pinmux_ctl(3, 0xFFFFFFFF, CONFIG_SYS_DA850_PINMUX3);
+ da850_pinmux_ctl(4, 0xFFFFFFFF, CONFIG_SYS_DA850_PINMUX4);
+ da850_pinmux_ctl(5, 0xFFFFFFFF, CONFIG_SYS_DA850_PINMUX5);
+ da850_pinmux_ctl(6, 0xFFFFFFFF, CONFIG_SYS_DA850_PINMUX6);
+ da850_pinmux_ctl(7, 0xFFFFFFFF, CONFIG_SYS_DA850_PINMUX7);
+ da850_pinmux_ctl(8, 0xFFFFFFFF, CONFIG_SYS_DA850_PINMUX8);
+ da850_pinmux_ctl(9, 0xFFFFFFFF, CONFIG_SYS_DA850_PINMUX9);
+ da850_pinmux_ctl(10, 0xFFFFFFFF, CONFIG_SYS_DA850_PINMUX10);
+ da850_pinmux_ctl(11, 0xFFFFFFFF, CONFIG_SYS_DA850_PINMUX11);
+ da850_pinmux_ctl(12, 0xFFFFFFFF, CONFIG_SYS_DA850_PINMUX12);
+ da850_pinmux_ctl(13, 0xFFFFFFFF, CONFIG_SYS_DA850_PINMUX13);
+ da850_pinmux_ctl(14, 0xFFFFFFFF, CONFIG_SYS_DA850_PINMUX14);
+ da850_pinmux_ctl(15, 0xFFFFFFFF, CONFIG_SYS_DA850_PINMUX15);
+ da850_pinmux_ctl(16, 0xFFFFFFFF, CONFIG_SYS_DA850_PINMUX16);
+ da850_pinmux_ctl(17, 0xFFFFFFFF, CONFIG_SYS_DA850_PINMUX17);
+ da850_pinmux_ctl(18, 0xFFFFFFFF, CONFIG_SYS_DA850_PINMUX18);
+ da850_pinmux_ctl(19, 0xFFFFFFFF, CONFIG_SYS_DA850_PINMUX19);
+
+ /* PLL setup */
+ da850_pll_init(davinci_pllc0_regs, CONFIG_SYS_DA850_PLL0_PLLM);
+ da850_pll_init(davinci_pllc1_regs, CONFIG_SYS_DA850_PLL1_PLLM);
+
+ /* GPIO setup */
+ board_gpio_init();
+
+ /* setup CSn config */
+#if defined(CONFIG_SYS_DA850_CS2CFG)
+ writel(CONFIG_SYS_DA850_CS2CFG, &davinci_emif_regs->ab1cr);
+#endif
+#if defined(CONFIG_SYS_DA850_CS3CFG)
+ writel(CONFIG_SYS_DA850_CS3CFG, &davinci_emif_regs->ab2cr);
+#endif
+
+ lpsc_on(CONFIG_SYS_DA850_LPSC_UART);
+ NS16550_init((NS16550_t)(CONFIG_SYS_NS16550_COM1),
+ CONFIG_SYS_NS16550_CLK / 16 / CONFIG_BAUDRATE);
+
+ /*
+ * Fix Power and Emulation Management Register
+ * see sprufw3a.pdf page 37 Table 24
+ */
+ writel((DAVINCI_UART_PWREMU_MGMT_FREE | DAVINCI_UART_PWREMU_MGMT_URRST |
+ DAVINCI_UART_PWREMU_MGMT_UTRST),
+ &davinci_uart2_ctrl_regs->pwremu_mgmt);
+
+ da850_ddr_setup();
+ return 0;
+}
diff --git a/arch/arm/cpu/arm926ejs/davinci/dm365_lowlevel.c b/arch/arm/cpu/arm926ejs/davinci/dm365_lowlevel.c
index 3772e64..6e998de 100644
--- a/arch/arm/cpu/arm926ejs/davinci/dm365_lowlevel.c
+++ b/arch/arm/cpu/arm926ejs/davinci/dm365_lowlevel.c
@@ -45,7 +45,8 @@
clrbits_le32(&dv_pll0_regs->pllctl, PLLCTL_PLLPWRDN);
clrbits_le32(&dv_pll0_regs->pllctl, PLLCTL_RES_9);
- setbits_le32(&dv_pll0_regs->pllctl, clksrc << 8);
+ setbits_le32(&dv_pll0_regs->pllctl,
+ clksrc << PLLCTL_CLOCK_MODE_SHIFT);
/*
* Set PLLENSRC '0', PLL Enable(PLLEN) selection is controlled
@@ -82,7 +83,7 @@
writel(PLLSECCTL_STOPMODE | PLLSECCTL_TINITZ, &dv_pll0_regs->secctl);
/* Program the PostDiv for PLL1 */
- writel(0x8000, &dv_pll0_regs->postdiv);
+ writel(PLL_POSTDEN, &dv_pll0_regs->postdiv);
/* Post divider setting for PLL1 */
writel(CONFIG_SYS_DM36x_PLL1_PLLDIV1, &dv_pll0_regs->plldiv1);
@@ -126,7 +127,8 @@
* VDB has input on MXI pin
*/
clrbits_le32(&dv_pll1_regs->pllctl, PLLCTL_RES_9);
- setbits_le32(&dv_pll1_regs->pllctl, clksrc << 8);
+ setbits_le32(&dv_pll1_regs->pllctl,
+ clksrc << PLLCTL_CLOCK_MODE_SHIFT);
/*
* Set PLLENSRC '0', PLL Enable(PLLEN) selection is controlled
@@ -151,7 +153,7 @@
writel(pllm, &dv_pll1_regs->pllm);
writel(prediv, &dv_pll1_regs->prediv);
- writel(0x8000, &dv_pll1_regs->postdiv);
+ writel(PLL_POSTDEN, &dv_pll1_regs->postdiv);
/* Assert TENABLE = 1, TENABLEDIV = 1, TINITZ = 1 */
writel(PLLSECCTL_STOPMODE | PLLSECCTL_TENABLEDIV | PLLSECCTL_TENABLE |
@@ -261,21 +263,23 @@
VPSS_CLK_CTL_VPSS_CLKMD);
/* LPSC SyncReset DDR Clock Enable */
- writel(((readl(&dv_psc_regs->mdctl[47]) & ~PSC_MD_STATE_MSK) |
- PSC_SYNCRESET), &dv_psc_regs->mdctl[47]);
+ writel(((readl(&dv_psc_regs->mdctl[DAVINCI_LPSC_VPSSMASTER]) &
+ ~PSC_MD_STATE_MSK) | PSC_SYNCRESET),
+ &dv_psc_regs->mdctl[DAVINCI_LPSC_VPSSMASTER]);
writel((1 << PdNum), &dv_psc_regs->ptcmd);
while (!(((readl(&dv_psc_regs->ptstat) >> PdNum) & PSC_GOSTAT) == 0))
;
- while (!((readl(&dv_psc_regs->mdstat[47]) & PSC_MD_STATE_MSK) ==
- PSC_SYNCRESET))
+ while (!((readl(&dv_psc_regs->mdstat[DAVINCI_LPSC_VPSSMASTER]) &
+ PSC_MD_STATE_MSK) == PSC_SYNCRESET))
;
}
void dm365_por_reset(void)
{
- if (readl(&dv_pll0_regs->rstype) & 3)
+ if (readl(&dv_pll0_regs->rstype) &
+ (PLL_RSTYPE_POR | PLL_RSTYPE_XWRST))
dm365_vpss_sync_reset();
}
@@ -291,19 +295,20 @@
for (lpscgroup = lpscmin; lpscgroup <= lpscmax; lpscgroup++) {
if (lpscgroup == 0) {
- lpsc_start = 0; /* Enabling LPSC 3 to 28 SCR first */
- lpsc_end = 28;
+ /* Enabling LPSC 3 to 28 SCR first */
+ lpsc_start = DAVINCI_LPSC_VPSSMSTR;
+ lpsc_end = DAVINCI_LPSC_TIMER1;
} else if (lpscgroup == 1) { /* Skip locked LPSCs [29-37] */
- lpsc_start = 38;
- lpsc_end = 47;
+ lpsc_start = DAVINCI_LPSC_CFG5;
+ lpsc_end = DAVINCI_LPSC_VPSSMASTER;
} else {
- lpsc_start = 50;
- lpsc_end = 51;
+ lpsc_start = DAVINCI_LPSC_MJCP;
+ lpsc_end = DAVINCI_LPSC_HDVICP;
}
/* NEXT=0x3, Enable LPSC's */
for (i = lpsc_start; i <= lpsc_end; i++)
- setbits_le32(&dv_psc_regs->mdctl[i], 0x3);
+ setbits_le32(&dv_psc_regs->mdctl[i], PSC_ENABLE);
/*
* Program goctl to start transition sequence for LPSCs
@@ -322,7 +327,7 @@
/* Wait for MODSTAT = ENABLE from LPSC's */
for (i = lpsc_start; i <= lpsc_end; i++)
while (!((readl(&dv_psc_regs->mdstat[i]) &
- PSC_MD_STATE_MSK) == 0x3))
+ PSC_MD_STATE_MSK) == PSC_ENABLE))
;
}
}
@@ -332,7 +337,7 @@
writel(CONFIG_SYS_DM36x_AWCCR, &davinci_emif_regs->awccr);
writel(CONFIG_SYS_DM36x_AB1CR, &davinci_emif_regs->ab1cr);
- setbits_le32(&davinci_emif_regs->nandfcr, 1);
+ setbits_le32(&davinci_emif_regs->nandfcr, DAVINCI_NANDFCR_CS2NAND);
writel(CONFIG_SYS_DM36x_AB2CR, &davinci_emif_regs->ab2cr);
@@ -361,31 +366,12 @@
void dm36x_lowlevel_init(ulong bootflag)
{
- /*
- * copied from arch/arm/cpu/arm926ejs/start.S
- *
- * flush v4 I/D caches
- */
- asm("mov r0, #0");
- asm("mcr p15, 0, r0, c7, c7, 0"); /* flush v3/v4 cache */
- asm("mcr p15, 0, r0, c8, c7, 0"); /* flush v4 TLB */
-
- /*
- * disable MMU stuff and caches
- */
- asm("mrc p15, 0, r0, c1, c0, 0");
- /* clear bits 13, 9:8 (--V- --RS) */
- asm("bic r0, r0, #0x00002300");
- /* clear bits 7, 2:0 (B--- -CAM) */
- asm("bic r0, r0, #0x00000087");
- /* set bit 2 (A) Align */
- asm("orr r0, r0, #0x00000002");
- /* set bit 12 (I) I-Cache */
- asm("orr r0, r0, #0x00001000");
- asm("mcr p15, 0, r0, c1, c0, 0");
+ struct davinci_uart_ctrl_regs *davinci_uart_ctrl_regs =
+ (struct davinci_uart_ctrl_regs *)(CONFIG_SYS_NS16550_COM1 +
+ DAVINCI_UART_CTRL_BASE);
/* Mask all interrupts */
- writel(0x04, &dv_aintc_regs->intctl);
+ writel(DV_AINTC_INTCTL_IDMODE, &dv_aintc_regs->intctl);
writel(0x0, &dv_aintc_regs->eabase);
writel(0x0, &dv_aintc_regs->eint0);
writel(0x0, &dv_aintc_regs->eint1);
@@ -422,7 +408,10 @@
* Fix Power and Emulation Management Register
* see sprufh2.pdf page 38 Table 22
*/
- writel(0x0000e003, (CONFIG_SYS_NS16550_COM1 + 0x30));
+ writel((DAVINCI_UART_PWREMU_MGMT_FREE | DAVINCI_UART_PWREMU_MGMT_URRST |
+ DAVINCI_UART_PWREMU_MGMT_UTRST),
+ &davinci_uart_ctrl_regs->pwremu_mgmt);
+
puts("ddr init\n");
dm365_ddr_setup();
diff --git a/board/csb226/Makefile b/arch/arm/cpu/arm926ejs/mx28/Makefile
similarity index 86%
rename from board/csb226/Makefile
rename to arch/arm/cpu/arm926ejs/mx28/Makefile
index 6fe9bec..7845310 100644
--- a/board/csb226/Makefile
+++ b/arch/arm/cpu/arm926ejs/mx28/Makefile
@@ -23,14 +23,17 @@
include $(TOPDIR)/config.mk
-LIB = $(obj)lib$(BOARD).o
+LIB = $(obj)lib$(SOC).o
-COBJS := csb226.o flash.o
+COBJS = clock.o mx28.o iomux.o timer.o
-SRCS := $(COBJS:.o=.c)
+SRCS := $(START:.o=.S) $(COBJS:.o=.c)
OBJS := $(addprefix $(obj),$(COBJS))
+START := $(addprefix $(obj),$(START))
-$(LIB): $(obj).depend $(OBJS)
+all: $(obj).depend $(LIB)
+
+$(LIB): $(OBJS)
$(call cmd_link_o_target, $(OBJS))
#########################################################################
diff --git a/arch/arm/cpu/arm926ejs/mx28/clock.c b/arch/arm/cpu/arm926ejs/mx28/clock.c
new file mode 100644
index 0000000..f698506
--- /dev/null
+++ b/arch/arm/cpu/arm926ejs/mx28/clock.c
@@ -0,0 +1,355 @@
+/*
+ * Freescale i.MX28 clock setup code
+ *
+ * Copyright (C) 2011 Marek Vasut <marek.vasut@gmail.com>
+ * on behalf of DENX Software Engineering GmbH
+ *
+ * Based on code from LTIB:
+ * Copyright (C) 2010 Freescale Semiconductor, Inc.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <asm/errno.h>
+#include <asm/io.h>
+#include <asm/arch/clock.h>
+#include <asm/arch/imx-regs.h>
+
+/* The PLL frequency is always 480MHz, see section 10.2 in iMX28 datasheet. */
+#define PLL_FREQ_KHZ 480000
+#define PLL_FREQ_COEF 18
+/* The XTAL frequency is always 24MHz, see section 10.2 in iMX28 datasheet. */
+#define XTAL_FREQ_KHZ 24000
+
+#define PLL_FREQ_MHZ (PLL_FREQ_KHZ / 1000)
+#define XTAL_FREQ_MHZ (XTAL_FREQ_KHZ / 1000)
+
+static uint32_t mx28_get_pclk(void)
+{
+ struct mx28_clkctrl_regs *clkctrl_regs =
+ (struct mx28_clkctrl_regs *)MXS_CLKCTRL_BASE;
+
+ uint32_t clkctrl, clkseq, clkfrac;
+ uint32_t frac, div;
+
+ clkctrl = readl(&clkctrl_regs->hw_clkctrl_cpu);
+
+ /* No support of fractional divider calculation */
+ if (clkctrl &
+ (CLKCTRL_CPU_DIV_XTAL_FRAC_EN | CLKCTRL_CPU_DIV_CPU_FRAC_EN)) {
+ return 0;
+ }
+
+ clkseq = readl(&clkctrl_regs->hw_clkctrl_clkseq);
+
+ /* XTAL Path */
+ if (clkseq & CLKCTRL_CLKSEQ_BYPASS_CPU) {
+ div = (clkctrl & CLKCTRL_CPU_DIV_XTAL_MASK) >>
+ CLKCTRL_CPU_DIV_XTAL_OFFSET;
+ return XTAL_FREQ_MHZ / div;
+ }
+
+ /* REF Path */
+ clkfrac = readl(&clkctrl_regs->hw_clkctrl_frac0);
+ frac = clkfrac & CLKCTRL_FRAC0_CPUFRAC_MASK;
+ div = clkctrl & CLKCTRL_CPU_DIV_CPU_MASK;
+ return (PLL_FREQ_MHZ * PLL_FREQ_COEF / frac) / div;
+}
+
+static uint32_t mx28_get_hclk(void)
+{
+ struct mx28_clkctrl_regs *clkctrl_regs =
+ (struct mx28_clkctrl_regs *)MXS_CLKCTRL_BASE;
+
+ uint32_t div;
+ uint32_t clkctrl;
+
+ clkctrl = readl(&clkctrl_regs->hw_clkctrl_hbus);
+
+ /* No support of fractional divider calculation */
+ if (clkctrl & CLKCTRL_HBUS_DIV_FRAC_EN)
+ return 0;
+
+ div = clkctrl & CLKCTRL_HBUS_DIV_MASK;
+ return mx28_get_pclk() / div;
+}
+
+static uint32_t mx28_get_emiclk(void)
+{
+ struct mx28_clkctrl_regs *clkctrl_regs =
+ (struct mx28_clkctrl_regs *)MXS_CLKCTRL_BASE;
+
+ uint32_t frac, div;
+ uint32_t clkctrl, clkseq, clkfrac;
+
+ clkseq = readl(&clkctrl_regs->hw_clkctrl_clkseq);
+ clkctrl = readl(&clkctrl_regs->hw_clkctrl_emi);
+
+ /* XTAL Path */
+ if (clkseq & CLKCTRL_CLKSEQ_BYPASS_EMI) {
+ div = (clkctrl & CLKCTRL_EMI_DIV_XTAL_MASK) >>
+ CLKCTRL_EMI_DIV_XTAL_OFFSET;
+ return XTAL_FREQ_MHZ / div;
+ }
+
+ clkfrac = readl(&clkctrl_regs->hw_clkctrl_frac0);
+
+ /* REF Path */
+ frac = (clkfrac & CLKCTRL_FRAC0_EMIFRAC_MASK) >>
+ CLKCTRL_FRAC0_EMIFRAC_OFFSET;
+ div = clkctrl & CLKCTRL_EMI_DIV_EMI_MASK;
+ return (PLL_FREQ_MHZ * PLL_FREQ_COEF / frac) / div;
+}
+
+static uint32_t mx28_get_gpmiclk(void)
+{
+ struct mx28_clkctrl_regs *clkctrl_regs =
+ (struct mx28_clkctrl_regs *)MXS_CLKCTRL_BASE;
+
+ uint32_t frac, div;
+ uint32_t clkctrl, clkseq, clkfrac;
+
+ clkseq = readl(&clkctrl_regs->hw_clkctrl_clkseq);
+ clkctrl = readl(&clkctrl_regs->hw_clkctrl_gpmi);
+
+ /* XTAL Path */
+ if (clkseq & CLKCTRL_CLKSEQ_BYPASS_GPMI) {
+ div = clkctrl & CLKCTRL_GPMI_DIV_MASK;
+ return XTAL_FREQ_MHZ / div;
+ }
+
+ clkfrac = readl(&clkctrl_regs->hw_clkctrl_frac1);
+
+ /* REF Path */
+ frac = (clkfrac & CLKCTRL_FRAC1_GPMIFRAC_MASK) >>
+ CLKCTRL_FRAC1_GPMIFRAC_OFFSET;
+ div = clkctrl & CLKCTRL_GPMI_DIV_MASK;
+ return (PLL_FREQ_MHZ * PLL_FREQ_COEF / frac) / div;
+}
+
+/*
+ * Set IO clock frequency, in kHz
+ */
+void mx28_set_ioclk(enum mxs_ioclock io, uint32_t freq)
+{
+ struct mx28_clkctrl_regs *clkctrl_regs =
+ (struct mx28_clkctrl_regs *)MXS_CLKCTRL_BASE;
+ uint32_t div;
+
+ if (freq == 0)
+ return;
+
+ if (io > MXC_IOCLK1)
+ return;
+
+ div = (PLL_FREQ_KHZ * PLL_FREQ_COEF) / freq;
+
+ if (div < 18)
+ div = 18;
+
+ if (div > 35)
+ div = 35;
+
+ if (io == MXC_IOCLK0) {
+ writel(CLKCTRL_FRAC0_CLKGATEIO0,
+ &clkctrl_regs->hw_clkctrl_frac0_set);
+ clrsetbits_le32(&clkctrl_regs->hw_clkctrl_frac0,
+ CLKCTRL_FRAC0_IO0FRAC_MASK,
+ div << CLKCTRL_FRAC0_IO0FRAC_OFFSET);
+ writel(CLKCTRL_FRAC0_CLKGATEIO0,
+ &clkctrl_regs->hw_clkctrl_frac0_clr);
+ } else {
+ writel(CLKCTRL_FRAC0_CLKGATEIO1,
+ &clkctrl_regs->hw_clkctrl_frac0_set);
+ clrsetbits_le32(&clkctrl_regs->hw_clkctrl_frac0,
+ CLKCTRL_FRAC0_IO1FRAC_MASK,
+ div << CLKCTRL_FRAC0_IO1FRAC_OFFSET);
+ writel(CLKCTRL_FRAC0_CLKGATEIO1,
+ &clkctrl_regs->hw_clkctrl_frac0_clr);
+ }
+}
+
+/*
+ * Get IO clock, returns IO clock in kHz
+ */
+static uint32_t mx28_get_ioclk(enum mxs_ioclock io)
+{
+ struct mx28_clkctrl_regs *clkctrl_regs =
+ (struct mx28_clkctrl_regs *)MXS_CLKCTRL_BASE;
+ uint32_t tmp, ret;
+
+ if (io > MXC_IOCLK1)
+ return 0;
+
+ tmp = readl(&clkctrl_regs->hw_clkctrl_frac0);
+
+ if (io == MXC_IOCLK0)
+ ret = (tmp & CLKCTRL_FRAC0_IO0FRAC_MASK) >>
+ CLKCTRL_FRAC0_IO0FRAC_OFFSET;
+ else
+ ret = (tmp & CLKCTRL_FRAC0_IO1FRAC_MASK) >>
+ CLKCTRL_FRAC0_IO1FRAC_OFFSET;
+
+ return (PLL_FREQ_KHZ * PLL_FREQ_COEF) / ret;
+}
+
+/*
+ * Configure SSP clock frequency, in kHz
+ */
+void mx28_set_sspclk(enum mxs_sspclock ssp, uint32_t freq, int xtal)
+{
+ struct mx28_clkctrl_regs *clkctrl_regs =
+ (struct mx28_clkctrl_regs *)MXS_CLKCTRL_BASE;
+ uint32_t clk, clkreg;
+
+ if (ssp > MXC_SSPCLK3)
+ return;
+
+ clkreg = (uint32_t)(&clkctrl_regs->hw_clkctrl_ssp0) +
+ (ssp * sizeof(struct mx28_register));
+
+ clrbits_le32(clkreg, CLKCTRL_SSP_CLKGATE);
+ while (readl(clkreg) & CLKCTRL_SSP_CLKGATE)
+ ;
+
+ if (xtal)
+ clk = XTAL_FREQ_KHZ;
+ else
+ clk = mx28_get_ioclk(ssp >> 1);
+
+ if (freq > clk)
+ return;
+
+ /* Calculate the divider and cap it if necessary */
+ clk /= freq;
+ if (clk > CLKCTRL_SSP_DIV_MASK)
+ clk = CLKCTRL_SSP_DIV_MASK;
+
+ clrsetbits_le32(clkreg, CLKCTRL_SSP_DIV_MASK, clk);
+ while (readl(clkreg) & CLKCTRL_SSP_BUSY)
+ ;
+
+ if (xtal)
+ writel(CLKCTRL_CLKSEQ_BYPASS_SSP0 << ssp,
+ &clkctrl_regs->hw_clkctrl_clkseq_set);
+ else
+ writel(CLKCTRL_CLKSEQ_BYPASS_SSP0 << ssp,
+ &clkctrl_regs->hw_clkctrl_clkseq_clr);
+}
+
+/*
+ * Return SSP frequency, in kHz
+ */
+static uint32_t mx28_get_sspclk(enum mxs_sspclock ssp)
+{
+ struct mx28_clkctrl_regs *clkctrl_regs =
+ (struct mx28_clkctrl_regs *)MXS_CLKCTRL_BASE;
+ uint32_t clkreg;
+ uint32_t clk, tmp;
+
+ if (ssp > MXC_SSPCLK3)
+ return 0;
+
+ tmp = readl(&clkctrl_regs->hw_clkctrl_clkseq);
+ if (tmp & (CLKCTRL_CLKSEQ_BYPASS_SSP0 << ssp))
+ return XTAL_FREQ_KHZ;
+
+ clkreg = (uint32_t)(&clkctrl_regs->hw_clkctrl_ssp0) +
+ (ssp * sizeof(struct mx28_register));
+
+ tmp = readl(clkreg) & CLKCTRL_SSP_DIV_MASK;
+
+ if (tmp == 0)
+ return 0;
+
+ clk = mx28_get_ioclk(ssp >> 1);
+
+ return clk / tmp;
+}
+
+/*
+ * Set SSP/MMC bus frequency, in kHz)
+ */
+void mx28_set_ssp_busclock(unsigned int bus, uint32_t freq)
+{
+ struct mx28_ssp_regs *ssp_regs;
+ const uint32_t sspclk = mx28_get_sspclk(bus);
+ uint32_t reg;
+ uint32_t divide, rate, tgtclk;
+
+ ssp_regs = (struct mx28_ssp_regs *)(MXS_SSP0_BASE + (bus * 0x2000));
+
+ /*
+ * SSP bit rate = SSPCLK / (CLOCK_DIVIDE * (1 + CLOCK_RATE)),
+ * CLOCK_DIVIDE has to be an even value from 2 to 254, and
+ * CLOCK_RATE could be any integer from 0 to 255.
+ */
+ for (divide = 2; divide < 254; divide += 2) {
+ rate = sspclk / freq / divide;
+ if (rate <= 256)
+ break;
+ }
+
+ tgtclk = sspclk / divide / rate;
+ while (tgtclk > freq) {
+ rate++;
+ tgtclk = sspclk / divide / rate;
+ }
+ if (rate > 256)
+ rate = 256;
+
+ /* Always set timeout the maximum */
+ reg = SSP_TIMING_TIMEOUT_MASK |
+ (divide << SSP_TIMING_CLOCK_DIVIDE_OFFSET) |
+ ((rate - 1) << SSP_TIMING_CLOCK_RATE_OFFSET);
+ writel(reg, &ssp_regs->hw_ssp_timing);
+
+ debug("SPI%d: Set freq rate to %d KHz (requested %d KHz)\n",
+ bus, tgtclk, freq);
+}
+
+uint32_t mxc_get_clock(enum mxc_clock clk)
+{
+ switch (clk) {
+ case MXC_ARM_CLK:
+ return mx28_get_pclk() * 1000000;
+ case MXC_GPMI_CLK:
+ return mx28_get_gpmiclk() * 1000000;
+ case MXC_AHB_CLK:
+ case MXC_IPG_CLK:
+ return mx28_get_hclk() * 1000000;
+ case MXC_EMI_CLK:
+ return mx28_get_emiclk();
+ case MXC_IO0_CLK:
+ return mx28_get_ioclk(MXC_IOCLK0);
+ case MXC_IO1_CLK:
+ return mx28_get_ioclk(MXC_IOCLK1);
+ case MXC_SSP0_CLK:
+ return mx28_get_sspclk(MXC_SSPCLK0);
+ case MXC_SSP1_CLK:
+ return mx28_get_sspclk(MXC_SSPCLK1);
+ case MXC_SSP2_CLK:
+ return mx28_get_sspclk(MXC_SSPCLK2);
+ case MXC_SSP3_CLK:
+ return mx28_get_sspclk(MXC_SSPCLK3);
+ }
+
+ return 0;
+}
diff --git a/arch/arm/cpu/arm926ejs/mx28/iomux.c b/arch/arm/cpu/arm926ejs/mx28/iomux.c
new file mode 100644
index 0000000..9ea411f
--- /dev/null
+++ b/arch/arm/cpu/arm926ejs/mx28/iomux.c
@@ -0,0 +1,109 @@
+/*
+ * Copyright 2004-2006,2010 Freescale Semiconductor, Inc. All Rights Reserved.
+ * Copyright (C) 2008 by Sascha Hauer <kernel@pengutronix.de>
+ * Copyright (C) 2009 by Jan Weitzel Phytec Messtechnik GmbH,
+ * <armlinux@phytec.de>
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * as published by the Free Software Foundation; either version 2
+ * of the License, or (at your option) any later version.
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
+ * MA 02110-1301, USA.
+ */
+
+#include <common.h>
+#include <asm/errno.h>
+#include <asm/io.h>
+#include <asm/arch/clock.h>
+#include <asm/arch/iomux.h>
+#include <asm/arch/imx-regs.h>
+
+#if defined(CONFIG_MX23)
+#define DRIVE_OFFSET 0x200
+#define PULL_OFFSET 0x400
+#elif defined(CONFIG_MX28)
+#define DRIVE_OFFSET 0x300
+#define PULL_OFFSET 0x600
+#else
+#error "Please select CONFIG_MX23 or CONFIG_MX28"
+#endif
+
+/*
+ * configures a single pad in the iomuxer
+ */
+int mxs_iomux_setup_pad(iomux_cfg_t pad)
+{
+ u32 reg, ofs, bp, bm;
+ void *iomux_base = (void *)MXS_PINCTRL_BASE;
+ struct mx28_register *mxs_reg;
+
+ /* muxsel */
+ ofs = 0x100;
+ ofs += PAD_BANK(pad) * 0x20 + PAD_PIN(pad) / 16 * 0x10;
+ bp = PAD_PIN(pad) % 16 * 2;
+ bm = 0x3 << bp;
+ reg = readl(iomux_base + ofs);
+ reg &= ~bm;
+ reg |= PAD_MUXSEL(pad) << bp;
+ writel(reg, iomux_base + ofs);
+
+ /* drive */
+ ofs = DRIVE_OFFSET;
+ ofs += PAD_BANK(pad) * 0x40 + PAD_PIN(pad) / 8 * 0x10;
+ /* mA */
+ if (PAD_MA_VALID(pad)) {
+ bp = PAD_PIN(pad) % 8 * 4;
+ bm = 0x3 << bp;
+ reg = readl(iomux_base + ofs);
+ reg &= ~bm;
+ reg |= PAD_MA(pad) << bp;
+ writel(reg, iomux_base + ofs);
+ }
+ /* vol */
+ if (PAD_VOL_VALID(pad)) {
+ bp = PAD_PIN(pad) % 8 * 4 + 2;
+ mxs_reg = (struct mx28_register *)(iomux_base + ofs);
+ if (PAD_VOL(pad))
+ writel(1 << bp, &mxs_reg->reg_set);
+ else
+ writel(1 << bp, &mxs_reg->reg_clr);
+ }
+
+ /* pull */
+ if (PAD_PULL_VALID(pad)) {
+ ofs = PULL_OFFSET;
+ ofs += PAD_BANK(pad) * 0x10;
+ bp = PAD_PIN(pad);
+ mxs_reg = (struct mx28_register *)(iomux_base + ofs);
+ if (PAD_PULL(pad))
+ writel(1 << bp, &mxs_reg->reg_set);
+ else
+ writel(1 << bp, &mxs_reg->reg_clr);
+ }
+
+ return 0;
+}
+
+int mxs_iomux_setup_multiple_pads(const iomux_cfg_t *pad_list, unsigned count)
+{
+ const iomux_cfg_t *p = pad_list;
+ int i;
+ int ret;
+
+ for (i = 0; i < count; i++) {
+ ret = mxs_iomux_setup_pad(*p);
+ if (ret)
+ return ret;
+ p++;
+ }
+
+ return 0;
+}
diff --git a/arch/arm/cpu/arm926ejs/mx28/mx28.c b/arch/arm/cpu/arm926ejs/mx28/mx28.c
new file mode 100644
index 0000000..088c019
--- /dev/null
+++ b/arch/arm/cpu/arm926ejs/mx28/mx28.c
@@ -0,0 +1,221 @@
+/*
+ * Freescale i.MX28 common code
+ *
+ * Copyright (C) 2011 Marek Vasut <marek.vasut@gmail.com>
+ * on behalf of DENX Software Engineering GmbH
+ *
+ * Based on code from LTIB:
+ * Copyright (C) 2010 Freescale Semiconductor, Inc.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <asm/errno.h>
+#include <asm/io.h>
+#include <asm/arch/clock.h>
+#include <asm/arch/gpio.h>
+#include <asm/arch/iomux.h>
+#include <asm/arch/imx-regs.h>
+#include <asm/arch/sys_proto.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+/* 1 second delay should be plenty of time for block reset. */
+#define RESET_MAX_TIMEOUT 1000000
+
+#define MX28_BLOCK_SFTRST (1 << 31)
+#define MX28_BLOCK_CLKGATE (1 << 30)
+
+/* Lowlevel init isn't used on i.MX28, so just have a dummy here */
+inline void lowlevel_init(void) {}
+
+void reset_cpu(ulong ignored) __attribute__((noreturn));
+
+void reset_cpu(ulong ignored)
+{
+
+ struct mx28_rtc_regs *rtc_regs =
+ (struct mx28_rtc_regs *)MXS_RTC_BASE;
+
+ /* Wait 1 uS before doing the actual watchdog reset */
+ writel(1, &rtc_regs->hw_rtc_watchdog);
+ writel(RTC_CTRL_WATCHDOGEN, &rtc_regs->hw_rtc_ctrl_set);
+
+ /* Endless loop, reset will exit from here */
+ for (;;)
+ ;
+}
+
+int mx28_wait_mask_set(struct mx28_register *reg, uint32_t mask, int timeout)
+{
+ while (--timeout) {
+ if ((readl(®->reg) & mask) == mask)
+ break;
+ udelay(1);
+ }
+
+ return !timeout;
+}
+
+int mx28_wait_mask_clr(struct mx28_register *reg, uint32_t mask, int timeout)
+{
+ while (--timeout) {
+ if ((readl(®->reg) & mask) == 0)
+ break;
+ udelay(1);
+ }
+
+ return !timeout;
+}
+
+int mx28_reset_block(struct mx28_register *reg)
+{
+ /* Clear SFTRST */
+ writel(MX28_BLOCK_SFTRST, ®->reg_clr);
+
+ if (mx28_wait_mask_clr(reg, MX28_BLOCK_SFTRST, RESET_MAX_TIMEOUT))
+ return 1;
+
+ /* Clear CLKGATE */
+ writel(MX28_BLOCK_CLKGATE, ®->reg_clr);
+
+ /* Set SFTRST */
+ writel(MX28_BLOCK_SFTRST, ®->reg_set);
+
+ /* Wait for CLKGATE being set */
+ if (mx28_wait_mask_set(reg, MX28_BLOCK_CLKGATE, RESET_MAX_TIMEOUT))
+ return 1;
+
+ /* Clear SFTRST */
+ writel(MX28_BLOCK_SFTRST, ®->reg_clr);
+
+ if (mx28_wait_mask_clr(reg, MX28_BLOCK_SFTRST, RESET_MAX_TIMEOUT))
+ return 1;
+
+ /* Clear CLKGATE */
+ writel(MX28_BLOCK_CLKGATE, ®->reg_clr);
+
+ if (mx28_wait_mask_clr(reg, MX28_BLOCK_CLKGATE, RESET_MAX_TIMEOUT))
+ return 1;
+
+ return 0;
+}
+
+void mx28_fixup_vt(uint32_t start_addr)
+{
+ uint32_t *vt = (uint32_t *)0x20;
+ int i;
+
+ for (i = 0; i < 8; i++)
+ vt[i] = start_addr + (4 * i);
+}
+
+#ifdef CONFIG_ARCH_MISC_INIT
+int arch_misc_init(void)
+{
+ mx28_fixup_vt(gd->relocaddr);
+ return 0;
+}
+#endif
+
+#ifdef CONFIG_ARCH_CPU_INIT
+int arch_cpu_init(void)
+{
+ struct mx28_clkctrl_regs *clkctrl_regs =
+ (struct mx28_clkctrl_regs *)MXS_CLKCTRL_BASE;
+ extern uint32_t _start;
+
+ mx28_fixup_vt((uint32_t)&_start);
+
+ /*
+ * Enable NAND clock
+ */
+ /* Clear bypass bit */
+ writel(CLKCTRL_CLKSEQ_BYPASS_GPMI,
+ &clkctrl_regs->hw_clkctrl_clkseq_set);
+
+ /* Set GPMI clock to ref_gpmi / 12 */
+ clrsetbits_le32(&clkctrl_regs->hw_clkctrl_gpmi,
+ CLKCTRL_GPMI_CLKGATE | CLKCTRL_GPMI_DIV_MASK, 1);
+
+ udelay(1000);
+
+ /*
+ * Configure GPIO unit
+ */
+ mxs_gpio_init();
+
+ return 0;
+}
+#endif
+
+#if defined(CONFIG_DISPLAY_CPUINFO)
+int print_cpuinfo(void)
+{
+ printf("Freescale i.MX28 family\n");
+ return 0;
+}
+#endif
+
+int do_mx28_showclocks(cmd_tbl_t *cmdtp, int flag, int argc, char *const argv[])
+{
+ printf("CPU: %3d MHz\n", mxc_get_clock(MXC_ARM_CLK) / 1000000);
+ printf("BUS: %3d MHz\n", mxc_get_clock(MXC_AHB_CLK) / 1000000);
+ printf("EMI: %3d MHz\n", mxc_get_clock(MXC_EMI_CLK));
+ printf("GPMI: %3d MHz\n", mxc_get_clock(MXC_GPMI_CLK) / 1000000);
+ return 0;
+}
+
+/*
+ * Initializes on-chip ethernet controllers.
+ */
+#ifdef CONFIG_CMD_NET
+int cpu_eth_init(bd_t *bis)
+{
+ struct mx28_clkctrl_regs *clkctrl_regs =
+ (struct mx28_clkctrl_regs *)MXS_CLKCTRL_BASE;
+
+ /* Turn on ENET clocks */
+ clrbits_le32(&clkctrl_regs->hw_clkctrl_enet,
+ CLKCTRL_ENET_SLEEP | CLKCTRL_ENET_DISABLE);
+
+ /* Set up ENET PLL for 50 MHz */
+ /* Power on ENET PLL */
+ writel(CLKCTRL_PLL2CTRL0_POWER,
+ &clkctrl_regs->hw_clkctrl_pll2ctrl0_set);
+
+ udelay(10);
+
+ /* Gate on ENET PLL */
+ writel(CLKCTRL_PLL2CTRL0_CLKGATE,
+ &clkctrl_regs->hw_clkctrl_pll2ctrl0_clr);
+
+ /* Enable pad output */
+ setbits_le32(&clkctrl_regs->hw_clkctrl_enet, CLKCTRL_ENET_CLK_OUT_EN);
+
+ return 0;
+}
+#endif
+
+U_BOOT_CMD(
+ clocks, CONFIG_SYS_MAXARGS, 1, do_mx28_showclocks,
+ "display clocks",
+ ""
+);
diff --git a/arch/arm/cpu/arm926ejs/mx28/timer.c b/arch/arm/cpu/arm926ejs/mx28/timer.c
new file mode 100644
index 0000000..dbc904d
--- /dev/null
+++ b/arch/arm/cpu/arm926ejs/mx28/timer.c
@@ -0,0 +1,141 @@
+/*
+ * Freescale i.MX28 timer driver
+ *
+ * Copyright (C) 2011 Marek Vasut <marek.vasut@gmail.com>
+ * on behalf of DENX Software Engineering GmbH
+ *
+ * Based on code from LTIB:
+ * (C) Copyright 2009-2010 Freescale Semiconductor, Inc.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <asm/io.h>
+#include <asm/arch/imx-regs.h>
+#include <asm/arch/sys_proto.h>
+
+/* Maximum fixed count */
+#define TIMER_LOAD_VAL 0xffffffff
+
+DECLARE_GLOBAL_DATA_PTR;
+
+#define timestamp (gd->tbl)
+#define lastdec (gd->lastinc)
+
+/*
+ * This driver uses 1kHz clock source.
+ */
+#define MX28_INCREMENTER_HZ 1000
+
+static inline unsigned long tick_to_time(unsigned long tick)
+{
+ return tick / (MX28_INCREMENTER_HZ / CONFIG_SYS_HZ);
+}
+
+static inline unsigned long time_to_tick(unsigned long time)
+{
+ return time * (MX28_INCREMENTER_HZ / CONFIG_SYS_HZ);
+}
+
+/* Calculate how many ticks happen in "us" microseconds */
+static inline unsigned long us_to_tick(unsigned long us)
+{
+ return (us * MX28_INCREMENTER_HZ) / 1000000;
+}
+
+int timer_init(void)
+{
+ struct mx28_timrot_regs *timrot_regs =
+ (struct mx28_timrot_regs *)MXS_TIMROT_BASE;
+
+ /* Reset Timers and Rotary Encoder module */
+ mx28_reset_block(&timrot_regs->hw_timrot_rotctrl_reg);
+
+ /* Set fixed_count to 0 */
+ writel(0, &timrot_regs->hw_timrot_fixed_count0);
+
+ /* Set UPDATE bit and 1Khz frequency */
+ writel(TIMROT_TIMCTRLn_UPDATE | TIMROT_TIMCTRLn_RELOAD |
+ TIMROT_TIMCTRLn_SELECT_1KHZ_XTAL,
+ &timrot_regs->hw_timrot_timctrl0);
+
+ /* Set fixed_count to maximal value */
+ writel(TIMER_LOAD_VAL, &timrot_regs->hw_timrot_fixed_count0);
+
+ return 0;
+}
+
+ulong get_timer(ulong base)
+{
+ struct mx28_timrot_regs *timrot_regs =
+ (struct mx28_timrot_regs *)MXS_TIMROT_BASE;
+
+ /* Current tick value */
+ uint32_t now = readl(&timrot_regs->hw_timrot_running_count0);
+
+ if (lastdec >= now) {
+ /*
+ * normal mode (non roll)
+ * move stamp forward with absolut diff ticks
+ */
+ timestamp += (lastdec - now);
+ } else {
+ /* we have rollover of decrementer */
+ timestamp += (TIMER_LOAD_VAL - now) + lastdec;
+
+ }
+ lastdec = now;
+
+ return tick_to_time(timestamp) - base;
+}
+
+/* We use the HW_DIGCTL_MICROSECONDS register for sub-millisecond timer. */
+#define MX28_HW_DIGCTL_MICROSECONDS 0x8001c0c0
+
+void __udelay(unsigned long usec)
+{
+ uint32_t old, new, incr;
+ uint32_t counter = 0;
+
+ old = readl(MX28_HW_DIGCTL_MICROSECONDS);
+
+ while (counter < usec) {
+ new = readl(MX28_HW_DIGCTL_MICROSECONDS);
+
+ /* Check if the timer wrapped. */
+ if (new < old) {
+ incr = 0xffffffff - old;
+ incr += new;
+ } else {
+ incr = new - old;
+ }
+
+ /*
+ * Check if we are close to the maximum time and the counter
+ * would wrap if incremented. If that's the case, break out
+ * from the loop as the requested delay time passed.
+ */
+ if (counter + incr < counter)
+ break;
+
+ counter += incr;
+ old = new;
+ }
+}
diff --git a/arch/arm/cpu/armv7/omap-common/Makefile b/arch/arm/cpu/armv7/omap-common/Makefile
index 1dee81f..a684611 100644
--- a/arch/arm/cpu/armv7/omap-common/Makefile
+++ b/arch/arm/cpu/armv7/omap-common/Makefile
@@ -33,6 +33,13 @@
COBJS += gpio.o
endif
+ifneq ($(CONFIG_OMAP44XX)$(CONFIG_OMAP54XX),)
+COBJS += hwinit-common.o
+COBJS += clocks-common.o
+COBJS += emif-common.o
+SOBJS += lowlevel_init.o
+endif
+
ifdef CONFIG_SPL_BUILD
COBJS += spl.o
ifdef CONFIG_SPL_NAND_SUPPORT
@@ -43,6 +50,12 @@
endif
endif
+ifndef CONFIG_SPL_BUILD
+ifneq ($(CONFIG_OMAP44XX)$(CONFIG_OMAP54XX),)
+COBJS += mem-common.o
+endif
+endif
+
SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c)
OBJS := $(addprefix $(obj),$(SOBJS) $(COBJS))
diff --git a/arch/arm/cpu/armv7/omap-common/clocks-common.c b/arch/arm/cpu/armv7/omap-common/clocks-common.c
new file mode 100644
index 0000000..f64a10b
--- /dev/null
+++ b/arch/arm/cpu/armv7/omap-common/clocks-common.c
@@ -0,0 +1,609 @@
+/*
+ *
+ * Clock initialization for OMAP4
+ *
+ * (C) Copyright 2010
+ * Texas Instruments, <www.ti.com>
+ *
+ * Aneesh V <aneesh@ti.com>
+ *
+ * Based on previous work by:
+ * Santosh Shilimkar <santosh.shilimkar@ti.com>
+ * Rajendra Nayak <rnayak@ti.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+#include <common.h>
+#include <asm/omap_common.h>
+#include <asm/gpio.h>
+#include <asm/arch/clocks.h>
+#include <asm/arch/sys_proto.h>
+#include <asm/utils.h>
+#include <asm/omap_gpio.h>
+
+#ifndef CONFIG_SPL_BUILD
+/*
+ * printing to console doesn't work unless
+ * this code is executed from SPL
+ */
+#define printf(fmt, args...)
+#define puts(s)
+#endif
+
+static inline u32 __get_sys_clk_index(void)
+{
+ u32 ind;
+ /*
+ * For ES1 the ROM code calibration of sys clock is not reliable
+ * due to hw issue. So, use hard-coded value. If this value is not
+ * correct for any board over-ride this function in board file
+ * From ES2.0 onwards you will get this information from
+ * CM_SYS_CLKSEL
+ */
+ if (omap_revision() == OMAP4430_ES1_0)
+ ind = OMAP_SYS_CLK_IND_38_4_MHZ;
+ else {
+ /* SYS_CLKSEL - 1 to match the dpll param array indices */
+ ind = (readl(&prcm->cm_sys_clksel) &
+ CM_SYS_CLKSEL_SYS_CLKSEL_MASK) - 1;
+ }
+ return ind;
+}
+
+u32 get_sys_clk_index(void)
+ __attribute__ ((weak, alias("__get_sys_clk_index")));
+
+u32 get_sys_clk_freq(void)
+{
+ u8 index = get_sys_clk_index();
+ return sys_clk_array[index];
+}
+
+static inline void do_bypass_dpll(u32 *const base)
+{
+ struct dpll_regs *dpll_regs = (struct dpll_regs *)base;
+
+ clrsetbits_le32(&dpll_regs->cm_clkmode_dpll,
+ CM_CLKMODE_DPLL_DPLL_EN_MASK,
+ DPLL_EN_FAST_RELOCK_BYPASS <<
+ CM_CLKMODE_DPLL_EN_SHIFT);
+}
+
+static inline void wait_for_bypass(u32 *const base)
+{
+ struct dpll_regs *const dpll_regs = (struct dpll_regs *)base;
+
+ if (!wait_on_value(ST_DPLL_CLK_MASK, 0, &dpll_regs->cm_idlest_dpll,
+ LDELAY)) {
+ printf("Bypassing DPLL failed %p\n", base);
+ }
+}
+
+static inline void do_lock_dpll(u32 *const base)
+{
+ struct dpll_regs *const dpll_regs = (struct dpll_regs *)base;
+
+ clrsetbits_le32(&dpll_regs->cm_clkmode_dpll,
+ CM_CLKMODE_DPLL_DPLL_EN_MASK,
+ DPLL_EN_LOCK << CM_CLKMODE_DPLL_EN_SHIFT);
+}
+
+static inline void wait_for_lock(u32 *const base)
+{
+ struct dpll_regs *const dpll_regs = (struct dpll_regs *)base;
+
+ if (!wait_on_value(ST_DPLL_CLK_MASK, ST_DPLL_CLK_MASK,
+ &dpll_regs->cm_idlest_dpll, LDELAY)) {
+ printf("DPLL locking failed for %p\n", base);
+ hang();
+ }
+}
+
+inline u32 check_for_lock(u32 *const base)
+{
+ struct dpll_regs *const dpll_regs = (struct dpll_regs *)base;
+ u32 lock = readl(&dpll_regs->cm_idlest_dpll) & ST_DPLL_CLK_MASK;
+
+ return lock;
+}
+
+static void do_setup_dpll(u32 *const base, const struct dpll_params *params,
+ u8 lock, char *dpll)
+{
+ u32 temp, M, N;
+ struct dpll_regs *const dpll_regs = (struct dpll_regs *)base;
+
+ temp = readl(&dpll_regs->cm_clksel_dpll);
+
+ if (check_for_lock(base)) {
+ /*
+ * The Dpll has already been locked by rom code using CH.
+ * Check if M,N are matching with Ideal nominal opp values.
+ * If matches, skip the rest otherwise relock.
+ */
+ M = (temp & CM_CLKSEL_DPLL_M_MASK) >> CM_CLKSEL_DPLL_M_SHIFT;
+ N = (temp & CM_CLKSEL_DPLL_N_MASK) >> CM_CLKSEL_DPLL_N_SHIFT;
+ if ((M != (params->m)) || (N != (params->n))) {
+ debug("\n %s Dpll locked, but not for ideal M = %d,"
+ "N = %d values, current values are M = %d,"
+ "N= %d" , dpll, params->m, params->n,
+ M, N);
+ } else {
+ /* Dpll locked with ideal values for nominal opps. */
+ debug("\n %s Dpll already locked with ideal"
+ "nominal opp values", dpll);
+ goto setup_post_dividers;
+ }
+ }
+
+ bypass_dpll(base);
+
+ /* Set M & N */
+ temp &= ~CM_CLKSEL_DPLL_M_MASK;
+ temp |= (params->m << CM_CLKSEL_DPLL_M_SHIFT) & CM_CLKSEL_DPLL_M_MASK;
+
+ temp &= ~CM_CLKSEL_DPLL_N_MASK;
+ temp |= (params->n << CM_CLKSEL_DPLL_N_SHIFT) & CM_CLKSEL_DPLL_N_MASK;
+
+ writel(temp, &dpll_regs->cm_clksel_dpll);
+
+ /* Lock */
+ if (lock)
+ do_lock_dpll(base);
+
+setup_post_dividers:
+ setup_post_dividers(base, params);
+
+ /* Wait till the DPLL locks */
+ if (lock)
+ wait_for_lock(base);
+}
+
+u32 omap_ddr_clk(void)
+{
+ u32 ddr_clk, sys_clk_khz, omap_rev, divider;
+ const struct dpll_params *core_dpll_params;
+
+ omap_rev = omap_revision();
+ sys_clk_khz = get_sys_clk_freq() / 1000;
+
+ core_dpll_params = get_core_dpll_params();
+
+ debug("sys_clk %d\n ", sys_clk_khz * 1000);
+
+ /* Find Core DPLL locked frequency first */
+ ddr_clk = sys_clk_khz * 2 * core_dpll_params->m /
+ (core_dpll_params->n + 1);
+
+ if (omap_rev < OMAP5430_ES1_0) {
+ /*
+ * DDR frequency is PHY_ROOT_CLK/2
+ * PHY_ROOT_CLK = Fdpll/2/M2
+ */
+ divider = 4;
+ } else {
+ /*
+ * DDR frequency is PHY_ROOT_CLK
+ * PHY_ROOT_CLK = Fdpll/2/M2
+ */
+ divider = 2;
+ }
+
+ ddr_clk = ddr_clk / divider / core_dpll_params->m2;
+ ddr_clk *= 1000; /* convert to Hz */
+ debug("ddr_clk %d\n ", ddr_clk);
+
+ return ddr_clk;
+}
+
+/*
+ * Lock MPU dpll
+ *
+ * Resulting MPU frequencies:
+ * 4430 ES1.0 : 600 MHz
+ * 4430 ES2.x : 792 MHz (OPP Turbo)
+ * 4460 : 920 MHz (OPP Turbo) - DCC disabled
+ */
+void configure_mpu_dpll(void)
+{
+ const struct dpll_params *params;
+ struct dpll_regs *mpu_dpll_regs;
+ u32 omap_rev;
+ omap_rev = omap_revision();
+
+ /*
+ * DCC and clock divider settings for 4460.
+ * DCC is required, if more than a certain frequency is required.
+ * For, 4460 > 1GHZ.
+ * 5430 > 1.4GHZ.
+ */
+ if ((omap_rev >= OMAP4460_ES1_0) && (omap_rev < OMAP5430_ES1_0)) {
+ mpu_dpll_regs =
+ (struct dpll_regs *)&prcm->cm_clkmode_dpll_mpu;
+ bypass_dpll(&prcm->cm_clkmode_dpll_mpu);
+ clrbits_le32(&prcm->cm_mpu_mpu_clkctrl,
+ MPU_CLKCTRL_CLKSEL_EMIF_DIV_MODE_MASK);
+ setbits_le32(&prcm->cm_mpu_mpu_clkctrl,
+ MPU_CLKCTRL_CLKSEL_ABE_DIV_MODE_MASK);
+ clrbits_le32(&mpu_dpll_regs->cm_clksel_dpll,
+ CM_CLKSEL_DCC_EN_MASK);
+ }
+
+ params = get_mpu_dpll_params();
+
+ do_setup_dpll(&prcm->cm_clkmode_dpll_mpu, params, DPLL_LOCK, "mpu");
+ debug("MPU DPLL locked\n");
+}
+
+static void setup_dplls(void)
+{
+ u32 sysclk_ind, temp;
+ const struct dpll_params *params;
+ debug("setup_dplls\n");
+
+ sysclk_ind = get_sys_clk_index();
+
+ /* CORE dpll */
+ params = get_core_dpll_params(); /* default - safest */
+ /*
+ * Do not lock the core DPLL now. Just set it up.
+ * Core DPLL will be locked after setting up EMIF
+ * using the FREQ_UPDATE method(freq_update_core())
+ */
+ do_setup_dpll(&prcm->cm_clkmode_dpll_core, params, DPLL_NO_LOCK,
+ "core");
+ /* Set the ratios for CORE_CLK, L3_CLK, L4_CLK */
+ temp = (CLKSEL_CORE_X2_DIV_1 << CLKSEL_CORE_SHIFT) |
+ (CLKSEL_L3_CORE_DIV_2 << CLKSEL_L3_SHIFT) |
+ (CLKSEL_L4_L3_DIV_2 << CLKSEL_L4_SHIFT);
+ writel(temp, &prcm->cm_clksel_core);
+ debug("Core DPLL configured\n");
+
+ /* lock PER dpll */
+ params = get_per_dpll_params();
+ do_setup_dpll(&prcm->cm_clkmode_dpll_per,
+ params, DPLL_LOCK, "per");
+ debug("PER DPLL locked\n");
+
+ /* MPU dpll */
+ configure_mpu_dpll();
+}
+
+#ifdef CONFIG_SYS_CLOCKS_ENABLE_ALL
+static void setup_non_essential_dplls(void)
+{
+ u32 sys_clk_khz, abe_ref_clk;
+ u32 sysclk_ind, sd_div, num, den;
+ const struct dpll_params *params;
+
+ sysclk_ind = get_sys_clk_index();
+ sys_clk_khz = get_sys_clk_freq() / 1000;
+
+ /* IVA */
+ clrsetbits_le32(&prcm->cm_bypclk_dpll_iva,
+ CM_BYPCLK_DPLL_IVA_CLKSEL_MASK, DPLL_IVA_CLKSEL_CORE_X2_DIV_2);
+
+ params = get_iva_dpll_params();
+ do_setup_dpll(&prcm->cm_clkmode_dpll_iva, params, DPLL_LOCK, "iva");
+
+ /*
+ * USB:
+ * USB dpll is J-type. Need to set DPLL_SD_DIV for jitter correction
+ * DPLL_SD_DIV = CEILING ([DPLL_MULT/(DPLL_DIV+1)]* CLKINP / 250)
+ * - where CLKINP is sys_clk in MHz
+ * Use CLKINP in KHz and adjust the denominator accordingly so
+ * that we have enough accuracy and at the same time no overflow
+ */
+ params = get_usb_dpll_params();
+ num = params->m * sys_clk_khz;
+ den = (params->n + 1) * 250 * 1000;
+ num += den - 1;
+ sd_div = num / den;
+ clrsetbits_le32(&prcm->cm_clksel_dpll_usb,
+ CM_CLKSEL_DPLL_DPLL_SD_DIV_MASK,
+ sd_div << CM_CLKSEL_DPLL_DPLL_SD_DIV_SHIFT);
+
+ /* Now setup the dpll with the regular function */
+ do_setup_dpll(&prcm->cm_clkmode_dpll_usb, params, DPLL_LOCK, "usb");
+
+ /* Configure ABE dpll */
+ params = get_abe_dpll_params();
+#ifdef CONFIG_SYS_OMAP_ABE_SYSCK
+ abe_ref_clk = CM_ABE_PLL_REF_CLKSEL_CLKSEL_SYSCLK;
+#else
+ abe_ref_clk = CM_ABE_PLL_REF_CLKSEL_CLKSEL_32KCLK;
+ /*
+ * We need to enable some additional options to achieve
+ * 196.608MHz from 32768 Hz
+ */
+ setbits_le32(&prcm->cm_clkmode_dpll_abe,
+ CM_CLKMODE_DPLL_DRIFTGUARD_EN_MASK|
+ CM_CLKMODE_DPLL_RELOCK_RAMP_EN_MASK|
+ CM_CLKMODE_DPLL_LPMODE_EN_MASK|
+ CM_CLKMODE_DPLL_REGM4XEN_MASK);
+ /* Spend 4 REFCLK cycles at each stage */
+ clrsetbits_le32(&prcm->cm_clkmode_dpll_abe,
+ CM_CLKMODE_DPLL_RAMP_RATE_MASK,
+ 1 << CM_CLKMODE_DPLL_RAMP_RATE_SHIFT);
+#endif
+
+ /* Select the right reference clk */
+ clrsetbits_le32(&prcm->cm_abe_pll_ref_clksel,
+ CM_ABE_PLL_REF_CLKSEL_CLKSEL_MASK,
+ abe_ref_clk << CM_ABE_PLL_REF_CLKSEL_CLKSEL_SHIFT);
+ /* Lock the dpll */
+ do_setup_dpll(&prcm->cm_clkmode_dpll_abe, params, DPLL_LOCK, "abe");
+}
+#endif
+
+void do_scale_tps62361(u32 reg, u32 volt_mv)
+{
+ u32 temp, step;
+
+ step = volt_mv - TPS62361_BASE_VOLT_MV;
+ step /= 10;
+
+ /*
+ * Select SET1 in TPS62361:
+ * VSEL1 is grounded on board. So the following selects
+ * VSEL1 = 0 and VSEL0 = 1
+ */
+ gpio_direction_output(TPS62361_VSEL0_GPIO, 0);
+ gpio_set_value(TPS62361_VSEL0_GPIO, 1);
+
+ temp = TPS62361_I2C_SLAVE_ADDR |
+ (reg << PRM_VC_VAL_BYPASS_REGADDR_SHIFT) |
+ (step << PRM_VC_VAL_BYPASS_DATA_SHIFT) |
+ PRM_VC_VAL_BYPASS_VALID_BIT;
+ debug("do_scale_tps62361: volt - %d step - 0x%x\n", volt_mv, step);
+
+ writel(temp, &prcm->prm_vc_val_bypass);
+ if (!wait_on_value(PRM_VC_VAL_BYPASS_VALID_BIT, 0,
+ &prcm->prm_vc_val_bypass, LDELAY)) {
+ puts("Scaling voltage failed for vdd_mpu from TPS\n");
+ }
+}
+
+void do_scale_vcore(u32 vcore_reg, u32 volt_mv)
+{
+ u32 temp, offset_code;
+ u32 step = 12660; /* 12.66 mV represented in uV */
+ u32 offset = volt_mv;
+
+ /* convert to uV for better accuracy in the calculations */
+ offset *= 1000;
+
+ if (omap_revision() == OMAP4430_ES1_0)
+ offset -= PHOENIX_SMPS_BASE_VOLT_STD_MODE_UV;
+ else
+ offset -= PHOENIX_SMPS_BASE_VOLT_STD_MODE_WITH_OFFSET_UV;
+
+ offset_code = (offset + step - 1) / step;
+ /* The code starts at 1 not 0 */
+ offset_code++;
+
+ debug("do_scale_vcore: volt - %d offset_code - 0x%x\n", volt_mv,
+ offset_code);
+
+ temp = SMPS_I2C_SLAVE_ADDR |
+ (vcore_reg << PRM_VC_VAL_BYPASS_REGADDR_SHIFT) |
+ (offset_code << PRM_VC_VAL_BYPASS_DATA_SHIFT) |
+ PRM_VC_VAL_BYPASS_VALID_BIT;
+ writel(temp, &prcm->prm_vc_val_bypass);
+ if (!wait_on_value(PRM_VC_VAL_BYPASS_VALID_BIT, 0,
+ &prcm->prm_vc_val_bypass, LDELAY)) {
+ printf("Scaling voltage failed for 0x%x\n", vcore_reg);
+ }
+}
+
+static inline void enable_clock_domain(u32 *const clkctrl_reg, u32 enable_mode)
+{
+ clrsetbits_le32(clkctrl_reg, CD_CLKCTRL_CLKTRCTRL_MASK,
+ enable_mode << CD_CLKCTRL_CLKTRCTRL_SHIFT);
+ debug("Enable clock domain - %p\n", clkctrl_reg);
+}
+
+static inline void wait_for_clk_enable(u32 *clkctrl_addr)
+{
+ u32 clkctrl, idlest = MODULE_CLKCTRL_IDLEST_DISABLED;
+ u32 bound = LDELAY;
+
+ while ((idlest == MODULE_CLKCTRL_IDLEST_DISABLED) ||
+ (idlest == MODULE_CLKCTRL_IDLEST_TRANSITIONING)) {
+
+ clkctrl = readl(clkctrl_addr);
+ idlest = (clkctrl & MODULE_CLKCTRL_IDLEST_MASK) >>
+ MODULE_CLKCTRL_IDLEST_SHIFT;
+ if (--bound == 0) {
+ printf("Clock enable failed for 0x%p idlest 0x%x\n",
+ clkctrl_addr, clkctrl);
+ return;
+ }
+ }
+}
+
+static inline void enable_clock_module(u32 *const clkctrl_addr, u32 enable_mode,
+ u32 wait_for_enable)
+{
+ clrsetbits_le32(clkctrl_addr, MODULE_CLKCTRL_MODULEMODE_MASK,
+ enable_mode << MODULE_CLKCTRL_MODULEMODE_SHIFT);
+ debug("Enable clock module - %p\n", clkctrl_addr);
+ if (wait_for_enable)
+ wait_for_clk_enable(clkctrl_addr);
+}
+
+void freq_update_core(void)
+{
+ u32 freq_config1 = 0;
+ const struct dpll_params *core_dpll_params;
+
+ core_dpll_params = get_core_dpll_params();
+ /* Put EMIF clock domain in sw wakeup mode */
+ enable_clock_domain(&prcm->cm_memif_clkstctrl,
+ CD_CLKCTRL_CLKTRCTRL_SW_WKUP);
+ wait_for_clk_enable(&prcm->cm_memif_emif_1_clkctrl);
+ wait_for_clk_enable(&prcm->cm_memif_emif_2_clkctrl);
+
+ freq_config1 = SHADOW_FREQ_CONFIG1_FREQ_UPDATE_MASK |
+ SHADOW_FREQ_CONFIG1_DLL_RESET_MASK;
+
+ freq_config1 |= (DPLL_EN_LOCK << SHADOW_FREQ_CONFIG1_DPLL_EN_SHIFT) &
+ SHADOW_FREQ_CONFIG1_DPLL_EN_MASK;
+
+ freq_config1 |= (core_dpll_params->m2 <<
+ SHADOW_FREQ_CONFIG1_M2_DIV_SHIFT) &
+ SHADOW_FREQ_CONFIG1_M2_DIV_MASK;
+
+ writel(freq_config1, &prcm->cm_shadow_freq_config1);
+ if (!wait_on_value(SHADOW_FREQ_CONFIG1_FREQ_UPDATE_MASK, 0,
+ &prcm->cm_shadow_freq_config1, LDELAY)) {
+ puts("FREQ UPDATE procedure failed!!");
+ hang();
+ }
+
+ /* Put EMIF clock domain back in hw auto mode */
+ enable_clock_domain(&prcm->cm_memif_clkstctrl,
+ CD_CLKCTRL_CLKTRCTRL_HW_AUTO);
+ wait_for_clk_enable(&prcm->cm_memif_emif_1_clkctrl);
+ wait_for_clk_enable(&prcm->cm_memif_emif_2_clkctrl);
+}
+
+void bypass_dpll(u32 *const base)
+{
+ do_bypass_dpll(base);
+ wait_for_bypass(base);
+}
+
+void lock_dpll(u32 *const base)
+{
+ do_lock_dpll(base);
+ wait_for_lock(base);
+}
+
+void setup_clocks_for_console(void)
+{
+ /* Do not add any spl_debug prints in this function */
+ clrsetbits_le32(&prcm->cm_l4per_clkstctrl, CD_CLKCTRL_CLKTRCTRL_MASK,
+ CD_CLKCTRL_CLKTRCTRL_SW_WKUP <<
+ CD_CLKCTRL_CLKTRCTRL_SHIFT);
+
+ /* Enable all UARTs - console will be on one of them */
+ clrsetbits_le32(&prcm->cm_l4per_uart1_clkctrl,
+ MODULE_CLKCTRL_MODULEMODE_MASK,
+ MODULE_CLKCTRL_MODULEMODE_SW_EXPLICIT_EN <<
+ MODULE_CLKCTRL_MODULEMODE_SHIFT);
+
+ clrsetbits_le32(&prcm->cm_l4per_uart2_clkctrl,
+ MODULE_CLKCTRL_MODULEMODE_MASK,
+ MODULE_CLKCTRL_MODULEMODE_SW_EXPLICIT_EN <<
+ MODULE_CLKCTRL_MODULEMODE_SHIFT);
+
+ clrsetbits_le32(&prcm->cm_l4per_uart3_clkctrl,
+ MODULE_CLKCTRL_MODULEMODE_MASK,
+ MODULE_CLKCTRL_MODULEMODE_SW_EXPLICIT_EN <<
+ MODULE_CLKCTRL_MODULEMODE_SHIFT);
+
+ clrsetbits_le32(&prcm->cm_l4per_uart3_clkctrl,
+ MODULE_CLKCTRL_MODULEMODE_MASK,
+ MODULE_CLKCTRL_MODULEMODE_SW_EXPLICIT_EN <<
+ MODULE_CLKCTRL_MODULEMODE_SHIFT);
+
+ clrsetbits_le32(&prcm->cm_l4per_clkstctrl, CD_CLKCTRL_CLKTRCTRL_MASK,
+ CD_CLKCTRL_CLKTRCTRL_HW_AUTO <<
+ CD_CLKCTRL_CLKTRCTRL_SHIFT);
+}
+
+void setup_sri2c(void)
+{
+ u32 sys_clk_khz, cycles_hi, cycles_low, temp;
+
+ sys_clk_khz = get_sys_clk_freq() / 1000;
+
+ /*
+ * Setup the dedicated I2C controller for Voltage Control
+ * I2C clk - high period 40% low period 60%
+ */
+ cycles_hi = sys_clk_khz * 4 / PRM_VC_I2C_CHANNEL_FREQ_KHZ / 10;
+ cycles_low = sys_clk_khz * 6 / PRM_VC_I2C_CHANNEL_FREQ_KHZ / 10;
+ /* values to be set in register - less by 5 & 7 respectively */
+ cycles_hi -= 5;
+ cycles_low -= 7;
+ temp = (cycles_hi << PRM_VC_CFG_I2C_CLK_SCLH_SHIFT) |
+ (cycles_low << PRM_VC_CFG_I2C_CLK_SCLL_SHIFT);
+ writel(temp, &prcm->prm_vc_cfg_i2c_clk);
+
+ /* Disable high speed mode and all advanced features */
+ writel(0x0, &prcm->prm_vc_cfg_i2c_mode);
+}
+
+void do_enable_clocks(u32 *const *clk_domains,
+ u32 *const *clk_modules_hw_auto,
+ u32 *const *clk_modules_explicit_en,
+ u8 wait_for_enable)
+{
+ u32 i, max = 100;
+
+ /* Put the clock domains in SW_WKUP mode */
+ for (i = 0; (i < max) && clk_domains[i]; i++) {
+ enable_clock_domain(clk_domains[i],
+ CD_CLKCTRL_CLKTRCTRL_SW_WKUP);
+ }
+
+ /* Clock modules that need to be put in HW_AUTO */
+ for (i = 0; (i < max) && clk_modules_hw_auto[i]; i++) {
+ enable_clock_module(clk_modules_hw_auto[i],
+ MODULE_CLKCTRL_MODULEMODE_HW_AUTO,
+ wait_for_enable);
+ };
+
+ /* Clock modules that need to be put in SW_EXPLICIT_EN mode */
+ for (i = 0; (i < max) && clk_modules_explicit_en[i]; i++) {
+ enable_clock_module(clk_modules_explicit_en[i],
+ MODULE_CLKCTRL_MODULEMODE_SW_EXPLICIT_EN,
+ wait_for_enable);
+ };
+
+ /* Put the clock domains in HW_AUTO mode now */
+ for (i = 0; (i < max) && clk_domains[i]; i++) {
+ enable_clock_domain(clk_domains[i],
+ CD_CLKCTRL_CLKTRCTRL_HW_AUTO);
+ }
+}
+
+void prcm_init(void)
+{
+ switch (omap_hw_init_context()) {
+ case OMAP_INIT_CONTEXT_SPL:
+ case OMAP_INIT_CONTEXT_UBOOT_FROM_NOR:
+ case OMAP_INIT_CONTEXT_UBOOT_AFTER_CH:
+ enable_basic_clocks();
+ scale_vcores();
+ setup_dplls();
+#ifdef CONFIG_SYS_CLOCKS_ENABLE_ALL
+ setup_non_essential_dplls();
+ enable_non_essential_clocks();
+#endif
+ break;
+ default:
+ break;
+ }
+
+ if (OMAP_INIT_CONTEXT_SPL != omap_hw_init_context())
+ enable_basic_uboot_clocks();
+}
diff --git a/arch/arm/cpu/armv7/omap-common/emif-common.c b/arch/arm/cpu/armv7/omap-common/emif-common.c
new file mode 100644
index 0000000..ce03b5c
--- /dev/null
+++ b/arch/arm/cpu/armv7/omap-common/emif-common.c
@@ -0,0 +1,1140 @@
+/*
+ * EMIF programming
+ *
+ * (C) Copyright 2010
+ * Texas Instruments, <www.ti.com>
+ *
+ * Aneesh V <aneesh@ti.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <asm/emif.h>
+#include <asm/arch/clocks.h>
+#include <asm/arch/sys_proto.h>
+#include <asm/omap_common.h>
+#include <asm/utils.h>
+
+inline u32 emif_num(u32 base)
+{
+ if (base == EMIF1_BASE)
+ return 1;
+ else if (base == EMIF2_BASE)
+ return 2;
+ else
+ return 0;
+}
+
+
+static inline u32 get_mr(u32 base, u32 cs, u32 mr_addr)
+{
+ u32 mr;
+ struct emif_reg_struct *emif = (struct emif_reg_struct *)base;
+
+ mr_addr |= cs << EMIF_REG_CS_SHIFT;
+ writel(mr_addr, &emif->emif_lpddr2_mode_reg_cfg);
+ if (omap_revision() == OMAP4430_ES2_0)
+ mr = readl(&emif->emif_lpddr2_mode_reg_data_es2);
+ else
+ mr = readl(&emif->emif_lpddr2_mode_reg_data);
+ debug("get_mr: EMIF%d cs %d mr %08x val 0x%x\n", emif_num(base),
+ cs, mr_addr, mr);
+ return mr;
+}
+
+static inline void set_mr(u32 base, u32 cs, u32 mr_addr, u32 mr_val)
+{
+ struct emif_reg_struct *emif = (struct emif_reg_struct *)base;
+
+ mr_addr |= cs << EMIF_REG_CS_SHIFT;
+ writel(mr_addr, &emif->emif_lpddr2_mode_reg_cfg);
+ writel(mr_val, &emif->emif_lpddr2_mode_reg_data);
+}
+
+void emif_reset_phy(u32 base)
+{
+ struct emif_reg_struct *emif = (struct emif_reg_struct *)base;
+ u32 iodft;
+
+ iodft = readl(&emif->emif_iodft_tlgc);
+ iodft |= EMIF_REG_RESET_PHY_MASK;
+ writel(iodft, &emif->emif_iodft_tlgc);
+}
+
+static void do_lpddr2_init(u32 base, u32 cs)
+{
+ u32 mr_addr;
+
+ /* Wait till device auto initialization is complete */
+ while (get_mr(base, cs, LPDDR2_MR0) & LPDDR2_MR0_DAI_MASK)
+ ;
+ set_mr(base, cs, LPDDR2_MR10, MR10_ZQ_ZQINIT);
+ /*
+ * tZQINIT = 1 us
+ * Enough loops assuming a maximum of 2GHz
+ */
+ sdelay(2000);
+ set_mr(base, cs, LPDDR2_MR1, MR1_BL_8_BT_SEQ_WRAP_EN_NWR_3);
+ set_mr(base, cs, LPDDR2_MR16, MR16_REF_FULL_ARRAY);
+ /*
+ * Enable refresh along with writing MR2
+ * Encoding of RL in MR2 is (RL - 2)
+ */
+ mr_addr = LPDDR2_MR2 | EMIF_REG_REFRESH_EN_MASK;
+ set_mr(base, cs, mr_addr, RL_FINAL - 2);
+}
+
+static void lpddr2_init(u32 base, const struct emif_regs *regs)
+{
+ struct emif_reg_struct *emif = (struct emif_reg_struct *)base;
+
+ /* Not NVM */
+ clrbits_le32(&emif->emif_lpddr2_nvm_config, EMIF_REG_CS1NVMEN_MASK);
+
+ /*
+ * Keep REG_INITREF_DIS = 1 to prevent re-initialization of SDRAM
+ * when EMIF_SDRAM_CONFIG register is written
+ */
+ setbits_le32(&emif->emif_sdram_ref_ctrl, EMIF_REG_INITREF_DIS_MASK);
+
+ /*
+ * Set the SDRAM_CONFIG and PHY_CTRL for the
+ * un-locked frequency & default RL
+ */
+ writel(regs->sdram_config_init, &emif->emif_sdram_config);
+ writel(regs->emif_ddr_phy_ctlr_1_init, &emif->emif_ddr_phy_ctrl_1);
+
+ do_lpddr2_init(base, CS0);
+ if (regs->sdram_config & EMIF_REG_EBANK_MASK)
+ do_lpddr2_init(base, CS1);
+
+ writel(regs->sdram_config, &emif->emif_sdram_config);
+ writel(regs->emif_ddr_phy_ctlr_1, &emif->emif_ddr_phy_ctrl_1);
+
+ /* Enable refresh now */
+ clrbits_le32(&emif->emif_sdram_ref_ctrl, EMIF_REG_INITREF_DIS_MASK);
+
+}
+
+void emif_update_timings(u32 base, const struct emif_regs *regs)
+{
+ struct emif_reg_struct *emif = (struct emif_reg_struct *)base;
+
+ writel(regs->ref_ctrl, &emif->emif_sdram_ref_ctrl_shdw);
+ writel(regs->sdram_tim1, &emif->emif_sdram_tim_1_shdw);
+ writel(regs->sdram_tim2, &emif->emif_sdram_tim_2_shdw);
+ writel(regs->sdram_tim3, &emif->emif_sdram_tim_3_shdw);
+ if (omap_revision() == OMAP4430_ES1_0) {
+ /* ES1 bug EMIF should be in force idle during freq_update */
+ writel(0, &emif->emif_pwr_mgmt_ctrl);
+ } else {
+ writel(EMIF_PWR_MGMT_CTRL, &emif->emif_pwr_mgmt_ctrl);
+ writel(EMIF_PWR_MGMT_CTRL_SHDW, &emif->emif_pwr_mgmt_ctrl_shdw);
+ }
+ writel(regs->read_idle_ctrl, &emif->emif_read_idlectrl_shdw);
+ writel(regs->zq_config, &emif->emif_zq_config);
+ writel(regs->temp_alert_config, &emif->emif_temp_alert_config);
+ writel(regs->emif_ddr_phy_ctlr_1, &emif->emif_ddr_phy_ctrl_1_shdw);
+
+ if (omap_revision() == OMAP5430_ES1_0) {
+ writel(EMIF_L3_CONFIG_VAL_SYS_10_MPU_5_LL_0,
+ &emif->emif_l3_config);
+ } else if (omap_revision() >= OMAP4460_ES1_0) {
+ writel(EMIF_L3_CONFIG_VAL_SYS_10_MPU_3_LL_0,
+ &emif->emif_l3_config);
+ } else {
+ writel(EMIF_L3_CONFIG_VAL_SYS_10_LL_0,
+ &emif->emif_l3_config);
+ }
+}
+
+#ifndef CONFIG_SYS_EMIF_PRECALCULATED_TIMING_REGS
+#define print_timing_reg(reg) debug(#reg" - 0x%08x\n", (reg))
+
+/*
+ * Organization and refresh requirements for LPDDR2 devices of different
+ * types and densities. Derived from JESD209-2 section 2.4
+ */
+const struct lpddr2_addressing addressing_table[] = {
+ /* Banks tREFIx10 rowx32,rowx16 colx32,colx16 density */
+ {BANKS4, T_REFI_15_6, {ROW_12, ROW_12}, {COL_7, COL_8} },/*64M */
+ {BANKS4, T_REFI_15_6, {ROW_12, ROW_12}, {COL_8, COL_9} },/*128M */
+ {BANKS4, T_REFI_7_8, {ROW_13, ROW_13}, {COL_8, COL_9} },/*256M */
+ {BANKS4, T_REFI_7_8, {ROW_13, ROW_13}, {COL_9, COL_10} },/*512M */
+ {BANKS8, T_REFI_7_8, {ROW_13, ROW_13}, {COL_9, COL_10} },/*1GS4 */
+ {BANKS8, T_REFI_3_9, {ROW_14, ROW_14}, {COL_9, COL_10} },/*2GS4 */
+ {BANKS8, T_REFI_3_9, {ROW_14, ROW_14}, {COL_10, COL_11} },/*4G */
+ {BANKS8, T_REFI_3_9, {ROW_15, ROW_15}, {COL_10, COL_11} },/*8G */
+ {BANKS4, T_REFI_7_8, {ROW_14, ROW_14}, {COL_9, COL_10} },/*1GS2 */
+ {BANKS4, T_REFI_3_9, {ROW_15, ROW_15}, {COL_9, COL_10} },/*2GS2 */
+};
+
+static const u32 lpddr2_density_2_size_in_mbytes[] = {
+ 8, /* 64Mb */
+ 16, /* 128Mb */
+ 32, /* 256Mb */
+ 64, /* 512Mb */
+ 128, /* 1Gb */
+ 256, /* 2Gb */
+ 512, /* 4Gb */
+ 1024, /* 8Gb */
+ 2048, /* 16Gb */
+ 4096 /* 32Gb */
+};
+
+/*
+ * Calculate the period of DDR clock from frequency value and set the
+ * denominator and numerator in global variables for easy access later
+ */
+static void set_ddr_clk_period(u32 freq)
+{
+ /*
+ * period = 1/freq
+ * period_in_ns = 10^9/freq
+ */
+ *T_num = 1000000000;
+ *T_den = freq;
+ cancel_out(T_num, T_den, 200);
+
+}
+
+/*
+ * Convert time in nano seconds to number of cycles of DDR clock
+ */
+static inline u32 ns_2_cycles(u32 ns)
+{
+ return ((ns * (*T_den)) + (*T_num) - 1) / (*T_num);
+}
+
+/*
+ * ns_2_cycles with the difference that the time passed is 2 times the actual
+ * value(to avoid fractions). The cycles returned is for the original value of
+ * the timing parameter
+ */
+static inline u32 ns_x2_2_cycles(u32 ns)
+{
+ return ((ns * (*T_den)) + (*T_num) * 2 - 1) / ((*T_num) * 2);
+}
+
+/*
+ * Find addressing table index based on the device's type(S2 or S4) and
+ * density
+ */
+s8 addressing_table_index(u8 type, u8 density, u8 width)
+{
+ u8 index;
+ if ((density > LPDDR2_DENSITY_8Gb) || (width == LPDDR2_IO_WIDTH_8))
+ return -1;
+
+ /*
+ * Look at the way ADDR_TABLE_INDEX* values have been defined
+ * in emif.h compared to LPDDR2_DENSITY_* values
+ * The table is layed out in the increasing order of density
+ * (ignoring type). The exceptions 1GS2 and 2GS2 have been placed
+ * at the end
+ */
+ if ((type == LPDDR2_TYPE_S2) && (density == LPDDR2_DENSITY_1Gb))
+ index = ADDR_TABLE_INDEX1GS2;
+ else if ((type == LPDDR2_TYPE_S2) && (density == LPDDR2_DENSITY_2Gb))
+ index = ADDR_TABLE_INDEX2GS2;
+ else
+ index = density;
+
+ debug("emif: addressing table index %d\n", index);
+
+ return index;
+}
+
+/*
+ * Find the the right timing table from the array of timing
+ * tables of the device using DDR clock frequency
+ */
+static const struct lpddr2_ac_timings *get_timings_table(const struct
+ lpddr2_ac_timings const *const *device_timings,
+ u32 freq)
+{
+ u32 i, temp, freq_nearest;
+ const struct lpddr2_ac_timings *timings = 0;
+
+ emif_assert(freq <= MAX_LPDDR2_FREQ);
+ emif_assert(device_timings);
+
+ /*
+ * Start with the maximum allowed frequency - that is always safe
+ */
+ freq_nearest = MAX_LPDDR2_FREQ;
+ /*
+ * Find the timings table that has the max frequency value:
+ * i. Above or equal to the DDR frequency - safe
+ * ii. The lowest that satisfies condition (i) - optimal
+ */
+ for (i = 0; (i < MAX_NUM_SPEEDBINS) && device_timings[i]; i++) {
+ temp = device_timings[i]->max_freq;
+ if ((temp >= freq) && (temp <= freq_nearest)) {
+ freq_nearest = temp;
+ timings = device_timings[i];
+ }
+ }
+ debug("emif: timings table: %d\n", freq_nearest);
+ return timings;
+}
+
+/*
+ * Finds the value of emif_sdram_config_reg
+ * All parameters are programmed based on the device on CS0.
+ * If there is a device on CS1, it will be same as that on CS0 or
+ * it will be NVM. We don't support NVM yet.
+ * If cs1_device pointer is NULL it is assumed that there is no device
+ * on CS1
+ */
+static u32 get_sdram_config_reg(const struct lpddr2_device_details *cs0_device,
+ const struct lpddr2_device_details *cs1_device,
+ const struct lpddr2_addressing *addressing,
+ u8 RL)
+{
+ u32 config_reg = 0;
+
+ config_reg |= (cs0_device->type + 4) << EMIF_REG_SDRAM_TYPE_SHIFT;
+ config_reg |= EMIF_INTERLEAVING_POLICY_MAX_INTERLEAVING <<
+ EMIF_REG_IBANK_POS_SHIFT;
+
+ config_reg |= cs0_device->io_width << EMIF_REG_NARROW_MODE_SHIFT;
+
+ config_reg |= RL << EMIF_REG_CL_SHIFT;
+
+ config_reg |= addressing->row_sz[cs0_device->io_width] <<
+ EMIF_REG_ROWSIZE_SHIFT;
+
+ config_reg |= addressing->num_banks << EMIF_REG_IBANK_SHIFT;
+
+ config_reg |= (cs1_device ? EBANK_CS1_EN : EBANK_CS1_DIS) <<
+ EMIF_REG_EBANK_SHIFT;
+
+ config_reg |= addressing->col_sz[cs0_device->io_width] <<
+ EMIF_REG_PAGESIZE_SHIFT;
+
+ return config_reg;
+}
+
+static u32 get_sdram_ref_ctrl(u32 freq,
+ const struct lpddr2_addressing *addressing)
+{
+ u32 ref_ctrl = 0, val = 0, freq_khz;
+ freq_khz = freq / 1000;
+ /*
+ * refresh rate to be set is 'tREFI * freq in MHz
+ * division by 10000 to account for khz and x10 in t_REFI_us_x10
+ */
+ val = addressing->t_REFI_us_x10 * freq_khz / 10000;
+ ref_ctrl |= val << EMIF_REG_REFRESH_RATE_SHIFT;
+
+ return ref_ctrl;
+}
+
+static u32 get_sdram_tim_1_reg(const struct lpddr2_ac_timings *timings,
+ const struct lpddr2_min_tck *min_tck,
+ const struct lpddr2_addressing *addressing)
+{
+ u32 tim1 = 0, val = 0;
+ val = max(min_tck->tWTR, ns_x2_2_cycles(timings->tWTRx2)) - 1;
+ tim1 |= val << EMIF_REG_T_WTR_SHIFT;
+
+ if (addressing->num_banks == BANKS8)
+ val = (timings->tFAW * (*T_den) + 4 * (*T_num) - 1) /
+ (4 * (*T_num)) - 1;
+ else
+ val = max(min_tck->tRRD, ns_2_cycles(timings->tRRD)) - 1;
+
+ tim1 |= val << EMIF_REG_T_RRD_SHIFT;
+
+ val = ns_2_cycles(timings->tRASmin + timings->tRPab) - 1;
+ tim1 |= val << EMIF_REG_T_RC_SHIFT;
+
+ val = max(min_tck->tRAS_MIN, ns_2_cycles(timings->tRASmin)) - 1;
+ tim1 |= val << EMIF_REG_T_RAS_SHIFT;
+
+ val = max(min_tck->tWR, ns_2_cycles(timings->tWR)) - 1;
+ tim1 |= val << EMIF_REG_T_WR_SHIFT;
+
+ val = max(min_tck->tRCD, ns_2_cycles(timings->tRCD)) - 1;
+ tim1 |= val << EMIF_REG_T_RCD_SHIFT;
+
+ val = max(min_tck->tRP_AB, ns_2_cycles(timings->tRPab)) - 1;
+ tim1 |= val << EMIF_REG_T_RP_SHIFT;
+
+ return tim1;
+}
+
+static u32 get_sdram_tim_2_reg(const struct lpddr2_ac_timings *timings,
+ const struct lpddr2_min_tck *min_tck)
+{
+ u32 tim2 = 0, val = 0;
+ val = max(min_tck->tCKE, timings->tCKE) - 1;
+ tim2 |= val << EMIF_REG_T_CKE_SHIFT;
+
+ val = max(min_tck->tRTP, ns_x2_2_cycles(timings->tRTPx2)) - 1;
+ tim2 |= val << EMIF_REG_T_RTP_SHIFT;
+
+ /*
+ * tXSRD = tRFCab + 10 ns. XSRD and XSNR should have the
+ * same value
+ */
+ val = ns_2_cycles(timings->tXSR) - 1;
+ tim2 |= val << EMIF_REG_T_XSRD_SHIFT;
+ tim2 |= val << EMIF_REG_T_XSNR_SHIFT;
+
+ val = max(min_tck->tXP, ns_x2_2_cycles(timings->tXPx2)) - 1;
+ tim2 |= val << EMIF_REG_T_XP_SHIFT;
+
+ return tim2;
+}
+
+static u32 get_sdram_tim_3_reg(const struct lpddr2_ac_timings *timings,
+ const struct lpddr2_min_tck *min_tck,
+ const struct lpddr2_addressing *addressing)
+{
+ u32 tim3 = 0, val = 0;
+ val = min(timings->tRASmax * 10 / addressing->t_REFI_us_x10 - 1, 0xF);
+ tim3 |= val << EMIF_REG_T_RAS_MAX_SHIFT;
+
+ val = ns_2_cycles(timings->tRFCab) - 1;
+ tim3 |= val << EMIF_REG_T_RFC_SHIFT;
+
+ val = ns_x2_2_cycles(timings->tDQSCKMAXx2) - 1;
+ tim3 |= val << EMIF_REG_T_TDQSCKMAX_SHIFT;
+
+ val = ns_2_cycles(timings->tZQCS) - 1;
+ tim3 |= val << EMIF_REG_ZQ_ZQCS_SHIFT;
+
+ val = max(min_tck->tCKESR, ns_2_cycles(timings->tCKESR)) - 1;
+ tim3 |= val << EMIF_REG_T_CKESR_SHIFT;
+
+ return tim3;
+}
+
+static u32 get_zq_config_reg(const struct lpddr2_device_details *cs1_device,
+ const struct lpddr2_addressing *addressing,
+ u8 volt_ramp)
+{
+ u32 zq = 0, val = 0;
+ if (volt_ramp)
+ val =
+ EMIF_ZQCS_INTERVAL_DVFS_IN_US * 10 /
+ addressing->t_REFI_us_x10;
+ else
+ val =
+ EMIF_ZQCS_INTERVAL_NORMAL_IN_US * 10 /
+ addressing->t_REFI_us_x10;
+ zq |= val << EMIF_REG_ZQ_REFINTERVAL_SHIFT;
+
+ zq |= (REG_ZQ_ZQCL_MULT - 1) << EMIF_REG_ZQ_ZQCL_MULT_SHIFT;
+
+ zq |= (REG_ZQ_ZQINIT_MULT - 1) << EMIF_REG_ZQ_ZQINIT_MULT_SHIFT;
+
+ zq |= REG_ZQ_SFEXITEN_ENABLE << EMIF_REG_ZQ_SFEXITEN_SHIFT;
+
+ /*
+ * Assuming that two chipselects have a single calibration resistor
+ * If there are indeed two calibration resistors, then this flag should
+ * be enabled to take advantage of dual calibration feature.
+ * This data should ideally come from board files. But considering
+ * that none of the boards today have calibration resistors per CS,
+ * it would be an unnecessary overhead.
+ */
+ zq |= REG_ZQ_DUALCALEN_DISABLE << EMIF_REG_ZQ_DUALCALEN_SHIFT;
+
+ zq |= REG_ZQ_CS0EN_ENABLE << EMIF_REG_ZQ_CS0EN_SHIFT;
+
+ zq |= (cs1_device ? 1 : 0) << EMIF_REG_ZQ_CS1EN_SHIFT;
+
+ return zq;
+}
+
+static u32 get_temp_alert_config(const struct lpddr2_device_details *cs1_device,
+ const struct lpddr2_addressing *addressing,
+ u8 is_derated)
+{
+ u32 alert = 0, interval;
+ interval =
+ TEMP_ALERT_POLL_INTERVAL_MS * 10000 / addressing->t_REFI_us_x10;
+ if (is_derated)
+ interval *= 4;
+ alert |= interval << EMIF_REG_TA_REFINTERVAL_SHIFT;
+
+ alert |= TEMP_ALERT_CONFIG_DEVCT_1 << EMIF_REG_TA_DEVCNT_SHIFT;
+
+ alert |= TEMP_ALERT_CONFIG_DEVWDT_32 << EMIF_REG_TA_DEVWDT_SHIFT;
+
+ alert |= 1 << EMIF_REG_TA_SFEXITEN_SHIFT;
+
+ alert |= 1 << EMIF_REG_TA_CS0EN_SHIFT;
+
+ alert |= (cs1_device ? 1 : 0) << EMIF_REG_TA_CS1EN_SHIFT;
+
+ return alert;
+}
+
+static u32 get_read_idle_ctrl_reg(u8 volt_ramp)
+{
+ u32 idle = 0, val = 0;
+ if (volt_ramp)
+ val = ns_2_cycles(READ_IDLE_INTERVAL_DVFS) / 64 - 1;
+ else
+ /*Maximum value in normal conditions - suggested by hw team */
+ val = 0x1FF;
+ idle |= val << EMIF_REG_READ_IDLE_INTERVAL_SHIFT;
+
+ idle |= EMIF_REG_READ_IDLE_LEN_VAL << EMIF_REG_READ_IDLE_LEN_SHIFT;
+
+ return idle;
+}
+
+static u32 get_ddr_phy_ctrl_1(u32 freq, u8 RL)
+{
+ u32 phy = 0, val = 0;
+
+ phy |= (RL + 2) << EMIF_REG_READ_LATENCY_SHIFT;
+
+ if (freq <= 100000000)
+ val = EMIF_DLL_SLAVE_DLY_CTRL_100_MHZ_AND_LESS;
+ else if (freq <= 200000000)
+ val = EMIF_DLL_SLAVE_DLY_CTRL_200_MHZ;
+ else
+ val = EMIF_DLL_SLAVE_DLY_CTRL_400_MHZ;
+ phy |= val << EMIF_REG_DLL_SLAVE_DLY_CTRL_SHIFT;
+
+ /* Other fields are constant magic values. Hardcode them together */
+ phy |= EMIF_DDR_PHY_CTRL_1_BASE_VAL <<
+ EMIF_EMIF_DDR_PHY_CTRL_1_BASE_VAL_SHIFT;
+
+ return phy;
+}
+
+static u32 get_emif_mem_size(struct emif_device_details *devices)
+{
+ u32 size_mbytes = 0, temp;
+
+ if (!devices)
+ return 0;
+
+ if (devices->cs0_device_details) {
+ temp = devices->cs0_device_details->density;
+ size_mbytes += lpddr2_density_2_size_in_mbytes[temp];
+ }
+
+ if (devices->cs1_device_details) {
+ temp = devices->cs1_device_details->density;
+ size_mbytes += lpddr2_density_2_size_in_mbytes[temp];
+ }
+ /* convert to bytes */
+ return size_mbytes << 20;
+}
+
+/* Gets the encoding corresponding to a given DMM section size */
+u32 get_dmm_section_size_map(u32 section_size)
+{
+ /*
+ * Section size mapping:
+ * 0x0: 16-MiB section
+ * 0x1: 32-MiB section
+ * 0x2: 64-MiB section
+ * 0x3: 128-MiB section
+ * 0x4: 256-MiB section
+ * 0x5: 512-MiB section
+ * 0x6: 1-GiB section
+ * 0x7: 2-GiB section
+ */
+ section_size >>= 24; /* divide by 16 MB */
+ return log_2_n_round_down(section_size);
+}
+
+static void emif_calculate_regs(
+ const struct emif_device_details *emif_dev_details,
+ u32 freq, struct emif_regs *regs)
+{
+ u32 temp, sys_freq;
+ const struct lpddr2_addressing *addressing;
+ const struct lpddr2_ac_timings *timings;
+ const struct lpddr2_min_tck *min_tck;
+ const struct lpddr2_device_details *cs0_dev_details =
+ emif_dev_details->cs0_device_details;
+ const struct lpddr2_device_details *cs1_dev_details =
+ emif_dev_details->cs1_device_details;
+ const struct lpddr2_device_timings *cs0_dev_timings =
+ emif_dev_details->cs0_device_timings;
+
+ emif_assert(emif_dev_details);
+ emif_assert(regs);
+ /*
+ * You can not have a device on CS1 without one on CS0
+ * So configuring EMIF without a device on CS0 doesn't
+ * make sense
+ */
+ emif_assert(cs0_dev_details);
+ emif_assert(cs0_dev_details->type != LPDDR2_TYPE_NVM);
+ /*
+ * If there is a device on CS1 it should be same type as CS0
+ * (or NVM. But NVM is not supported in this driver yet)
+ */
+ emif_assert((cs1_dev_details == NULL) ||
+ (cs1_dev_details->type == LPDDR2_TYPE_NVM) ||
+ (cs0_dev_details->type == cs1_dev_details->type));
+ emif_assert(freq <= MAX_LPDDR2_FREQ);
+
+ set_ddr_clk_period(freq);
+
+ /*
+ * The device on CS0 is used for all timing calculations
+ * There is only one set of registers for timings per EMIF. So, if the
+ * second CS(CS1) has a device, it should have the same timings as the
+ * device on CS0
+ */
+ timings = get_timings_table(cs0_dev_timings->ac_timings, freq);
+ emif_assert(timings);
+ min_tck = cs0_dev_timings->min_tck;
+
+ temp = addressing_table_index(cs0_dev_details->type,
+ cs0_dev_details->density,
+ cs0_dev_details->io_width);
+
+ emif_assert((temp >= 0));
+ addressing = &(addressing_table[temp]);
+ emif_assert(addressing);
+
+ sys_freq = get_sys_clk_freq();
+
+ regs->sdram_config_init = get_sdram_config_reg(cs0_dev_details,
+ cs1_dev_details,
+ addressing, RL_BOOT);
+
+ regs->sdram_config = get_sdram_config_reg(cs0_dev_details,
+ cs1_dev_details,
+ addressing, RL_FINAL);
+
+ regs->ref_ctrl = get_sdram_ref_ctrl(freq, addressing);
+
+ regs->sdram_tim1 = get_sdram_tim_1_reg(timings, min_tck, addressing);
+
+ regs->sdram_tim2 = get_sdram_tim_2_reg(timings, min_tck);
+
+ regs->sdram_tim3 = get_sdram_tim_3_reg(timings, min_tck, addressing);
+
+ regs->read_idle_ctrl = get_read_idle_ctrl_reg(LPDDR2_VOLTAGE_STABLE);
+
+ regs->temp_alert_config =
+ get_temp_alert_config(cs1_dev_details, addressing, 0);
+
+ regs->zq_config = get_zq_config_reg(cs1_dev_details, addressing,
+ LPDDR2_VOLTAGE_STABLE);
+
+ regs->emif_ddr_phy_ctlr_1_init =
+ get_ddr_phy_ctrl_1(sys_freq / 2, RL_BOOT);
+
+ regs->emif_ddr_phy_ctlr_1 =
+ get_ddr_phy_ctrl_1(freq, RL_FINAL);
+
+ regs->freq = freq;
+
+ print_timing_reg(regs->sdram_config_init);
+ print_timing_reg(regs->sdram_config);
+ print_timing_reg(regs->ref_ctrl);
+ print_timing_reg(regs->sdram_tim1);
+ print_timing_reg(regs->sdram_tim2);
+ print_timing_reg(regs->sdram_tim3);
+ print_timing_reg(regs->read_idle_ctrl);
+ print_timing_reg(regs->temp_alert_config);
+ print_timing_reg(regs->zq_config);
+ print_timing_reg(regs->emif_ddr_phy_ctlr_1);
+ print_timing_reg(regs->emif_ddr_phy_ctlr_1_init);
+}
+#endif /* CONFIG_SYS_EMIF_PRECALCULATED_TIMING_REGS */
+
+#ifdef CONFIG_SYS_AUTOMATIC_SDRAM_DETECTION
+const char *get_lpddr2_type(u8 type_id)
+{
+ switch (type_id) {
+ case LPDDR2_TYPE_S4:
+ return "LPDDR2-S4";
+ case LPDDR2_TYPE_S2:
+ return "LPDDR2-S2";
+ default:
+ return NULL;
+ }
+}
+
+const char *get_lpddr2_io_width(u8 width_id)
+{
+ switch (width_id) {
+ case LPDDR2_IO_WIDTH_8:
+ return "x8";
+ case LPDDR2_IO_WIDTH_16:
+ return "x16";
+ case LPDDR2_IO_WIDTH_32:
+ return "x32";
+ default:
+ return NULL;
+ }
+}
+
+const char *get_lpddr2_manufacturer(u32 manufacturer)
+{
+ switch (manufacturer) {
+ case LPDDR2_MANUFACTURER_SAMSUNG:
+ return "Samsung";
+ case LPDDR2_MANUFACTURER_QIMONDA:
+ return "Qimonda";
+ case LPDDR2_MANUFACTURER_ELPIDA:
+ return "Elpida";
+ case LPDDR2_MANUFACTURER_ETRON:
+ return "Etron";
+ case LPDDR2_MANUFACTURER_NANYA:
+ return "Nanya";
+ case LPDDR2_MANUFACTURER_HYNIX:
+ return "Hynix";
+ case LPDDR2_MANUFACTURER_MOSEL:
+ return "Mosel";
+ case LPDDR2_MANUFACTURER_WINBOND:
+ return "Winbond";
+ case LPDDR2_MANUFACTURER_ESMT:
+ return "ESMT";
+ case LPDDR2_MANUFACTURER_SPANSION:
+ return "Spansion";
+ case LPDDR2_MANUFACTURER_SST:
+ return "SST";
+ case LPDDR2_MANUFACTURER_ZMOS:
+ return "ZMOS";
+ case LPDDR2_MANUFACTURER_INTEL:
+ return "Intel";
+ case LPDDR2_MANUFACTURER_NUMONYX:
+ return "Numonyx";
+ case LPDDR2_MANUFACTURER_MICRON:
+ return "Micron";
+ default:
+ return NULL;
+ }
+}
+
+static void display_sdram_details(u32 emif_nr, u32 cs,
+ struct lpddr2_device_details *device)
+{
+ const char *mfg_str;
+ const char *type_str;
+ char density_str[10];
+ u32 density;
+
+ debug("EMIF%d CS%d\t", emif_nr, cs);
+
+ if (!device) {
+ debug("None\n");
+ return;
+ }
+
+ mfg_str = get_lpddr2_manufacturer(device->manufacturer);
+ type_str = get_lpddr2_type(device->type);
+
+ density = lpddr2_density_2_size_in_mbytes[device->density];
+ if ((density / 1024 * 1024) == density) {
+ density /= 1024;
+ sprintf(density_str, "%d GB", density);
+ } else
+ sprintf(density_str, "%d MB", density);
+ if (mfg_str && type_str)
+ debug("%s\t\t%s\t%s\n", mfg_str, type_str, density_str);
+}
+
+static u8 is_lpddr2_sdram_present(u32 base, u32 cs,
+ struct lpddr2_device_details *lpddr2_device)
+{
+ u32 mr = 0, temp;
+
+ mr = get_mr(base, cs, LPDDR2_MR0);
+ if (mr > 0xFF) {
+ /* Mode register value bigger than 8 bit */
+ return 0;
+ }
+
+ temp = (mr & LPDDR2_MR0_DI_MASK) >> LPDDR2_MR0_DI_SHIFT;
+ if (temp) {
+ /* Not SDRAM */
+ return 0;
+ }
+ temp = (mr & LPDDR2_MR0_DNVI_MASK) >> LPDDR2_MR0_DNVI_SHIFT;
+
+ if (temp) {
+ /* DNV supported - But DNV is only supported for NVM */
+ return 0;
+ }
+
+ mr = get_mr(base, cs, LPDDR2_MR4);
+ if (mr > 0xFF) {
+ /* Mode register value bigger than 8 bit */
+ return 0;
+ }
+
+ mr = get_mr(base, cs, LPDDR2_MR5);
+ if (mr >= 0xFF) {
+ /* Mode register value bigger than 8 bit */
+ return 0;
+ }
+
+ if (!get_lpddr2_manufacturer(mr)) {
+ /* Manufacturer not identified */
+ return 0;
+ }
+ lpddr2_device->manufacturer = mr;
+
+ mr = get_mr(base, cs, LPDDR2_MR6);
+ if (mr >= 0xFF) {
+ /* Mode register value bigger than 8 bit */
+ return 0;
+ }
+
+ mr = get_mr(base, cs, LPDDR2_MR7);
+ if (mr >= 0xFF) {
+ /* Mode register value bigger than 8 bit */
+ return 0;
+ }
+
+ mr = get_mr(base, cs, LPDDR2_MR8);
+ if (mr >= 0xFF) {
+ /* Mode register value bigger than 8 bit */
+ return 0;
+ }
+
+ temp = (mr & MR8_TYPE_MASK) >> MR8_TYPE_SHIFT;
+ if (!get_lpddr2_type(temp)) {
+ /* Not SDRAM */
+ return 0;
+ }
+ lpddr2_device->type = temp;
+
+ temp = (mr & MR8_DENSITY_MASK) >> MR8_DENSITY_SHIFT;
+ if (temp > LPDDR2_DENSITY_32Gb) {
+ /* Density not supported */
+ return 0;
+ }
+ lpddr2_device->density = temp;
+
+ temp = (mr & MR8_IO_WIDTH_MASK) >> MR8_IO_WIDTH_SHIFT;
+ if (!get_lpddr2_io_width(temp)) {
+ /* IO width unsupported value */
+ return 0;
+ }
+ lpddr2_device->io_width = temp;
+
+ /*
+ * If all the above tests pass we should
+ * have a device on this chip-select
+ */
+ return 1;
+}
+
+struct lpddr2_device_details *emif_get_device_details(u32 emif_nr, u8 cs,
+ struct lpddr2_device_details *lpddr2_dev_details)
+{
+ u32 phy;
+ u32 base = (emif_nr == 1) ? EMIF1_BASE : EMIF2_BASE;
+
+ struct emif_reg_struct *emif = (struct emif_reg_struct *)base;
+
+ if (!lpddr2_dev_details)
+ return NULL;
+
+ /* Do the minimum init for mode register accesses */
+ if (!running_from_sdram()) {
+ phy = get_ddr_phy_ctrl_1(get_sys_clk_freq() / 2, RL_BOOT);
+ writel(phy, &emif->emif_ddr_phy_ctrl_1);
+ }
+
+ if (!(is_lpddr2_sdram_present(base, cs, lpddr2_dev_details)))
+ return NULL;
+
+ display_sdram_details(emif_num(base), cs, lpddr2_dev_details);
+
+ return lpddr2_dev_details;
+}
+#endif /* CONFIG_SYS_AUTOMATIC_SDRAM_DETECTION */
+
+static void do_sdram_init(u32 base)
+{
+ const struct emif_regs *regs;
+ u32 in_sdram, emif_nr;
+
+ debug(">>do_sdram_init() %x\n", base);
+
+ in_sdram = running_from_sdram();
+ emif_nr = (base == EMIF1_BASE) ? 1 : 2;
+
+#ifdef CONFIG_SYS_EMIF_PRECALCULATED_TIMING_REGS
+ emif_get_reg_dump(emif_nr, ®s);
+ if (!regs) {
+ debug("EMIF: reg dump not provided\n");
+ return;
+ }
+#else
+ /*
+ * The user has not provided the register values. We need to
+ * calculate it based on the timings and the DDR frequency
+ */
+ struct emif_device_details dev_details;
+ struct emif_regs calculated_regs;
+
+ /*
+ * Get device details:
+ * - Discovered if CONFIG_SYS_AUTOMATIC_SDRAM_DETECTION is set
+ * - Obtained from user otherwise
+ */
+ struct lpddr2_device_details cs0_dev_details, cs1_dev_details;
+ emif_reset_phy(base);
+ dev_details.cs0_device_details = emif_get_device_details(base, CS0,
+ &cs0_dev_details);
+ dev_details.cs1_device_details = emif_get_device_details(base, CS1,
+ &cs1_dev_details);
+ emif_reset_phy(base);
+
+ /* Return if no devices on this EMIF */
+ if (!dev_details.cs0_device_details &&
+ !dev_details.cs1_device_details) {
+ emif_sizes[emif_nr - 1] = 0;
+ return;
+ }
+
+ if (!in_sdram)
+ emif_sizes[emif_nr - 1] = get_emif_mem_size(&dev_details);
+
+ /*
+ * Get device timings:
+ * - Default timings specified by JESD209-2 if
+ * CONFIG_SYS_DEFAULT_LPDDR2_TIMINGS is set
+ * - Obtained from user otherwise
+ */
+ emif_get_device_timings(emif_nr, &dev_details.cs0_device_timings,
+ &dev_details.cs1_device_timings);
+
+ /* Calculate the register values */
+ emif_calculate_regs(&dev_details, omap_ddr_clk(), &calculated_regs);
+ regs = &calculated_regs;
+#endif /* CONFIG_SYS_EMIF_PRECALCULATED_TIMING_REGS */
+
+ /*
+ * Initializing the LPDDR2 device can not happen from SDRAM.
+ * Changing the timing registers in EMIF can happen(going from one
+ * OPP to another)
+ */
+ if (!in_sdram)
+ lpddr2_init(base, regs);
+
+ /* Write to the shadow registers */
+ emif_update_timings(base, regs);
+
+ debug("<<do_sdram_init() %x\n", base);
+}
+
+void emif_post_init_config(u32 base)
+{
+ struct emif_reg_struct *emif = (struct emif_reg_struct *)base;
+ u32 omap_rev = omap_revision();
+
+ if (omap_rev == OMAP5430_ES1_0)
+ return;
+
+ /* reset phy on ES2.0 */
+ if (omap_rev == OMAP4430_ES2_0)
+ emif_reset_phy(base);
+
+ /* Put EMIF back in smart idle on ES1.0 */
+ if (omap_rev == OMAP4430_ES1_0)
+ writel(0x80000000, &emif->emif_pwr_mgmt_ctrl);
+}
+
+void dmm_init(u32 base)
+{
+ const struct dmm_lisa_map_regs *lisa_map_regs;
+
+#ifdef CONFIG_SYS_EMIF_PRECALCULATED_TIMING_REGS
+ emif_get_dmm_regs(&lisa_map_regs);
+#else
+ u32 emif1_size, emif2_size, mapped_size, section_map = 0;
+ u32 section_cnt, sys_addr;
+ struct dmm_lisa_map_regs lis_map_regs_calculated = {0};
+
+ mapped_size = 0;
+ section_cnt = 3;
+ sys_addr = CONFIG_SYS_SDRAM_BASE;
+ emif1_size = emif_sizes[0];
+ emif2_size = emif_sizes[1];
+ debug("emif1_size 0x%x emif2_size 0x%x\n", emif1_size, emif2_size);
+
+ if (!emif1_size && !emif2_size)
+ return;
+
+ /* symmetric interleaved section */
+ if (emif1_size && emif2_size) {
+ mapped_size = min(emif1_size, emif2_size);
+ section_map = DMM_LISA_MAP_INTERLEAVED_BASE_VAL;
+ section_map |= 0 << EMIF_SDRC_ADDR_SHIFT;
+ /* only MSB */
+ section_map |= (sys_addr >> 24) <<
+ EMIF_SYS_ADDR_SHIFT;
+ section_map |= get_dmm_section_size_map(mapped_size * 2)
+ << EMIF_SYS_SIZE_SHIFT;
+ lis_map_regs_calculated.dmm_lisa_map_3 = section_map;
+ emif1_size -= mapped_size;
+ emif2_size -= mapped_size;
+ sys_addr += (mapped_size * 2);
+ section_cnt--;
+ }
+
+ /*
+ * Single EMIF section(we can have a maximum of 1 single EMIF
+ * section- either EMIF1 or EMIF2 or none, but not both)
+ */
+ if (emif1_size) {
+ section_map = DMM_LISA_MAP_EMIF1_ONLY_BASE_VAL;
+ section_map |= get_dmm_section_size_map(emif1_size)
+ << EMIF_SYS_SIZE_SHIFT;
+ /* only MSB */
+ section_map |= (mapped_size >> 24) <<
+ EMIF_SDRC_ADDR_SHIFT;
+ /* only MSB */
+ section_map |= (sys_addr >> 24) << EMIF_SYS_ADDR_SHIFT;
+ section_cnt--;
+ }
+ if (emif2_size) {
+ section_map = DMM_LISA_MAP_EMIF2_ONLY_BASE_VAL;
+ section_map |= get_dmm_section_size_map(emif2_size) <<
+ EMIF_SYS_SIZE_SHIFT;
+ /* only MSB */
+ section_map |= mapped_size >> 24 << EMIF_SDRC_ADDR_SHIFT;
+ /* only MSB */
+ section_map |= sys_addr >> 24 << EMIF_SYS_ADDR_SHIFT;
+ section_cnt--;
+ }
+
+ if (section_cnt == 2) {
+ /* Only 1 section - either symmetric or single EMIF */
+ lis_map_regs_calculated.dmm_lisa_map_3 = section_map;
+ lis_map_regs_calculated.dmm_lisa_map_2 = 0;
+ lis_map_regs_calculated.dmm_lisa_map_1 = 0;
+ } else {
+ /* 2 sections - 1 symmetric, 1 single EMIF */
+ lis_map_regs_calculated.dmm_lisa_map_2 = section_map;
+ lis_map_regs_calculated.dmm_lisa_map_1 = 0;
+ }
+
+ /* TRAP for invalid TILER mappings in section 0 */
+ lis_map_regs_calculated.dmm_lisa_map_0 = DMM_LISA_MAP_0_INVAL_ADDR_TRAP;
+
+ lisa_map_regs = &lis_map_regs_calculated;
+#endif
+ struct dmm_lisa_map_regs *hw_lisa_map_regs =
+ (struct dmm_lisa_map_regs *)base;
+
+ writel(0, &hw_lisa_map_regs->dmm_lisa_map_3);
+ writel(0, &hw_lisa_map_regs->dmm_lisa_map_2);
+ writel(0, &hw_lisa_map_regs->dmm_lisa_map_1);
+ writel(0, &hw_lisa_map_regs->dmm_lisa_map_0);
+
+ writel(lisa_map_regs->dmm_lisa_map_3,
+ &hw_lisa_map_regs->dmm_lisa_map_3);
+ writel(lisa_map_regs->dmm_lisa_map_2,
+ &hw_lisa_map_regs->dmm_lisa_map_2);
+ writel(lisa_map_regs->dmm_lisa_map_1,
+ &hw_lisa_map_regs->dmm_lisa_map_1);
+ writel(lisa_map_regs->dmm_lisa_map_0,
+ &hw_lisa_map_regs->dmm_lisa_map_0);
+
+ if (omap_revision() >= OMAP4460_ES1_0) {
+ hw_lisa_map_regs =
+ (struct dmm_lisa_map_regs *)MA_BASE;
+
+ writel(lisa_map_regs->dmm_lisa_map_3,
+ &hw_lisa_map_regs->dmm_lisa_map_3);
+ writel(lisa_map_regs->dmm_lisa_map_2,
+ &hw_lisa_map_regs->dmm_lisa_map_2);
+ writel(lisa_map_regs->dmm_lisa_map_1,
+ &hw_lisa_map_regs->dmm_lisa_map_1);
+ writel(lisa_map_regs->dmm_lisa_map_0,
+ &hw_lisa_map_regs->dmm_lisa_map_0);
+ }
+}
+
+/*
+ * SDRAM initialization:
+ * SDRAM initialization has two parts:
+ * 1. Configuring the SDRAM device
+ * 2. Update the AC timings related parameters in the EMIF module
+ * (1) should be done only once and should not be done while we are
+ * running from SDRAM.
+ * (2) can and should be done more than once if OPP changes.
+ * Particularly, this may be needed when we boot without SPL and
+ * and using Configuration Header(CH). ROM code supports only at 50% OPP
+ * at boot (low power boot). So u-boot has to switch to OPP100 and update
+ * the frequency. So,
+ * Doing (1) and (2) makes sense - first time initialization
+ * Doing (2) and not (1) makes sense - OPP change (when using CH)
+ * Doing (1) and not (2) doen't make sense
+ * See do_sdram_init() for the details
+ */
+void sdram_init(void)
+{
+ u32 in_sdram, size_prog, size_detect;
+
+ debug(">>sdram_init()\n");
+
+ if (omap_hw_init_context() == OMAP_INIT_CONTEXT_UBOOT_AFTER_SPL)
+ return;
+
+ in_sdram = running_from_sdram();
+ debug("in_sdram = %d\n", in_sdram);
+
+ if (!in_sdram)
+ bypass_dpll(&prcm->cm_clkmode_dpll_core);
+
+
+ do_sdram_init(EMIF1_BASE);
+ do_sdram_init(EMIF2_BASE);
+
+ if (!in_sdram) {
+ dmm_init(DMM_BASE);
+ emif_post_init_config(EMIF1_BASE);
+ emif_post_init_config(EMIF2_BASE);
+ }
+
+ /* for the shadow registers to take effect */
+ freq_update_core();
+
+ /* Do some testing after the init */
+ if (!in_sdram) {
+ size_prog = omap_sdram_size();
+ size_detect = get_ram_size((long *)CONFIG_SYS_SDRAM_BASE,
+ size_prog);
+ /* Compare with the size programmed */
+ if (size_detect != size_prog) {
+ printf("SDRAM: identified size not same as expected"
+ " size identified: %x expected: %x\n",
+ size_detect,
+ size_prog);
+ } else
+ debug("get_ram_size() successful");
+ }
+
+ debug("<<sdram_init()\n");
+}
diff --git a/arch/arm/cpu/armv7/omap-common/hwinit-common.c b/arch/arm/cpu/armv7/omap-common/hwinit-common.c
new file mode 100644
index 0000000..f65705d
--- /dev/null
+++ b/arch/arm/cpu/armv7/omap-common/hwinit-common.c
@@ -0,0 +1,267 @@
+/*
+ *
+ * Common functions for OMAP4/5 based boards
+ *
+ * (C) Copyright 2010
+ * Texas Instruments, <www.ti.com>
+ *
+ * Author :
+ * Aneesh V <aneesh@ti.com>
+ * Steve Sakoman <steve@sakoman.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+#include <common.h>
+#include <asm/arch/sys_proto.h>
+#include <asm/sizes.h>
+#include <asm/emif.h>
+#include <asm/omap_common.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+/*
+ * This is used to verify if the configuration header
+ * was executed by rom code prior to control of transfer
+ * to the bootloader. SPL is responsible for saving and
+ * passing the boot_params pointer to the u-boot.
+ */
+struct omap_boot_parameters boot_params __attribute__ ((section(".data")));
+
+#ifdef CONFIG_SPL_BUILD
+/*
+ * We use static variables because global data is not ready yet.
+ * Initialized data is available in SPL right from the beginning.
+ * We would not typically need to save these parameters in regular
+ * U-Boot. This is needed only in SPL at the moment.
+ */
+u32 omap_bootmode = MMCSD_MODE_FAT;
+
+u32 omap_boot_device(void)
+{
+ return (u32) (boot_params.omap_bootdevice);
+}
+
+u32 omap_boot_mode(void)
+{
+ return omap_bootmode;
+}
+#endif
+
+void do_set_mux(u32 base, struct pad_conf_entry const *array, int size)
+{
+ int i;
+ struct pad_conf_entry *pad = (struct pad_conf_entry *) array;
+
+ for (i = 0; i < size; i++, pad++)
+ writew(pad->val, base + pad->offset);
+}
+
+static void set_mux_conf_regs(void)
+{
+ switch (omap_hw_init_context()) {
+ case OMAP_INIT_CONTEXT_SPL:
+ set_muxconf_regs_essential();
+ break;
+ case OMAP_INIT_CONTEXT_UBOOT_AFTER_SPL:
+#ifdef CONFIG_SYS_ENABLE_PADS_ALL
+ set_muxconf_regs_non_essential();
+#endif
+ break;
+ case OMAP_INIT_CONTEXT_UBOOT_FROM_NOR:
+ case OMAP_INIT_CONTEXT_UBOOT_AFTER_CH:
+ set_muxconf_regs_essential();
+#ifdef CONFIG_SYS_ENABLE_PADS_ALL
+ set_muxconf_regs_non_essential();
+#endif
+ break;
+ }
+}
+
+u32 cortex_rev(void)
+{
+
+ unsigned int rev;
+
+ /* Read Main ID Register (MIDR) */
+ asm ("mrc p15, 0, %0, c0, c0, 0" : "=r" (rev));
+
+ return rev;
+}
+
+void omap_rev_string(char *omap_rev_string)
+{
+ u32 omap_rev = omap_revision();
+ u32 omap_variant = (omap_rev & 0xFFFF0000) >> 16;
+ u32 major_rev = (omap_rev & 0x00000F00) >> 8;
+ u32 minor_rev = (omap_rev & 0x000000F0) >> 4;
+
+ sprintf(omap_rev_string, "OMAP%x ES%x.%x", omap_variant, major_rev,
+ minor_rev);
+}
+
+#ifdef CONFIG_SPL_BUILD
+static void init_boot_params(void)
+{
+ boot_params_ptr = (u32 *) &boot_params;
+}
+#endif
+
+/*
+ * Routine: s_init
+ * Description: Does early system init of watchdog, muxing, andclocks
+ * Watchdog disable is done always. For the rest what gets done
+ * depends on the boot mode in which this function is executed
+ * 1. s_init of SPL running from SRAM
+ * 2. s_init of U-Boot running from FLASH
+ * 3. s_init of U-Boot loaded to SDRAM by SPL
+ * 4. s_init of U-Boot loaded to SDRAM by ROM code using the
+ * Configuration Header feature
+ * Please have a look at the respective functions to see what gets
+ * done in each of these cases
+ * This function is called with SRAM stack.
+ */
+void s_init(void)
+{
+ init_omap_revision();
+ watchdog_init();
+ set_mux_conf_regs();
+#ifdef CONFIG_SPL_BUILD
+ setup_clocks_for_console();
+ preloader_console_init();
+ do_io_settings();
+#endif
+ prcm_init();
+#ifdef CONFIG_SPL_BUILD
+ /* For regular u-boot sdram_init() is called from dram_init() */
+ sdram_init();
+ init_boot_params();
+#endif
+}
+
+/*
+ * Routine: wait_for_command_complete
+ * Description: Wait for posting to finish on watchdog
+ */
+void wait_for_command_complete(struct watchdog *wd_base)
+{
+ int pending = 1;
+ do {
+ pending = readl(&wd_base->wwps);
+ } while (pending);
+}
+
+/*
+ * Routine: watchdog_init
+ * Description: Shut down watch dogs
+ */
+void watchdog_init(void)
+{
+ struct watchdog *wd2_base = (struct watchdog *)WDT2_BASE;
+
+ writel(WD_UNLOCK1, &wd2_base->wspr);
+ wait_for_command_complete(wd2_base);
+ writel(WD_UNLOCK2, &wd2_base->wspr);
+}
+
+
+/*
+ * This function finds the SDRAM size available in the system
+ * based on DMM section configurations
+ * This is needed because the size of memory installed may be
+ * different on different versions of the board
+ */
+u32 omap_sdram_size(void)
+{
+ u32 section, i, total_size = 0, size, addr;
+
+ for (i = 0; i < 4; i++) {
+ section = __raw_readl(DMM_BASE + i*4);
+ addr = section & EMIF_SYS_ADDR_MASK;
+ /* See if the address is valid */
+ if ((addr >= DRAM_ADDR_SPACE_START) &&
+ (addr < DRAM_ADDR_SPACE_END)) {
+ size = ((section & EMIF_SYS_SIZE_MASK) >>
+ EMIF_SYS_SIZE_SHIFT);
+ size = 1 << size;
+ size *= SZ_16M;
+ total_size += size;
+ }
+ }
+
+ return total_size;
+}
+
+
+/*
+ * Routine: dram_init
+ * Description: sets uboots idea of sdram size
+ */
+int dram_init(void)
+{
+ sdram_init();
+ gd->ram_size = omap_sdram_size();
+ return 0;
+}
+
+/*
+ * Print board information
+ */
+int checkboard(void)
+{
+ puts(sysinfo.board_string);
+ return 0;
+}
+
+/*
+* This function is called by start_armboot. You can reliably use static
+* data. Any boot-time function that require static data should be
+* called from here
+*/
+int arch_cpu_init(void)
+{
+ return 0;
+}
+
+/*
+ * get_device_type(): tell if GP/HS/EMU/TST
+ */
+u32 get_device_type(void)
+{
+ return 0;
+}
+
+/*
+ * Print CPU information
+ */
+int print_cpuinfo(void)
+{
+ char rev_string_buffer[50];
+
+ omap_rev_string(rev_string_buffer);
+ printf("CPU : %s\n", rev_string_buffer);
+
+ return 0;
+}
+#ifndef CONFIG_SYS_DCACHE_OFF
+void enable_caches(void)
+{
+ /* Enable D-cache. I-cache is already enabled in start.S */
+ dcache_enable();
+}
+#endif
diff --git a/arch/arm/cpu/armv7/omap4/lowlevel_init.S b/arch/arm/cpu/armv7/omap-common/lowlevel_init.S
similarity index 76%
rename from arch/arm/cpu/armv7/omap4/lowlevel_init.S
rename to arch/arm/cpu/armv7/omap-common/lowlevel_init.S
index 91525ec..35f38ac 100644
--- a/arch/arm/cpu/armv7/omap4/lowlevel_init.S
+++ b/arch/arm/cpu/armv7/omap-common/lowlevel_init.S
@@ -26,8 +26,8 @@
* MA 02111-1307 USA
*/
-#include <asm/arch/omap4.h>
-#ifdef CONFIG_SPL_BUILD
+#include <asm/arch/omap.h>
+
.global save_boot_params
save_boot_params:
/*
@@ -43,21 +43,40 @@
cmp r2, r0
blt 1f
- /* Store the boot device in omap4_boot_device */
- ldr r2, [r0, #BOOT_DEVICE_OFFSET] @ r1 <- value of boot device
+ /*
+ * store the boot params passed from rom code or saved
+ * and passed by SPL
+ */
+ cmp r0, #0
+ beq 1f
+ ldr r1, =boot_params
+ str r0, [r1]
+#ifdef CONFIG_SPL_BUILD
+ /* Store the boot device in omap_boot_device */
+ ldrb r2, [r0, #BOOT_DEVICE_OFFSET] @ r1 <- value of boot device
and r2, #BOOT_DEVICE_MASK
- ldr r3, =omap4_boot_device
- str r2, [r3] @ omap4_boot_device <- r1
+ ldr r3, =boot_params
+ strb r2, [r3, #BOOT_DEVICE_OFFSET] @ omap_boot_device <- r1
- /* Store the boot mode (raw/FAT) in omap4_boot_mode */
+ /* boot mode is passed only for devices that can raw/fat mode */
+ cmp r2, #2
+ blt 2f
+ cmp r2, #7
+ bgt 2f
+ /* Store the boot mode (raw/FAT) in omap_boot_mode */
ldr r2, [r0, #DEV_DESC_PTR_OFFSET] @ get the device descriptor ptr
ldr r2, [r2, #DEV_DATA_PTR_OFFSET] @ get the pDeviceData ptr
ldr r2, [r2, #BOOT_MODE_OFFSET] @ get the boot mode
- ldr r3, =omap4_boot_mode
+ ldr r3, =omap_bootmode
str r2, [r3]
+#endif
+2:
+ ldrb r2, [r0, #CH_FLAGS_OFFSET]
+ ldr r3, =boot_params
+ strb r2, [r3, #CH_FLAGS_OFFSET]
1:
bx lr
-#endif
+
.globl lowlevel_init
lowlevel_init:
diff --git a/arch/arm/cpu/armv7/omap4/mem.c b/arch/arm/cpu/armv7/omap-common/mem-common.c
similarity index 100%
rename from arch/arm/cpu/armv7/omap4/mem.c
rename to arch/arm/cpu/armv7/omap-common/mem-common.c
diff --git a/arch/arm/cpu/armv7/omap-common/spl.c b/arch/arm/cpu/armv7/omap-common/spl.c
index 2c59d2b..d6d7d65 100644
--- a/arch/arm/cpu/armv7/omap-common/spl.c
+++ b/arch/arm/cpu/armv7/omap-common/spl.c
@@ -38,6 +38,7 @@
DECLARE_GLOBAL_DATA_PTR;
+u32* boot_params_ptr = NULL;
struct spl_image_info spl_image;
/* Define global data structure pointer to it*/
@@ -92,12 +93,16 @@
static void jump_to_image_no_args(void)
{
- typedef void (*image_entry_noargs_t)(void)__attribute__ ((noreturn));
+ typedef void (*image_entry_noargs_t)(u32 *)__attribute__ ((noreturn));
image_entry_noargs_t image_entry =
(image_entry_noargs_t) spl_image.entry_point;
debug("image entry point: 0x%X\n", spl_image.entry_point);
- image_entry();
+ /* Pass the saved boot_params from rom code */
+#if defined(CONFIG_VIRTIO) || defined(CONFIG_ZEBU)
+ image_entry = 0x80100000;
+#endif
+ image_entry((u32 *)&boot_params_ptr);
}
void jump_to_image_no_args(void) __attribute__ ((noreturn));
diff --git a/arch/arm/cpu/armv7/omap4/Makefile b/arch/arm/cpu/armv7/omap4/Makefile
index e7ee0b8..83160a2 100644
--- a/arch/arm/cpu/armv7/omap4/Makefile
+++ b/arch/arm/cpu/armv7/omap4/Makefile
@@ -25,17 +25,10 @@
LIB = $(obj)lib$(SOC).o
-SOBJS += lowlevel_init.o
-
-COBJS += board.o
+COBJS += sdram_elpida.o
+COBJS += hwinit.o
COBJS += clocks.o
COBJS += emif.o
-COBJS += sdram_elpida.o
-
-ifndef CONFIG_SPL_BUILD
-COBJS += mem.o
-COBJS += sys_info.o
-endif
SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c)
OBJS := $(addprefix $(obj),$(COBJS) $(SOBJS))
diff --git a/arch/arm/cpu/armv7/omap4/board.c b/arch/arm/cpu/armv7/omap4/board.c
deleted file mode 100644
index 2497e3e..0000000
--- a/arch/arm/cpu/armv7/omap4/board.c
+++ /dev/null
@@ -1,384 +0,0 @@
-/*
- *
- * Common functions for OMAP4 based boards
- *
- * (C) Copyright 2010
- * Texas Instruments, <www.ti.com>
- *
- * Author :
- * Aneesh V <aneesh@ti.com>
- * Steve Sakoman <steve@sakoman.com>
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-#include <common.h>
-#include <asm/armv7.h>
-#include <asm/arch/cpu.h>
-#include <asm/arch/sys_proto.h>
-#include <asm/sizes.h>
-#include <asm/arch/emif.h>
-#include <asm/arch/gpio.h>
-#include "omap4_mux_data.h"
-
-DECLARE_GLOBAL_DATA_PTR;
-
-u32 *const omap4_revision = (u32 *)OMAP4_SRAM_SCRATCH_OMAP4_REV;
-
-static const struct gpio_bank gpio_bank_44xx[6] = {
- { (void *)OMAP44XX_GPIO1_BASE, METHOD_GPIO_24XX },
- { (void *)OMAP44XX_GPIO2_BASE, METHOD_GPIO_24XX },
- { (void *)OMAP44XX_GPIO3_BASE, METHOD_GPIO_24XX },
- { (void *)OMAP44XX_GPIO4_BASE, METHOD_GPIO_24XX },
- { (void *)OMAP44XX_GPIO5_BASE, METHOD_GPIO_24XX },
- { (void *)OMAP44XX_GPIO6_BASE, METHOD_GPIO_24XX },
-};
-
-const struct gpio_bank *const omap_gpio_bank = gpio_bank_44xx;
-
-#ifdef CONFIG_SPL_BUILD
-/*
- * We use static variables because global data is not ready yet.
- * Initialized data is available in SPL right from the beginning.
- * We would not typically need to save these parameters in regular
- * U-Boot. This is needed only in SPL at the moment.
- */
-u32 omap4_boot_device = BOOT_DEVICE_MMC1;
-u32 omap4_boot_mode = MMCSD_MODE_FAT;
-
-u32 omap_boot_device(void)
-{
- return omap4_boot_device;
-}
-
-u32 omap_boot_mode(void)
-{
- return omap4_boot_mode;
-}
-
-/*
- * Some tuning of IOs for optimal power and performance
- */
-static void do_io_settings(void)
-{
- u32 lpddr2io;
- struct control_lpddr2io_regs *lpddr2io_regs =
- (struct control_lpddr2io_regs *)LPDDR2_IO_REGS_BASE;
- struct omap4_sys_ctrl_regs *const ctrl =
- (struct omap4_sys_ctrl_regs *)SYSCTRL_GENERAL_CORE_BASE;
-
- u32 omap4_rev = omap_revision();
-
- if (omap4_rev == OMAP4430_ES1_0)
- lpddr2io = CONTROL_LPDDR2IO_SLEW_125PS_DRV8_PULL_DOWN;
- else if (omap4_rev == OMAP4430_ES2_0)
- lpddr2io = CONTROL_LPDDR2IO_SLEW_325PS_DRV8_GATE_KEEPER;
- else
- lpddr2io = CONTROL_LPDDR2IO_SLEW_315PS_DRV12_PULL_DOWN;
-
- /* EMIF1 */
- writel(lpddr2io, &lpddr2io_regs->control_lpddr2io1_0);
- writel(lpddr2io, &lpddr2io_regs->control_lpddr2io1_1);
- /* No pull for GR10 as per hw team's recommendation */
- writel(lpddr2io & ~LPDDR2IO_GR10_WD_MASK,
- &lpddr2io_regs->control_lpddr2io1_2);
- writel(CONTROL_LPDDR2IO_3_VAL, &lpddr2io_regs->control_lpddr2io1_3);
-
- /* EMIF2 */
- writel(lpddr2io, &lpddr2io_regs->control_lpddr2io2_0);
- writel(lpddr2io, &lpddr2io_regs->control_lpddr2io2_1);
- /* No pull for GR10 as per hw team's recommendation */
- writel(lpddr2io & ~LPDDR2IO_GR10_WD_MASK,
- &lpddr2io_regs->control_lpddr2io2_2);
- writel(CONTROL_LPDDR2IO_3_VAL, &lpddr2io_regs->control_lpddr2io2_3);
-
- /*
- * Some of these settings (TRIM values) come from eFuse and are
- * in turn programmed in the eFuse at manufacturing time after
- * calibration of the device. Do the software over-ride only if
- * the device is not correctly trimmed
- */
- if (!(readl(&ctrl->control_std_fuse_opp_bgap) & 0xFFFF)) {
-
- writel(LDOSRAM_VOLT_CTRL_OVERRIDE,
- &ctrl->control_ldosram_iva_voltage_ctrl);
-
- writel(LDOSRAM_VOLT_CTRL_OVERRIDE,
- &ctrl->control_ldosram_mpu_voltage_ctrl);
-
- writel(LDOSRAM_VOLT_CTRL_OVERRIDE,
- &ctrl->control_ldosram_core_voltage_ctrl);
- }
-
- if (!readl(&ctrl->control_efuse_1))
- writel(CONTROL_EFUSE_1_OVERRIDE, &ctrl->control_efuse_1);
-
- if (!readl(&ctrl->control_efuse_2))
- writel(CONTROL_EFUSE_2_OVERRIDE, &ctrl->control_efuse_2);
-}
-#endif
-
-void do_set_mux(u32 base, struct pad_conf_entry const *array, int size)
-{
- int i;
- struct pad_conf_entry *pad = (struct pad_conf_entry *) array;
-
- for (i = 0; i < size; i++, pad++)
- writew(pad->val, base + pad->offset);
-}
-
-static void set_muxconf_regs_essential(void)
-{
- do_set_mux(CONTROL_PADCONF_CORE, core_padconf_array_essential,
- sizeof(core_padconf_array_essential) /
- sizeof(struct pad_conf_entry));
-
- do_set_mux(CONTROL_PADCONF_WKUP, wkup_padconf_array_essential,
- sizeof(wkup_padconf_array_essential) /
- sizeof(struct pad_conf_entry));
-
- if (omap_revision() >= OMAP4460_ES1_0)
- do_set_mux(CONTROL_PADCONF_WKUP,
- wkup_padconf_array_essential_4460,
- sizeof(wkup_padconf_array_essential_4460) /
- sizeof(struct pad_conf_entry));
-}
-
-static void set_mux_conf_regs(void)
-{
- switch (omap4_hw_init_context()) {
- case OMAP_INIT_CONTEXT_SPL:
- set_muxconf_regs_essential();
- break;
- case OMAP_INIT_CONTEXT_UBOOT_AFTER_SPL:
- set_muxconf_regs_non_essential();
- break;
- case OMAP_INIT_CONTEXT_UBOOT_FROM_NOR:
- case OMAP_INIT_CONTEXT_UBOOT_AFTER_CH:
- set_muxconf_regs_essential();
- set_muxconf_regs_non_essential();
- break;
- }
-}
-
-static u32 cortex_a9_rev(void)
-{
-
- unsigned int rev;
-
- /* Read Main ID Register (MIDR) */
- asm ("mrc p15, 0, %0, c0, c0, 0" : "=r" (rev));
-
- return rev;
-}
-
-static void init_omap4_revision(void)
-{
- /*
- * For some of the ES2/ES1 boards ID_CODE is not reliable:
- * Also, ES1 and ES2 have different ARM revisions
- * So use ARM revision for identification
- */
- unsigned int arm_rev = cortex_a9_rev();
-
- switch (arm_rev) {
- case MIDR_CORTEX_A9_R0P1:
- *omap4_revision = OMAP4430_ES1_0;
- break;
- case MIDR_CORTEX_A9_R1P2:
- switch (readl(CONTROL_ID_CODE)) {
- case OMAP4430_CONTROL_ID_CODE_ES2_0:
- *omap4_revision = OMAP4430_ES2_0;
- break;
- case OMAP4430_CONTROL_ID_CODE_ES2_1:
- *omap4_revision = OMAP4430_ES2_1;
- break;
- case OMAP4430_CONTROL_ID_CODE_ES2_2:
- *omap4_revision = OMAP4430_ES2_2;
- break;
- default:
- *omap4_revision = OMAP4430_ES2_0;
- break;
- }
- break;
- case MIDR_CORTEX_A9_R1P3:
- *omap4_revision = OMAP4430_ES2_3;
- break;
- case MIDR_CORTEX_A9_R2P10:
- switch (readl(CONTROL_ID_CODE)) {
- case OMAP4460_CONTROL_ID_CODE_ES1_0:
- *omap4_revision = OMAP4460_ES1_0;
- break;
- case OMAP4460_CONTROL_ID_CODE_ES1_1:
- *omap4_revision = OMAP4460_ES1_1;
- break;
- default:
- *omap4_revision = OMAP4460_ES1_0;
- break;
- }
- break;
- default:
- *omap4_revision = OMAP4430_SILICON_ID_INVALID;
- break;
- }
-}
-
-void omap_rev_string(char *omap4_rev_string)
-{
- u32 omap4_rev = omap_revision();
- u32 omap4_variant = (omap4_rev & 0xFFFF0000) >> 16;
- u32 major_rev = (omap4_rev & 0x00000F00) >> 8;
- u32 minor_rev = (omap4_rev & 0x000000F0) >> 4;
-
- sprintf(omap4_rev_string, "OMAP%x ES%x.%x", omap4_variant, major_rev,
- minor_rev);
-}
-
-/*
- * Routine: s_init
- * Description: Does early system init of watchdog, muxing, andclocks
- * Watchdog disable is done always. For the rest what gets done
- * depends on the boot mode in which this function is executed
- * 1. s_init of SPL running from SRAM
- * 2. s_init of U-Boot running from FLASH
- * 3. s_init of U-Boot loaded to SDRAM by SPL
- * 4. s_init of U-Boot loaded to SDRAM by ROM code using the
- * Configuration Header feature
- * Please have a look at the respective functions to see what gets
- * done in each of these cases
- * This function is called with SRAM stack.
- */
-void s_init(void)
-{
- init_omap4_revision();
- watchdog_init();
- set_mux_conf_regs();
-#ifdef CONFIG_SPL_BUILD
- setup_clocks_for_console();
- preloader_console_init();
- do_io_settings();
-#endif
- prcm_init();
-#ifdef CONFIG_SPL_BUILD
- /* For regular u-boot sdram_init() is called from dram_init() */
- sdram_init();
-#endif
-}
-
-/*
- * Routine: wait_for_command_complete
- * Description: Wait for posting to finish on watchdog
- */
-void wait_for_command_complete(struct watchdog *wd_base)
-{
- int pending = 1;
- do {
- pending = readl(&wd_base->wwps);
- } while (pending);
-}
-
-/*
- * Routine: watchdog_init
- * Description: Shut down watch dogs
- */
-void watchdog_init(void)
-{
- struct watchdog *wd2_base = (struct watchdog *)WDT2_BASE;
-
- writel(WD_UNLOCK1, &wd2_base->wspr);
- wait_for_command_complete(wd2_base);
- writel(WD_UNLOCK2, &wd2_base->wspr);
-}
-
-
-/*
- * This function finds the SDRAM size available in the system
- * based on DMM section configurations
- * This is needed because the size of memory installed may be
- * different on different versions of the board
- */
-u32 omap4_sdram_size(void)
-{
- u32 section, i, total_size = 0, size, addr;
- for (i = 0; i < 4; i++) {
- section = __raw_readl(OMAP44XX_DMM_LISA_MAP_BASE + i*4);
- addr = section & OMAP44XX_SYS_ADDR_MASK;
- /* See if the address is valid */
- if ((addr >= OMAP44XX_DRAM_ADDR_SPACE_START) &&
- (addr < OMAP44XX_DRAM_ADDR_SPACE_END)) {
- size = ((section & OMAP44XX_SYS_SIZE_MASK) >>
- OMAP44XX_SYS_SIZE_SHIFT);
- size = 1 << size;
- size *= SZ_16M;
- total_size += size;
- }
- }
- return total_size;
-}
-
-
-/*
- * Routine: dram_init
- * Description: sets uboots idea of sdram size
- */
-int dram_init(void)
-{
- sdram_init();
- gd->ram_size = omap4_sdram_size();
-
- return 0;
-}
-
-/*
- * Print board information
- */
-int checkboard(void)
-{
- puts(sysinfo.board_string);
- return 0;
-}
-
-/*
-* This function is called by start_armboot. You can reliably use static
-* data. Any boot-time function that require static data should be
-* called from here
-*/
-int arch_cpu_init(void)
-{
- return 0;
-}
-
-#ifndef CONFIG_SYS_L2CACHE_OFF
-void v7_outer_cache_enable(void)
-{
- set_pl310_ctrl_reg(1);
-}
-
-void v7_outer_cache_disable(void)
-{
- set_pl310_ctrl_reg(0);
-}
-#endif
-
-#ifndef CONFIG_SYS_DCACHE_OFF
-void enable_caches(void)
-{
- /* Enable D-cache. I-cache is already enabled in start.S */
- dcache_enable();
-}
-#endif
diff --git a/arch/arm/cpu/armv7/omap4/clocks.c b/arch/arm/cpu/armv7/omap4/clocks.c
index 095ba39..0886f92 100644
--- a/arch/arm/cpu/armv7/omap4/clocks.c
+++ b/arch/arm/cpu/armv7/omap4/clocks.c
@@ -50,7 +50,7 @@
struct omap4_prcm_regs *const prcm = (struct omap4_prcm_regs *)0x4A004100;
-static const u32 sys_clk_array[8] = {
+const u32 sys_clk_array[8] = {
12000000, /* 12 MHz */
13000000, /* 13 MHz */
16800000, /* 16.8 MHz */
@@ -79,14 +79,14 @@
};
/* dpll locked at 1584 MHz - MPU clk at 792 MHz(OPP Turbo 4430) */
-static const struct dpll_params mpu_dpll_params_1584mhz[NUM_SYS_CLKS] = {
- {66, 0, 1, -1, -1, -1, -1, -1}, /* 12 MHz */
- {792, 12, 1, -1, -1, -1, -1, -1}, /* 13 MHz */
- {330, 6, 1, -1, -1, -1, -1, -1}, /* 16.8 MHz */
- {165, 3, 1, -1, -1, -1, -1, -1}, /* 19.2 MHz */
- {396, 12, 1, -1, -1, -1, -1, -1}, /* 26 MHz */
- {88, 2, 1, -1, -1, -1, -1, -1}, /* 27 MHz */
- {165, 7, 1, -1, -1, -1, -1, -1} /* 38.4 MHz */
+static const struct dpll_params mpu_dpll_params_1600mhz[NUM_SYS_CLKS] = {
+ {200, 2, 1, -1, -1, -1, -1, -1}, /* 12 MHz */
+ {800, 12, 1, -1, -1, -1, -1, -1}, /* 13 MHz */
+ {619, 12, 1, -1, -1, -1, -1, -1}, /* 16.8 MHz */
+ {125, 2, 1, -1, -1, -1, -1, -1}, /* 19.2 MHz */
+ {400, 12, 1, -1, -1, -1, -1, -1}, /* 26 MHz */
+ {800, 26, 1, -1, -1, -1, -1, -1}, /* 27 MHz */
+ {125, 5, 1, -1, -1, -1, -1, -1} /* 38.4 MHz */
};
/* dpll locked at 1200 MHz - MPU clk at 600 MHz */
@@ -168,7 +168,6 @@
750, 0, 1, 1, -1, -1, -1, -1
};
-
static const struct dpll_params usb_dpll_params_1920mhz[NUM_SYS_CLKS] = {
{80, 0, 2, -1, -1, -1, -1, -1}, /* 12 MHz */
{960, 12, 2, -1, -1, -1, -1, -1}, /* 13 MHz */
@@ -179,98 +178,10 @@
{25, 0, 2, -1, -1, -1, -1, -1} /* 38.4 MHz */
};
-static inline u32 __get_sys_clk_index(void)
-{
- u32 ind;
- /*
- * For ES1 the ROM code calibration of sys clock is not reliable
- * due to hw issue. So, use hard-coded value. If this value is not
- * correct for any board over-ride this function in board file
- * From ES2.0 onwards you will get this information from
- * CM_SYS_CLKSEL
- */
- if (omap_revision() == OMAP4430_ES1_0)
- ind = OMAP_SYS_CLK_IND_38_4_MHZ;
- else {
- /* SYS_CLKSEL - 1 to match the dpll param array indices */
- ind = (readl(&prcm->cm_sys_clksel) &
- CM_SYS_CLKSEL_SYS_CLKSEL_MASK) - 1;
- }
- return ind;
-}
-
-u32 get_sys_clk_index(void)
- __attribute__ ((weak, alias("__get_sys_clk_index")));
-
-u32 get_sys_clk_freq(void)
-{
- u8 index = get_sys_clk_index();
- return sys_clk_array[index];
-}
-
-static inline void do_bypass_dpll(u32 *const base)
-{
- struct dpll_regs *dpll_regs = (struct dpll_regs *)base;
-
- clrsetbits_le32(&dpll_regs->cm_clkmode_dpll,
- CM_CLKMODE_DPLL_DPLL_EN_MASK,
- DPLL_EN_FAST_RELOCK_BYPASS <<
- CM_CLKMODE_DPLL_EN_SHIFT);
-}
-
-static inline void wait_for_bypass(u32 *const base)
+void setup_post_dividers(u32 *const base, const struct dpll_params *params)
{
struct dpll_regs *const dpll_regs = (struct dpll_regs *)base;
- if (!wait_on_value(ST_DPLL_CLK_MASK, 0, &dpll_regs->cm_idlest_dpll,
- LDELAY)) {
- printf("Bypassing DPLL failed %p\n", base);
- }
-}
-
-static inline void do_lock_dpll(u32 *const base)
-{
- struct dpll_regs *const dpll_regs = (struct dpll_regs *)base;
-
- clrsetbits_le32(&dpll_regs->cm_clkmode_dpll,
- CM_CLKMODE_DPLL_DPLL_EN_MASK,
- DPLL_EN_LOCK << CM_CLKMODE_DPLL_EN_SHIFT);
-}
-
-static inline void wait_for_lock(u32 *const base)
-{
- struct dpll_regs *const dpll_regs = (struct dpll_regs *)base;
-
- if (!wait_on_value(ST_DPLL_CLK_MASK, ST_DPLL_CLK_MASK,
- &dpll_regs->cm_idlest_dpll, LDELAY)) {
- printf("DPLL locking failed for %p\n", base);
- hang();
- }
-}
-
-static void do_setup_dpll(u32 *const base, const struct dpll_params *params,
- u8 lock)
-{
- u32 temp;
- struct dpll_regs *const dpll_regs = (struct dpll_regs *)base;
-
- bypass_dpll(base);
-
- /* Set M & N */
- temp = readl(&dpll_regs->cm_clksel_dpll);
-
- temp &= ~CM_CLKSEL_DPLL_M_MASK;
- temp |= (params->m << CM_CLKSEL_DPLL_M_SHIFT) & CM_CLKSEL_DPLL_M_MASK;
-
- temp &= ~CM_CLKSEL_DPLL_N_MASK;
- temp |= (params->n << CM_CLKSEL_DPLL_N_SHIFT) & CM_CLKSEL_DPLL_N_MASK;
-
- writel(temp, &dpll_regs->cm_clksel_dpll);
-
- /* Lock */
- if (lock)
- do_lock_dpll(base);
-
/* Setup post-dividers */
if (params->m2 >= 0)
writel(params->m2, &dpll_regs->cm_div_m2_dpll);
@@ -284,10 +195,29 @@
writel(params->m6, &dpll_regs->cm_div_m6_dpll);
if (params->m7 >= 0)
writel(params->m7, &dpll_regs->cm_div_m7_dpll);
+}
- /* Wait till the DPLL locks */
- if (lock)
- wait_for_lock(base);
+/*
+ * Lock MPU dpll
+ *
+ * Resulting MPU frequencies:
+ * 4430 ES1.0 : 600 MHz
+ * 4430 ES2.x : 792 MHz (OPP Turbo)
+ * 4460 : 920 MHz (OPP Turbo) - DCC disabled
+ */
+const struct dpll_params *get_mpu_dpll_params(void)
+{
+ u32 omap_rev, sysclk_ind;
+
+ omap_rev = omap_revision();
+ sysclk_ind = get_sys_clk_index();
+
+ if (omap_rev == OMAP4430_ES1_0)
+ return &mpu_dpll_params_1200mhz[sysclk_ind];
+ else if (omap_rev < OMAP4460_ES1_0)
+ return &mpu_dpll_params_1600mhz[sysclk_ind];
+ else
+ return &mpu_dpll_params_1840mhz[sysclk_ind];
}
const struct dpll_params *get_core_dpll_params(void)
@@ -306,228 +236,33 @@
}
}
-u32 omap4_ddr_clk(void)
+
+const struct dpll_params *get_per_dpll_params(void)
{
- u32 ddr_clk, sys_clk_khz;
- const struct dpll_params *core_dpll_params;
-
- sys_clk_khz = get_sys_clk_freq() / 1000;
-
- core_dpll_params = get_core_dpll_params();
-
- debug("sys_clk %d\n ", sys_clk_khz * 1000);
-
- /* Find Core DPLL locked frequency first */
- ddr_clk = sys_clk_khz * 2 * core_dpll_params->m /
- (core_dpll_params->n + 1);
- /*
- * DDR frequency is PHY_ROOT_CLK/2
- * PHY_ROOT_CLK = Fdpll/2/M2
- */
- ddr_clk = ddr_clk / 4 / core_dpll_params->m2;
-
- ddr_clk *= 1000; /* convert to Hz */
- debug("ddr_clk %d\n ", ddr_clk);
-
- return ddr_clk;
+ u32 sysclk_ind = get_sys_clk_index();
+ return &per_dpll_params_1536mhz[sysclk_ind];
}
-/*
- * Lock MPU dpll
- *
- * Resulting MPU frequencies:
- * 4430 ES1.0 : 600 MHz
- * 4430 ES2.x : 792 MHz (OPP Turbo)
- * 4460 : 920 MHz (OPP Turbo) - DCC disabled
- */
-void configure_mpu_dpll(void)
+const struct dpll_params *get_iva_dpll_params(void)
{
- const struct dpll_params *params;
- struct dpll_regs *mpu_dpll_regs;
- u32 omap4_rev, sysclk_ind;
-
- omap4_rev = omap_revision();
- sysclk_ind = get_sys_clk_index();
-
- if (omap4_rev == OMAP4430_ES1_0)
- params = &mpu_dpll_params_1200mhz[sysclk_ind];
- else if (omap4_rev < OMAP4460_ES1_0)
- params = &mpu_dpll_params_1584mhz[sysclk_ind];
- else
- params = &mpu_dpll_params_1840mhz[sysclk_ind];
-
- /* DCC and clock divider settings for 4460 */
- if (omap4_rev >= OMAP4460_ES1_0) {
- mpu_dpll_regs =
- (struct dpll_regs *)&prcm->cm_clkmode_dpll_mpu;
- bypass_dpll(&prcm->cm_clkmode_dpll_mpu);
- clrbits_le32(&prcm->cm_mpu_mpu_clkctrl,
- MPU_CLKCTRL_CLKSEL_EMIF_DIV_MODE_MASK);
- setbits_le32(&prcm->cm_mpu_mpu_clkctrl,
- MPU_CLKCTRL_CLKSEL_ABE_DIV_MODE_MASK);
- clrbits_le32(&mpu_dpll_regs->cm_clksel_dpll,
- CM_CLKSEL_DCC_EN_MASK);
- }
-
- do_setup_dpll(&prcm->cm_clkmode_dpll_mpu, params, DPLL_LOCK);
- debug("MPU DPLL locked\n");
+ u32 sysclk_ind = get_sys_clk_index();
+ return &iva_dpll_params_1862mhz[sysclk_ind];
}
-static void setup_dplls(void)
+const struct dpll_params *get_usb_dpll_params(void)
{
- u32 sysclk_ind, temp;
- const struct dpll_params *params;
- debug("setup_dplls\n");
-
- sysclk_ind = get_sys_clk_index();
-
- /* CORE dpll */
- params = get_core_dpll_params(); /* default - safest */
- /*
- * Do not lock the core DPLL now. Just set it up.
- * Core DPLL will be locked after setting up EMIF
- * using the FREQ_UPDATE method(freq_update_core())
- */
- do_setup_dpll(&prcm->cm_clkmode_dpll_core, params, DPLL_NO_LOCK);
- /* Set the ratios for CORE_CLK, L3_CLK, L4_CLK */
- temp = (CLKSEL_CORE_X2_DIV_1 << CLKSEL_CORE_SHIFT) |
- (CLKSEL_L3_CORE_DIV_2 << CLKSEL_L3_SHIFT) |
- (CLKSEL_L4_L3_DIV_2 << CLKSEL_L4_SHIFT);
- writel(temp, &prcm->cm_clksel_core);
- debug("Core DPLL configured\n");
-
- /* lock PER dpll */
- do_setup_dpll(&prcm->cm_clkmode_dpll_per,
- &per_dpll_params_1536mhz[sysclk_ind], DPLL_LOCK);
- debug("PER DPLL locked\n");
-
- /* MPU dpll */
- configure_mpu_dpll();
+ u32 sysclk_ind = get_sys_clk_index();
+ return &usb_dpll_params_1920mhz[sysclk_ind];
}
-static void setup_non_essential_dplls(void)
+const struct dpll_params *get_abe_dpll_params(void)
{
- u32 sys_clk_khz, abe_ref_clk;
- u32 sysclk_ind, sd_div, num, den;
- const struct dpll_params *params;
-
- sysclk_ind = get_sys_clk_index();
- sys_clk_khz = get_sys_clk_freq() / 1000;
-
- /* IVA */
- clrsetbits_le32(&prcm->cm_bypclk_dpll_iva,
- CM_BYPCLK_DPLL_IVA_CLKSEL_MASK, DPLL_IVA_CLKSEL_CORE_X2_DIV_2);
-
- do_setup_dpll(&prcm->cm_clkmode_dpll_iva,
- &iva_dpll_params_1862mhz[sysclk_ind], DPLL_LOCK);
-
- /*
- * USB:
- * USB dpll is J-type. Need to set DPLL_SD_DIV for jitter correction
- * DPLL_SD_DIV = CEILING ([DPLL_MULT/(DPLL_DIV+1)]* CLKINP / 250)
- * - where CLKINP is sys_clk in MHz
- * Use CLKINP in KHz and adjust the denominator accordingly so
- * that we have enough accuracy and at the same time no overflow
- */
- params = &usb_dpll_params_1920mhz[sysclk_ind];
- num = params->m * sys_clk_khz;
- den = (params->n + 1) * 250 * 1000;
- num += den - 1;
- sd_div = num / den;
- clrsetbits_le32(&prcm->cm_clksel_dpll_usb,
- CM_CLKSEL_DPLL_DPLL_SD_DIV_MASK,
- sd_div << CM_CLKSEL_DPLL_DPLL_SD_DIV_SHIFT);
-
- /* Now setup the dpll with the regular function */
- do_setup_dpll(&prcm->cm_clkmode_dpll_usb, params, DPLL_LOCK);
-
-#ifdef CONFIG_SYS_OMAP4_ABE_SYSCK
- params = &abe_dpll_params_sysclk_196608khz[sysclk_ind];
- abe_ref_clk = CM_ABE_PLL_REF_CLKSEL_CLKSEL_SYSCLK;
+#ifdef CONFIG_SYS_OMAP_ABE_SYSCK
+ u32 sysclk_ind = get_sys_clk_index();
+ return &abe_dpll_params_sysclk_196608khz[sysclk_ind];
#else
- params = &abe_dpll_params_32k_196608khz;
- abe_ref_clk = CM_ABE_PLL_REF_CLKSEL_CLKSEL_32KCLK;
- /*
- * We need to enable some additional options to achieve
- * 196.608MHz from 32768 Hz
- */
- setbits_le32(&prcm->cm_clkmode_dpll_abe,
- CM_CLKMODE_DPLL_DRIFTGUARD_EN_MASK|
- CM_CLKMODE_DPLL_RELOCK_RAMP_EN_MASK|
- CM_CLKMODE_DPLL_LPMODE_EN_MASK|
- CM_CLKMODE_DPLL_REGM4XEN_MASK);
- /* Spend 4 REFCLK cycles at each stage */
- clrsetbits_le32(&prcm->cm_clkmode_dpll_abe,
- CM_CLKMODE_DPLL_RAMP_RATE_MASK,
- 1 << CM_CLKMODE_DPLL_RAMP_RATE_SHIFT);
+ return &abe_dpll_params_32k_196608khz;
#endif
-
- /* Select the right reference clk */
- clrsetbits_le32(&prcm->cm_abe_pll_ref_clksel,
- CM_ABE_PLL_REF_CLKSEL_CLKSEL_MASK,
- abe_ref_clk << CM_ABE_PLL_REF_CLKSEL_CLKSEL_SHIFT);
- /* Lock the dpll */
- do_setup_dpll(&prcm->cm_clkmode_dpll_abe, params, DPLL_LOCK);
-}
-
-static void do_scale_tps62361(u32 reg, u32 volt_mv)
-{
- u32 temp, step;
-
- step = volt_mv - TPS62361_BASE_VOLT_MV;
- step /= 10;
-
- /*
- * Select SET1 in TPS62361:
- * VSEL1 is grounded on board. So the following selects
- * VSEL1 = 0 and VSEL0 = 1
- */
- gpio_direction_output(TPS62361_VSEL0_GPIO, 0);
- gpio_set_value(TPS62361_VSEL0_GPIO, 1);
-
- temp = TPS62361_I2C_SLAVE_ADDR |
- (reg << PRM_VC_VAL_BYPASS_REGADDR_SHIFT) |
- (step << PRM_VC_VAL_BYPASS_DATA_SHIFT) |
- PRM_VC_VAL_BYPASS_VALID_BIT;
- debug("do_scale_tps62361: volt - %d step - 0x%x\n", volt_mv, step);
-
- writel(temp, &prcm->prm_vc_val_bypass);
- if (!wait_on_value(PRM_VC_VAL_BYPASS_VALID_BIT, 0,
- &prcm->prm_vc_val_bypass, LDELAY)) {
- puts("Scaling voltage failed for vdd_mpu from TPS\n");
- }
-}
-
-static void do_scale_vcore(u32 vcore_reg, u32 volt_mv)
-{
- u32 temp, offset_code;
- u32 step = 12660; /* 12.66 mV represented in uV */
- u32 offset = volt_mv;
-
- /* convert to uV for better accuracy in the calculations */
- offset *= 1000;
-
- if (omap_revision() == OMAP4430_ES1_0)
- offset -= PHOENIX_SMPS_BASE_VOLT_STD_MODE_UV;
- else
- offset -= PHOENIX_SMPS_BASE_VOLT_STD_MODE_WITH_OFFSET_UV;
-
- offset_code = (offset + step - 1) / step;
- /* The code starts at 1 not 0 */
- offset_code++;
-
- debug("do_scale_vcore: volt - %d offset_code - 0x%x\n", volt_mv,
- offset_code);
-
- temp = SMPS_I2C_SLAVE_ADDR |
- (vcore_reg << PRM_VC_VAL_BYPASS_REGADDR_SHIFT) |
- (offset_code << PRM_VC_VAL_BYPASS_DATA_SHIFT) |
- PRM_VC_VAL_BYPASS_VALID_BIT;
- writel(temp, &prcm->prm_vc_val_bypass);
- if (!wait_on_value(PRM_VC_VAL_BYPASS_VALID_BIT, 0,
- &prcm->prm_vc_val_bypass, LDELAY)) {
- printf("Scaling voltage failed for 0x%x\n", vcore_reg);
- }
}
/*
@@ -536,32 +271,16 @@
* enabled in bootloader. Voltage initialization in the kernel will set
* these to the nominal values after enabling Smart-Reflex
*/
-static void scale_vcores(void)
+void scale_vcores(void)
{
- u32 volt, sys_clk_khz, cycles_hi, cycles_low, temp, omap4_rev;
+ u32 volt, omap_rev;
- sys_clk_khz = get_sys_clk_freq() / 1000;
+ setup_sri2c();
- /*
- * Setup the dedicated I2C controller for Voltage Control
- * I2C clk - high period 40% low period 60%
- */
- cycles_hi = sys_clk_khz * 4 / PRM_VC_I2C_CHANNEL_FREQ_KHZ / 10;
- cycles_low = sys_clk_khz * 6 / PRM_VC_I2C_CHANNEL_FREQ_KHZ / 10;
- /* values to be set in register - less by 5 & 7 respectively */
- cycles_hi -= 5;
- cycles_low -= 7;
- temp = (cycles_hi << PRM_VC_CFG_I2C_CLK_SCLH_SHIFT) |
- (cycles_low << PRM_VC_CFG_I2C_CLK_SCLL_SHIFT);
- writel(temp, &prcm->prm_vc_cfg_i2c_clk);
-
- /* Disable high speed mode and all advanced features */
- writel(0x0, &prcm->prm_vc_cfg_i2c_mode);
-
- omap4_rev = omap_revision();
+ omap_rev = omap_revision();
/* TPS - supplies vdd_mpu on 4460 */
- if (omap4_rev >= OMAP4460_ES1_0) {
- volt = 1430;
+ if (omap_rev >= OMAP4460_ES1_0) {
+ volt = 1313;
do_scale_tps62361(TPS62361_REG_ADDR_SET1, volt);
}
@@ -576,8 +295,8 @@
*
* 4460 : supplies vdd_core
*/
- if (omap4_rev < OMAP4460_ES1_0) {
- volt = 1417;
+ if (omap_rev < OMAP4460_ES1_0) {
+ volt = 1325;
do_scale_vcore(SMPS_REG_ADDR_VCORE1, volt);
} else {
volt = 1200;
@@ -593,55 +312,18 @@
* 4430 : supplies vdd_core
* 4460 : not connected
*/
- if (omap4_rev < OMAP4460_ES1_0) {
+ if (omap_rev < OMAP4460_ES1_0) {
volt = 1200;
do_scale_vcore(SMPS_REG_ADDR_VCORE3, volt);
}
}
-static inline void enable_clock_domain(u32 *const clkctrl_reg, u32 enable_mode)
-{
- clrsetbits_le32(clkctrl_reg, CD_CLKCTRL_CLKTRCTRL_MASK,
- enable_mode << CD_CLKCTRL_CLKTRCTRL_SHIFT);
- debug("Enable clock domain - %p\n", clkctrl_reg);
-}
-
-static inline void wait_for_clk_enable(u32 *clkctrl_addr)
-{
- u32 clkctrl, idlest = MODULE_CLKCTRL_IDLEST_DISABLED;
- u32 bound = LDELAY;
-
- while ((idlest == MODULE_CLKCTRL_IDLEST_DISABLED) ||
- (idlest == MODULE_CLKCTRL_IDLEST_TRANSITIONING)) {
-
- clkctrl = readl(clkctrl_addr);
- idlest = (clkctrl & MODULE_CLKCTRL_IDLEST_MASK) >>
- MODULE_CLKCTRL_IDLEST_SHIFT;
- if (--bound == 0) {
- printf("Clock enable failed for 0x%p idlest 0x%x\n",
- clkctrl_addr, clkctrl);
- return;
- }
- }
-}
-
-static inline void enable_clock_module(u32 *const clkctrl_addr, u32 enable_mode,
- u32 wait_for_enable)
-{
- clrsetbits_le32(clkctrl_addr, MODULE_CLKCTRL_MODULEMODE_MASK,
- enable_mode << MODULE_CLKCTRL_MODULEMODE_SHIFT);
- debug("Enable clock module - %p\n", clkctrl_addr);
- if (wait_for_enable)
- wait_for_clk_enable(clkctrl_addr);
-}
-
/*
* Enable essential clock domains, modules and
* do some additional special settings needed
*/
-static void enable_basic_clocks(void)
+void enable_basic_clocks(void)
{
- u32 i, max = 100, wait_for_enable = 1;
u32 *const clk_domains_essential[] = {
&prcm->cm_l4per_clkstctrl,
&prcm->cm_l3init_clkstctrl,
@@ -651,30 +333,23 @@
};
u32 *const clk_modules_hw_auto_essential[] = {
+ &prcm->cm_memif_emif_1_clkctrl,
+ &prcm->cm_memif_emif_2_clkctrl,
+ &prcm->cm_l4cfg_l4_cfg_clkctrl,
&prcm->cm_wkup_gpio1_clkctrl,
&prcm->cm_l4per_gpio2_clkctrl,
&prcm->cm_l4per_gpio3_clkctrl,
&prcm->cm_l4per_gpio4_clkctrl,
&prcm->cm_l4per_gpio5_clkctrl,
&prcm->cm_l4per_gpio6_clkctrl,
- &prcm->cm_memif_emif_1_clkctrl,
- &prcm->cm_memif_emif_2_clkctrl,
- &prcm->cm_l3init_hsusbotg_clkctrl,
- &prcm->cm_l3init_usbphy_clkctrl,
- &prcm->cm_l4cfg_l4_cfg_clkctrl,
0
};
u32 *const clk_modules_explicit_en_essential[] = {
- &prcm->cm_l4per_gptimer2_clkctrl,
+ &prcm->cm_wkup_gptimer1_clkctrl,
&prcm->cm_l3init_hsmmc1_clkctrl,
&prcm->cm_l3init_hsmmc2_clkctrl,
- &prcm->cm_l4per_mcspi1_clkctrl,
- &prcm->cm_wkup_gptimer1_clkctrl,
- &prcm->cm_l4per_i2c1_clkctrl,
- &prcm->cm_l4per_i2c2_clkctrl,
- &prcm->cm_l4per_i2c3_clkctrl,
- &prcm->cm_l4per_i2c4_clkctrl,
+ &prcm->cm_l4per_gptimer2_clkctrl,
&prcm->cm_wkup_wdtimer2_clkctrl,
&prcm->cm_l4per_uart3_clkctrl,
0
@@ -698,40 +373,45 @@
setbits_le32(&prcm->cm_l3init_usbphy_clkctrl,
USBPHY_CLKCTRL_OPTFCLKEN_PHY_48M_MASK);
- /* Put the clock domains in SW_WKUP mode */
- for (i = 0; (i < max) && clk_domains_essential[i]; i++) {
- enable_clock_domain(clk_domains_essential[i],
- CD_CLKCTRL_CLKTRCTRL_SW_WKUP);
- }
+ do_enable_clocks(clk_domains_essential,
+ clk_modules_hw_auto_essential,
+ clk_modules_explicit_en_essential,
+ 1);
+}
- /* Clock modules that need to be put in HW_AUTO */
- for (i = 0; (i < max) && clk_modules_hw_auto_essential[i]; i++) {
- enable_clock_module(clk_modules_hw_auto_essential[i],
- MODULE_CLKCTRL_MODULEMODE_HW_AUTO,
- wait_for_enable);
+void enable_basic_uboot_clocks(void)
+{
+ u32 *const clk_domains_essential[] = {
+ 0
};
- /* Clock modules that need to be put in SW_EXPLICIT_EN mode */
- for (i = 0; (i < max) && clk_modules_explicit_en_essential[i]; i++) {
- enable_clock_module(clk_modules_explicit_en_essential[i],
- MODULE_CLKCTRL_MODULEMODE_SW_EXPLICIT_EN,
- wait_for_enable);
+ u32 *const clk_modules_hw_auto_essential[] = {
+ &prcm->cm_l3init_hsusbotg_clkctrl,
+ &prcm->cm_l3init_usbphy_clkctrl,
+ 0
};
- /* Put the clock domains in HW_AUTO mode now */
- for (i = 0; (i < max) && clk_domains_essential[i]; i++) {
- enable_clock_domain(clk_domains_essential[i],
- CD_CLKCTRL_CLKTRCTRL_HW_AUTO);
- }
+ u32 *const clk_modules_explicit_en_essential[] = {
+ &prcm->cm_l4per_mcspi1_clkctrl,
+ &prcm->cm_l4per_i2c1_clkctrl,
+ &prcm->cm_l4per_i2c2_clkctrl,
+ &prcm->cm_l4per_i2c3_clkctrl,
+ &prcm->cm_l4per_i2c4_clkctrl,
+ 0
+ };
+
+ do_enable_clocks(clk_domains_essential,
+ clk_modules_hw_auto_essential,
+ clk_modules_explicit_en_essential,
+ 1);
}
/*
* Enable non-essential clock domains, modules and
* do some additional special settings needed
*/
-static void enable_non_essential_clocks(void)
+void enable_non_essential_clocks(void)
{
- u32 i, max = 100, wait_for_enable = 0;
u32 *const clk_domains_non_essential[] = {
&prcm->cm_mpu_m3_clkstctrl,
&prcm->cm_ivahd_clkstctrl,
@@ -807,135 +487,13 @@
/* Enable all optional functional clocks of DSS */
setbits_le32(&prcm->cm_dss_dss_clkctrl, DSS_CLKCTRL_OPTFCLKEN_MASK);
-
- /* Put the clock domains in SW_WKUP mode */
- for (i = 0; (i < max) && clk_domains_non_essential[i]; i++) {
- enable_clock_domain(clk_domains_non_essential[i],
- CD_CLKCTRL_CLKTRCTRL_SW_WKUP);
- }
-
- /* Clock modules that need to be put in HW_AUTO */
- for (i = 0; (i < max) && clk_modules_hw_auto_non_essential[i]; i++) {
- enable_clock_module(clk_modules_hw_auto_non_essential[i],
- MODULE_CLKCTRL_MODULEMODE_HW_AUTO,
- wait_for_enable);
- };
-
- /* Clock modules that need to be put in SW_EXPLICIT_EN mode */
- for (i = 0; (i < max) && clk_modules_explicit_en_non_essential[i];
- i++) {
- enable_clock_module(clk_modules_explicit_en_non_essential[i],
- MODULE_CLKCTRL_MODULEMODE_SW_EXPLICIT_EN,
- wait_for_enable);
- };
-
- /* Put the clock domains in HW_AUTO mode now */
- for (i = 0; (i < max) && clk_domains_non_essential[i]; i++) {
- enable_clock_domain(clk_domains_non_essential[i],
- CD_CLKCTRL_CLKTRCTRL_HW_AUTO);
- }
+ do_enable_clocks(clk_domains_non_essential,
+ clk_modules_hw_auto_non_essential,
+ clk_modules_explicit_en_non_essential,
+ 0);
/* Put camera module in no sleep mode */
clrsetbits_le32(&prcm->cm_cam_clkstctrl, MODULE_CLKCTRL_MODULEMODE_MASK,
CD_CLKCTRL_CLKTRCTRL_NO_SLEEP <<
MODULE_CLKCTRL_MODULEMODE_SHIFT);
}
-
-
-void freq_update_core(void)
-{
- u32 freq_config1 = 0;
- const struct dpll_params *core_dpll_params;
-
- core_dpll_params = get_core_dpll_params();
- /* Put EMIF clock domain in sw wakeup mode */
- enable_clock_domain(&prcm->cm_memif_clkstctrl,
- CD_CLKCTRL_CLKTRCTRL_SW_WKUP);
- wait_for_clk_enable(&prcm->cm_memif_emif_1_clkctrl);
- wait_for_clk_enable(&prcm->cm_memif_emif_2_clkctrl);
-
- freq_config1 = SHADOW_FREQ_CONFIG1_FREQ_UPDATE_MASK |
- SHADOW_FREQ_CONFIG1_DLL_RESET_MASK;
-
- freq_config1 |= (DPLL_EN_LOCK << SHADOW_FREQ_CONFIG1_DPLL_EN_SHIFT) &
- SHADOW_FREQ_CONFIG1_DPLL_EN_MASK;
-
- freq_config1 |= (core_dpll_params->m2 <<
- SHADOW_FREQ_CONFIG1_M2_DIV_SHIFT) &
- SHADOW_FREQ_CONFIG1_M2_DIV_MASK;
-
- writel(freq_config1, &prcm->cm_shadow_freq_config1);
- if (!wait_on_value(SHADOW_FREQ_CONFIG1_FREQ_UPDATE_MASK, 0,
- &prcm->cm_shadow_freq_config1, LDELAY)) {
- puts("FREQ UPDATE procedure failed!!");
- hang();
- }
-
- /* Put EMIF clock domain back in hw auto mode */
- enable_clock_domain(&prcm->cm_memif_clkstctrl,
- CD_CLKCTRL_CLKTRCTRL_HW_AUTO);
- wait_for_clk_enable(&prcm->cm_memif_emif_1_clkctrl);
- wait_for_clk_enable(&prcm->cm_memif_emif_2_clkctrl);
-}
-
-void bypass_dpll(u32 *const base)
-{
- do_bypass_dpll(base);
- wait_for_bypass(base);
-}
-
-void lock_dpll(u32 *const base)
-{
- do_lock_dpll(base);
- wait_for_lock(base);
-}
-
-void setup_clocks_for_console(void)
-{
- /* Do not add any spl_debug prints in this function */
- clrsetbits_le32(&prcm->cm_l4per_clkstctrl, CD_CLKCTRL_CLKTRCTRL_MASK,
- CD_CLKCTRL_CLKTRCTRL_SW_WKUP <<
- CD_CLKCTRL_CLKTRCTRL_SHIFT);
-
- /* Enable all UARTs - console will be on one of them */
- clrsetbits_le32(&prcm->cm_l4per_uart1_clkctrl,
- MODULE_CLKCTRL_MODULEMODE_MASK,
- MODULE_CLKCTRL_MODULEMODE_SW_EXPLICIT_EN <<
- MODULE_CLKCTRL_MODULEMODE_SHIFT);
-
- clrsetbits_le32(&prcm->cm_l4per_uart2_clkctrl,
- MODULE_CLKCTRL_MODULEMODE_MASK,
- MODULE_CLKCTRL_MODULEMODE_SW_EXPLICIT_EN <<
- MODULE_CLKCTRL_MODULEMODE_SHIFT);
-
- clrsetbits_le32(&prcm->cm_l4per_uart3_clkctrl,
- MODULE_CLKCTRL_MODULEMODE_MASK,
- MODULE_CLKCTRL_MODULEMODE_SW_EXPLICIT_EN <<
- MODULE_CLKCTRL_MODULEMODE_SHIFT);
-
- clrsetbits_le32(&prcm->cm_l4per_uart3_clkctrl,
- MODULE_CLKCTRL_MODULEMODE_MASK,
- MODULE_CLKCTRL_MODULEMODE_SW_EXPLICIT_EN <<
- MODULE_CLKCTRL_MODULEMODE_SHIFT);
-
- clrsetbits_le32(&prcm->cm_l4per_clkstctrl, CD_CLKCTRL_CLKTRCTRL_MASK,
- CD_CLKCTRL_CLKTRCTRL_HW_AUTO <<
- CD_CLKCTRL_CLKTRCTRL_SHIFT);
-}
-
-void prcm_init(void)
-{
- switch (omap4_hw_init_context()) {
- case OMAP_INIT_CONTEXT_SPL:
- case OMAP_INIT_CONTEXT_UBOOT_FROM_NOR:
- case OMAP_INIT_CONTEXT_UBOOT_AFTER_CH:
- enable_basic_clocks();
- scale_vcores();
- setup_dplls();
- setup_non_essential_dplls();
- enable_non_essential_clocks();
- break;
- default:
- break;
- }
-}
diff --git a/arch/arm/cpu/armv7/omap4/emif.c b/arch/arm/cpu/armv7/omap4/emif.c
index 988b205..ca4823d 100644
--- a/arch/arm/cpu/armv7/omap4/emif.c
+++ b/arch/arm/cpu/armv7/omap4/emif.c
@@ -26,645 +26,15 @@
*/
#include <common.h>
-#include <asm/arch/emif.h>
-#include <asm/arch/clocks.h>
+#include <asm/emif.h>
#include <asm/arch/sys_proto.h>
-#include <asm/omap_common.h>
#include <asm/utils.h>
-static inline u32 emif_num(u32 base)
-{
- if (base == OMAP44XX_EMIF1)
- return 1;
- else if (base == OMAP44XX_EMIF2)
- return 2;
- else
- return 0;
-}
-
-static inline u32 get_mr(u32 base, u32 cs, u32 mr_addr)
-{
- u32 mr;
- struct emif_reg_struct *emif = (struct emif_reg_struct *)base;
-
- mr_addr |= cs << OMAP44XX_REG_CS_SHIFT;
- writel(mr_addr, &emif->emif_lpddr2_mode_reg_cfg);
- if (omap_revision() == OMAP4430_ES2_0)
- mr = readl(&emif->emif_lpddr2_mode_reg_data_es2);
- else
- mr = readl(&emif->emif_lpddr2_mode_reg_data);
- debug("get_mr: EMIF%d cs %d mr %08x val 0x%x\n", emif_num(base),
- cs, mr_addr, mr);
- return mr;
-}
-
-static inline void set_mr(u32 base, u32 cs, u32 mr_addr, u32 mr_val)
-{
- struct emif_reg_struct *emif = (struct emif_reg_struct *)base;
-
- mr_addr |= cs << OMAP44XX_REG_CS_SHIFT;
- writel(mr_addr, &emif->emif_lpddr2_mode_reg_cfg);
- writel(mr_val, &emif->emif_lpddr2_mode_reg_data);
-}
-
-void emif_reset_phy(u32 base)
-{
- struct emif_reg_struct *emif = (struct emif_reg_struct *)base;
- u32 iodft;
-
- iodft = readl(&emif->emif_iodft_tlgc);
- iodft |= OMAP44XX_REG_RESET_PHY_MASK;
- writel(iodft, &emif->emif_iodft_tlgc);
-}
-
-static void do_lpddr2_init(u32 base, u32 cs)
-{
- u32 mr_addr;
-
- /* Wait till device auto initialization is complete */
- while (get_mr(base, cs, LPDDR2_MR0) & LPDDR2_MR0_DAI_MASK)
- ;
- set_mr(base, cs, LPDDR2_MR10, MR10_ZQ_ZQINIT);
- /*
- * tZQINIT = 1 us
- * Enough loops assuming a maximum of 2GHz
- */
- sdelay(2000);
- set_mr(base, cs, LPDDR2_MR1, MR1_BL_8_BT_SEQ_WRAP_EN_NWR_3);
- set_mr(base, cs, LPDDR2_MR16, MR16_REF_FULL_ARRAY);
- /*
- * Enable refresh along with writing MR2
- * Encoding of RL in MR2 is (RL - 2)
- */
- mr_addr = LPDDR2_MR2 | OMAP44XX_REG_REFRESH_EN_MASK;
- set_mr(base, cs, mr_addr, RL_FINAL - 2);
-}
-
-static void lpddr2_init(u32 base, const struct emif_regs *regs)
-{
- struct emif_reg_struct *emif = (struct emif_reg_struct *)base;
-
- /* Not NVM */
- clrbits_le32(&emif->emif_lpddr2_nvm_config, OMAP44XX_REG_CS1NVMEN_MASK);
-
- /*
- * Keep REG_INITREF_DIS = 1 to prevent re-initialization of SDRAM
- * when EMIF_SDRAM_CONFIG register is written
- */
- setbits_le32(&emif->emif_sdram_ref_ctrl, OMAP44XX_REG_INITREF_DIS_MASK);
-
- /*
- * Set the SDRAM_CONFIG and PHY_CTRL for the
- * un-locked frequency & default RL
- */
- writel(regs->sdram_config_init, &emif->emif_sdram_config);
- writel(regs->emif_ddr_phy_ctlr_1_init, &emif->emif_ddr_phy_ctrl_1);
-
- do_lpddr2_init(base, CS0);
- if (regs->sdram_config & OMAP44XX_REG_EBANK_MASK)
- do_lpddr2_init(base, CS1);
-
- writel(regs->sdram_config, &emif->emif_sdram_config);
- writel(regs->emif_ddr_phy_ctlr_1, &emif->emif_ddr_phy_ctrl_1);
-
- /* Enable refresh now */
- clrbits_le32(&emif->emif_sdram_ref_ctrl, OMAP44XX_REG_INITREF_DIS_MASK);
-
-}
-
-static void emif_update_timings(u32 base, const struct emif_regs *regs)
-{
- struct emif_reg_struct *emif = (struct emif_reg_struct *)base;
-
- writel(regs->ref_ctrl, &emif->emif_sdram_ref_ctrl_shdw);
- writel(regs->sdram_tim1, &emif->emif_sdram_tim_1_shdw);
- writel(regs->sdram_tim2, &emif->emif_sdram_tim_2_shdw);
- writel(regs->sdram_tim3, &emif->emif_sdram_tim_3_shdw);
- if (omap_revision() == OMAP4430_ES1_0) {
- /* ES1 bug EMIF should be in force idle during freq_update */
- writel(0, &emif->emif_pwr_mgmt_ctrl);
- } else {
- writel(EMIF_PWR_MGMT_CTRL, &emif->emif_pwr_mgmt_ctrl);
- writel(EMIF_PWR_MGMT_CTRL_SHDW, &emif->emif_pwr_mgmt_ctrl_shdw);
- }
- writel(regs->read_idle_ctrl, &emif->emif_read_idlectrl_shdw);
- writel(regs->zq_config, &emif->emif_zq_config);
- writel(regs->temp_alert_config, &emif->emif_temp_alert_config);
- writel(regs->emif_ddr_phy_ctlr_1, &emif->emif_ddr_phy_ctrl_1_shdw);
-
- if (omap_revision() >= OMAP4460_ES1_0) {
- writel(EMIF_L3_CONFIG_VAL_SYS_10_MPU_3_LL_0,
- &emif->emif_l3_config);
- } else {
- writel(EMIF_L3_CONFIG_VAL_SYS_10_LL_0,
- &emif->emif_l3_config);
- }
-}
-
#ifndef CONFIG_SYS_EMIF_PRECALCULATED_TIMING_REGS
-#define print_timing_reg(reg) debug(#reg" - 0x%08x\n", (reg))
-
-static u32 *const T_num = (u32 *)OMAP4_SRAM_SCRATCH_EMIF_T_NUM;
-static u32 *const T_den = (u32 *)OMAP4_SRAM_SCRATCH_EMIF_T_DEN;
-static u32 *const emif_sizes = (u32 *)OMAP4_SRAM_SCRATCH_EMIF_SIZE;
-
-/*
- * Organization and refresh requirements for LPDDR2 devices of different
- * types and densities. Derived from JESD209-2 section 2.4
- */
-const struct lpddr2_addressing addressing_table[] = {
- /* Banks tREFIx10 rowx32,rowx16 colx32,colx16 density */
- {BANKS4, T_REFI_15_6, {ROW_12, ROW_12}, {COL_7, COL_8} },/*64M */
- {BANKS4, T_REFI_15_6, {ROW_12, ROW_12}, {COL_8, COL_9} },/*128M */
- {BANKS4, T_REFI_7_8, {ROW_13, ROW_13}, {COL_8, COL_9} },/*256M */
- {BANKS4, T_REFI_7_8, {ROW_13, ROW_13}, {COL_9, COL_10} },/*512M */
- {BANKS8, T_REFI_7_8, {ROW_13, ROW_13}, {COL_9, COL_10} },/*1GS4 */
- {BANKS8, T_REFI_3_9, {ROW_14, ROW_14}, {COL_9, COL_10} },/*2GS4 */
- {BANKS8, T_REFI_3_9, {ROW_14, ROW_14}, {COL_10, COL_11} },/*4G */
- {BANKS8, T_REFI_3_9, {ROW_15, ROW_15}, {COL_10, COL_11} },/*8G */
- {BANKS4, T_REFI_7_8, {ROW_14, ROW_14}, {COL_9, COL_10} },/*1GS2 */
- {BANKS4, T_REFI_3_9, {ROW_15, ROW_15}, {COL_9, COL_10} },/*2GS2 */
-};
-
-static const u32 lpddr2_density_2_size_in_mbytes[] = {
- 8, /* 64Mb */
- 16, /* 128Mb */
- 32, /* 256Mb */
- 64, /* 512Mb */
- 128, /* 1Gb */
- 256, /* 2Gb */
- 512, /* 4Gb */
- 1024, /* 8Gb */
- 2048, /* 16Gb */
- 4096 /* 32Gb */
-};
-
-/*
- * Calculate the period of DDR clock from frequency value and set the
- * denominator and numerator in global variables for easy access later
- */
-static void set_ddr_clk_period(u32 freq)
-{
- /*
- * period = 1/freq
- * period_in_ns = 10^9/freq
- */
- *T_num = 1000000000;
- *T_den = freq;
- cancel_out(T_num, T_den, 200);
-
-}
-
-/*
- * Convert time in nano seconds to number of cycles of DDR clock
- */
-static inline u32 ns_2_cycles(u32 ns)
-{
- return ((ns * (*T_den)) + (*T_num) - 1) / (*T_num);
-}
-
-/*
- * ns_2_cycles with the difference that the time passed is 2 times the actual
- * value(to avoid fractions). The cycles returned is for the original value of
- * the timing parameter
- */
-static inline u32 ns_x2_2_cycles(u32 ns)
-{
- return ((ns * (*T_den)) + (*T_num) * 2 - 1) / ((*T_num) * 2);
-}
-
-/*
- * Find addressing table index based on the device's type(S2 or S4) and
- * density
- */
-s8 addressing_table_index(u8 type, u8 density, u8 width)
-{
- u8 index;
- if ((density > LPDDR2_DENSITY_8Gb) || (width == LPDDR2_IO_WIDTH_8))
- return -1;
-
- /*
- * Look at the way ADDR_TABLE_INDEX* values have been defined
- * in emif.h compared to LPDDR2_DENSITY_* values
- * The table is layed out in the increasing order of density
- * (ignoring type). The exceptions 1GS2 and 2GS2 have been placed
- * at the end
- */
- if ((type == LPDDR2_TYPE_S2) && (density == LPDDR2_DENSITY_1Gb))
- index = ADDR_TABLE_INDEX1GS2;
- else if ((type == LPDDR2_TYPE_S2) && (density == LPDDR2_DENSITY_2Gb))
- index = ADDR_TABLE_INDEX2GS2;
- else
- index = density;
-
- debug("emif: addressing table index %d\n", index);
-
- return index;
-}
-
-/*
- * Find the the right timing table from the array of timing
- * tables of the device using DDR clock frequency
- */
-static const struct lpddr2_ac_timings *get_timings_table(const struct
- lpddr2_ac_timings const *const *device_timings,
- u32 freq)
-{
- u32 i, temp, freq_nearest;
- const struct lpddr2_ac_timings *timings = 0;
-
- emif_assert(freq <= MAX_LPDDR2_FREQ);
- emif_assert(device_timings);
-
- /*
- * Start with the maximum allowed frequency - that is always safe
- */
- freq_nearest = MAX_LPDDR2_FREQ;
- /*
- * Find the timings table that has the max frequency value:
- * i. Above or equal to the DDR frequency - safe
- * ii. The lowest that satisfies condition (i) - optimal
- */
- for (i = 0; (i < MAX_NUM_SPEEDBINS) && device_timings[i]; i++) {
- temp = device_timings[i]->max_freq;
- if ((temp >= freq) && (temp <= freq_nearest)) {
- freq_nearest = temp;
- timings = device_timings[i];
- }
- }
- debug("emif: timings table: %d\n", freq_nearest);
- return timings;
-}
-
-/*
- * Finds the value of emif_sdram_config_reg
- * All parameters are programmed based on the device on CS0.
- * If there is a device on CS1, it will be same as that on CS0 or
- * it will be NVM. We don't support NVM yet.
- * If cs1_device pointer is NULL it is assumed that there is no device
- * on CS1
- */
-static u32 get_sdram_config_reg(const struct lpddr2_device_details *cs0_device,
- const struct lpddr2_device_details *cs1_device,
- const struct lpddr2_addressing *addressing,
- u8 RL)
-{
- u32 config_reg = 0;
-
- config_reg |= (cs0_device->type + 4) << OMAP44XX_REG_SDRAM_TYPE_SHIFT;
- config_reg |= EMIF_INTERLEAVING_POLICY_MAX_INTERLEAVING <<
- OMAP44XX_REG_IBANK_POS_SHIFT;
-
- config_reg |= cs0_device->io_width << OMAP44XX_REG_NARROW_MODE_SHIFT;
-
- config_reg |= RL << OMAP44XX_REG_CL_SHIFT;
-
- config_reg |= addressing->row_sz[cs0_device->io_width] <<
- OMAP44XX_REG_ROWSIZE_SHIFT;
-
- config_reg |= addressing->num_banks << OMAP44XX_REG_IBANK_SHIFT;
-
- config_reg |= (cs1_device ? EBANK_CS1_EN : EBANK_CS1_DIS) <<
- OMAP44XX_REG_EBANK_SHIFT;
-
- config_reg |= addressing->col_sz[cs0_device->io_width] <<
- OMAP44XX_REG_PAGESIZE_SHIFT;
-
- return config_reg;
-}
-
-static u32 get_sdram_ref_ctrl(u32 freq,
- const struct lpddr2_addressing *addressing)
-{
- u32 ref_ctrl = 0, val = 0, freq_khz;
- freq_khz = freq / 1000;
- /*
- * refresh rate to be set is 'tREFI * freq in MHz
- * division by 10000 to account for khz and x10 in t_REFI_us_x10
- */
- val = addressing->t_REFI_us_x10 * freq_khz / 10000;
- ref_ctrl |= val << OMAP44XX_REG_REFRESH_RATE_SHIFT;
-
- return ref_ctrl;
-}
-
-static u32 get_sdram_tim_1_reg(const struct lpddr2_ac_timings *timings,
- const struct lpddr2_min_tck *min_tck,
- const struct lpddr2_addressing *addressing)
-{
- u32 tim1 = 0, val = 0;
- val = max(min_tck->tWTR, ns_x2_2_cycles(timings->tWTRx2)) - 1;
- tim1 |= val << OMAP44XX_REG_T_WTR_SHIFT;
-
- if (addressing->num_banks == BANKS8)
- val = (timings->tFAW * (*T_den) + 4 * (*T_num) - 1) /
- (4 * (*T_num)) - 1;
- else
- val = max(min_tck->tRRD, ns_2_cycles(timings->tRRD)) - 1;
-
- tim1 |= val << OMAP44XX_REG_T_RRD_SHIFT;
-
- val = ns_2_cycles(timings->tRASmin + timings->tRPab) - 1;
- tim1 |= val << OMAP44XX_REG_T_RC_SHIFT;
-
- val = max(min_tck->tRAS_MIN, ns_2_cycles(timings->tRASmin)) - 1;
- tim1 |= val << OMAP44XX_REG_T_RAS_SHIFT;
-
- val = max(min_tck->tWR, ns_2_cycles(timings->tWR)) - 1;
- tim1 |= val << OMAP44XX_REG_T_WR_SHIFT;
-
- val = max(min_tck->tRCD, ns_2_cycles(timings->tRCD)) - 1;
- tim1 |= val << OMAP44XX_REG_T_RCD_SHIFT;
-
- val = max(min_tck->tRP_AB, ns_2_cycles(timings->tRPab)) - 1;
- tim1 |= val << OMAP44XX_REG_T_RP_SHIFT;
-
- return tim1;
-}
-
-static u32 get_sdram_tim_2_reg(const struct lpddr2_ac_timings *timings,
- const struct lpddr2_min_tck *min_tck)
-{
- u32 tim2 = 0, val = 0;
- val = max(min_tck->tCKE, timings->tCKE) - 1;
- tim2 |= val << OMAP44XX_REG_T_CKE_SHIFT;
-
- val = max(min_tck->tRTP, ns_x2_2_cycles(timings->tRTPx2)) - 1;
- tim2 |= val << OMAP44XX_REG_T_RTP_SHIFT;
-
- /*
- * tXSRD = tRFCab + 10 ns. XSRD and XSNR should have the
- * same value
- */
- val = ns_2_cycles(timings->tXSR) - 1;
- tim2 |= val << OMAP44XX_REG_T_XSRD_SHIFT;
- tim2 |= val << OMAP44XX_REG_T_XSNR_SHIFT;
-
- val = max(min_tck->tXP, ns_x2_2_cycles(timings->tXPx2)) - 1;
- tim2 |= val << OMAP44XX_REG_T_XP_SHIFT;
-
- return tim2;
-}
-
-static u32 get_sdram_tim_3_reg(const struct lpddr2_ac_timings *timings,
- const struct lpddr2_min_tck *min_tck,
- const struct lpddr2_addressing *addressing)
-{
- u32 tim3 = 0, val = 0;
- val = min(timings->tRASmax * 10 / addressing->t_REFI_us_x10 - 1, 0xF);
- tim3 |= val << OMAP44XX_REG_T_RAS_MAX_SHIFT;
-
- val = ns_2_cycles(timings->tRFCab) - 1;
- tim3 |= val << OMAP44XX_REG_T_RFC_SHIFT;
-
- val = ns_x2_2_cycles(timings->tDQSCKMAXx2) - 1;
- tim3 |= val << OMAP44XX_REG_T_TDQSCKMAX_SHIFT;
-
- val = ns_2_cycles(timings->tZQCS) - 1;
- tim3 |= val << OMAP44XX_REG_ZQ_ZQCS_SHIFT;
-
- val = max(min_tck->tCKESR, ns_2_cycles(timings->tCKESR)) - 1;
- tim3 |= val << OMAP44XX_REG_T_CKESR_SHIFT;
-
- return tim3;
-}
-
-static u32 get_zq_config_reg(const struct lpddr2_device_details *cs1_device,
- const struct lpddr2_addressing *addressing,
- u8 volt_ramp)
-{
- u32 zq = 0, val = 0;
- if (volt_ramp)
- val =
- EMIF_ZQCS_INTERVAL_DVFS_IN_US * 10 /
- addressing->t_REFI_us_x10;
- else
- val =
- EMIF_ZQCS_INTERVAL_NORMAL_IN_US * 10 /
- addressing->t_REFI_us_x10;
- zq |= val << OMAP44XX_REG_ZQ_REFINTERVAL_SHIFT;
-
- zq |= (REG_ZQ_ZQCL_MULT - 1) << OMAP44XX_REG_ZQ_ZQCL_MULT_SHIFT;
-
- zq |= (REG_ZQ_ZQINIT_MULT - 1) << OMAP44XX_REG_ZQ_ZQINIT_MULT_SHIFT;
-
- zq |= REG_ZQ_SFEXITEN_ENABLE << OMAP44XX_REG_ZQ_SFEXITEN_SHIFT;
-
- /*
- * Assuming that two chipselects have a single calibration resistor
- * If there are indeed two calibration resistors, then this flag should
- * be enabled to take advantage of dual calibration feature.
- * This data should ideally come from board files. But considering
- * that none of the boards today have calibration resistors per CS,
- * it would be an unnecessary overhead.
- */
- zq |= REG_ZQ_DUALCALEN_DISABLE << OMAP44XX_REG_ZQ_DUALCALEN_SHIFT;
-
- zq |= REG_ZQ_CS0EN_ENABLE << OMAP44XX_REG_ZQ_CS0EN_SHIFT;
-
- zq |= (cs1_device ? 1 : 0) << OMAP44XX_REG_ZQ_CS1EN_SHIFT;
-
- return zq;
-}
-
-static u32 get_temp_alert_config(const struct lpddr2_device_details *cs1_device,
- const struct lpddr2_addressing *addressing,
- u8 is_derated)
-{
- u32 alert = 0, interval;
- interval =
- TEMP_ALERT_POLL_INTERVAL_MS * 10000 / addressing->t_REFI_us_x10;
- if (is_derated)
- interval *= 4;
- alert |= interval << OMAP44XX_REG_TA_REFINTERVAL_SHIFT;
-
- alert |= TEMP_ALERT_CONFIG_DEVCT_1 << OMAP44XX_REG_TA_DEVCNT_SHIFT;
-
- alert |= TEMP_ALERT_CONFIG_DEVWDT_32 << OMAP44XX_REG_TA_DEVWDT_SHIFT;
-
- alert |= 1 << OMAP44XX_REG_TA_SFEXITEN_SHIFT;
-
- alert |= 1 << OMAP44XX_REG_TA_CS0EN_SHIFT;
-
- alert |= (cs1_device ? 1 : 0) << OMAP44XX_REG_TA_CS1EN_SHIFT;
-
- return alert;
-}
-
-static u32 get_read_idle_ctrl_reg(u8 volt_ramp)
-{
- u32 idle = 0, val = 0;
- if (volt_ramp)
- val = ns_2_cycles(READ_IDLE_INTERVAL_DVFS) / 64 - 1;
- else
- /*Maximum value in normal conditions - suggested by hw team */
- val = 0x1FF;
- idle |= val << OMAP44XX_REG_READ_IDLE_INTERVAL_SHIFT;
-
- idle |= EMIF_REG_READ_IDLE_LEN_VAL << OMAP44XX_REG_READ_IDLE_LEN_SHIFT;
-
- return idle;
-}
-
-static u32 get_ddr_phy_ctrl_1(u32 freq, u8 RL)
-{
- u32 phy = 0, val = 0;
-
- phy |= (RL + 2) << OMAP44XX_REG_READ_LATENCY_SHIFT;
-
- if (freq <= 100000000)
- val = EMIF_DLL_SLAVE_DLY_CTRL_100_MHZ_AND_LESS;
- else if (freq <= 200000000)
- val = EMIF_DLL_SLAVE_DLY_CTRL_200_MHZ;
- else
- val = EMIF_DLL_SLAVE_DLY_CTRL_400_MHZ;
- phy |= val << OMAP44XX_REG_DLL_SLAVE_DLY_CTRL_SHIFT;
-
- /* Other fields are constant magic values. Hardcode them together */
- phy |= EMIF_DDR_PHY_CTRL_1_BASE_VAL <<
- OMAP44XX_EMIF_DDR_PHY_CTRL_1_BASE_VAL_SHIFT;
-
- return phy;
-}
-
-static u32 get_emif_mem_size(struct emif_device_details *devices)
-{
- u32 size_mbytes = 0, temp;
-
- if (!devices)
- return 0;
-
- if (devices->cs0_device_details) {
- temp = devices->cs0_device_details->density;
- size_mbytes += lpddr2_density_2_size_in_mbytes[temp];
- }
-
- if (devices->cs1_device_details) {
- temp = devices->cs1_device_details->density;
- size_mbytes += lpddr2_density_2_size_in_mbytes[temp];
- }
- /* convert to bytes */
- return size_mbytes << 20;
-}
-
-/* Gets the encoding corresponding to a given DMM section size */
-u32 get_dmm_section_size_map(u32 section_size)
-{
- /*
- * Section size mapping:
- * 0x0: 16-MiB section
- * 0x1: 32-MiB section
- * 0x2: 64-MiB section
- * 0x3: 128-MiB section
- * 0x4: 256-MiB section
- * 0x5: 512-MiB section
- * 0x6: 1-GiB section
- * 0x7: 2-GiB section
- */
- section_size >>= 24; /* divide by 16 MB */
- return log_2_n_round_down(section_size);
-}
-
-static void emif_calculate_regs(
- const struct emif_device_details *emif_dev_details,
- u32 freq, struct emif_regs *regs)
-{
- u32 temp, sys_freq;
- const struct lpddr2_addressing *addressing;
- const struct lpddr2_ac_timings *timings;
- const struct lpddr2_min_tck *min_tck;
- const struct lpddr2_device_details *cs0_dev_details =
- emif_dev_details->cs0_device_details;
- const struct lpddr2_device_details *cs1_dev_details =
- emif_dev_details->cs1_device_details;
- const struct lpddr2_device_timings *cs0_dev_timings =
- emif_dev_details->cs0_device_timings;
-
- emif_assert(emif_dev_details);
- emif_assert(regs);
- /*
- * You can not have a device on CS1 without one on CS0
- * So configuring EMIF without a device on CS0 doesn't
- * make sense
- */
- emif_assert(cs0_dev_details);
- emif_assert(cs0_dev_details->type != LPDDR2_TYPE_NVM);
- /*
- * If there is a device on CS1 it should be same type as CS0
- * (or NVM. But NVM is not supported in this driver yet)
- */
- emif_assert((cs1_dev_details == NULL) ||
- (cs1_dev_details->type == LPDDR2_TYPE_NVM) ||
- (cs0_dev_details->type == cs1_dev_details->type));
- emif_assert(freq <= MAX_LPDDR2_FREQ);
-
- set_ddr_clk_period(freq);
-
- /*
- * The device on CS0 is used for all timing calculations
- * There is only one set of registers for timings per EMIF. So, if the
- * second CS(CS1) has a device, it should have the same timings as the
- * device on CS0
- */
- timings = get_timings_table(cs0_dev_timings->ac_timings, freq);
- emif_assert(timings);
- min_tck = cs0_dev_timings->min_tck;
-
- temp = addressing_table_index(cs0_dev_details->type,
- cs0_dev_details->density,
- cs0_dev_details->io_width);
-
- emif_assert((temp >= 0));
- addressing = &(addressing_table[temp]);
- emif_assert(addressing);
-
- sys_freq = get_sys_clk_freq();
-
- regs->sdram_config_init = get_sdram_config_reg(cs0_dev_details,
- cs1_dev_details,
- addressing, RL_BOOT);
-
- regs->sdram_config = get_sdram_config_reg(cs0_dev_details,
- cs1_dev_details,
- addressing, RL_FINAL);
-
- regs->ref_ctrl = get_sdram_ref_ctrl(freq, addressing);
-
- regs->sdram_tim1 = get_sdram_tim_1_reg(timings, min_tck, addressing);
-
- regs->sdram_tim2 = get_sdram_tim_2_reg(timings, min_tck);
-
- regs->sdram_tim3 = get_sdram_tim_3_reg(timings, min_tck, addressing);
-
- regs->read_idle_ctrl = get_read_idle_ctrl_reg(LPDDR2_VOLTAGE_STABLE);
-
- regs->temp_alert_config =
- get_temp_alert_config(cs1_dev_details, addressing, 0);
-
- regs->zq_config = get_zq_config_reg(cs1_dev_details, addressing,
- LPDDR2_VOLTAGE_STABLE);
-
- regs->emif_ddr_phy_ctlr_1_init =
- get_ddr_phy_ctrl_1(sys_freq / 2, RL_BOOT);
-
- regs->emif_ddr_phy_ctlr_1 =
- get_ddr_phy_ctrl_1(freq, RL_FINAL);
-
- regs->freq = freq;
-
- print_timing_reg(regs->sdram_config_init);
- print_timing_reg(regs->sdram_config);
- print_timing_reg(regs->ref_ctrl);
- print_timing_reg(regs->sdram_tim1);
- print_timing_reg(regs->sdram_tim2);
- print_timing_reg(regs->sdram_tim3);
- print_timing_reg(regs->read_idle_ctrl);
- print_timing_reg(regs->temp_alert_config);
- print_timing_reg(regs->zq_config);
- print_timing_reg(regs->emif_ddr_phy_ctlr_1);
- print_timing_reg(regs->emif_ddr_phy_ctlr_1_init);
-}
-#endif /* CONFIG_SYS_EMIF_PRECALCULATED_TIMING_REGS */
+u32 *const T_num = (u32 *)OMAP4_SRAM_SCRATCH_EMIF_T_NUM;
+u32 *const T_den = (u32 *)OMAP4_SRAM_SCRATCH_EMIF_T_DEN;
+u32 *const emif_sizes = (u32 *)OMAP4_SRAM_SCRATCH_EMIF_SIZE;
+#endif
#ifdef CONFIG_SYS_DEFAULT_LPDDR2_TIMINGS
/* Base AC Timing values specified by JESD209-2 for 400MHz operation */
@@ -691,30 +61,6 @@
.tFAW = 50
};
-/* Base AC Timing values specified by JESD209-2 for 333 MHz operation */
-static const struct lpddr2_ac_timings timings_jedec_333_mhz = {
- .max_freq = 333000000,
- .RL = 5,
- .tRPab = 21,
- .tRCD = 18,
- .tWR = 15,
- .tRASmin = 42,
- .tRRD = 10,
- .tWTRx2 = 15,
- .tXSR = 140,
- .tXPx2 = 15,
- .tRFCab = 130,
- .tRTPx2 = 15,
- .tCKE = 3,
- .tCKESR = 15,
- .tZQCS = 90,
- .tZQCL = 360,
- .tZQINIT = 1000,
- .tDQSCKMAXx2 = 11,
- .tRASmax = 70,
- .tFAW = 50
-};
-
/* Base AC Timing values specified by JESD209-2 for 200 MHz operation */
static const struct lpddr2_ac_timings timings_jedec_200_mhz = {
.max_freq = 200000000,
@@ -764,7 +110,6 @@
static const struct lpddr2_ac_timings const*
jedec_ac_timings[MAX_NUM_SPEEDBINS] = {
&timings_jedec_200_mhz,
- &timings_jedec_333_mhz,
&timings_jedec_400_mhz
};
@@ -782,473 +127,3 @@
*cs1_device_timings = &jedec_default_timings;
}
#endif /* CONFIG_SYS_DEFAULT_LPDDR2_TIMINGS */
-
-#ifdef CONFIG_SYS_AUTOMATIC_SDRAM_DETECTION
-const char *get_lpddr2_type(u8 type_id)
-{
- switch (type_id) {
- case LPDDR2_TYPE_S4:
- return "LPDDR2-S4";
- case LPDDR2_TYPE_S2:
- return "LPDDR2-S2";
- default:
- return NULL;
- }
-}
-
-const char *get_lpddr2_io_width(u8 width_id)
-{
- switch (width_id) {
- case LPDDR2_IO_WIDTH_8:
- return "x8";
- case LPDDR2_IO_WIDTH_16:
- return "x16";
- case LPDDR2_IO_WIDTH_32:
- return "x32";
- default:
- return NULL;
- }
-}
-
-const char *get_lpddr2_manufacturer(u32 manufacturer)
-{
- switch (manufacturer) {
- case LPDDR2_MANUFACTURER_SAMSUNG:
- return "Samsung";
- case LPDDR2_MANUFACTURER_QIMONDA:
- return "Qimonda";
- case LPDDR2_MANUFACTURER_ELPIDA:
- return "Elpida";
- case LPDDR2_MANUFACTURER_ETRON:
- return "Etron";
- case LPDDR2_MANUFACTURER_NANYA:
- return "Nanya";
- case LPDDR2_MANUFACTURER_HYNIX:
- return "Hynix";
- case LPDDR2_MANUFACTURER_MOSEL:
- return "Mosel";
- case LPDDR2_MANUFACTURER_WINBOND:
- return "Winbond";
- case LPDDR2_MANUFACTURER_ESMT:
- return "ESMT";
- case LPDDR2_MANUFACTURER_SPANSION:
- return "Spansion";
- case LPDDR2_MANUFACTURER_SST:
- return "SST";
- case LPDDR2_MANUFACTURER_ZMOS:
- return "ZMOS";
- case LPDDR2_MANUFACTURER_INTEL:
- return "Intel";
- case LPDDR2_MANUFACTURER_NUMONYX:
- return "Numonyx";
- case LPDDR2_MANUFACTURER_MICRON:
- return "Micron";
- default:
- return NULL;
- }
-}
-
-static void display_sdram_details(u32 emif_nr, u32 cs,
- struct lpddr2_device_details *device)
-{
- const char *mfg_str;
- const char *type_str;
- char density_str[10];
- u32 density;
-
- debug("EMIF%d CS%d\t", emif_nr, cs);
-
- if (!device) {
- debug("None\n");
- return;
- }
-
- mfg_str = get_lpddr2_manufacturer(device->manufacturer);
- type_str = get_lpddr2_type(device->type);
-
- density = lpddr2_density_2_size_in_mbytes[device->density];
- if ((density / 1024 * 1024) == density) {
- density /= 1024;
- sprintf(density_str, "%d GB", density);
- } else
- sprintf(density_str, "%d MB", density);
- if (mfg_str && type_str)
- debug("%s\t\t%s\t%s\n", mfg_str, type_str, density_str);
-}
-
-static u8 is_lpddr2_sdram_present(u32 base, u32 cs,
- struct lpddr2_device_details *lpddr2_device)
-{
- u32 mr = 0, temp;
-
- mr = get_mr(base, cs, LPDDR2_MR0);
- if (mr > 0xFF) {
- /* Mode register value bigger than 8 bit */
- return 0;
- }
-
- temp = (mr & LPDDR2_MR0_DI_MASK) >> LPDDR2_MR0_DI_SHIFT;
- if (temp) {
- /* Not SDRAM */
- return 0;
- }
- temp = (mr & LPDDR2_MR0_DNVI_MASK) >> LPDDR2_MR0_DNVI_SHIFT;
-
- if (temp) {
- /* DNV supported - But DNV is only supported for NVM */
- return 0;
- }
-
- mr = get_mr(base, cs, LPDDR2_MR4);
- if (mr > 0xFF) {
- /* Mode register value bigger than 8 bit */
- return 0;
- }
-
- mr = get_mr(base, cs, LPDDR2_MR5);
- if (mr >= 0xFF) {
- /* Mode register value bigger than 8 bit */
- return 0;
- }
-
- if (!get_lpddr2_manufacturer(mr)) {
- /* Manufacturer not identified */
- return 0;
- }
- lpddr2_device->manufacturer = mr;
-
- mr = get_mr(base, cs, LPDDR2_MR6);
- if (mr >= 0xFF) {
- /* Mode register value bigger than 8 bit */
- return 0;
- }
-
- mr = get_mr(base, cs, LPDDR2_MR7);
- if (mr >= 0xFF) {
- /* Mode register value bigger than 8 bit */
- return 0;
- }
-
- mr = get_mr(base, cs, LPDDR2_MR8);
- if (mr >= 0xFF) {
- /* Mode register value bigger than 8 bit */
- return 0;
- }
-
- temp = (mr & MR8_TYPE_MASK) >> MR8_TYPE_SHIFT;
- if (!get_lpddr2_type(temp)) {
- /* Not SDRAM */
- return 0;
- }
- lpddr2_device->type = temp;
-
- temp = (mr & MR8_DENSITY_MASK) >> MR8_DENSITY_SHIFT;
- if (temp > LPDDR2_DENSITY_32Gb) {
- /* Density not supported */
- return 0;
- }
- lpddr2_device->density = temp;
-
- temp = (mr & MR8_IO_WIDTH_MASK) >> MR8_IO_WIDTH_SHIFT;
- if (!get_lpddr2_io_width(temp)) {
- /* IO width unsupported value */
- return 0;
- }
- lpddr2_device->io_width = temp;
-
- /*
- * If all the above tests pass we should
- * have a device on this chip-select
- */
- return 1;
-}
-
-struct lpddr2_device_details *emif_get_device_details(u32 emif_nr, u8 cs,
- struct lpddr2_device_details *lpddr2_dev_details)
-{
- u32 phy;
- u32 base = (emif_nr == 1) ? OMAP44XX_EMIF1 : OMAP44XX_EMIF2;
- struct emif_reg_struct *emif = (struct emif_reg_struct *)base;
-
- if (!lpddr2_dev_details)
- return NULL;
-
- /* Do the minimum init for mode register accesses */
- if (!running_from_sdram()) {
- phy = get_ddr_phy_ctrl_1(get_sys_clk_freq() / 2, RL_BOOT);
- writel(phy, &emif->emif_ddr_phy_ctrl_1);
- }
-
- if (!(is_lpddr2_sdram_present(base, cs, lpddr2_dev_details)))
- return NULL;
-
- display_sdram_details(emif_num(base), cs, lpddr2_dev_details);
-
- return lpddr2_dev_details;
-}
-#endif /* CONFIG_SYS_AUTOMATIC_SDRAM_DETECTION */
-
-static void do_sdram_init(u32 base)
-{
- const struct emif_regs *regs;
- u32 in_sdram, emif_nr;
-
- debug(">>do_sdram_init() %x\n", base);
-
- in_sdram = running_from_sdram();
- emif_nr = (base == OMAP44XX_EMIF1) ? 1 : 2;
-
-#ifdef CONFIG_SYS_EMIF_PRECALCULATED_TIMING_REGS
- emif_get_reg_dump(emif_nr, ®s);
- if (!regs) {
- debug("EMIF: reg dump not provided\n");
- return;
- }
-#else
- /*
- * The user has not provided the register values. We need to
- * calculate it based on the timings and the DDR frequency
- */
- struct emif_device_details dev_details;
- struct emif_regs calculated_regs;
-
- /*
- * Get device details:
- * - Discovered if CONFIG_SYS_AUTOMATIC_SDRAM_DETECTION is set
- * - Obtained from user otherwise
- */
- struct lpddr2_device_details cs0_dev_details, cs1_dev_details;
- emif_reset_phy(base);
- dev_details.cs0_device_details = emif_get_device_details(base, CS0,
- &cs0_dev_details);
- dev_details.cs1_device_details = emif_get_device_details(base, CS1,
- &cs1_dev_details);
- emif_reset_phy(base);
-
- /* Return if no devices on this EMIF */
- if (!dev_details.cs0_device_details &&
- !dev_details.cs1_device_details) {
- emif_sizes[emif_nr - 1] = 0;
- return;
- }
-
- if (!in_sdram)
- emif_sizes[emif_nr - 1] = get_emif_mem_size(&dev_details);
-
- /*
- * Get device timings:
- * - Default timings specified by JESD209-2 if
- * CONFIG_SYS_DEFAULT_LPDDR2_TIMINGS is set
- * - Obtained from user otherwise
- */
- emif_get_device_timings(emif_nr, &dev_details.cs0_device_timings,
- &dev_details.cs1_device_timings);
-
- /* Calculate the register values */
- emif_calculate_regs(&dev_details, omap4_ddr_clk(), &calculated_regs);
- regs = &calculated_regs;
-#endif /* CONFIG_SYS_EMIF_PRECALCULATED_TIMING_REGS */
-
- /*
- * Initializing the LPDDR2 device can not happen from SDRAM.
- * Changing the timing registers in EMIF can happen(going from one
- * OPP to another)
- */
- if (!in_sdram)
- lpddr2_init(base, regs);
-
- /* Write to the shadow registers */
- emif_update_timings(base, regs);
-
- debug("<<do_sdram_init() %x\n", base);
-}
-
-static void emif_post_init_config(u32 base)
-{
- struct emif_reg_struct *emif = (struct emif_reg_struct *)base;
- u32 omap4_rev = omap_revision();
-
- /* reset phy on ES2.0 */
- if (omap4_rev == OMAP4430_ES2_0)
- emif_reset_phy(base);
-
- /* Put EMIF back in smart idle on ES1.0 */
- if (omap4_rev == OMAP4430_ES1_0)
- writel(0x80000000, &emif->emif_pwr_mgmt_ctrl);
-}
-
-static void dmm_init(u32 base)
-{
- const struct dmm_lisa_map_regs *lisa_map_regs;
-
-#ifdef CONFIG_SYS_EMIF_PRECALCULATED_TIMING_REGS
- emif_get_dmm_regs(&lisa_map_regs);
-#else
- u32 emif1_size, emif2_size, mapped_size, section_map = 0;
- u32 section_cnt, sys_addr;
- struct dmm_lisa_map_regs lis_map_regs_calculated = {0};
-
- mapped_size = 0;
- section_cnt = 3;
- sys_addr = CONFIG_SYS_SDRAM_BASE;
- emif1_size = emif_sizes[0];
- emif2_size = emif_sizes[1];
- debug("emif1_size 0x%x emif2_size 0x%x\n", emif1_size, emif2_size);
-
- if (!emif1_size && !emif2_size)
- return;
-
- /* symmetric interleaved section */
- if (emif1_size && emif2_size) {
- mapped_size = min(emif1_size, emif2_size);
- section_map = DMM_LISA_MAP_INTERLEAVED_BASE_VAL;
- section_map |= 0 << OMAP44XX_SDRC_ADDR_SHIFT;
- /* only MSB */
- section_map |= (sys_addr >> 24) <<
- OMAP44XX_SYS_ADDR_SHIFT;
- section_map |= get_dmm_section_size_map(mapped_size * 2)
- << OMAP44XX_SYS_SIZE_SHIFT;
- lis_map_regs_calculated.dmm_lisa_map_3 = section_map;
- emif1_size -= mapped_size;
- emif2_size -= mapped_size;
- sys_addr += (mapped_size * 2);
- section_cnt--;
- }
-
- /*
- * Single EMIF section(we can have a maximum of 1 single EMIF
- * section- either EMIF1 or EMIF2 or none, but not both)
- */
- if (emif1_size) {
- section_map = DMM_LISA_MAP_EMIF1_ONLY_BASE_VAL;
- section_map |= get_dmm_section_size_map(emif1_size)
- << OMAP44XX_SYS_SIZE_SHIFT;
- /* only MSB */
- section_map |= (mapped_size >> 24) <<
- OMAP44XX_SDRC_ADDR_SHIFT;
- /* only MSB */
- section_map |= (sys_addr >> 24) << OMAP44XX_SYS_ADDR_SHIFT;
- section_cnt--;
- }
- if (emif2_size) {
- section_map = DMM_LISA_MAP_EMIF2_ONLY_BASE_VAL;
- section_map |= get_dmm_section_size_map(emif2_size) <<
- OMAP44XX_SYS_SIZE_SHIFT;
- /* only MSB */
- section_map |= mapped_size >> 24 << OMAP44XX_SDRC_ADDR_SHIFT;
- /* only MSB */
- section_map |= sys_addr >> 24 << OMAP44XX_SYS_ADDR_SHIFT;
- section_cnt--;
- }
-
- if (section_cnt == 2) {
- /* Only 1 section - either symmetric or single EMIF */
- lis_map_regs_calculated.dmm_lisa_map_3 = section_map;
- lis_map_regs_calculated.dmm_lisa_map_2 = 0;
- lis_map_regs_calculated.dmm_lisa_map_1 = 0;
- } else {
- /* 2 sections - 1 symmetric, 1 single EMIF */
- lis_map_regs_calculated.dmm_lisa_map_2 = section_map;
- lis_map_regs_calculated.dmm_lisa_map_1 = 0;
- }
-
- /* TRAP for invalid TILER mappings in section 0 */
- lis_map_regs_calculated.dmm_lisa_map_0 = DMM_LISA_MAP_0_INVAL_ADDR_TRAP;
-
- lisa_map_regs = &lis_map_regs_calculated;
-#endif
- struct dmm_lisa_map_regs *hw_lisa_map_regs =
- (struct dmm_lisa_map_regs *)base;
-
- writel(0, &hw_lisa_map_regs->dmm_lisa_map_3);
- writel(0, &hw_lisa_map_regs->dmm_lisa_map_2);
- writel(0, &hw_lisa_map_regs->dmm_lisa_map_1);
- writel(0, &hw_lisa_map_regs->dmm_lisa_map_0);
-
- writel(lisa_map_regs->dmm_lisa_map_3,
- &hw_lisa_map_regs->dmm_lisa_map_3);
- writel(lisa_map_regs->dmm_lisa_map_2,
- &hw_lisa_map_regs->dmm_lisa_map_2);
- writel(lisa_map_regs->dmm_lisa_map_1,
- &hw_lisa_map_regs->dmm_lisa_map_1);
- writel(lisa_map_regs->dmm_lisa_map_0,
- &hw_lisa_map_regs->dmm_lisa_map_0);
-
- if (omap_revision() >= OMAP4460_ES1_0) {
- hw_lisa_map_regs =
- (struct dmm_lisa_map_regs *)OMAP44XX_MA_LISA_MAP_BASE;
-
- writel(lisa_map_regs->dmm_lisa_map_3,
- &hw_lisa_map_regs->dmm_lisa_map_3);
- writel(lisa_map_regs->dmm_lisa_map_2,
- &hw_lisa_map_regs->dmm_lisa_map_2);
- writel(lisa_map_regs->dmm_lisa_map_1,
- &hw_lisa_map_regs->dmm_lisa_map_1);
- writel(lisa_map_regs->dmm_lisa_map_0,
- &hw_lisa_map_regs->dmm_lisa_map_0);
- }
-}
-
-/*
- * SDRAM initialization:
- * SDRAM initialization has two parts:
- * 1. Configuring the SDRAM device
- * 2. Update the AC timings related parameters in the EMIF module
- * (1) should be done only once and should not be done while we are
- * running from SDRAM.
- * (2) can and should be done more than once if OPP changes.
- * Particularly, this may be needed when we boot without SPL and
- * and using Configuration Header(CH). ROM code supports only at 50% OPP
- * at boot (low power boot). So u-boot has to switch to OPP100 and update
- * the frequency. So,
- * Doing (1) and (2) makes sense - first time initialization
- * Doing (2) and not (1) makes sense - OPP change (when using CH)
- * Doing (1) and not (2) doen't make sense
- * See do_sdram_init() for the details
- */
-void sdram_init(void)
-{
- u32 in_sdram, size_prog, size_detect;
-
- debug(">>sdram_init()\n");
-
- if (omap4_hw_init_context() == OMAP_INIT_CONTEXT_UBOOT_AFTER_SPL)
- return;
-
- in_sdram = running_from_sdram();
- debug("in_sdram = %d\n", in_sdram);
-
- if (!in_sdram) {
- bypass_dpll(&prcm->cm_clkmode_dpll_core);
- }
-
- do_sdram_init(OMAP44XX_EMIF1);
- do_sdram_init(OMAP44XX_EMIF2);
-
- if (!in_sdram) {
- dmm_init(OMAP44XX_DMM_LISA_MAP_BASE);
- emif_post_init_config(OMAP44XX_EMIF1);
- emif_post_init_config(OMAP44XX_EMIF2);
-
- }
-
- /* for the shadow registers to take effect */
- freq_update_core();
-
- /* Do some testing after the init */
- if (!in_sdram) {
- size_prog = omap4_sdram_size();
- size_detect = get_ram_size((long *)CONFIG_SYS_SDRAM_BASE,
- size_prog);
- /* Compare with the size programmed */
- if (size_detect != size_prog) {
- printf("SDRAM: identified size not same as expected"
- " size identified: %x expected: %x\n",
- size_detect,
- size_prog);
- } else
- debug("get_ram_size() successful");
- }
-
- debug("<<sdram_init()\n");
-}
diff --git a/arch/arm/cpu/armv7/omap4/hwinit.c b/arch/arm/cpu/armv7/omap4/hwinit.c
new file mode 100644
index 0000000..52c9b19
--- /dev/null
+++ b/arch/arm/cpu/armv7/omap4/hwinit.c
@@ -0,0 +1,167 @@
+/*
+ *
+ * Common functions for OMAP4 based boards
+ *
+ * (C) Copyright 2010
+ * Texas Instruments, <www.ti.com>
+ *
+ * Author :
+ * Aneesh V <aneesh@ti.com>
+ * Steve Sakoman <steve@sakoman.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+#include <common.h>
+#include <asm/armv7.h>
+#include <asm/arch/cpu.h>
+#include <asm/arch/sys_proto.h>
+#include <asm/sizes.h>
+#include <asm/emif.h>
+#include <asm/arch/gpio.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+u32 *const omap4_revision = (u32 *)OMAP4_SRAM_SCRATCH_OMAP4_REV;
+
+static const struct gpio_bank gpio_bank_44xx[6] = {
+ { (void *)OMAP44XX_GPIO1_BASE, METHOD_GPIO_24XX },
+ { (void *)OMAP44XX_GPIO2_BASE, METHOD_GPIO_24XX },
+ { (void *)OMAP44XX_GPIO3_BASE, METHOD_GPIO_24XX },
+ { (void *)OMAP44XX_GPIO4_BASE, METHOD_GPIO_24XX },
+ { (void *)OMAP44XX_GPIO5_BASE, METHOD_GPIO_24XX },
+ { (void *)OMAP44XX_GPIO6_BASE, METHOD_GPIO_24XX },
+};
+
+const struct gpio_bank *const omap_gpio_bank = gpio_bank_44xx;
+
+#ifdef CONFIG_SPL_BUILD
+/*
+ * Some tuning of IOs for optimal power and performance
+ */
+void do_io_settings(void)
+{
+ u32 lpddr2io;
+ struct control_lpddr2io_regs *lpddr2io_regs =
+ (struct control_lpddr2io_regs *)LPDDR2_IO_REGS_BASE;
+ struct omap4_sys_ctrl_regs *const ctrl =
+ (struct omap4_sys_ctrl_regs *)SYSCTRL_GENERAL_CORE_BASE;
+
+ u32 omap4_rev = omap_revision();
+
+ if (omap4_rev == OMAP4430_ES1_0)
+ lpddr2io = CONTROL_LPDDR2IO_SLEW_125PS_DRV8_PULL_DOWN;
+ else if (omap4_rev == OMAP4430_ES2_0)
+ lpddr2io = CONTROL_LPDDR2IO_SLEW_325PS_DRV8_GATE_KEEPER;
+ else
+ lpddr2io = CONTROL_LPDDR2IO_SLEW_315PS_DRV12_PULL_DOWN;
+
+ /* EMIF1 */
+ writel(lpddr2io, &lpddr2io_regs->control_lpddr2io1_0);
+ writel(lpddr2io, &lpddr2io_regs->control_lpddr2io1_1);
+ /* No pull for GR10 as per hw team's recommendation */
+ writel(lpddr2io & ~LPDDR2IO_GR10_WD_MASK,
+ &lpddr2io_regs->control_lpddr2io1_2);
+ writel(CONTROL_LPDDR2IO_3_VAL, &lpddr2io_regs->control_lpddr2io1_3);
+
+ /* EMIF2 */
+ writel(lpddr2io, &lpddr2io_regs->control_lpddr2io2_0);
+ writel(lpddr2io, &lpddr2io_regs->control_lpddr2io2_1);
+ /* No pull for GR10 as per hw team's recommendation */
+ writel(lpddr2io & ~LPDDR2IO_GR10_WD_MASK,
+ &lpddr2io_regs->control_lpddr2io2_2);
+ writel(CONTROL_LPDDR2IO_3_VAL, &lpddr2io_regs->control_lpddr2io2_3);
+
+ /*
+ * Some of these settings (TRIM values) come from eFuse and are
+ * in turn programmed in the eFuse at manufacturing time after
+ * calibration of the device. Do the software over-ride only if
+ * the device is not correctly trimmed
+ */
+ if (!(readl(&ctrl->control_std_fuse_opp_bgap) & 0xFFFF)) {
+
+ writel(LDOSRAM_VOLT_CTRL_OVERRIDE,
+ &ctrl->control_ldosram_iva_voltage_ctrl);
+
+ writel(LDOSRAM_VOLT_CTRL_OVERRIDE,
+ &ctrl->control_ldosram_mpu_voltage_ctrl);
+
+ writel(LDOSRAM_VOLT_CTRL_OVERRIDE,
+ &ctrl->control_ldosram_core_voltage_ctrl);
+ }
+
+ if (!readl(&ctrl->control_efuse_1))
+ writel(CONTROL_EFUSE_1_OVERRIDE, &ctrl->control_efuse_1);
+
+ if (!readl(&ctrl->control_efuse_2))
+ writel(CONTROL_EFUSE_2_OVERRIDE, &ctrl->control_efuse_2);
+}
+#endif
+
+void init_omap_revision(void)
+{
+ /*
+ * For some of the ES2/ES1 boards ID_CODE is not reliable:
+ * Also, ES1 and ES2 have different ARM revisions
+ * So use ARM revision for identification
+ */
+ unsigned int arm_rev = cortex_rev();
+
+ switch (arm_rev) {
+ case MIDR_CORTEX_A9_R0P1:
+ *omap4_revision = OMAP4430_ES1_0;
+ break;
+ case MIDR_CORTEX_A9_R1P2:
+ switch (readl(CONTROL_ID_CODE)) {
+ case OMAP4_CONTROL_ID_CODE_ES2_0:
+ *omap4_revision = OMAP4430_ES2_0;
+ break;
+ case OMAP4_CONTROL_ID_CODE_ES2_1:
+ *omap4_revision = OMAP4430_ES2_1;
+ break;
+ case OMAP4_CONTROL_ID_CODE_ES2_2:
+ *omap4_revision = OMAP4430_ES2_2;
+ break;
+ default:
+ *omap4_revision = OMAP4430_ES2_0;
+ break;
+ }
+ break;
+ case MIDR_CORTEX_A9_R1P3:
+ *omap4_revision = OMAP4430_ES2_3;
+ break;
+ case MIDR_CORTEX_A9_R2P10:
+ *omap4_revision = OMAP4460_ES1_0;
+ break;
+ default:
+ *omap4_revision = OMAP4430_SILICON_ID_INVALID;
+ break;
+ }
+}
+
+#ifndef CONFIG_SYS_L2CACHE_OFF
+void v7_outer_cache_enable(void)
+{
+ set_pl310_ctrl_reg(1);
+}
+
+void v7_outer_cache_disable(void)
+{
+ set_pl310_ctrl_reg(0);
+}
+#endif
diff --git a/arch/arm/cpu/armv7/omap4/omap4_mux_data.h b/arch/arm/cpu/armv7/omap4/omap4_mux_data.h
deleted file mode 100644
index b940391..0000000
--- a/arch/arm/cpu/armv7/omap4/omap4_mux_data.h
+++ /dev/null
@@ -1,83 +0,0 @@
- /*
- * (C) Copyright 2010
- * Texas Instruments Incorporated, <www.ti.com>
- *
- * Balaji Krishnamoorthy <balajitk@ti.com>
- * Aneesh V <aneesh@ti.com>
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-#ifndef _OMAP4_MUX_DATA_H_
-#define _OMAP4_MUX_DATA_H_
-
-#include <asm/arch/mux_omap4.h>
-
-const struct pad_conf_entry core_padconf_array_essential[] = {
-
-{GPMC_AD0, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M1)}, /* sdmmc2_dat0 */
-{GPMC_AD1, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M1)}, /* sdmmc2_dat1 */
-{GPMC_AD2, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M1)}, /* sdmmc2_dat2 */
-{GPMC_AD3, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M1)}, /* sdmmc2_dat3 */
-{GPMC_AD4, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M1)}, /* sdmmc2_dat4 */
-{GPMC_AD5, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M1)}, /* sdmmc2_dat5 */
-{GPMC_AD6, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M1)}, /* sdmmc2_dat6 */
-{GPMC_AD7, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M1)}, /* sdmmc2_dat7 */
-{GPMC_NOE, (PTU | IEN | OFF_EN | OFF_OUT_PTD | M1)}, /* sdmmc2_clk */
-{GPMC_NWE, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M1)}, /* sdmmc2_cmd */
-{SDMMC1_CLK, (PTU | OFF_EN | OFF_OUT_PTD | M0)}, /* sdmmc1_clk */
-{SDMMC1_CMD, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M0)}, /* sdmmc1_cmd */
-{SDMMC1_DAT0, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M0)}, /* sdmmc1_dat0 */
-{SDMMC1_DAT1, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M0)}, /* sdmmc1_dat1 */
-{SDMMC1_DAT2, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M0)}, /* sdmmc1_dat2 */
-{SDMMC1_DAT3, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M0)}, /* sdmmc1_dat3 */
-{SDMMC1_DAT4, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M0)}, /* sdmmc1_dat4 */
-{SDMMC1_DAT5, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M0)}, /* sdmmc1_dat5 */
-{SDMMC1_DAT6, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M0)}, /* sdmmc1_dat6 */
-{SDMMC1_DAT7, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M0)}, /* sdmmc1_dat7 */
-{I2C1_SCL, (PTU | IEN | M0)}, /* i2c1_scl */
-{I2C1_SDA, (PTU | IEN | M0)}, /* i2c1_sda */
-{I2C2_SCL, (PTU | IEN | M0)}, /* i2c2_scl */
-{I2C2_SDA, (PTU | IEN | M0)}, /* i2c2_sda */
-{I2C3_SCL, (PTU | IEN | M0)}, /* i2c3_scl */
-{I2C3_SDA, (PTU | IEN | M0)}, /* i2c3_sda */
-{I2C4_SCL, (PTU | IEN | M0)}, /* i2c4_scl */
-{I2C4_SDA, (PTU | IEN | M0)}, /* i2c4_sda */
-{UART3_CTS_RCTX, (PTU | IEN | M0)}, /* uart3_tx */
-{UART3_RTS_SD, (M0)}, /* uart3_rts_sd */
-{UART3_RX_IRRX, (IEN | M0)}, /* uart3_rx */
-{UART3_TX_IRTX, (M0)} /* uart3_tx */
-
-};
-
-const struct pad_conf_entry wkup_padconf_array_essential[] = {
-
-{PAD1_SR_SCL, (PTU | IEN | M0)}, /* sr_scl */
-{PAD0_SR_SDA, (PTU | IEN | M0)}, /* sr_sda */
-{PAD1_SYS_32K, (IEN | M0)} /* sys_32k */
-
-};
-
-const struct pad_conf_entry wkup_padconf_array_essential_4460[] = {
-
-{PAD1_FREF_CLK4_REQ, (M3)}, /* gpio_wk7, TPS */
-
-};
-
-
-#endif /* _OMAP4_MUX_DATA_H_ */
diff --git a/arch/arm/cpu/armv7/omap4/sdram_elpida.c b/arch/arm/cpu/armv7/omap4/sdram_elpida.c
index edc5326..a5ec7d3 100644
--- a/arch/arm/cpu/armv7/omap4/sdram_elpida.c
+++ b/arch/arm/cpu/armv7/omap4/sdram_elpida.c
@@ -26,7 +26,7 @@
* MA 02111-1307 USA
*/
-#include <asm/arch/emif.h>
+#include <asm/emif.h>
#include <asm/arch/sys_proto.h>
/*
diff --git a/arch/arm/cpu/armv7/omap4/sys_info.c b/arch/arm/cpu/armv7/omap4/sys_info.c
deleted file mode 100644
index b9e5765..0000000
--- a/arch/arm/cpu/armv7/omap4/sys_info.c
+++ /dev/null
@@ -1,53 +0,0 @@
-/*
- * (C) Copyright 2010
- * Texas Instruments, <www.ti.com>
- *
- * Author :
- * Aneesh V <aneesh@ti.com>
- * Steve Sakoman <steve@sakoman.com>
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-#include <common.h>
-#include <asm/arch/sys_proto.h>
-
-/*
- * get_device_type(): tell if GP/HS/EMU/TST
- */
-u32 get_device_type(void)
-{
- return 0;
-}
-
-/*
- * get_board_rev() - get board revision
- */
-u32 get_board_rev(void)
-{
- return 0x20;
-}
-
-/*
- * Print CPU information
- */
-int print_cpuinfo(void)
-{
-
- puts("CPU : OMAP4430\n");
-
- return 0;
-}
diff --git a/board/csb226/Makefile b/arch/arm/cpu/armv7/omap5/Makefile
similarity index 81%
copy from board/csb226/Makefile
copy to arch/arm/cpu/armv7/omap5/Makefile
index 6fe9bec..f8ca9ac 100644
--- a/board/csb226/Makefile
+++ b/arch/arm/cpu/armv7/omap5/Makefile
@@ -1,5 +1,5 @@
#
-# (C) Copyright 2000-2006
+# (C) Copyright 2000-2010
# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
#
# See file CREDITS for list of people who contributed to this
@@ -23,14 +23,19 @@
include $(TOPDIR)/config.mk
-LIB = $(obj)lib$(BOARD).o
+LIB = $(obj)lib$(SOC).o
-COBJS := csb226.o flash.o
+COBJS += hwinit.o
+COBJS += clocks.o
+COBJS += emif.o
+COBJS += sdram_elpida.o
-SRCS := $(COBJS:.o=.c)
-OBJS := $(addprefix $(obj),$(COBJS))
+SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c)
+OBJS := $(addprefix $(obj),$(COBJS) $(SOBJS))
-$(LIB): $(obj).depend $(OBJS)
+all: $(obj).depend $(LIB)
+
+$(LIB): $(OBJS)
$(call cmd_link_o_target, $(OBJS))
#########################################################################
diff --git a/arch/arm/cpu/armv7/omap5/clocks.c b/arch/arm/cpu/armv7/omap5/clocks.c
new file mode 100644
index 0000000..dd882a2
--- /dev/null
+++ b/arch/arm/cpu/armv7/omap5/clocks.c
@@ -0,0 +1,432 @@
+/*
+ *
+ * Clock initialization for OMAP5
+ *
+ * (C) Copyright 2010
+ * Texas Instruments, <www.ti.com>
+ *
+ * Aneesh V <aneesh@ti.com>
+ * Sricharan R <r.sricharan@ti.com>
+ *
+ * Based on previous work by:
+ * Santosh Shilimkar <santosh.shilimkar@ti.com>
+ * Rajendra Nayak <rnayak@ti.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+#include <common.h>
+#include <asm/omap_common.h>
+#include <asm/arch/clocks.h>
+#include <asm/arch/sys_proto.h>
+#include <asm/utils.h>
+#include <asm/omap_gpio.h>
+
+#ifndef CONFIG_SPL_BUILD
+/*
+ * printing to console doesn't work unless
+ * this code is executed from SPL
+ */
+#define printf(fmt, args...)
+#define puts(s)
+#endif
+
+struct omap5_prcm_regs *const prcm = (struct omap5_prcm_regs *)0x4A004100;
+
+const u32 sys_clk_array[8] = {
+ 12000000, /* 12 MHz */
+ 0, /* NA */
+ 16800000, /* 16.8 MHz */
+ 19200000, /* 19.2 MHz */
+ 26000000, /* 26 MHz */
+ 0, /* NA */
+ 38400000, /* 38.4 MHz */
+};
+
+static const struct dpll_params mpu_dpll_params_1_5ghz[NUM_SYS_CLKS] = {
+ {125, 0, 1, -1, -1, -1, -1, -1, -1, -1}, /* 12 MHz */
+ {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 13 MHz */
+ {625, 6, 1, -1, -1, -1, -1, -1, -1, -1}, /* 16.8 MHz */
+ {625, 7, 1, -1, -1, -1, -1, -1, -1, -1}, /* 19.2 MHz */
+ {750, 12, 1, -1, -1, -1, -1, -1, -1, -1}, /* 26 MHz */
+ {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 27 MHz */
+ {625, 15, 1, -1, -1, -1, -1, -1, -1, -1} /* 38.4 MHz */
+};
+
+static const struct dpll_params mpu_dpll_params_2ghz[NUM_SYS_CLKS] = {
+ {500, 2, 1, -1, -1, -1, -1, -1, -1, -1}, /* 12 MHz */
+ {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 13 MHz */
+ {2024, 16, 1, -1, -1, -1, -1, -1, -1, -1}, /* 16.8 MHz */
+ {625, 5, 1, -1, -1, -1, -1, -1, -1, -1}, /* 19.2 MHz */
+ {1000, 12, 1, -1, -1, -1, -1, -1, -1, -1}, /* 26 MHz */
+ {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 27 MHz */
+ {625, 11, 1, -1, -1, -1, -1, -1, -1, -1} /* 38.4 MHz */
+};
+
+static const struct dpll_params mpu_dpll_params_1100mhz[NUM_SYS_CLKS] = {
+ {275, 2, 1, -1, -1, -1, -1, -1, -1, -1}, /* 12 MHz */
+ {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 13 MHz */
+ {1375, 20, 1, -1, -1, -1, -1, -1, -1, -1}, /* 16.8 MHz */
+ {1375, 23, 1, -1, -1, -1, -1, -1, -1, -1}, /* 19.2 MHz */
+ {550, 12, 1, -1, -1, -1, -1, -1, -1, -1}, /* 26 MHz */
+ {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 27 MHz */
+ {1375, 47, 1, -1, -1, -1, -1, -1, -1, -1} /* 38.4 MHz */
+};
+
+static const struct dpll_params mpu_dpll_params_550mhz[NUM_SYS_CLKS] = {
+ {275, 2, 2, -1, -1, -1, -1, -1, -1, -1}, /* 12 MHz */
+ {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 13 MHz */
+ {1375, 20, 2, -1, -1, -1, -1, -1, -1, -1}, /* 16.8 MHz */
+ {1375, 23, 2, -1, -1, -1, -1, -1, -1, -1}, /* 19.2 MHz */
+ {550, 12, 2, -1, -1, -1, -1, -1, -1, -1}, /* 26 MHz */
+ {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 27 MHz */
+ {1375, 47, 2, -1, -1, -1, -1, -1, -1, -1} /* 38.4 MHz */
+};
+
+static const struct dpll_params
+ core_dpll_params_2128mhz_ddr532[NUM_SYS_CLKS] = {
+ {266, 2, 1, 5, 8, 4, 62, 5, 5, 7}, /* 12 MHz */
+ {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 13 MHz */
+ {570, 8, 1, 5, 8, 4, 62, 5, 5, 7}, /* 16.8 MHz */
+ {665, 11, 1, 5, 8, 4, 62, 5, 5, 7}, /* 19.2 MHz */
+ {532, 12, 1, 5, 8, 4, 62, 5, 5, 7}, /* 26 MHz */
+ {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 27 MHz */
+ {665, 23, 1, 5, 8, 4, 62, 5, 5, 7} /* 38.4 MHz */
+};
+
+static const struct dpll_params
+ core_dpll_params_2128mhz_ddr266[NUM_SYS_CLKS] = {
+ {266, 2, 2, 5, 8, 4, 62, 5, 5, 7}, /* 12 MHz */
+ {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 13 MHz */
+ {570, 8, 2, 5, 8, 4, 62, 5, 5, 7}, /* 16.8 MHz */
+ {665, 11, 2, 5, 8, 4, 62, 5, 5, 7}, /* 19.2 MHz */
+ {532, 12, 2, 5, 8, 4, 62, 5, 5, 7}, /* 26 MHz */
+ {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 27 MHz */
+ {665, 23, 2, 5, 8, 4, 62, 5, 5, 7} /* 38.4 MHz */
+};
+
+static const struct dpll_params per_dpll_params_768mhz[NUM_SYS_CLKS] = {
+ {32, 0, 4, 3, 6, 4, -1, 2, -1, -1}, /* 12 MHz */
+ {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 13 MHz */
+ {160, 6, 4, 3, 6, 4, -1, 2, -1, -1}, /* 16.8 MHz */
+ {20, 0, 4, 3, 6, 4, -1, 2, -1, -1}, /* 19.2 MHz */
+ {192, 12, 4, 3, 6, 4, -1, 2, -1, -1}, /* 26 MHz */
+ {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 27 MHz */
+ {10, 0, 4, 3, 6, 4, -1, 2, -1, -1} /* 38.4 MHz */
+};
+
+static const struct dpll_params iva_dpll_params_2330mhz[NUM_SYS_CLKS] = {
+ {931, 11, -1, -1, 4, 7, -1, -1}, /* 12 MHz */
+ {931, 12, -1, -1, 4, 7, -1, -1}, /* 13 MHz */
+ {665, 11, -1, -1, 4, 7, -1, -1}, /* 16.8 MHz */
+ {727, 14, -1, -1, 4, 7, -1, -1}, /* 19.2 MHz */
+ {931, 25, -1, -1, 4, 7, -1, -1}, /* 26 MHz */
+ {931, 26, -1, -1, 4, 7, -1, -1}, /* 27 MHz */
+ {412, 16, -1, -1, 4, 7, -1, -1} /* 38.4 MHz */
+};
+
+/* ABE M & N values with sys_clk as source */
+static const struct dpll_params
+ abe_dpll_params_sysclk_196608khz[NUM_SYS_CLKS] = {
+ {49, 5, 1, 1, -1, -1, -1, -1}, /* 12 MHz */
+ {68, 8, 1, 1, -1, -1, -1, -1}, /* 13 MHz */
+ {35, 5, 1, 1, -1, -1, -1, -1}, /* 16.8 MHz */
+ {46, 8, 1, 1, -1, -1, -1, -1}, /* 19.2 MHz */
+ {34, 8, 1, 1, -1, -1, -1, -1}, /* 26 MHz */
+ {29, 7, 1, 1, -1, -1, -1, -1}, /* 27 MHz */
+ {64, 24, 1, 1, -1, -1, -1, -1} /* 38.4 MHz */
+};
+
+/* ABE M & N values with 32K clock as source */
+static const struct dpll_params abe_dpll_params_32k_196608khz = {
+ 750, 0, 1, 1, -1, -1, -1, -1
+};
+
+static const struct dpll_params usb_dpll_params_1920mhz[NUM_SYS_CLKS] = {
+ {80, 0, 2, -1, -1, -1, -1, -1}, /* 12 MHz */
+ {960, 12, 2, -1, -1, -1, -1, -1}, /* 13 MHz */
+ {400, 6, 2, -1, -1, -1, -1, -1}, /* 16.8 MHz */
+ {50, 0, 2, -1, -1, -1, -1, -1}, /* 19.2 MHz */
+ {480, 12, 2, -1, -1, -1, -1, -1}, /* 26 MHz */
+ {320, 8, 2, -1, -1, -1, -1, -1}, /* 27 MHz */
+ {25, 0, 2, -1, -1, -1, -1, -1} /* 38.4 MHz */
+};
+
+void setup_post_dividers(u32 *const base, const struct dpll_params *params)
+{
+ struct dpll_regs *const dpll_regs = (struct dpll_regs *)base;
+
+ /* Setup post-dividers */
+ if (params->m2 >= 0)
+ writel(params->m2, &dpll_regs->cm_div_m2_dpll);
+ if (params->m3 >= 0)
+ writel(params->m3, &dpll_regs->cm_div_m3_dpll);
+ if (params->h11 >= 0)
+ writel(params->h11, &dpll_regs->cm_div_h11_dpll);
+ if (params->h12 >= 0)
+ writel(params->h12, &dpll_regs->cm_div_h12_dpll);
+ if (params->h13 >= 0)
+ writel(params->h13, &dpll_regs->cm_div_h13_dpll);
+ if (params->h14 >= 0)
+ writel(params->h14, &dpll_regs->cm_div_h14_dpll);
+ if (params->h22 >= 0)
+ writel(params->h22, &dpll_regs->cm_div_h22_dpll);
+ if (params->h23 >= 0)
+ writel(params->h23, &dpll_regs->cm_div_h23_dpll);
+}
+
+const struct dpll_params *get_mpu_dpll_params(void)
+{
+ u32 sysclk_ind = get_sys_clk_index();
+ return &mpu_dpll_params_1100mhz[sysclk_ind];
+}
+
+const struct dpll_params *get_core_dpll_params(void)
+{
+ u32 sysclk_ind = get_sys_clk_index();
+
+ /* Configuring the DDR to be at 532mhz */
+ return &core_dpll_params_2128mhz_ddr266[sysclk_ind];
+
+}
+
+const struct dpll_params *get_per_dpll_params(void)
+{
+ u32 sysclk_ind = get_sys_clk_index();
+ return &per_dpll_params_768mhz[sysclk_ind];
+}
+
+const struct dpll_params *get_iva_dpll_params(void)
+{
+ u32 sysclk_ind = get_sys_clk_index();
+ return &iva_dpll_params_2330mhz[sysclk_ind];
+}
+
+const struct dpll_params *get_usb_dpll_params(void)
+{
+ u32 sysclk_ind = get_sys_clk_index();
+ return &usb_dpll_params_1920mhz[sysclk_ind];
+}
+
+const struct dpll_params *get_abe_dpll_params(void)
+{
+#ifdef CONFIG_SYS_OMAP_ABE_SYSCK
+ u32 sysclk_ind = get_sys_clk_index();
+ return &abe_dpll_params_sysclk_196608khz[sysclk_ind];
+#else
+ return &abe_dpll_params_32k_196608khz;
+#endif
+}
+
+/*
+ * Setup the voltages for vdd_mpu, vdd_core, and vdd_iva
+ * We set the maximum voltages allowed here because Smart-Reflex is not
+ * enabled in bootloader. Voltage initialization in the kernel will set
+ * these to the nominal values after enabling Smart-Reflex
+ */
+void scale_vcores(void)
+{
+ u32 volt;
+
+ setup_sri2c();
+
+ /* Enable 1.22V from TPS for vdd_mpu */
+ volt = 1220;
+ do_scale_tps62361(TPS62361_REG_ADDR_SET1, volt);
+
+ /* VCORE 1 - for vdd_core */
+ volt = 1000;
+ do_scale_vcore(SMPS_REG_ADDR_VCORE1, volt);
+
+ /* VCORE 2 - for vdd_MM */
+ volt = 1125;
+ do_scale_vcore(SMPS_REG_ADDR_VCORE2, volt);
+}
+
+/*
+ * Enable essential clock domains, modules and
+ * do some additional special settings needed
+ */
+void enable_basic_clocks(void)
+{
+ u32 *const clk_domains_essential[] = {
+ &prcm->cm_l4per_clkstctrl,
+ &prcm->cm_l3init_clkstctrl,
+ &prcm->cm_memif_clkstctrl,
+ &prcm->cm_l4cfg_clkstctrl,
+ 0
+ };
+
+ u32 *const clk_modules_hw_auto_essential[] = {
+ &prcm->cm_memif_emif_1_clkctrl,
+ &prcm->cm_memif_emif_2_clkctrl,
+ &prcm->cm_l4cfg_l4_cfg_clkctrl,
+ &prcm->cm_wkup_gpio1_clkctrl,
+ &prcm->cm_l4per_gpio2_clkctrl,
+ &prcm->cm_l4per_gpio3_clkctrl,
+ &prcm->cm_l4per_gpio4_clkctrl,
+ &prcm->cm_l4per_gpio5_clkctrl,
+ &prcm->cm_l4per_gpio6_clkctrl,
+ 0
+ };
+
+ u32 *const clk_modules_explicit_en_essential[] = {
+ &prcm->cm_wkup_gptimer1_clkctrl,
+ &prcm->cm_l3init_hsmmc1_clkctrl,
+ &prcm->cm_l3init_hsmmc2_clkctrl,
+ &prcm->cm_l4per_gptimer2_clkctrl,
+ &prcm->cm_wkup_wdtimer2_clkctrl,
+ &prcm->cm_l4per_uart3_clkctrl,
+ &prcm->cm_l4per_i2c1_clkctrl,
+ 0
+ };
+
+ /* Enable optional additional functional clock for GPIO4 */
+ setbits_le32(&prcm->cm_l4per_gpio4_clkctrl,
+ GPIO4_CLKCTRL_OPTFCLKEN_MASK);
+
+ /* Enable 96 MHz clock for MMC1 & MMC2 */
+ setbits_le32(&prcm->cm_l3init_hsmmc1_clkctrl,
+ HSMMC_CLKCTRL_CLKSEL_MASK);
+ setbits_le32(&prcm->cm_l3init_hsmmc2_clkctrl,
+ HSMMC_CLKCTRL_CLKSEL_MASK);
+
+ /* Select 32KHz clock as the source of GPTIMER1 */
+ setbits_le32(&prcm->cm_wkup_gptimer1_clkctrl,
+ GPTIMER1_CLKCTRL_CLKSEL_MASK);
+
+ do_enable_clocks(clk_domains_essential,
+ clk_modules_hw_auto_essential,
+ clk_modules_explicit_en_essential,
+ 1);
+}
+
+void enable_basic_uboot_clocks(void)
+{
+ u32 *const clk_domains_essential[] = {
+ 0
+ };
+
+ u32 *const clk_modules_hw_auto_essential[] = {
+ 0
+ };
+
+ u32 *const clk_modules_explicit_en_essential[] = {
+ &prcm->cm_l4per_mcspi1_clkctrl,
+ &prcm->cm_l4per_i2c2_clkctrl,
+ &prcm->cm_l4per_i2c3_clkctrl,
+ &prcm->cm_l4per_i2c4_clkctrl,
+ 0
+ };
+
+ do_enable_clocks(clk_domains_essential,
+ clk_modules_hw_auto_essential,
+ clk_modules_explicit_en_essential,
+ 1);
+}
+
+/*
+ * Enable non-essential clock domains, modules and
+ * do some additional special settings needed
+ */
+void enable_non_essential_clocks(void)
+{
+ u32 *const clk_domains_non_essential[] = {
+ &prcm->cm_mpu_m3_clkstctrl,
+ &prcm->cm_ivahd_clkstctrl,
+ &prcm->cm_dsp_clkstctrl,
+ &prcm->cm_dss_clkstctrl,
+ &prcm->cm_sgx_clkstctrl,
+ &prcm->cm1_abe_clkstctrl,
+ &prcm->cm_c2c_clkstctrl,
+ &prcm->cm_cam_clkstctrl,
+ &prcm->cm_dss_clkstctrl,
+ &prcm->cm_sdma_clkstctrl,
+ 0
+ };
+
+ u32 *const clk_modules_hw_auto_non_essential[] = {
+ &prcm->cm_mpu_m3_mpu_m3_clkctrl,
+ &prcm->cm_ivahd_ivahd_clkctrl,
+ &prcm->cm_ivahd_sl2_clkctrl,
+ &prcm->cm_dsp_dsp_clkctrl,
+ &prcm->cm_l3_2_gpmc_clkctrl,
+ &prcm->cm_l3instr_l3_3_clkctrl,
+ &prcm->cm_l3instr_l3_instr_clkctrl,
+ &prcm->cm_l3instr_intrconn_wp1_clkctrl,
+ &prcm->cm_l3init_hsi_clkctrl,
+ &prcm->cm_l3init_hsusbtll_clkctrl,
+ 0
+ };
+
+ u32 *const clk_modules_explicit_en_non_essential[] = {
+ &prcm->cm1_abe_aess_clkctrl,
+ &prcm->cm1_abe_pdm_clkctrl,
+ &prcm->cm1_abe_dmic_clkctrl,
+ &prcm->cm1_abe_mcasp_clkctrl,
+ &prcm->cm1_abe_mcbsp1_clkctrl,
+ &prcm->cm1_abe_mcbsp2_clkctrl,
+ &prcm->cm1_abe_mcbsp3_clkctrl,
+ &prcm->cm1_abe_slimbus_clkctrl,
+ &prcm->cm1_abe_timer5_clkctrl,
+ &prcm->cm1_abe_timer6_clkctrl,
+ &prcm->cm1_abe_timer7_clkctrl,
+ &prcm->cm1_abe_timer8_clkctrl,
+ &prcm->cm1_abe_wdt3_clkctrl,
+ &prcm->cm_l4per_gptimer9_clkctrl,
+ &prcm->cm_l4per_gptimer10_clkctrl,
+ &prcm->cm_l4per_gptimer11_clkctrl,
+ &prcm->cm_l4per_gptimer3_clkctrl,
+ &prcm->cm_l4per_gptimer4_clkctrl,
+ &prcm->cm_l4per_hdq1w_clkctrl,
+ &prcm->cm_l4per_mcspi2_clkctrl,
+ &prcm->cm_l4per_mcspi3_clkctrl,
+ &prcm->cm_l4per_mcspi4_clkctrl,
+ &prcm->cm_l4per_mmcsd3_clkctrl,
+ &prcm->cm_l4per_mmcsd4_clkctrl,
+ &prcm->cm_l4per_mmcsd5_clkctrl,
+ &prcm->cm_l4per_uart1_clkctrl,
+ &prcm->cm_l4per_uart2_clkctrl,
+ &prcm->cm_l4per_uart4_clkctrl,
+ &prcm->cm_wkup_keyboard_clkctrl,
+ &prcm->cm_wkup_wdtimer2_clkctrl,
+ &prcm->cm_cam_iss_clkctrl,
+ &prcm->cm_cam_fdif_clkctrl,
+ &prcm->cm_dss_dss_clkctrl,
+ &prcm->cm_sgx_sgx_clkctrl,
+ &prcm->cm_l3init_hsusbhost_clkctrl,
+ &prcm->cm_l3init_fsusb_clkctrl,
+ 0
+ };
+
+ /* Enable optional functional clock for ISS */
+ setbits_le32(&prcm->cm_cam_iss_clkctrl, ISS_CLKCTRL_OPTFCLKEN_MASK);
+
+ /* Enable all optional functional clocks of DSS */
+ setbits_le32(&prcm->cm_dss_dss_clkctrl, DSS_CLKCTRL_OPTFCLKEN_MASK);
+
+ do_enable_clocks(clk_domains_non_essential,
+ clk_modules_hw_auto_non_essential,
+ clk_modules_explicit_en_non_essential,
+ 0);
+
+ /* Put camera module in no sleep mode */
+ clrsetbits_le32(&prcm->cm_cam_clkstctrl, MODULE_CLKCTRL_MODULEMODE_MASK,
+ CD_CLKCTRL_CLKTRCTRL_NO_SLEEP <<
+ MODULE_CLKCTRL_MODULEMODE_SHIFT);
+}
diff --git a/arch/arm/cpu/armv7/omap5/config.mk b/arch/arm/cpu/armv7/omap5/config.mk
new file mode 100644
index 0000000..639f699
--- /dev/null
+++ b/arch/arm/cpu/armv7/omap5/config.mk
@@ -0,0 +1,28 @@
+#
+# Copyright 2011 Linaro Limited
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# Aneesh V <annesh@ti.com>
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+ifdef CONFIG_SPL_BUILD
+ALL-y += $(OBJTREE)/MLO
+else
+ALL-y += $(obj)u-boot.img
+endif
diff --git a/arch/arm/cpu/armv7/omap5/emif.c b/arch/arm/cpu/armv7/omap5/emif.c
new file mode 100644
index 0000000..8019ffe
--- /dev/null
+++ b/arch/arm/cpu/armv7/omap5/emif.c
@@ -0,0 +1,105 @@
+/*
+ * EMIF programming
+ *
+ * (C) Copyright 2010
+ * Texas Instruments, <www.ti.com>
+ *
+ * Aneesh V <aneesh@ti.com> for OMAP4
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <asm/emif.h>
+#include <asm/arch/sys_proto.h>
+#include <asm/utils.h>
+
+#ifndef CONFIG_SYS_EMIF_PRECALCULATED_TIMING_REGS
+#define print_timing_reg(reg) debug(#reg" - 0x%08x\n", (reg))
+static u32 *const T_num = (u32 *)OMAP5_SRAM_SCRATCH_EMIF_T_NUM;
+static u32 *const T_den = (u32 *)OMAP5_SRAM_SCRATCH_EMIF_T_DEN;
+static u32 *const emif_sizes = (u32 *)OMAP5_SRAM_SCRATCH_EMIF_SIZE;
+#endif
+
+#ifdef CONFIG_SYS_DEFAULT_LPDDR2_TIMINGS
+/* Base AC Timing values specified by JESD209-2 for 532MHz operation */
+static const struct lpddr2_ac_timings timings_jedec_532_mhz = {
+ .max_freq = 532000000,
+ .RL = 8,
+ .tRPab = 21,
+ .tRCD = 18,
+ .tWR = 15,
+ .tRASmin = 42,
+ .tRRD = 10,
+ .tWTRx2 = 15,
+ .tXSR = 140,
+ .tXPx2 = 15,
+ .tRFCab = 130,
+ .tRTPx2 = 15,
+ .tCKE = 3,
+ .tCKESR = 15,
+ .tZQCS = 90,
+ .tZQCL = 360,
+ .tZQINIT = 1000,
+ .tDQSCKMAXx2 = 11,
+ .tRASmax = 70,
+ .tFAW = 50
+};
+
+/*
+ * Min tCK values specified by JESD209-2
+ * Min tCK specifies the minimum duration of some AC timing parameters in terms
+ * of the number of cycles. If the calculated number of cycles based on the
+ * absolute time value is less than the min tCK value, min tCK value should
+ * be used instead. This typically happens at low frequencies.
+ */
+static const struct lpddr2_min_tck min_tck_jedec = {
+ .tRL = 3,
+ .tRP_AB = 3,
+ .tRCD = 3,
+ .tWR = 3,
+ .tRAS_MIN = 3,
+ .tRRD = 2,
+ .tWTR = 2,
+ .tXP = 2,
+ .tRTP = 2,
+ .tCKE = 3,
+ .tCKESR = 3,
+ .tFAW = 8
+};
+
+static const struct lpddr2_ac_timings const*
+ jedec_ac_timings[MAX_NUM_SPEEDBINS] = {
+ &timings_jedec_532_mhz
+};
+
+static const struct lpddr2_device_timings jedec_default_timings = {
+ .ac_timings = jedec_ac_timings,
+ .min_tck = &min_tck_jedec
+};
+
+void emif_get_device_timings(u32 emif_nr,
+ const struct lpddr2_device_timings **cs0_device_timings,
+ const struct lpddr2_device_timings **cs1_device_timings)
+{
+ /* Assume Identical devices on EMIF1 & EMIF2 */
+ *cs0_device_timings = &jedec_default_timings;
+ *cs1_device_timings = NULL;
+}
+#endif /* CONFIG_SYS_DEFAULT_LPDDR2_TIMINGS */
diff --git a/arch/arm/cpu/armv7/omap5/hwinit.c b/arch/arm/cpu/armv7/omap5/hwinit.c
new file mode 100644
index 0000000..fa8e390
--- /dev/null
+++ b/arch/arm/cpu/armv7/omap5/hwinit.c
@@ -0,0 +1,78 @@
+/*
+ *
+ * Functions for omap5 based boards.
+ *
+ * (C) Copyright 2011
+ * Texas Instruments, <www.ti.com>
+ *
+ * Author :
+ * Aneesh V <aneesh@ti.com>
+ * Steve Sakoman <steve@sakoman.com>
+ * Sricharan <r.sricharan@ti.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+#include <common.h>
+#include <asm/armv7.h>
+#include <asm/arch/cpu.h>
+#include <asm/arch/sys_proto.h>
+#include <asm/sizes.h>
+#include <asm/utils.h>
+#include <asm/arch/gpio.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+u32 *const omap5_revision = (u32 *)OMAP5_SRAM_SCRATCH_OMAP5_REV;
+
+static struct gpio_bank gpio_bank_54xx[6] = {
+ { (void *)OMAP54XX_GPIO1_BASE, METHOD_GPIO_24XX },
+ { (void *)OMAP54XX_GPIO2_BASE, METHOD_GPIO_24XX },
+ { (void *)OMAP54XX_GPIO3_BASE, METHOD_GPIO_24XX },
+ { (void *)OMAP54XX_GPIO4_BASE, METHOD_GPIO_24XX },
+ { (void *)OMAP54XX_GPIO5_BASE, METHOD_GPIO_24XX },
+ { (void *)OMAP54XX_GPIO6_BASE, METHOD_GPIO_24XX },
+};
+
+const struct gpio_bank *const omap_gpio_bank = gpio_bank_54xx;
+
+#ifdef CONFIG_SPL_BUILD
+/*
+ * Some tuning of IOs for optimal power and performance
+ */
+void do_io_settings(void)
+{
+}
+#endif
+
+void init_omap_revision(void)
+{
+ /*
+ * For some of the ES2/ES1 boards ID_CODE is not reliable:
+ * Also, ES1 and ES2 have different ARM revisions
+ * So use ARM revision for identification
+ */
+ unsigned int rev = cortex_rev();
+
+ switch (rev) {
+ case MIDR_CORTEX_A15_R0P0:
+ *omap5_revision = OMAP5430_ES1_0;
+ default:
+ *omap5_revision = OMAP5430_SILICON_ID_INVALID;
+ }
+}
diff --git a/arch/arm/cpu/armv7/omap5/sdram_elpida.c b/arch/arm/cpu/armv7/omap5/sdram_elpida.c
new file mode 100644
index 0000000..ad198e6
--- /dev/null
+++ b/arch/arm/cpu/armv7/omap5/sdram_elpida.c
@@ -0,0 +1,178 @@
+/*
+ * Timing and Organization details of the Elpida parts used in OMAP5
+ * EVM
+ *
+ * (C) Copyright 2010
+ * Texas Instruments, <www.ti.com>
+ *
+ * Aneesh V <aneesh@ti.com>
+ * Sricharan R <r.sricharan@ti.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <asm/emif.h>
+#include <asm/arch/sys_proto.h>
+
+/*
+ * This file provides details of the LPDDR2 SDRAM parts used on OMAP5
+ * EVM. Since the parts used and geometry are identical for
+ * evm for a given OMAP5 revision, this information is kept
+ * here instead of being in board directory. However the key functions
+ * exported are weakly linked so that they can be over-ridden in the board
+ * directory if there is a OMAP5 board in the future that uses a different
+ * memory device or geometry.
+ *
+ * For any new board with different memory devices over-ride one or more
+ * of the following functions as per the CONFIG flags you intend to enable:
+ * - emif_get_reg_dump()
+ * - emif_get_dmm_regs()
+ * - emif_get_device_details()
+ * - emif_get_device_timings()
+ */
+
+#ifdef CONFIG_SYS_EMIF_PRECALCULATED_TIMING_REGS
+
+const struct emif_regs emif_regs_elpida_532_mhz_1cs = {
+ .sdram_config_init = 0x80801aB2,
+ .sdram_config = 0x808022B2,
+ .ref_ctrl = 0x0000081A,
+ .sdram_tim1 = 0x772F6873,
+ .sdram_tim2 = 0x304A129A,
+ .sdram_tim3 = 0x02F7E45F,
+ .read_idle_ctrl = 0x00050000,
+ .zq_config = 0x000B3215,
+ .temp_alert_config = 0x08000A05,
+ .emif_ddr_phy_ctlr_1_init = 0x0E38200D,
+ .emif_ddr_phy_ctlr_1 = 0x0E38200D
+};
+
+const struct dmm_lisa_map_regs lisa_map_4G_x_1_x_2 = {
+ .dmm_lisa_map_0 = 0xFF020100,
+ .dmm_lisa_map_1 = 0,
+ .dmm_lisa_map_2 = 0,
+ .dmm_lisa_map_3 = 0x80640300
+};
+
+static void emif_get_reg_dump_sdp(u32 emif_nr, const struct emif_regs **regs)
+{
+ *regs = &emif_regs_elpida_532_mhz_1cs;
+}
+void emif_get_reg_dump(u32 emif_nr, const struct emif_regs **regs)
+ __attribute__((weak, alias("emif_get_reg_dump_sdp")));
+
+static void emif_get_dmm_regs_sdp(const struct dmm_lisa_map_regs
+ **dmm_lisa_regs)
+{
+ *dmm_lisa_regs = &lisa_map_4G_x_1_x_2;
+}
+
+void emif_get_dmm_regs(const struct dmm_lisa_map_regs **dmm_lisa_regs)
+ __attribute__((weak, alias("emif_get_dmm_regs_sdp")));
+
+#else
+
+static const struct lpddr2_device_details elpida_4G_S4_details = {
+ .type = LPDDR2_TYPE_S4,
+ .density = LPDDR2_DENSITY_4Gb,
+ .io_width = LPDDR2_IO_WIDTH_32,
+ .manufacturer = LPDDR2_MANUFACTURER_ELPIDA
+};
+
+static void emif_get_device_details_sdp(u32 emif_nr,
+ struct lpddr2_device_details *cs0_device_details,
+ struct lpddr2_device_details *cs1_device_details)
+{
+ /* EMIF1 & EMIF2 have identical configuration */
+ *cs0_device_details = elpida_4G_S4_details;
+
+ /* Nothing is conected on cs1 */
+ cs1_device_details = NULL;
+}
+
+void emif_get_device_details(u32 emif_nr,
+ struct lpddr2_device_details *cs0_device_details,
+ struct lpddr2_device_details *cs1_device_details)
+ __attribute__((weak, alias("emif_get_device_details_sdp")));
+
+#endif /* CONFIG_SYS_EMIF_PRECALCULATED_TIMING_REGS */
+
+#ifndef CONFIG_SYS_DEFAULT_LPDDR2_TIMINGS
+static const struct lpddr2_ac_timings timings_jedec_532_mhz = {
+ .max_freq = 532000000,
+ .RL = 8,
+ .tRPab = 21,
+ .tRCD = 18,
+ .tWR = 15,
+ .tRASmin = 42,
+ .tRRD = 10,
+ .tWTRx2 = 15,
+ .tXSR = 140,
+ .tXPx2 = 15,
+ .tRFCab = 130,
+ .tRTPx2 = 15,
+ .tCKE = 3,
+ .tCKESR = 15,
+ .tZQCS = 90,
+ .tZQCL = 360,
+ .tZQINIT = 1000,
+ .tDQSCKMAXx2 = 11,
+ .tRASmax = 70,
+ .tFAW = 50
+};
+
+static const struct lpddr2_min_tck min_tck_elpida = {
+ .tRL = 3,
+ .tRP_AB = 3,
+ .tRCD = 3,
+ .tWR = 3,
+ .tRAS_MIN = 3,
+ .tRRD = 2,
+ .tWTR = 2,
+ .tXP = 2,
+ .tRTP = 2,
+ .tCKE = 3,
+ .tCKESR = 3,
+ .tFAW = 8
+};
+
+static const struct lpddr2_ac_timings *elpida_ac_timings[MAX_NUM_SPEEDBINS] = {
+ &timings_jedec_532_mhz
+};
+
+static const struct lpddr2_device_timings elpida_4G_S4_timings = {
+ .ac_timings = elpida_ac_timings,
+ .min_tck = &min_tck_elpida,
+};
+
+void emif_get_device_timings_sdp(u32 emif_nr,
+ const struct lpddr2_device_timings **cs0_device_timings,
+ const struct lpddr2_device_timings **cs1_device_timings)
+{
+ /* Identical devices on EMIF1 & EMIF2 */
+ *cs0_device_timings = &elpida_4G_S4_timings;
+ *cs1_device_timings = NULL;
+}
+
+void emif_get_device_timings(u32 emif_nr,
+ const struct lpddr2_device_timings **cs0_device_timings,
+ const struct lpddr2_device_timings **cs1_device_timings)
+ __attribute__((weak, alias("emif_get_device_timings_sdp")));
+
+#endif /* CONFIG_SYS_DEFAULT_LPDDR2_TIMINGS */
diff --git a/arch/arm/cpu/armv7/s5p-common/pwm.c b/arch/arm/cpu/armv7/s5p-common/pwm.c
index ff95b84..58d279e 100644
--- a/arch/arm/cpu/armv7/s5p-common/pwm.c
+++ b/arch/arm/cpu/armv7/s5p-common/pwm.c
@@ -82,7 +82,6 @@
unsigned long period;
unsigned long tcon;
unsigned long tcnt;
- unsigned long timer_rate_hz;
unsigned long tcmp;
/*
@@ -100,7 +99,6 @@
/* Check to see if we are changing the clock rate of the PWM */
tin_rate = pwm_calc_tin(pwm_id, period);
- timer_rate_hz = tin_rate;
tin_ns = NS_IN_HZ / tin_rate;
tcnt = period_ns / tin_ns;
diff --git a/arch/arm/include/asm/arch-davinci/aintc_defs.h b/arch/arm/include/asm/arch-davinci/aintc_defs.h
index 8f37053..38f814c 100644
--- a/arch/arm/include/asm/arch-davinci/aintc_defs.h
+++ b/arch/arm/include/asm/arch-davinci/aintc_defs.h
@@ -47,4 +47,6 @@
#define dv_aintc_regs ((struct dv_aintc_regs *)DAVINCI_ARM_INTC_BASE)
+#define DV_AINTC_INTCTL_IDMODE (1 << 2)
+
#endif /* _DV_AINTC_DEFS_H_ */
diff --git a/arch/arm/include/asm/arch-davinci/am1808_lowlevel.h b/arch/arm/include/asm/arch-davinci/da850_lowlevel.h
similarity index 63%
rename from arch/arm/include/asm/arch-davinci/am1808_lowlevel.h
rename to arch/arm/include/asm/arch-davinci/da850_lowlevel.h
index 0bc7f76..e489c47 100644
--- a/arch/arm/include/asm/arch-davinci/am1808_lowlevel.h
+++ b/arch/arm/include/asm/arch-davinci/da850_lowlevel.h
@@ -1,5 +1,5 @@
/*
- * SoC-specific lowlevel code for AM1808 and similar chips
+ * SoC-specific lowlevel code for DA850
*
* Copyright (C) 2011
* Heiko Schocher, DENX Software Engineering, hs@denx.de.
@@ -21,24 +21,24 @@
* along with this program; if not, write to the Free Software
* Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
*/
-#ifndef __AM1808_LOWLEVEL_H
-#define __AM1808_LOWLEVEL_H
+#ifndef __DA850_LOWLEVEL_H
+#define __DA850_LOWLEVEL_H
/* NOR Boot Configuration Word Field Descriptions */
-#define AM1808_NORBOOT_COPY_XK(X) ((X - 1) << 8)
-#define AM1808_NORBOOT_METHOD_DIRECT (1 << 4)
-#define AM1808_NORBOOT_16BIT (1 << 0)
+#define DA850_NORBOOT_COPY_XK(X) ((X - 1) << 8)
+#define DA850_NORBOOT_METHOD_DIRECT (1 << 4)
+#define DA850_NORBOOT_16BIT (1 << 0)
#define dv_maskbits(addr, val) \
writel((readl(addr) & val), addr)
-void am1808_waitloop(unsigned long loopcnt);
-int am1808_pll_init(struct davinci_pllc_regs *reg, unsigned long pllmult);
-void am1808_lpc_transition(unsigned char pscnum, unsigned char module,
+void da850_waitloop(unsigned long loopcnt);
+int da850_pll_init(struct davinci_pllc_regs *reg, unsigned long pllmult);
+void da850_lpc_transition(unsigned char pscnum, unsigned char module,
unsigned char domain, unsigned char state);
-int am1808_ddr_setup(unsigned int freq);
-void am1808_psc_init(void);
-void am1808_pinmux_ctl(unsigned long offset, unsigned long mask,
+int da850_ddr_setup(void);
+void da850_psc_init(void);
+void da850_pinmux_ctl(unsigned long offset, unsigned long mask,
unsigned long value);
-#endif /* #ifndef __AM1808_LOWLEVEL_H */
+#endif /* #ifndef __DA850_LOWLEVEL_H */
diff --git a/arch/arm/include/asm/arch-davinci/ddr2_defs.h b/arch/arm/include/asm/arch-davinci/ddr2_defs.h
index 1b9430c..4f943b8 100644
--- a/arch/arm/include/asm/arch-davinci/ddr2_defs.h
+++ b/arch/arm/include/asm/arch-davinci/ddr2_defs.h
@@ -63,6 +63,7 @@
#define DV_DDR_SDTMR2_RASMAX_SHIFT 27
#define DV_DDR_SDTMR2_XP_SHIFT 25
+#define DV_DDR_SDTMR2_ODT_SHIFT 23
#define DV_DDR_SDTMR2_XSNR_SHIFT 16
#define DV_DDR_SDTMR2_XSRD_SHIFT 8
#define DV_DDR_SDTMR2_RTP_SHIFT 5
@@ -84,6 +85,9 @@
#define DV_DDR_SDCR_IBANK_SHIFT 4
#define DV_DDR_SDCR_PAGESIZE_SHIFT 0
+#define DV_DDR_SDRCR_LPMODEN (1 << 31)
+#define DV_DDR_SDRCR_MCLKSTOPEN (1 << 30)
+
#define DV_DDR_SRCR_LPMODEN_SHIFT 31
#define DV_DDR_SRCR_MCLKSTOPEN_SHIFT 30
diff --git a/arch/arm/include/asm/arch-davinci/emif_defs.h b/arch/arm/include/asm/arch-davinci/emif_defs.h
index b48ec17..b9e78a5 100644
--- a/arch/arm/include/asm/arch-davinci/emif_defs.h
+++ b/arch/arm/include/asm/arch-davinci/emif_defs.h
@@ -70,6 +70,7 @@
#define DAVINCI_NANDFCR_1BIT_ECC_START(n) (1 << (8 + (n-2)))
#define DAVINCI_NANDFCR_4BIT_ECC_START (1 << 12)
#define DAVINCI_NANDFCR_4BIT_CALC_START (1 << 13)
+#define DAVINCI_NANDFCR_CS2NAND (1 << 0)
/* Chip Select setup */
#define DAVINCI_ABCR_STROBE_SELECT (1 << 31)
diff --git a/arch/arm/include/asm/arch-davinci/hardware.h b/arch/arm/include/asm/arch-davinci/hardware.h
index bea1499..3e9a3b6 100644
--- a/arch/arm/include/asm/arch-davinci/hardware.h
+++ b/arch/arm/include/asm/arch-davinci/hardware.h
@@ -230,6 +230,9 @@
#define DAVINCI_LPSC_CFG5 38
#define DAVINCI_LPSC_GEM 39
#define DAVINCI_LPSC_IMCOP 40
+#define DAVINCI_LPSC_VPSSMASTER 47
+#define DAVINCI_LPSC_MJCP 50
+#define DAVINCI_LPSC_HDVICP 51
#define DAVINCI_DM646X_LPSC_EMAC 14
#define DAVINCI_DM646X_LPSC_UART0 26
@@ -385,6 +388,20 @@
#define PINMUX3 0x01c4000c
#define PINMUX4 0x01c40010
+struct davinci_uart_ctrl_regs {
+ dv_reg revid1;
+ dv_reg res;
+ dv_reg pwremu_mgmt;
+ dv_reg mdr;
+};
+
+#define DAVINCI_UART_CTRL_BASE 0x28
+
+/* UART PWREMU_MGMT definitions */
+#define DAVINCI_UART_PWREMU_MGMT_FREE (1 << 0)
+#define DAVINCI_UART_PWREMU_MGMT_URRST (1 << 13)
+#define DAVINCI_UART_PWREMU_MGMT_UTRST (1 << 14)
+
#else /* CONFIG_SOC_DA8XX */
struct davinci_pllc_regs {
@@ -431,6 +448,7 @@
enum davinci_clk_ids {
DAVINCI_SPI0_CLKID = 2,
DAVINCI_UART2_CLKID = 2,
+ DAVINCI_MMC_CLKID = 2,
DAVINCI_MDIO_CLKID = 4,
DAVINCI_ARM_CLKID = 6,
DAVINCI_PLLM_CLKID = 0xff,
@@ -468,6 +486,7 @@
#define DAVINCI_SYSCFG_SUSPSRC_SPI0 (1 << 21)
#define DAVINCI_SYSCFG_SUSPSRC_SPI1 (1 << 22)
#define DAVINCI_SYSCFG_SUSPSRC_UART0 (1 << 18)
+#define DAVINCI_SYSCFG_SUSPSRC_UART2 (1 << 20)
#define DAVINCI_SYSCFG_SUSPSRC_TIMER0 (1 << 27)
struct davinci_syscfg1_regs {
@@ -491,6 +510,9 @@
#define VTP_READY (1 << 15)
#define VTP_IOPWRDWN (1 << 14)
+#define DV_SYSCFG_KICK0_UNLOCK 0x83e70b13
+#define DV_SYSCFG_KICK1_UNLOCK 0x95a4f1e0
+
/* Interrupt controller */
struct davinci_aintc_regs {
dv_reg revid;
diff --git a/arch/arm/include/asm/arch-davinci/pll_defs.h b/arch/arm/include/asm/arch-davinci/pll_defs.h
index 5c30953..f1396e3 100644
--- a/arch/arm/include/asm/arch-davinci/pll_defs.h
+++ b/arch/arm/include/asm/arch-davinci/pll_defs.h
@@ -57,11 +57,24 @@
unsigned int plldiv9; /* 0x174 */
};
+#define PLL_MASTER_LOCK (1 << 4)
+
+#define PLLCTL_CLOCK_MODE_SHIFT 8
#define PLLCTL_PLLEN (1 << 0)
#define PLLCTL_PLLPWRDN (1 << 1)
#define PLLCTL_PLLRST (1 << 3)
+#define PLLCTL_PLLDIS (1 << 4)
#define PLLCTL_PLLENSRC (1 << 5)
#define PLLCTL_RES_9 (1 << 8)
+#define PLLCTL_EXTCLKSRC (1 << 9)
+
+#define PLL_POSTDEN (1 << 15)
+
+#define PLL_SCSCFG3_DIV45PENA (1 << 2)
+#define PLL_SCSCFG3_EMA_CLKSRC (1 << 1)
+
+#define PLL_RSTYPE_POR (1 << 0)
+#define PLL_RSTYPE_XWRST (1 << 1)
#define PLLSECCTL_TINITZ (1 << 16)
#define PLLSECCTL_TENABLE (1 << 17)
@@ -69,6 +82,7 @@
#define PLLSECCTL_STOPMODE (1 << 22)
#define PLLCMD_GOSET (1 << 0)
+#define PLLCMD_GOSTAT (1 << 0)
#define PLL0_LOCK 0x07000000
#define PLL1_LOCK 0x07000000
diff --git a/arch/arm/include/asm/arch-mx28/clock.h b/arch/arm/include/asm/arch-mx28/clock.h
new file mode 100644
index 0000000..1700fe3
--- /dev/null
+++ b/arch/arm/include/asm/arch-mx28/clock.h
@@ -0,0 +1,61 @@
+/*
+ * Freescale i.MX28 Clock
+ *
+ * Copyright (C) 2011 Marek Vasut <marek.vasut@gmail.com>
+ * on behalf of DENX Software Engineering GmbH
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
+ *
+ */
+
+#ifndef __CLOCK_H__
+#define __CLOCK_H__
+
+enum mxc_clock {
+ MXC_ARM_CLK = 0,
+ MXC_AHB_CLK,
+ MXC_IPG_CLK,
+ MXC_EMI_CLK,
+ MXC_GPMI_CLK,
+ MXC_IO0_CLK,
+ MXC_IO1_CLK,
+ MXC_SSP0_CLK,
+ MXC_SSP1_CLK,
+ MXC_SSP2_CLK,
+ MXC_SSP3_CLK,
+};
+
+enum mxs_ioclock {
+ MXC_IOCLK0 = 0,
+ MXC_IOCLK1,
+};
+
+enum mxs_sspclock {
+ MXC_SSPCLK0 = 0,
+ MXC_SSPCLK1,
+ MXC_SSPCLK2,
+ MXC_SSPCLK3,
+};
+
+uint32_t mxc_get_clock(enum mxc_clock clk);
+
+void mx28_set_ioclk(enum mxs_ioclock io, uint32_t freq);
+void mx28_set_sspclk(enum mxs_sspclock ssp, uint32_t freq, int xtal);
+void mx28_set_ssp_busclock(unsigned int bus, uint32_t freq);
+
+/* Compatibility with the FEC Ethernet driver */
+#define imx_get_fecclk() mxc_get_clock(MXC_AHB_CLK)
+
+#endif /* __CLOCK_H__ */
diff --git a/arch/arm/include/asm/arch-mx28/dma.h b/arch/arm/include/asm/arch-mx28/dma.h
new file mode 100644
index 0000000..7061e7c
--- /dev/null
+++ b/arch/arm/include/asm/arch-mx28/dma.h
@@ -0,0 +1,170 @@
+/*
+ * Freescale i.MX28 APBH DMA
+ *
+ * Copyright (C) 2011 Marek Vasut <marek.vasut@gmail.com>
+ * on behalf of DENX Software Engineering GmbH
+ *
+ * Based on code from LTIB:
+ * Copyright 2008-2010 Freescale Semiconductor, Inc. All Rights Reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
+ *
+ */
+
+#ifndef __DMA_H__
+#define __DMA_H__
+
+#include <linux/list.h>
+
+#ifndef CONFIG_ARCH_DMA_PIO_WORDS
+#define DMA_PIO_WORDS 15
+#else
+#define DMA_PIO_WORDS CONFIG_ARCH_DMA_PIO_WORDS
+#endif
+
+#define MXS_DMA_ALIGNMENT 32
+
+/*
+ * MXS DMA channels
+ */
+enum {
+ MXS_DMA_CHANNEL_AHB_APBH_SSP0 = 0,
+ MXS_DMA_CHANNEL_AHB_APBH_SSP1,
+ MXS_DMA_CHANNEL_AHB_APBH_SSP2,
+ MXS_DMA_CHANNEL_AHB_APBH_SSP3,
+ MXS_DMA_CHANNEL_AHB_APBH_GPMI0,
+ MXS_DMA_CHANNEL_AHB_APBH_GPMI1,
+ MXS_DMA_CHANNEL_AHB_APBH_GPMI2,
+ MXS_DMA_CHANNEL_AHB_APBH_GPMI3,
+ MXS_DMA_CHANNEL_AHB_APBH_GPMI4,
+ MXS_DMA_CHANNEL_AHB_APBH_GPMI5,
+ MXS_DMA_CHANNEL_AHB_APBH_GPMI6,
+ MXS_DMA_CHANNEL_AHB_APBH_GPMI7,
+ MXS_DMA_CHANNEL_AHB_APBH_SSP,
+ MXS_MAX_DMA_CHANNELS,
+};
+
+/*
+ * MXS DMA hardware command.
+ *
+ * This structure describes the in-memory layout of an entire DMA command,
+ * including space for the maximum number of PIO accesses. See the appropriate
+ * reference manual for a detailed description of what these fields mean to the
+ * DMA hardware.
+ */
+#define MXS_DMA_DESC_COMMAND_MASK 0x3
+#define MXS_DMA_DESC_COMMAND_OFFSET 0
+#define MXS_DMA_DESC_COMMAND_NO_DMAXFER 0x0
+#define MXS_DMA_DESC_COMMAND_DMA_WRITE 0x1
+#define MXS_DMA_DESC_COMMAND_DMA_READ 0x2
+#define MXS_DMA_DESC_COMMAND_DMA_SENSE 0x3
+#define MXS_DMA_DESC_CHAIN (1 << 2)
+#define MXS_DMA_DESC_IRQ (1 << 3)
+#define MXS_DMA_DESC_NAND_LOCK (1 << 4)
+#define MXS_DMA_DESC_NAND_WAIT_4_READY (1 << 5)
+#define MXS_DMA_DESC_DEC_SEM (1 << 6)
+#define MXS_DMA_DESC_WAIT4END (1 << 7)
+#define MXS_DMA_DESC_HALT_ON_TERMINATE (1 << 8)
+#define MXS_DMA_DESC_TERMINATE_FLUSH (1 << 9)
+#define MXS_DMA_DESC_PIO_WORDS_MASK (0xf << 12)
+#define MXS_DMA_DESC_PIO_WORDS_OFFSET 12
+#define MXS_DMA_DESC_BYTES_MASK (0xffff << 16)
+#define MXS_DMA_DESC_BYTES_OFFSET 16
+
+struct mxs_dma_cmd {
+ unsigned long next;
+ unsigned long data;
+ union {
+ dma_addr_t address;
+ unsigned long alternate;
+ };
+ unsigned long pio_words[DMA_PIO_WORDS];
+};
+
+/*
+ * MXS DMA command descriptor.
+ *
+ * This structure incorporates an MXS DMA hardware command structure, along
+ * with metadata.
+ */
+#define MXS_DMA_DESC_FIRST (1 << 0)
+#define MXS_DMA_DESC_LAST (1 << 1)
+#define MXS_DMA_DESC_READY (1 << 31)
+
+struct mxs_dma_desc {
+ struct mxs_dma_cmd cmd;
+ unsigned int flags;
+ dma_addr_t address;
+ void *buffer;
+ struct list_head node;
+};
+
+/**
+ * MXS DMA channel
+ *
+ * This structure represents a single DMA channel. The MXS platform code
+ * maintains an array of these structures to represent every DMA channel in the
+ * system (see mxs_dma_channels).
+ */
+#define MXS_DMA_FLAGS_IDLE 0
+#define MXS_DMA_FLAGS_BUSY (1 << 0)
+#define MXS_DMA_FLAGS_FREE 0
+#define MXS_DMA_FLAGS_ALLOCATED (1 << 16)
+#define MXS_DMA_FLAGS_VALID (1 << 31)
+
+struct mxs_dma_chan {
+ const char *name;
+ unsigned long dev;
+ struct mxs_dma_device *dma;
+ unsigned int flags;
+ unsigned int active_num;
+ unsigned int pending_num;
+ struct list_head active;
+ struct list_head done;
+};
+
+/* Hardware management ops */
+int mxs_dma_enable(int channel);
+int mxs_dma_disable(int channel);
+int mxs_dma_reset(int channel);
+int mxs_dma_freeze(int channel);
+int mxs_dma_unfreeze(int channel);
+int mxs_dma_read_semaphore(int channel);
+int mxs_dma_enable_irq(int channel, int enable);
+int mxs_dma_irq_is_pending(int channel);
+int mxs_dma_ack_irq(int channel);
+
+/* Channel management ops */
+int mxs_dma_request(int channel);
+int mxs_dma_release(int channel);
+
+/* Descriptor management ops */
+struct mxs_dma_desc *mxs_dma_desc_alloc(void);
+void mxs_dma_desc_free(struct mxs_dma_desc *);
+
+unsigned int mxs_dma_cmd_address(struct mxs_dma_desc *desc);
+int mxs_dma_desc_pending(struct mxs_dma_desc *pdesc);
+
+int mxs_dma_desc_append(int channel, struct mxs_dma_desc *pdesc);
+
+int mxs_dma_get_finished(int channel, struct list_head *head);
+int mxs_dma_finish(int channel, struct list_head *head);
+
+int mxs_dma_wait_complete(uint32_t timeout, unsigned int chan);
+int mxs_dma_go(int chan);
+
+int mxs_dma_init(void);
+
+#endif /* __DMA_H__ */
diff --git a/arch/arm/include/asm/arch-mx28/gpio.h b/arch/arm/include/asm/arch-mx28/gpio.h
new file mode 100644
index 0000000..be1c944
--- /dev/null
+++ b/arch/arm/include/asm/arch-mx28/gpio.h
@@ -0,0 +1,32 @@
+/*
+ * Freescale i.MX28 GPIO
+ *
+ * Copyright (C) 2011 Marek Vasut <marek.vasut@gmail.com>
+ * on behalf of DENX Software Engineering GmbH
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
+ *
+ */
+
+#ifndef __MX28_GPIO_H__
+#define __MX28_GPIO_H__
+
+#ifdef CONFIG_MXS_GPIO
+void mxs_gpio_init(void);
+#else
+inline void mxs_gpio_init(void) {}
+#endif
+
+#endif /* __MX28_GPIO_H__ */
diff --git a/arch/arm/include/asm/arch-mx28/imx-regs.h b/arch/arm/include/asm/arch-mx28/imx-regs.h
new file mode 100644
index 0000000..9561b5e
--- /dev/null
+++ b/arch/arm/include/asm/arch-mx28/imx-regs.h
@@ -0,0 +1,39 @@
+/*
+ * Freescale i.MX28 Registers
+ *
+ * Copyright (C) 2011 Marek Vasut <marek.vasut@gmail.com>
+ * on behalf of DENX Software Engineering GmbH
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
+ *
+ */
+
+#ifndef __IMX_REGS_H__
+#define __IMX_REGS_H__
+
+#include <asm/arch/regs-apbh.h>
+#include <asm/arch/regs-base.h>
+#include <asm/arch/regs-bch.h>
+#include <asm/arch/regs-clkctrl.h>
+#include <asm/arch/regs-gpmi.h>
+#include <asm/arch/regs-i2c.h>
+#include <asm/arch/regs-ocotp.h>
+#include <asm/arch/regs-pinctrl.h>
+#include <asm/arch/regs-power.h>
+#include <asm/arch/regs-rtc.h>
+#include <asm/arch/regs-ssp.h>
+#include <asm/arch/regs-timrot.h>
+
+#endif /* __IMX_REGS_H__ */
diff --git a/arch/arm/include/asm/arch-mx28/iomux-mx28.h b/arch/arm/include/asm/arch-mx28/iomux-mx28.h
new file mode 100644
index 0000000..b42820d
--- /dev/null
+++ b/arch/arm/include/asm/arch-mx28/iomux-mx28.h
@@ -0,0 +1,537 @@
+/*
+ * Copyright (C) 2009-2010 Amit Kucheria <amit.kucheria@canonical.com>
+ * Copyright (C) 2010 Freescale Semiconductor, Inc.
+ *
+ * The code contained herein is licensed under the GNU General Public
+ * License. You may obtain a copy of the GNU General Public License
+ * Version 2 or later at the following locations:
+ *
+ * http://www.opensource.org/licenses/gpl-license.html
+ * http://www.gnu.org/copyleft/gpl.html
+ */
+
+#ifndef __MACH_IOMUX_MX28_H__
+#define __MACH_IOMUX_MX28_H__
+
+#include <asm/arch/iomux.h>
+
+/*
+ * The naming convention for the pad modes is MX28_PAD_<padname>__<padmode>
+ * If <padname> or <padmode> refers to a GPIO, it is named GPIO_<unit>_<num>
+ * See also iomux.h
+ *
+ * BANK PIN MUX
+ */
+/* MUXSEL_0 */
+#define MX28_PAD_GPMI_D00__GPMI_D0 MXS_IOMUX_PAD_NAKED(0, 0, PAD_MUXSEL_0)
+#define MX28_PAD_GPMI_D01__GPMI_D1 MXS_IOMUX_PAD_NAKED(0, 1, PAD_MUXSEL_0)
+#define MX28_PAD_GPMI_D02__GPMI_D2 MXS_IOMUX_PAD_NAKED(0, 2, PAD_MUXSEL_0)
+#define MX28_PAD_GPMI_D03__GPMI_D3 MXS_IOMUX_PAD_NAKED(0, 3, PAD_MUXSEL_0)
+#define MX28_PAD_GPMI_D04__GPMI_D4 MXS_IOMUX_PAD_NAKED(0, 4, PAD_MUXSEL_0)
+#define MX28_PAD_GPMI_D05__GPMI_D5 MXS_IOMUX_PAD_NAKED(0, 5, PAD_MUXSEL_0)
+#define MX28_PAD_GPMI_D06__GPMI_D6 MXS_IOMUX_PAD_NAKED(0, 6, PAD_MUXSEL_0)
+#define MX28_PAD_GPMI_D07__GPMI_D7 MXS_IOMUX_PAD_NAKED(0, 7, PAD_MUXSEL_0)
+#define MX28_PAD_GPMI_CE0N__GPMI_CE0N MXS_IOMUX_PAD_NAKED(0, 16, PAD_MUXSEL_0)
+#define MX28_PAD_GPMI_CE1N__GPMI_CE1N MXS_IOMUX_PAD_NAKED(0, 17, PAD_MUXSEL_0)
+#define MX28_PAD_GPMI_CE2N__GPMI_CE2N MXS_IOMUX_PAD_NAKED(0, 18, PAD_MUXSEL_0)
+#define MX28_PAD_GPMI_CE3N__GPMI_CE3N MXS_IOMUX_PAD_NAKED(0, 19, PAD_MUXSEL_0)
+#define MX28_PAD_GPMI_RDY0__GPMI_READY0 MXS_IOMUX_PAD_NAKED(0, 20, PAD_MUXSEL_0)
+#define MX28_PAD_GPMI_RDY1__GPMI_READY1 MXS_IOMUX_PAD_NAKED(0, 21, PAD_MUXSEL_0)
+#define MX28_PAD_GPMI_RDY2__GPMI_READY2 MXS_IOMUX_PAD_NAKED(0, 22, PAD_MUXSEL_0)
+#define MX28_PAD_GPMI_RDY3__GPMI_READY3 MXS_IOMUX_PAD_NAKED(0, 23, PAD_MUXSEL_0)
+#define MX28_PAD_GPMI_RDN__GPMI_RDN MXS_IOMUX_PAD_NAKED(0, 24, PAD_MUXSEL_0)
+#define MX28_PAD_GPMI_WRN__GPMI_WRN MXS_IOMUX_PAD_NAKED(0, 25, PAD_MUXSEL_0)
+#define MX28_PAD_GPMI_ALE__GPMI_ALE MXS_IOMUX_PAD_NAKED(0, 26, PAD_MUXSEL_0)
+#define MX28_PAD_GPMI_CLE__GPMI_CLE MXS_IOMUX_PAD_NAKED(0, 27, PAD_MUXSEL_0)
+#define MX28_PAD_GPMI_RESETN__GPMI_RESETN MXS_IOMUX_PAD_NAKED(0, 28, PAD_MUXSEL_0)
+
+#define MX28_PAD_LCD_D00__LCD_D0 MXS_IOMUX_PAD_NAKED(1, 0, PAD_MUXSEL_0)
+#define MX28_PAD_LCD_D01__LCD_D1 MXS_IOMUX_PAD_NAKED(1, 1, PAD_MUXSEL_0)
+#define MX28_PAD_LCD_D02__LCD_D2 MXS_IOMUX_PAD_NAKED(1, 2, PAD_MUXSEL_0)
+#define MX28_PAD_LCD_D03__LCD_D3 MXS_IOMUX_PAD_NAKED(1, 3, PAD_MUXSEL_0)
+#define MX28_PAD_LCD_D04__LCD_D4 MXS_IOMUX_PAD_NAKED(1, 4, PAD_MUXSEL_0)
+#define MX28_PAD_LCD_D05__LCD_D5 MXS_IOMUX_PAD_NAKED(1, 5, PAD_MUXSEL_0)
+#define MX28_PAD_LCD_D06__LCD_D6 MXS_IOMUX_PAD_NAKED(1, 6, PAD_MUXSEL_0)
+#define MX28_PAD_LCD_D07__LCD_D7 MXS_IOMUX_PAD_NAKED(1, 7, PAD_MUXSEL_0)
+#define MX28_PAD_LCD_D08__LCD_D8 MXS_IOMUX_PAD_NAKED(1, 8, PAD_MUXSEL_0)
+#define MX28_PAD_LCD_D09__LCD_D9 MXS_IOMUX_PAD_NAKED(1, 9, PAD_MUXSEL_0)
+#define MX28_PAD_LCD_D10__LCD_D10 MXS_IOMUX_PAD_NAKED(1, 10, PAD_MUXSEL_0)
+#define MX28_PAD_LCD_D11__LCD_D11 MXS_IOMUX_PAD_NAKED(1, 11, PAD_MUXSEL_0)
+#define MX28_PAD_LCD_D12__LCD_D12 MXS_IOMUX_PAD_NAKED(1, 12, PAD_MUXSEL_0)
+#define MX28_PAD_LCD_D13__LCD_D13 MXS_IOMUX_PAD_NAKED(1, 13, PAD_MUXSEL_0)
+#define MX28_PAD_LCD_D14__LCD_D14 MXS_IOMUX_PAD_NAKED(1, 14, PAD_MUXSEL_0)
+#define MX28_PAD_LCD_D15__LCD_D15 MXS_IOMUX_PAD_NAKED(1, 15, PAD_MUXSEL_0)
+#define MX28_PAD_LCD_D16__LCD_D16 MXS_IOMUX_PAD_NAKED(1, 16, PAD_MUXSEL_0)
+#define MX28_PAD_LCD_D17__LCD_D17 MXS_IOMUX_PAD_NAKED(1, 17, PAD_MUXSEL_0)
+#define MX28_PAD_LCD_D18__LCD_D18 MXS_IOMUX_PAD_NAKED(1, 18, PAD_MUXSEL_0)
+#define MX28_PAD_LCD_D19__LCD_D19 MXS_IOMUX_PAD_NAKED(1, 19, PAD_MUXSEL_0)
+#define MX28_PAD_LCD_D20__LCD_D20 MXS_IOMUX_PAD_NAKED(1, 20, PAD_MUXSEL_0)
+#define MX28_PAD_LCD_D21__LCD_D21 MXS_IOMUX_PAD_NAKED(1, 21, PAD_MUXSEL_0)
+#define MX28_PAD_LCD_D22__LCD_D22 MXS_IOMUX_PAD_NAKED(1, 22, PAD_MUXSEL_0)
+#define MX28_PAD_LCD_D23__LCD_D23 MXS_IOMUX_PAD_NAKED(1, 23, PAD_MUXSEL_0)
+#define MX28_PAD_LCD_RD_E__LCD_RD_E MXS_IOMUX_PAD_NAKED(1, 24, PAD_MUXSEL_0)
+#define MX28_PAD_LCD_WR_RWN__LCD_WR_RWN MXS_IOMUX_PAD_NAKED(1, 25, PAD_MUXSEL_0)
+#define MX28_PAD_LCD_RS__LCD_RS MXS_IOMUX_PAD_NAKED(1, 26, PAD_MUXSEL_0)
+#define MX28_PAD_LCD_CS__LCD_CS MXS_IOMUX_PAD_NAKED(1, 27, PAD_MUXSEL_0)
+#define MX28_PAD_LCD_VSYNC__LCD_VSYNC MXS_IOMUX_PAD_NAKED(1, 28, PAD_MUXSEL_0)
+#define MX28_PAD_LCD_HSYNC__LCD_HSYNC MXS_IOMUX_PAD_NAKED(1, 29, PAD_MUXSEL_0)
+#define MX28_PAD_LCD_DOTCLK__LCD_DOTCLK MXS_IOMUX_PAD_NAKED(1, 30, PAD_MUXSEL_0)
+#define MX28_PAD_LCD_ENABLE__LCD_ENABLE MXS_IOMUX_PAD_NAKED(1, 31, PAD_MUXSEL_0)
+
+#define MX28_PAD_SSP0_DATA0__SSP0_D0 MXS_IOMUX_PAD_NAKED(2, 0, PAD_MUXSEL_0)
+#define MX28_PAD_SSP0_DATA1__SSP0_D1 MXS_IOMUX_PAD_NAKED(2, 1, PAD_MUXSEL_0)
+#define MX28_PAD_SSP0_DATA2__SSP0_D2 MXS_IOMUX_PAD_NAKED(2, 2, PAD_MUXSEL_0)
+#define MX28_PAD_SSP0_DATA3__SSP0_D3 MXS_IOMUX_PAD_NAKED(2, 3, PAD_MUXSEL_0)
+#define MX28_PAD_SSP0_DATA4__SSP0_D4 MXS_IOMUX_PAD_NAKED(2, 4, PAD_MUXSEL_0)
+#define MX28_PAD_SSP0_DATA5__SSP0_D5 MXS_IOMUX_PAD_NAKED(2, 5, PAD_MUXSEL_0)
+#define MX28_PAD_SSP0_DATA6__SSP0_D6 MXS_IOMUX_PAD_NAKED(2, 6, PAD_MUXSEL_0)
+#define MX28_PAD_SSP0_DATA7__SSP0_D7 MXS_IOMUX_PAD_NAKED(2, 7, PAD_MUXSEL_0)
+#define MX28_PAD_SSP0_CMD__SSP0_CMD MXS_IOMUX_PAD_NAKED(2, 8, PAD_MUXSEL_0)
+#define MX28_PAD_SSP0_DETECT__SSP0_CARD_DETECT MXS_IOMUX_PAD_NAKED(2, 9, PAD_MUXSEL_0)
+#define MX28_PAD_SSP0_SCK__SSP0_SCK MXS_IOMUX_PAD_NAKED(2, 10, PAD_MUXSEL_0)
+#define MX28_PAD_SSP1_SCK__SSP1_SCK MXS_IOMUX_PAD_NAKED(2, 12, PAD_MUXSEL_0)
+#define MX28_PAD_SSP1_CMD__SSP1_CMD MXS_IOMUX_PAD_NAKED(2, 13, PAD_MUXSEL_0)
+#define MX28_PAD_SSP1_DATA0__SSP1_D0 MXS_IOMUX_PAD_NAKED(2, 14, PAD_MUXSEL_0)
+#define MX28_PAD_SSP1_DATA3__SSP1_D3 MXS_IOMUX_PAD_NAKED(2, 15, PAD_MUXSEL_0)
+#define MX28_PAD_SSP2_SCK__SSP2_SCK MXS_IOMUX_PAD_NAKED(2, 16, PAD_MUXSEL_0)
+#define MX28_PAD_SSP2_MOSI__SSP2_CMD MXS_IOMUX_PAD_NAKED(2, 17, PAD_MUXSEL_0)
+#define MX28_PAD_SSP2_MISO__SSP2_D0 MXS_IOMUX_PAD_NAKED(2, 18, PAD_MUXSEL_0)
+#define MX28_PAD_SSP2_SS0__SSP2_D3 MXS_IOMUX_PAD_NAKED(2, 19, PAD_MUXSEL_0)
+#define MX28_PAD_SSP2_SS1__SSP2_D4 MXS_IOMUX_PAD_NAKED(2, 20, PAD_MUXSEL_0)
+#define MX28_PAD_SSP2_SS2__SSP2_D5 MXS_IOMUX_PAD_NAKED(2, 21, PAD_MUXSEL_0)
+#define MX28_PAD_SSP3_SCK__SSP3_SCK MXS_IOMUX_PAD_NAKED(2, 24, PAD_MUXSEL_0)
+#define MX28_PAD_SSP3_MOSI__SSP3_CMD MXS_IOMUX_PAD_NAKED(2, 25, PAD_MUXSEL_0)
+#define MX28_PAD_SSP3_MISO__SSP3_D0 MXS_IOMUX_PAD_NAKED(2, 26, PAD_MUXSEL_0)
+#define MX28_PAD_SSP3_SS0__SSP3_D3 MXS_IOMUX_PAD_NAKED(2, 27, PAD_MUXSEL_0)
+
+#define MX28_PAD_AUART0_RX__AUART0_RX MXS_IOMUX_PAD_NAKED(3, 0, PAD_MUXSEL_0)
+#define MX28_PAD_AUART0_TX__AUART0_TX MXS_IOMUX_PAD_NAKED(3, 1, PAD_MUXSEL_0)
+#define MX28_PAD_AUART0_CTS__AUART0_CTS MXS_IOMUX_PAD_NAKED(3, 2, PAD_MUXSEL_0)
+#define MX28_PAD_AUART0_RTS__AUART0_RTS MXS_IOMUX_PAD_NAKED(3, 3, PAD_MUXSEL_0)
+#define MX28_PAD_AUART1_RX__AUART1_RX MXS_IOMUX_PAD_NAKED(3, 4, PAD_MUXSEL_0)
+#define MX28_PAD_AUART1_TX__AUART1_TX MXS_IOMUX_PAD_NAKED(3, 5, PAD_MUXSEL_0)
+#define MX28_PAD_AUART1_CTS__AUART1_CTS MXS_IOMUX_PAD_NAKED(3, 6, PAD_MUXSEL_0)
+#define MX28_PAD_AUART1_RTS__AUART1_RTS MXS_IOMUX_PAD_NAKED(3, 7, PAD_MUXSEL_0)
+#define MX28_PAD_AUART2_RX__AUART2_RX MXS_IOMUX_PAD_NAKED(3, 8, PAD_MUXSEL_0)
+#define MX28_PAD_AUART2_TX__AUART2_TX MXS_IOMUX_PAD_NAKED(3, 9, PAD_MUXSEL_0)
+#define MX28_PAD_AUART2_CTS__AUART2_CTS MXS_IOMUX_PAD_NAKED(3, 10, PAD_MUXSEL_0)
+#define MX28_PAD_AUART2_RTS__AUART2_RTS MXS_IOMUX_PAD_NAKED(3, 11, PAD_MUXSEL_0)
+#define MX28_PAD_AUART3_RX__AUART3_RX MXS_IOMUX_PAD_NAKED(3, 12, PAD_MUXSEL_0)
+#define MX28_PAD_AUART3_TX__AUART3_TX MXS_IOMUX_PAD_NAKED(3, 13, PAD_MUXSEL_0)
+#define MX28_PAD_AUART3_CTS__AUART3_CTS MXS_IOMUX_PAD_NAKED(3, 14, PAD_MUXSEL_0)
+#define MX28_PAD_AUART3_RTS__AUART3_RTS MXS_IOMUX_PAD_NAKED(3, 15, PAD_MUXSEL_0)
+#define MX28_PAD_PWM0__PWM_0 MXS_IOMUX_PAD_NAKED(3, 16, PAD_MUXSEL_0)
+#define MX28_PAD_PWM1__PWM_1 MXS_IOMUX_PAD_NAKED(3, 17, PAD_MUXSEL_0)
+#define MX28_PAD_PWM2__PWM_2 MXS_IOMUX_PAD_NAKED(3, 18, PAD_MUXSEL_0)
+#define MX28_PAD_SAIF0_MCLK__SAIF0_MCLK MXS_IOMUX_PAD_NAKED(3, 20, PAD_MUXSEL_0)
+#define MX28_PAD_SAIF0_LRCLK__SAIF0_LRCLK MXS_IOMUX_PAD_NAKED(3, 21, PAD_MUXSEL_0)
+#define MX28_PAD_SAIF0_BITCLK__SAIF0_BITCLK MXS_IOMUX_PAD_NAKED(3, 22, PAD_MUXSEL_0)
+#define MX28_PAD_SAIF0_SDATA0__SAIF0_SDATA0 MXS_IOMUX_PAD_NAKED(3, 23, PAD_MUXSEL_0)
+#define MX28_PAD_I2C0_SCL__I2C0_SCL MXS_IOMUX_PAD_NAKED(3, 24, PAD_MUXSEL_0)
+#define MX28_PAD_I2C0_SDA__I2C0_SDA MXS_IOMUX_PAD_NAKED(3, 25, PAD_MUXSEL_0)
+#define MX28_PAD_SAIF1_SDATA0__SAIF1_SDATA0 MXS_IOMUX_PAD_NAKED(3, 26, PAD_MUXSEL_0)
+#define MX28_PAD_SPDIF__SPDIF_TX MXS_IOMUX_PAD_NAKED(3, 27, PAD_MUXSEL_0)
+#define MX28_PAD_PWM3__PWM_3 MXS_IOMUX_PAD_NAKED(3, 28, PAD_MUXSEL_0)
+#define MX28_PAD_PWM4__PWM_4 MXS_IOMUX_PAD_NAKED(3, 29, PAD_MUXSEL_0)
+#define MX28_PAD_LCD_RESET__LCD_RESET MXS_IOMUX_PAD_NAKED(3, 30, PAD_MUXSEL_0)
+
+#define MX28_PAD_ENET0_MDC__ENET0_MDC MXS_IOMUX_PAD_NAKED(4, 0, PAD_MUXSEL_0)
+#define MX28_PAD_ENET0_MDIO__ENET0_MDIO MXS_IOMUX_PAD_NAKED(4, 1, PAD_MUXSEL_0)
+#define MX28_PAD_ENET0_RX_EN__ENET0_RX_EN MXS_IOMUX_PAD_NAKED(4, 2, PAD_MUXSEL_0)
+#define MX28_PAD_ENET0_RXD0__ENET0_RXD0 MXS_IOMUX_PAD_NAKED(4, 3, PAD_MUXSEL_0)
+#define MX28_PAD_ENET0_RXD1__ENET0_RXD1 MXS_IOMUX_PAD_NAKED(4, 4, PAD_MUXSEL_0)
+#define MX28_PAD_ENET0_TX_CLK__ENET0_TX_CLK MXS_IOMUX_PAD_NAKED(4, 5, PAD_MUXSEL_0)
+#define MX28_PAD_ENET0_TX_EN__ENET0_TX_EN MXS_IOMUX_PAD_NAKED(4, 6, PAD_MUXSEL_0)
+#define MX28_PAD_ENET0_TXD0__ENET0_TXD0 MXS_IOMUX_PAD_NAKED(4, 7, PAD_MUXSEL_0)
+#define MX28_PAD_ENET0_TXD1__ENET0_TXD1 MXS_IOMUX_PAD_NAKED(4, 8, PAD_MUXSEL_0)
+#define MX28_PAD_ENET0_RXD2__ENET0_RXD2 MXS_IOMUX_PAD_NAKED(4, 9, PAD_MUXSEL_0)
+#define MX28_PAD_ENET0_RXD3__ENET0_RXD3 MXS_IOMUX_PAD_NAKED(4, 10, PAD_MUXSEL_0)
+#define MX28_PAD_ENET0_TXD2__ENET0_TXD2 MXS_IOMUX_PAD_NAKED(4, 11, PAD_MUXSEL_0)
+#define MX28_PAD_ENET0_TXD3__ENET0_TXD3 MXS_IOMUX_PAD_NAKED(4, 12, PAD_MUXSEL_0)
+#define MX28_PAD_ENET0_RX_CLK__ENET0_RX_CLK MXS_IOMUX_PAD_NAKED(4, 13, PAD_MUXSEL_0)
+#define MX28_PAD_ENET0_COL__ENET0_COL MXS_IOMUX_PAD_NAKED(4, 14, PAD_MUXSEL_0)
+#define MX28_PAD_ENET0_CRS__ENET0_CRS MXS_IOMUX_PAD_NAKED(4, 15, PAD_MUXSEL_0)
+#define MX28_PAD_ENET_CLK__CLKCTRL_ENET MXS_IOMUX_PAD_NAKED(4, 16, PAD_MUXSEL_0)
+#define MX28_PAD_JTAG_RTCK__JTAG_RTCK MXS_IOMUX_PAD_NAKED(4, 20, PAD_MUXSEL_0)
+
+#define MX28_PAD_EMI_D00__EMI_DATA0 MXS_IOMUX_PAD_NAKED(5, 0, PAD_MUXSEL_0)
+#define MX28_PAD_EMI_D01__EMI_DATA1 MXS_IOMUX_PAD_NAKED(5, 1, PAD_MUXSEL_0)
+#define MX28_PAD_EMI_D02__EMI_DATA2 MXS_IOMUX_PAD_NAKED(5, 2, PAD_MUXSEL_0)
+#define MX28_PAD_EMI_D03__EMI_DATA3 MXS_IOMUX_PAD_NAKED(5, 3, PAD_MUXSEL_0)
+#define MX28_PAD_EMI_D04__EMI_DATA4 MXS_IOMUX_PAD_NAKED(5, 4, PAD_MUXSEL_0)
+#define MX28_PAD_EMI_D05__EMI_DATA5 MXS_IOMUX_PAD_NAKED(5, 5, PAD_MUXSEL_0)
+#define MX28_PAD_EMI_D06__EMI_DATA6 MXS_IOMUX_PAD_NAKED(5, 6, PAD_MUXSEL_0)
+#define MX28_PAD_EMI_D07__EMI_DATA7 MXS_IOMUX_PAD_NAKED(5, 7, PAD_MUXSEL_0)
+#define MX28_PAD_EMI_D08__EMI_DATA8 MXS_IOMUX_PAD_NAKED(5, 8, PAD_MUXSEL_0)
+#define MX28_PAD_EMI_D09__EMI_DATA9 MXS_IOMUX_PAD_NAKED(5, 9, PAD_MUXSEL_0)
+#define MX28_PAD_EMI_D10__EMI_DATA10 MXS_IOMUX_PAD_NAKED(5, 10, PAD_MUXSEL_0)
+#define MX28_PAD_EMI_D11__EMI_DATA11 MXS_IOMUX_PAD_NAKED(5, 11, PAD_MUXSEL_0)
+#define MX28_PAD_EMI_D12__EMI_DATA12 MXS_IOMUX_PAD_NAKED(5, 12, PAD_MUXSEL_0)
+#define MX28_PAD_EMI_D13__EMI_DATA13 MXS_IOMUX_PAD_NAKED(5, 13, PAD_MUXSEL_0)
+#define MX28_PAD_EMI_D14__EMI_DATA14 MXS_IOMUX_PAD_NAKED(5, 14, PAD_MUXSEL_0)
+#define MX28_PAD_EMI_D15__EMI_DATA15 MXS_IOMUX_PAD_NAKED(5, 15, PAD_MUXSEL_0)
+#define MX28_PAD_EMI_ODT0__EMI_ODT0 MXS_IOMUX_PAD_NAKED(5, 16, PAD_MUXSEL_0)
+#define MX28_PAD_EMI_DQM0__EMI_DQM0 MXS_IOMUX_PAD_NAKED(5, 17, PAD_MUXSEL_0)
+#define MX28_PAD_EMI_ODT1__EMI_ODT1 MXS_IOMUX_PAD_NAKED(5, 18, PAD_MUXSEL_0)
+#define MX28_PAD_EMI_DQM1__EMI_DQM1 MXS_IOMUX_PAD_NAKED(5, 19, PAD_MUXSEL_0)
+#define MX28_PAD_EMI_DDR_OPEN_FB__EMI_DDR_OPEN_FEEDBACK MXS_IOMUX_PAD_NAKED(5, 20, PAD_MUXSEL_0)
+#define MX28_PAD_EMI_CLK__EMI_CLK MXS_IOMUX_PAD_NAKED(5, 21, PAD_MUXSEL_0)
+#define MX28_PAD_EMI_DQS0__EMI_DQS0 MXS_IOMUX_PAD_NAKED(5, 22, PAD_MUXSEL_0)
+#define MX28_PAD_EMI_DQS1__EMI_DQS1 MXS_IOMUX_PAD_NAKED(5, 23, PAD_MUXSEL_0)
+#define MX28_PAD_EMI_DDR_OPEN__EMI_DDR_OPEN MXS_IOMUX_PAD_NAKED(5, 26, PAD_MUXSEL_0)
+
+#define MX28_PAD_EMI_A00__EMI_ADDR0 MXS_IOMUX_PAD_NAKED(6, 0, PAD_MUXSEL_0)
+#define MX28_PAD_EMI_A01__EMI_ADDR1 MXS_IOMUX_PAD_NAKED(6, 1, PAD_MUXSEL_0)
+#define MX28_PAD_EMI_A02__EMI_ADDR2 MXS_IOMUX_PAD_NAKED(6, 2, PAD_MUXSEL_0)
+#define MX28_PAD_EMI_A03__EMI_ADDR3 MXS_IOMUX_PAD_NAKED(6, 3, PAD_MUXSEL_0)
+#define MX28_PAD_EMI_A04__EMI_ADDR4 MXS_IOMUX_PAD_NAKED(6, 4, PAD_MUXSEL_0)
+#define MX28_PAD_EMI_A05__EMI_ADDR5 MXS_IOMUX_PAD_NAKED(6, 5, PAD_MUXSEL_0)
+#define MX28_PAD_EMI_A06__EMI_ADDR6 MXS_IOMUX_PAD_NAKED(6, 6, PAD_MUXSEL_0)
+#define MX28_PAD_EMI_A07__EMI_ADDR7 MXS_IOMUX_PAD_NAKED(6, 7, PAD_MUXSEL_0)
+#define MX28_PAD_EMI_A08__EMI_ADDR8 MXS_IOMUX_PAD_NAKED(6, 8, PAD_MUXSEL_0)
+#define MX28_PAD_EMI_A09__EMI_ADDR9 MXS_IOMUX_PAD_NAKED(6, 9, PAD_MUXSEL_0)
+#define MX28_PAD_EMI_A10__EMI_ADDR10 MXS_IOMUX_PAD_NAKED(6, 10, PAD_MUXSEL_0)
+#define MX28_PAD_EMI_A11__EMI_ADDR11 MXS_IOMUX_PAD_NAKED(6, 11, PAD_MUXSEL_0)
+#define MX28_PAD_EMI_A12__EMI_ADDR12 MXS_IOMUX_PAD_NAKED(6, 12, PAD_MUXSEL_0)
+#define MX28_PAD_EMI_A13__EMI_ADDR13 MXS_IOMUX_PAD_NAKED(6, 13, PAD_MUXSEL_0)
+#define MX28_PAD_EMI_A14__EMI_ADDR14 MXS_IOMUX_PAD_NAKED(6, 14, PAD_MUXSEL_0)
+#define MX28_PAD_EMI_BA0__EMI_BA0 MXS_IOMUX_PAD_NAKED(6, 16, PAD_MUXSEL_0)
+#define MX28_PAD_EMI_BA1__EMI_BA1 MXS_IOMUX_PAD_NAKED(6, 17, PAD_MUXSEL_0)
+#define MX28_PAD_EMI_BA2__EMI_BA2 MXS_IOMUX_PAD_NAKED(6, 18, PAD_MUXSEL_0)
+#define MX28_PAD_EMI_CASN__EMI_CASN MXS_IOMUX_PAD_NAKED(6, 19, PAD_MUXSEL_0)
+#define MX28_PAD_EMI_RASN__EMI_RASN MXS_IOMUX_PAD_NAKED(6, 20, PAD_MUXSEL_0)
+#define MX28_PAD_EMI_WEN__EMI_WEN MXS_IOMUX_PAD_NAKED(6, 21, PAD_MUXSEL_0)
+#define MX28_PAD_EMI_CE0N__EMI_CE0N MXS_IOMUX_PAD_NAKED(6, 22, PAD_MUXSEL_0)
+#define MX28_PAD_EMI_CE1N__EMI_CE1N MXS_IOMUX_PAD_NAKED(6, 23, PAD_MUXSEL_0)
+#define MX28_PAD_EMI_CKE__EMI_CKE MXS_IOMUX_PAD_NAKED(6, 24, PAD_MUXSEL_0)
+
+/* MUXSEL_1 */
+#define MX28_PAD_GPMI_D00__SSP1_D0 MXS_IOMUX_PAD_NAKED(0, 0, PAD_MUXSEL_1)
+#define MX28_PAD_GPMI_D01__SSP1_D1 MXS_IOMUX_PAD_NAKED(0, 1, PAD_MUXSEL_1)
+#define MX28_PAD_GPMI_D02__SSP1_D2 MXS_IOMUX_PAD_NAKED(0, 2, PAD_MUXSEL_1)
+#define MX28_PAD_GPMI_D03__SSP1_D3 MXS_IOMUX_PAD_NAKED(0, 3, PAD_MUXSEL_1)
+#define MX28_PAD_GPMI_D04__SSP1_D4 MXS_IOMUX_PAD_NAKED(0, 4, PAD_MUXSEL_1)
+#define MX28_PAD_GPMI_D05__SSP1_D5 MXS_IOMUX_PAD_NAKED(0, 5, PAD_MUXSEL_1)
+#define MX28_PAD_GPMI_D06__SSP1_D6 MXS_IOMUX_PAD_NAKED(0, 6, PAD_MUXSEL_1)
+#define MX28_PAD_GPMI_D07__SSP1_D7 MXS_IOMUX_PAD_NAKED(0, 7, PAD_MUXSEL_1)
+#define MX28_PAD_GPMI_CE0N__SSP3_D0 MXS_IOMUX_PAD_NAKED(0, 16, PAD_MUXSEL_1)
+#define MX28_PAD_GPMI_CE1N__SSP3_D3 MXS_IOMUX_PAD_NAKED(0, 17, PAD_MUXSEL_1)
+#define MX28_PAD_GPMI_CE2N__CAN1_TX MXS_IOMUX_PAD_NAKED(0, 18, PAD_MUXSEL_1)
+#define MX28_PAD_GPMI_CE3N__CAN1_RX MXS_IOMUX_PAD_NAKED(0, 19, PAD_MUXSEL_1)
+#define MX28_PAD_GPMI_RDY0__SSP1_CARD_DETECT MXS_IOMUX_PAD_NAKED(0, 20, PAD_MUXSEL_1)
+#define MX28_PAD_GPMI_RDY1__SSP1_CMD MXS_IOMUX_PAD_NAKED(0, 21, PAD_MUXSEL_1)
+#define MX28_PAD_GPMI_RDY2__CAN0_TX MXS_IOMUX_PAD_NAKED(0, 22, PAD_MUXSEL_1)
+#define MX28_PAD_GPMI_RDY3__CAN0_RX MXS_IOMUX_PAD_NAKED(0, 23, PAD_MUXSEL_1)
+#define MX28_PAD_GPMI_RDN__SSP3_SCK MXS_IOMUX_PAD_NAKED(0, 24, PAD_MUXSEL_1)
+#define MX28_PAD_GPMI_WRN__SSP1_SCK MXS_IOMUX_PAD_NAKED(0, 25, PAD_MUXSEL_1)
+#define MX28_PAD_GPMI_ALE__SSP3_D1 MXS_IOMUX_PAD_NAKED(0, 26, PAD_MUXSEL_1)
+#define MX28_PAD_GPMI_CLE__SSP3_D2 MXS_IOMUX_PAD_NAKED(0, 27, PAD_MUXSEL_1)
+#define MX28_PAD_GPMI_RESETN__SSP3_CMD MXS_IOMUX_PAD_NAKED(0, 28, PAD_MUXSEL_1)
+
+#define MX28_PAD_LCD_D03__ETM_DA8 MXS_IOMUX_PAD_NAKED(1, 3, PAD_MUXSEL_1)
+#define MX28_PAD_LCD_D04__ETM_DA9 MXS_IOMUX_PAD_NAKED(1, 4, PAD_MUXSEL_1)
+#define MX28_PAD_LCD_D08__ETM_DA3 MXS_IOMUX_PAD_NAKED(1, 8, PAD_MUXSEL_1)
+#define MX28_PAD_LCD_D09__ETM_DA4 MXS_IOMUX_PAD_NAKED(1, 9, PAD_MUXSEL_1)
+#define MX28_PAD_LCD_D20__ENET1_1588_EVENT2_OUT MXS_IOMUX_PAD_NAKED(1, 20, PAD_MUXSEL_1)
+#define MX28_PAD_LCD_D21__ENET1_1588_EVENT2_IN MXS_IOMUX_PAD_NAKED(1, 21, PAD_MUXSEL_1)
+#define MX28_PAD_LCD_D22__ENET1_1588_EVENT3_OUT MXS_IOMUX_PAD_NAKED(1, 22, PAD_MUXSEL_1)
+#define MX28_PAD_LCD_D23__ENET1_1588_EVENT3_IN MXS_IOMUX_PAD_NAKED(1, 23, PAD_MUXSEL_1)
+#define MX28_PAD_LCD_RD_E__LCD_VSYNC MXS_IOMUX_PAD_NAKED(1, 24, PAD_MUXSEL_1)
+#define MX28_PAD_LCD_WR_RWN__LCD_HSYNC MXS_IOMUX_PAD_NAKED(1, 25, PAD_MUXSEL_1)
+#define MX28_PAD_LCD_RS__LCD_DOTCLK MXS_IOMUX_PAD_NAKED(1, 26, PAD_MUXSEL_1)
+#define MX28_PAD_LCD_CS__LCD_ENABLE MXS_IOMUX_PAD_NAKED(1, 27, PAD_MUXSEL_1)
+#define MX28_PAD_LCD_VSYNC__SAIF1_SDATA0 MXS_IOMUX_PAD_NAKED(1, 28, PAD_MUXSEL_1)
+#define MX28_PAD_LCD_HSYNC__SAIF1_SDATA1 MXS_IOMUX_PAD_NAKED(1, 29, PAD_MUXSEL_1)
+#define MX28_PAD_LCD_DOTCLK__SAIF1_MCLK MXS_IOMUX_PAD_NAKED(1, 30, PAD_MUXSEL_1)
+
+#define MX28_PAD_SSP0_DATA4__SSP2_D0 MXS_IOMUX_PAD_NAKED(2, 4, PAD_MUXSEL_1)
+#define MX28_PAD_SSP0_DATA5__SSP2_D3 MXS_IOMUX_PAD_NAKED(2, 5, PAD_MUXSEL_1)
+#define MX28_PAD_SSP0_DATA6__SSP2_CMD MXS_IOMUX_PAD_NAKED(2, 6, PAD_MUXSEL_1)
+#define MX28_PAD_SSP0_DATA7__SSP2_SCK MXS_IOMUX_PAD_NAKED(2, 7, PAD_MUXSEL_1)
+#define MX28_PAD_SSP1_SCK__SSP2_D1 MXS_IOMUX_PAD_NAKED(2, 12, PAD_MUXSEL_1)
+#define MX28_PAD_SSP1_CMD__SSP2_D2 MXS_IOMUX_PAD_NAKED(2, 13, PAD_MUXSEL_1)
+#define MX28_PAD_SSP1_DATA0__SSP2_D6 MXS_IOMUX_PAD_NAKED(2, 14, PAD_MUXSEL_1)
+#define MX28_PAD_SSP1_DATA3__SSP2_D7 MXS_IOMUX_PAD_NAKED(2, 15, PAD_MUXSEL_1)
+#define MX28_PAD_SSP2_SCK__AUART2_RX MXS_IOMUX_PAD_NAKED(2, 16, PAD_MUXSEL_1)
+#define MX28_PAD_SSP2_MOSI__AUART2_TX MXS_IOMUX_PAD_NAKED(2, 17, PAD_MUXSEL_1)
+#define MX28_PAD_SSP2_MISO__AUART3_RX MXS_IOMUX_PAD_NAKED(2, 18, PAD_MUXSEL_1)
+#define MX28_PAD_SSP2_SS0__AUART3_TX MXS_IOMUX_PAD_NAKED(2, 19, PAD_MUXSEL_1)
+#define MX28_PAD_SSP2_SS1__SSP2_D1 MXS_IOMUX_PAD_NAKED(2, 20, PAD_MUXSEL_1)
+#define MX28_PAD_SSP2_SS2__SSP2_D2 MXS_IOMUX_PAD_NAKED(2, 21, PAD_MUXSEL_1)
+#define MX28_PAD_SSP3_SCK__AUART4_TX MXS_IOMUX_PAD_NAKED(2, 24, PAD_MUXSEL_1)
+#define MX28_PAD_SSP3_MOSI__AUART4_RX MXS_IOMUX_PAD_NAKED(2, 25, PAD_MUXSEL_1)
+#define MX28_PAD_SSP3_MISO__AUART4_RTS MXS_IOMUX_PAD_NAKED(2, 26, PAD_MUXSEL_1)
+#define MX28_PAD_SSP3_SS0__AUART4_CTS MXS_IOMUX_PAD_NAKED(2, 27, PAD_MUXSEL_1)
+
+#define MX28_PAD_AUART0_RX__I2C0_SCL MXS_IOMUX_PAD_NAKED(3, 0, PAD_MUXSEL_1)
+#define MX28_PAD_AUART0_TX__I2C0_SDA MXS_IOMUX_PAD_NAKED(3, 1, PAD_MUXSEL_1)
+#define MX28_PAD_AUART0_CTS__AUART4_RX MXS_IOMUX_PAD_NAKED(3, 2, PAD_MUXSEL_1)
+#define MX28_PAD_AUART0_RTS__AUART4_TX MXS_IOMUX_PAD_NAKED(3, 3, PAD_MUXSEL_1)
+#define MX28_PAD_AUART1_RX__SSP2_CARD_DETECT MXS_IOMUX_PAD_NAKED(3, 4, PAD_MUXSEL_1)
+#define MX28_PAD_AUART1_TX__SSP3_CARD_DETECT MXS_IOMUX_PAD_NAKED(3, 5, PAD_MUXSEL_1)
+#define MX28_PAD_AUART1_CTS__USB0_OVERCURRENT MXS_IOMUX_PAD_NAKED(3, 6, PAD_MUXSEL_1)
+#define MX28_PAD_AUART1_RTS__USB0_ID MXS_IOMUX_PAD_NAKED(3, 7, PAD_MUXSEL_1)
+#define MX28_PAD_AUART2_RX__SSP3_D1 MXS_IOMUX_PAD_NAKED(3, 8, PAD_MUXSEL_1)
+#define MX28_PAD_AUART2_TX__SSP3_D2 MXS_IOMUX_PAD_NAKED(3, 9, PAD_MUXSEL_1)
+#define MX28_PAD_AUART2_CTS__I2C1_SCL MXS_IOMUX_PAD_NAKED(3, 10, PAD_MUXSEL_1)
+#define MX28_PAD_AUART2_RTS__I2C1_SDA MXS_IOMUX_PAD_NAKED(3, 11, PAD_MUXSEL_1)
+#define MX28_PAD_AUART3_RX__CAN0_TX MXS_IOMUX_PAD_NAKED(3, 12, PAD_MUXSEL_1)
+#define MX28_PAD_AUART3_TX__CAN0_RX MXS_IOMUX_PAD_NAKED(3, 13, PAD_MUXSEL_1)
+#define MX28_PAD_AUART3_CTS__CAN1_TX MXS_IOMUX_PAD_NAKED(3, 14, PAD_MUXSEL_1)
+#define MX28_PAD_AUART3_RTS__CAN1_RX MXS_IOMUX_PAD_NAKED(3, 15, PAD_MUXSEL_1)
+#define MX28_PAD_PWM0__I2C1_SCL MXS_IOMUX_PAD_NAKED(3, 16, PAD_MUXSEL_1)
+#define MX28_PAD_PWM1__I2C1_SDA MXS_IOMUX_PAD_NAKED(3, 17, PAD_MUXSEL_1)
+#define MX28_PAD_PWM2__USB0_ID MXS_IOMUX_PAD_NAKED(3, 18, PAD_MUXSEL_1)
+#define MX28_PAD_SAIF0_MCLK__PWM_3 MXS_IOMUX_PAD_NAKED(3, 20, PAD_MUXSEL_1)
+#define MX28_PAD_SAIF0_LRCLK__PWM_4 MXS_IOMUX_PAD_NAKED(3, 21, PAD_MUXSEL_1)
+#define MX28_PAD_SAIF0_BITCLK__PWM_5 MXS_IOMUX_PAD_NAKED(3, 22, PAD_MUXSEL_1)
+#define MX28_PAD_SAIF0_SDATA0__PWM_6 MXS_IOMUX_PAD_NAKED(3, 23, PAD_MUXSEL_1)
+#define MX28_PAD_I2C0_SCL__TIMROT_ROTARYA MXS_IOMUX_PAD_NAKED(3, 24, PAD_MUXSEL_1)
+#define MX28_PAD_I2C0_SDA__TIMROT_ROTARYB MXS_IOMUX_PAD_NAKED(3, 25, PAD_MUXSEL_1)
+#define MX28_PAD_SAIF1_SDATA0__PWM_7 MXS_IOMUX_PAD_NAKED(3, 26, PAD_MUXSEL_1)
+#define MX28_PAD_LCD_RESET__LCD_VSYNC MXS_IOMUX_PAD_NAKED(3, 30, PAD_MUXSEL_1)
+
+#define MX28_PAD_ENET0_MDC__GPMI_CE4N MXS_IOMUX_PAD_NAKED(4, 0, PAD_MUXSEL_1)
+#define MX28_PAD_ENET0_MDIO__GPMI_CE5N MXS_IOMUX_PAD_NAKED(4, 1, PAD_MUXSEL_1)
+#define MX28_PAD_ENET0_RX_EN__GPMI_CE6N MXS_IOMUX_PAD_NAKED(4, 2, PAD_MUXSEL_1)
+#define MX28_PAD_ENET0_RXD0__GPMI_CE7N MXS_IOMUX_PAD_NAKED(4, 3, PAD_MUXSEL_1)
+#define MX28_PAD_ENET0_RXD1__GPMI_READY4 MXS_IOMUX_PAD_NAKED(4, 4, PAD_MUXSEL_1)
+#define MX28_PAD_ENET0_TX_CLK__HSADC_TRIGGER MXS_IOMUX_PAD_NAKED(4, 5, PAD_MUXSEL_1)
+#define MX28_PAD_ENET0_TX_EN__GPMI_READY5 MXS_IOMUX_PAD_NAKED(4, 6, PAD_MUXSEL_1)
+#define MX28_PAD_ENET0_TXD0__GPMI_READY6 MXS_IOMUX_PAD_NAKED(4, 7, PAD_MUXSEL_1)
+#define MX28_PAD_ENET0_TXD1__GPMI_READY7 MXS_IOMUX_PAD_NAKED(4, 8, PAD_MUXSEL_1)
+#define MX28_PAD_ENET0_RXD2__ENET1_RXD0 MXS_IOMUX_PAD_NAKED(4, 9, PAD_MUXSEL_1)
+#define MX28_PAD_ENET0_RXD3__ENET1_RXD1 MXS_IOMUX_PAD_NAKED(4, 10, PAD_MUXSEL_1)
+#define MX28_PAD_ENET0_TXD2__ENET1_TXD0 MXS_IOMUX_PAD_NAKED(4, 11, PAD_MUXSEL_1)
+#define MX28_PAD_ENET0_TXD3__ENET1_TXD1 MXS_IOMUX_PAD_NAKED(4, 12, PAD_MUXSEL_1)
+#define MX28_PAD_ENET0_RX_CLK__ENET0_RX_ER MXS_IOMUX_PAD_NAKED(4, 13, PAD_MUXSEL_1)
+#define MX28_PAD_ENET0_COL__ENET1_TX_EN MXS_IOMUX_PAD_NAKED(4, 14, PAD_MUXSEL_1)
+#define MX28_PAD_ENET0_CRS__ENET1_RX_EN MXS_IOMUX_PAD_NAKED(4, 15, PAD_MUXSEL_1)
+
+/* MUXSEL_2 */
+#define MX28_PAD_GPMI_CE2N__ENET0_RX_ER MXS_IOMUX_PAD_NAKED(0, 18, PAD_MUXSEL_2)
+#define MX28_PAD_GPMI_CE3N__SAIF1_MCLK MXS_IOMUX_PAD_NAKED(0, 19, PAD_MUXSEL_2)
+#define MX28_PAD_GPMI_RDY0__USB0_ID MXS_IOMUX_PAD_NAKED(0, 20, PAD_MUXSEL_2)
+#define MX28_PAD_GPMI_RDY2__ENET0_TX_ER MXS_IOMUX_PAD_NAKED(0, 22, PAD_MUXSEL_2)
+#define MX28_PAD_GPMI_RDY3__HSADC_TRIGGER MXS_IOMUX_PAD_NAKED(0, 23, PAD_MUXSEL_2)
+#define MX28_PAD_GPMI_ALE__SSP3_D4 MXS_IOMUX_PAD_NAKED(0, 26, PAD_MUXSEL_2)
+#define MX28_PAD_GPMI_CLE__SSP3_D5 MXS_IOMUX_PAD_NAKED(0, 27, PAD_MUXSEL_2)
+
+#define MX28_PAD_LCD_D00__ETM_DA0 MXS_IOMUX_PAD_NAKED(1, 0, PAD_MUXSEL_2)
+#define MX28_PAD_LCD_D01__ETM_DA1 MXS_IOMUX_PAD_NAKED(1, 1, PAD_MUXSEL_2)
+#define MX28_PAD_LCD_D02__ETM_DA2 MXS_IOMUX_PAD_NAKED(1, 2, PAD_MUXSEL_2)
+#define MX28_PAD_LCD_D03__ETM_DA3 MXS_IOMUX_PAD_NAKED(1, 3, PAD_MUXSEL_2)
+#define MX28_PAD_LCD_D04__ETM_DA4 MXS_IOMUX_PAD_NAKED(1, 4, PAD_MUXSEL_2)
+#define MX28_PAD_LCD_D05__ETM_DA5 MXS_IOMUX_PAD_NAKED(1, 5, PAD_MUXSEL_2)
+#define MX28_PAD_LCD_D06__ETM_DA6 MXS_IOMUX_PAD_NAKED(1, 6, PAD_MUXSEL_2)
+#define MX28_PAD_LCD_D07__ETM_DA7 MXS_IOMUX_PAD_NAKED(1, 7, PAD_MUXSEL_2)
+#define MX28_PAD_LCD_D08__ETM_DA8 MXS_IOMUX_PAD_NAKED(1, 8, PAD_MUXSEL_2)
+#define MX28_PAD_LCD_D09__ETM_DA9 MXS_IOMUX_PAD_NAKED(1, 9, PAD_MUXSEL_2)
+#define MX28_PAD_LCD_D10__ETM_DA10 MXS_IOMUX_PAD_NAKED(1, 10, PAD_MUXSEL_2)
+#define MX28_PAD_LCD_D11__ETM_DA11 MXS_IOMUX_PAD_NAKED(1, 11, PAD_MUXSEL_2)
+#define MX28_PAD_LCD_D12__ETM_DA12 MXS_IOMUX_PAD_NAKED(1, 12, PAD_MUXSEL_2)
+#define MX28_PAD_LCD_D13__ETM_DA13 MXS_IOMUX_PAD_NAKED(1, 13, PAD_MUXSEL_2)
+#define MX28_PAD_LCD_D14__ETM_DA14 MXS_IOMUX_PAD_NAKED(1, 14, PAD_MUXSEL_2)
+#define MX28_PAD_LCD_D15__ETM_DA15 MXS_IOMUX_PAD_NAKED(1, 15, PAD_MUXSEL_2)
+#define MX28_PAD_LCD_D16__ETM_DA7 MXS_IOMUX_PAD_NAKED(1, 16, PAD_MUXSEL_2)
+#define MX28_PAD_LCD_D17__ETM_DA6 MXS_IOMUX_PAD_NAKED(1, 17, PAD_MUXSEL_2)
+#define MX28_PAD_LCD_D18__ETM_DA5 MXS_IOMUX_PAD_NAKED(1, 18, PAD_MUXSEL_2)
+#define MX28_PAD_LCD_D19__ETM_DA4 MXS_IOMUX_PAD_NAKED(1, 19, PAD_MUXSEL_2)
+#define MX28_PAD_LCD_D20__ETM_DA3 MXS_IOMUX_PAD_NAKED(1, 20, PAD_MUXSEL_2)
+#define MX28_PAD_LCD_D21__ETM_DA2 MXS_IOMUX_PAD_NAKED(1, 21, PAD_MUXSEL_2)
+#define MX28_PAD_LCD_D22__ETM_DA1 MXS_IOMUX_PAD_NAKED(1, 22, PAD_MUXSEL_2)
+#define MX28_PAD_LCD_D23__ETM_DA0 MXS_IOMUX_PAD_NAKED(1, 23, PAD_MUXSEL_2)
+#define MX28_PAD_LCD_RD_E__ETM_TCTL MXS_IOMUX_PAD_NAKED(1, 24, PAD_MUXSEL_2)
+#define MX28_PAD_LCD_WR_RWN__ETM_TCLK MXS_IOMUX_PAD_NAKED(1, 25, PAD_MUXSEL_2)
+#define MX28_PAD_LCD_HSYNC__ETM_TCTL MXS_IOMUX_PAD_NAKED(1, 29, PAD_MUXSEL_2)
+#define MX28_PAD_LCD_DOTCLK__ETM_TCLK MXS_IOMUX_PAD_NAKED(1, 30, PAD_MUXSEL_2)
+
+#define MX28_PAD_SSP1_SCK__ENET0_1588_EVENT2_OUT MXS_IOMUX_PAD_NAKED(2, 12, PAD_MUXSEL_2)
+#define MX28_PAD_SSP1_CMD__ENET0_1588_EVENT2_IN MXS_IOMUX_PAD_NAKED(2, 13, PAD_MUXSEL_2)
+#define MX28_PAD_SSP1_DATA0__ENET0_1588_EVENT3_OUT MXS_IOMUX_PAD_NAKED(2, 14, PAD_MUXSEL_2)
+#define MX28_PAD_SSP1_DATA3__ENET0_1588_EVENT3_IN MXS_IOMUX_PAD_NAKED(2, 15, PAD_MUXSEL_2)
+#define MX28_PAD_SSP2_SCK__SAIF0_SDATA1 MXS_IOMUX_PAD_NAKED(2, 16, PAD_MUXSEL_2)
+#define MX28_PAD_SSP2_MOSI__SAIF0_SDATA2 MXS_IOMUX_PAD_NAKED(2, 17, PAD_MUXSEL_2)
+#define MX28_PAD_SSP2_MISO__SAIF1_SDATA1 MXS_IOMUX_PAD_NAKED(2, 18, PAD_MUXSEL_2)
+#define MX28_PAD_SSP2_SS0__SAIF1_SDATA2 MXS_IOMUX_PAD_NAKED(2, 19, PAD_MUXSEL_2)
+#define MX28_PAD_SSP2_SS1__USB1_OVERCURRENT MXS_IOMUX_PAD_NAKED(2, 20, PAD_MUXSEL_2)
+#define MX28_PAD_SSP2_SS2__USB0_OVERCURRENT MXS_IOMUX_PAD_NAKED(2, 21, PAD_MUXSEL_2)
+#define MX28_PAD_SSP3_SCK__ENET1_1588_EVENT0_OUT MXS_IOMUX_PAD_NAKED(2, 24, PAD_MUXSEL_2)
+#define MX28_PAD_SSP3_MOSI__ENET1_1588_EVENT0_IN MXS_IOMUX_PAD_NAKED(2, 25, PAD_MUXSEL_2)
+#define MX28_PAD_SSP3_MISO__ENET1_1588_EVENT1_OUT MXS_IOMUX_PAD_NAKED(2, 26, PAD_MUXSEL_2)
+#define MX28_PAD_SSP3_SS0__ENET1_1588_EVENT1_IN MXS_IOMUX_PAD_NAKED(2, 27, PAD_MUXSEL_2)
+
+#define MX28_PAD_AUART0_RX__DUART_CTS MXS_IOMUX_PAD_NAKED(3, 0, PAD_MUXSEL_2)
+#define MX28_PAD_AUART0_TX__DUART_RTS MXS_IOMUX_PAD_NAKED(3, 1, PAD_MUXSEL_2)
+#define MX28_PAD_AUART0_CTS__DUART_RX MXS_IOMUX_PAD_NAKED(3, 2, PAD_MUXSEL_2)
+#define MX28_PAD_AUART0_RTS__DUART_TX MXS_IOMUX_PAD_NAKED(3, 3, PAD_MUXSEL_2)
+#define MX28_PAD_AUART1_RX__PWM_0 MXS_IOMUX_PAD_NAKED(3, 4, PAD_MUXSEL_2)
+#define MX28_PAD_AUART1_TX__PWM_1 MXS_IOMUX_PAD_NAKED(3, 5, PAD_MUXSEL_2)
+#define MX28_PAD_AUART1_CTS__TIMROT_ROTARYA MXS_IOMUX_PAD_NAKED(3, 6, PAD_MUXSEL_2)
+#define MX28_PAD_AUART1_RTS__TIMROT_ROTARYB MXS_IOMUX_PAD_NAKED(3, 7, PAD_MUXSEL_2)
+#define MX28_PAD_AUART2_RX__SSP3_D4 MXS_IOMUX_PAD_NAKED(3, 8, PAD_MUXSEL_2)
+#define MX28_PAD_AUART2_TX__SSP3_D5 MXS_IOMUX_PAD_NAKED(3, 9, PAD_MUXSEL_2)
+#define MX28_PAD_AUART2_CTS__SAIF1_BITCLK MXS_IOMUX_PAD_NAKED(3, 10, PAD_MUXSEL_2)
+#define MX28_PAD_AUART2_RTS__SAIF1_LRCLK MXS_IOMUX_PAD_NAKED(3, 11, PAD_MUXSEL_2)
+#define MX28_PAD_AUART3_RX__ENET0_1588_EVENT0_OUT MXS_IOMUX_PAD_NAKED(3, 12, PAD_MUXSEL_2)
+#define MX28_PAD_AUART3_TX__ENET0_1588_EVENT0_IN MXS_IOMUX_PAD_NAKED(3, 13, PAD_MUXSEL_2)
+#define MX28_PAD_AUART3_CTS__ENET0_1588_EVENT1_OUT MXS_IOMUX_PAD_NAKED(3, 14, PAD_MUXSEL_2)
+#define MX28_PAD_AUART3_RTS__ENET0_1588_EVENT1_IN MXS_IOMUX_PAD_NAKED(3, 15, PAD_MUXSEL_2)
+#define MX28_PAD_PWM0__DUART_RX MXS_IOMUX_PAD_NAKED(3, 16, PAD_MUXSEL_2)
+#define MX28_PAD_PWM1__DUART_TX MXS_IOMUX_PAD_NAKED(3, 17, PAD_MUXSEL_2)
+#define MX28_PAD_PWM2__USB1_OVERCURRENT MXS_IOMUX_PAD_NAKED(3, 18, PAD_MUXSEL_2)
+#define MX28_PAD_SAIF0_MCLK__AUART4_CTS MXS_IOMUX_PAD_NAKED(3, 20, PAD_MUXSEL_2)
+#define MX28_PAD_SAIF0_LRCLK__AUART4_RTS MXS_IOMUX_PAD_NAKED(3, 21, PAD_MUXSEL_2)
+#define MX28_PAD_SAIF0_BITCLK__AUART4_RX MXS_IOMUX_PAD_NAKED(3, 22, PAD_MUXSEL_2)
+#define MX28_PAD_SAIF0_SDATA0__AUART4_TX MXS_IOMUX_PAD_NAKED(3, 23, PAD_MUXSEL_2)
+#define MX28_PAD_I2C0_SCL__DUART_RX MXS_IOMUX_PAD_NAKED(3, 24, PAD_MUXSEL_2)
+#define MX28_PAD_I2C0_SDA__DUART_TX MXS_IOMUX_PAD_NAKED(3, 25, PAD_MUXSEL_2)
+#define MX28_PAD_SAIF1_SDATA0__SAIF0_SDATA1 MXS_IOMUX_PAD_NAKED(3, 26, PAD_MUXSEL_2)
+#define MX28_PAD_SPDIF__ENET1_RX_ER MXS_IOMUX_PAD_NAKED(3, 27, PAD_MUXSEL_2)
+
+#define MX28_PAD_ENET0_MDC__SAIF0_SDATA1 MXS_IOMUX_PAD_NAKED(4, 0, PAD_MUXSEL_2)
+#define MX28_PAD_ENET0_MDIO__SAIF0_SDATA2 MXS_IOMUX_PAD_NAKED(4, 1, PAD_MUXSEL_2)
+#define MX28_PAD_ENET0_RX_EN__SAIF1_SDATA1 MXS_IOMUX_PAD_NAKED(4, 2, PAD_MUXSEL_2)
+#define MX28_PAD_ENET0_RXD0__SAIF1_SDATA2 MXS_IOMUX_PAD_NAKED(4, 3, PAD_MUXSEL_2)
+#define MX28_PAD_ENET0_TX_CLK__ENET0_1588_EVENT2_OUT MXS_IOMUX_PAD_NAKED(4, 5, PAD_MUXSEL_2)
+#define MX28_PAD_ENET0_RXD2__ENET0_1588_EVENT0_OUT MXS_IOMUX_PAD_NAKED(4, 9, PAD_MUXSEL_2)
+#define MX28_PAD_ENET0_RXD3__ENET0_1588_EVENT0_IN MXS_IOMUX_PAD_NAKED(4, 10, PAD_MUXSEL_2)
+#define MX28_PAD_ENET0_TXD2__ENET0_1588_EVENT1_OUT MXS_IOMUX_PAD_NAKED(4, 11, PAD_MUXSEL_2)
+#define MX28_PAD_ENET0_TXD3__ENET0_1588_EVENT1_IN MXS_IOMUX_PAD_NAKED(4, 12, PAD_MUXSEL_2)
+#define MX28_PAD_ENET0_RX_CLK__ENET0_1588_EVENT2_IN MXS_IOMUX_PAD_NAKED(4, 13, PAD_MUXSEL_2)
+#define MX28_PAD_ENET0_COL__ENET0_1588_EVENT3_OUT MXS_IOMUX_PAD_NAKED(4, 14, PAD_MUXSEL_2)
+#define MX28_PAD_ENET0_CRS__ENET0_1588_EVENT3_IN MXS_IOMUX_PAD_NAKED(4, 15, PAD_MUXSEL_2)
+
+/* MUXSEL_GPIO */
+#define MX28_PAD_GPMI_D00__GPIO_0_0 MXS_IOMUX_PAD_NAKED(0, 0, PAD_MUXSEL_GPIO)
+#define MX28_PAD_GPMI_D01__GPIO_0_1 MXS_IOMUX_PAD_NAKED(0, 1, PAD_MUXSEL_GPIO)
+#define MX28_PAD_GPMI_D02__GPIO_0_2 MXS_IOMUX_PAD_NAKED(0, 2, PAD_MUXSEL_GPIO)
+#define MX28_PAD_GPMI_D03__GPIO_0_3 MXS_IOMUX_PAD_NAKED(0, 3, PAD_MUXSEL_GPIO)
+#define MX28_PAD_GPMI_D04__GPIO_0_4 MXS_IOMUX_PAD_NAKED(0, 4, PAD_MUXSEL_GPIO)
+#define MX28_PAD_GPMI_D05__GPIO_0_5 MXS_IOMUX_PAD_NAKED(0, 5, PAD_MUXSEL_GPIO)
+#define MX28_PAD_GPMI_D06__GPIO_0_6 MXS_IOMUX_PAD_NAKED(0, 6, PAD_MUXSEL_GPIO)
+#define MX28_PAD_GPMI_D07__GPIO_0_7 MXS_IOMUX_PAD_NAKED(0, 7, PAD_MUXSEL_GPIO)
+#define MX28_PAD_GPMI_CE0N__GPIO_0_16 MXS_IOMUX_PAD_NAKED(0, 16, PAD_MUXSEL_GPIO)
+#define MX28_PAD_GPMI_CE1N__GPIO_0_17 MXS_IOMUX_PAD_NAKED(0, 17, PAD_MUXSEL_GPIO)
+#define MX28_PAD_GPMI_CE2N__GPIO_0_18 MXS_IOMUX_PAD_NAKED(0, 18, PAD_MUXSEL_GPIO)
+#define MX28_PAD_GPMI_CE3N__GPIO_0_19 MXS_IOMUX_PAD_NAKED(0, 19, PAD_MUXSEL_GPIO)
+#define MX28_PAD_GPMI_RDY0__GPIO_0_20 MXS_IOMUX_PAD_NAKED(0, 20, PAD_MUXSEL_GPIO)
+#define MX28_PAD_GPMI_RDY1__GPIO_0_21 MXS_IOMUX_PAD_NAKED(0, 21, PAD_MUXSEL_GPIO)
+#define MX28_PAD_GPMI_RDY2__GPIO_0_22 MXS_IOMUX_PAD_NAKED(0, 22, PAD_MUXSEL_GPIO)
+#define MX28_PAD_GPMI_RDY3__GPIO_0_23 MXS_IOMUX_PAD_NAKED(0, 23, PAD_MUXSEL_GPIO)
+#define MX28_PAD_GPMI_RDN__GPIO_0_24 MXS_IOMUX_PAD_NAKED(0, 24, PAD_MUXSEL_GPIO)
+#define MX28_PAD_GPMI_WRN__GPIO_0_25 MXS_IOMUX_PAD_NAKED(0, 25, PAD_MUXSEL_GPIO)
+#define MX28_PAD_GPMI_ALE__GPIO_0_26 MXS_IOMUX_PAD_NAKED(0, 26, PAD_MUXSEL_GPIO)
+#define MX28_PAD_GPMI_CLE__GPIO_0_27 MXS_IOMUX_PAD_NAKED(0, 27, PAD_MUXSEL_GPIO)
+#define MX28_PAD_GPMI_RESETN__GPIO_0_28 MXS_IOMUX_PAD_NAKED(0, 28, PAD_MUXSEL_GPIO)
+
+#define MX28_PAD_LCD_D00__GPIO_1_0 MXS_IOMUX_PAD_NAKED(1, 0, PAD_MUXSEL_GPIO)
+#define MX28_PAD_LCD_D01__GPIO_1_1 MXS_IOMUX_PAD_NAKED(1, 1, PAD_MUXSEL_GPIO)
+#define MX28_PAD_LCD_D02__GPIO_1_2 MXS_IOMUX_PAD_NAKED(1, 2, PAD_MUXSEL_GPIO)
+#define MX28_PAD_LCD_D03__GPIO_1_3 MXS_IOMUX_PAD_NAKED(1, 3, PAD_MUXSEL_GPIO)
+#define MX28_PAD_LCD_D04__GPIO_1_4 MXS_IOMUX_PAD_NAKED(1, 4, PAD_MUXSEL_GPIO)
+#define MX28_PAD_LCD_D05__GPIO_1_5 MXS_IOMUX_PAD_NAKED(1, 5, PAD_MUXSEL_GPIO)
+#define MX28_PAD_LCD_D06__GPIO_1_6 MXS_IOMUX_PAD_NAKED(1, 6, PAD_MUXSEL_GPIO)
+#define MX28_PAD_LCD_D07__GPIO_1_7 MXS_IOMUX_PAD_NAKED(1, 7, PAD_MUXSEL_GPIO)
+#define MX28_PAD_LCD_D08__GPIO_1_8 MXS_IOMUX_PAD_NAKED(1, 8, PAD_MUXSEL_GPIO)
+#define MX28_PAD_LCD_D09__GPIO_1_9 MXS_IOMUX_PAD_NAKED(1, 9, PAD_MUXSEL_GPIO)
+#define MX28_PAD_LCD_D10__GPIO_1_10 MXS_IOMUX_PAD_NAKED(1, 10, PAD_MUXSEL_GPIO)
+#define MX28_PAD_LCD_D11__GPIO_1_11 MXS_IOMUX_PAD_NAKED(1, 11, PAD_MUXSEL_GPIO)
+#define MX28_PAD_LCD_D12__GPIO_1_12 MXS_IOMUX_PAD_NAKED(1, 12, PAD_MUXSEL_GPIO)
+#define MX28_PAD_LCD_D13__GPIO_1_13 MXS_IOMUX_PAD_NAKED(1, 13, PAD_MUXSEL_GPIO)
+#define MX28_PAD_LCD_D14__GPIO_1_14 MXS_IOMUX_PAD_NAKED(1, 14, PAD_MUXSEL_GPIO)
+#define MX28_PAD_LCD_D15__GPIO_1_15 MXS_IOMUX_PAD_NAKED(1, 15, PAD_MUXSEL_GPIO)
+#define MX28_PAD_LCD_D16__GPIO_1_16 MXS_IOMUX_PAD_NAKED(1, 16, PAD_MUXSEL_GPIO)
+#define MX28_PAD_LCD_D17__GPIO_1_17 MXS_IOMUX_PAD_NAKED(1, 17, PAD_MUXSEL_GPIO)
+#define MX28_PAD_LCD_D18__GPIO_1_18 MXS_IOMUX_PAD_NAKED(1, 18, PAD_MUXSEL_GPIO)
+#define MX28_PAD_LCD_D19__GPIO_1_19 MXS_IOMUX_PAD_NAKED(1, 19, PAD_MUXSEL_GPIO)
+#define MX28_PAD_LCD_D20__GPIO_1_20 MXS_IOMUX_PAD_NAKED(1, 20, PAD_MUXSEL_GPIO)
+#define MX28_PAD_LCD_D21__GPIO_1_21 MXS_IOMUX_PAD_NAKED(1, 21, PAD_MUXSEL_GPIO)
+#define MX28_PAD_LCD_D22__GPIO_1_22 MXS_IOMUX_PAD_NAKED(1, 22, PAD_MUXSEL_GPIO)
+#define MX28_PAD_LCD_D23__GPIO_1_23 MXS_IOMUX_PAD_NAKED(1, 23, PAD_MUXSEL_GPIO)
+#define MX28_PAD_LCD_RD_E__GPIO_1_24 MXS_IOMUX_PAD_NAKED(1, 24, PAD_MUXSEL_GPIO)
+#define MX28_PAD_LCD_WR_RWN__GPIO_1_25 MXS_IOMUX_PAD_NAKED(1, 25, PAD_MUXSEL_GPIO)
+#define MX28_PAD_LCD_RS__GPIO_1_26 MXS_IOMUX_PAD_NAKED(1, 26, PAD_MUXSEL_GPIO)
+#define MX28_PAD_LCD_CS__GPIO_1_27 MXS_IOMUX_PAD_NAKED(1, 27, PAD_MUXSEL_GPIO)
+#define MX28_PAD_LCD_VSYNC__GPIO_1_28 MXS_IOMUX_PAD_NAKED(1, 28, PAD_MUXSEL_GPIO)
+#define MX28_PAD_LCD_HSYNC__GPIO_1_29 MXS_IOMUX_PAD_NAKED(1, 29, PAD_MUXSEL_GPIO)
+#define MX28_PAD_LCD_DOTCLK__GPIO_1_30 MXS_IOMUX_PAD_NAKED(1, 30, PAD_MUXSEL_GPIO)
+#define MX28_PAD_LCD_ENABLE__GPIO_1_31 MXS_IOMUX_PAD_NAKED(1, 31, PAD_MUXSEL_GPIO)
+
+#define MX28_PAD_SSP0_DATA0__GPIO_2_0 MXS_IOMUX_PAD_NAKED(2, 0, PAD_MUXSEL_GPIO)
+#define MX28_PAD_SSP0_DATA1__GPIO_2_1 MXS_IOMUX_PAD_NAKED(2, 1, PAD_MUXSEL_GPIO)
+#define MX28_PAD_SSP0_DATA2__GPIO_2_2 MXS_IOMUX_PAD_NAKED(2, 2, PAD_MUXSEL_GPIO)
+#define MX28_PAD_SSP0_DATA3__GPIO_2_3 MXS_IOMUX_PAD_NAKED(2, 3, PAD_MUXSEL_GPIO)
+#define MX28_PAD_SSP0_DATA4__GPIO_2_4 MXS_IOMUX_PAD_NAKED(2, 4, PAD_MUXSEL_GPIO)
+#define MX28_PAD_SSP0_DATA5__GPIO_2_5 MXS_IOMUX_PAD_NAKED(2, 5, PAD_MUXSEL_GPIO)
+#define MX28_PAD_SSP0_DATA6__GPIO_2_6 MXS_IOMUX_PAD_NAKED(2, 6, PAD_MUXSEL_GPIO)
+#define MX28_PAD_SSP0_DATA7__GPIO_2_7 MXS_IOMUX_PAD_NAKED(2, 7, PAD_MUXSEL_GPIO)
+#define MX28_PAD_SSP0_CMD__GPIO_2_8 MXS_IOMUX_PAD_NAKED(2, 8, PAD_MUXSEL_GPIO)
+#define MX28_PAD_SSP0_DETECT__GPIO_2_9 MXS_IOMUX_PAD_NAKED(2, 9, PAD_MUXSEL_GPIO)
+#define MX28_PAD_SSP0_SCK__GPIO_2_10 MXS_IOMUX_PAD_NAKED(2, 10, PAD_MUXSEL_GPIO)
+#define MX28_PAD_SSP1_SCK__GPIO_2_12 MXS_IOMUX_PAD_NAKED(2, 12, PAD_MUXSEL_GPIO)
+#define MX28_PAD_SSP1_CMD__GPIO_2_13 MXS_IOMUX_PAD_NAKED(2, 13, PAD_MUXSEL_GPIO)
+#define MX28_PAD_SSP1_DATA0__GPIO_2_14 MXS_IOMUX_PAD_NAKED(2, 14, PAD_MUXSEL_GPIO)
+#define MX28_PAD_SSP1_DATA3__GPIO_2_15 MXS_IOMUX_PAD_NAKED(2, 15, PAD_MUXSEL_GPIO)
+#define MX28_PAD_SSP2_SCK__GPIO_2_16 MXS_IOMUX_PAD_NAKED(2, 16, PAD_MUXSEL_GPIO)
+#define MX28_PAD_SSP2_MOSI__GPIO_2_17 MXS_IOMUX_PAD_NAKED(2, 17, PAD_MUXSEL_GPIO)
+#define MX28_PAD_SSP2_MISO__GPIO_2_18 MXS_IOMUX_PAD_NAKED(2, 18, PAD_MUXSEL_GPIO)
+#define MX28_PAD_SSP2_SS0__GPIO_2_19 MXS_IOMUX_PAD_NAKED(2, 19, PAD_MUXSEL_GPIO)
+#define MX28_PAD_SSP2_SS1__GPIO_2_20 MXS_IOMUX_PAD_NAKED(2, 20, PAD_MUXSEL_GPIO)
+#define MX28_PAD_SSP2_SS2__GPIO_2_21 MXS_IOMUX_PAD_NAKED(2, 21, PAD_MUXSEL_GPIO)
+#define MX28_PAD_SSP3_SCK__GPIO_2_24 MXS_IOMUX_PAD_NAKED(2, 24, PAD_MUXSEL_GPIO)
+#define MX28_PAD_SSP3_MOSI__GPIO_2_25 MXS_IOMUX_PAD_NAKED(2, 25, PAD_MUXSEL_GPIO)
+#define MX28_PAD_SSP3_MISO__GPIO_2_26 MXS_IOMUX_PAD_NAKED(2, 26, PAD_MUXSEL_GPIO)
+#define MX28_PAD_SSP3_SS0__GPIO_2_27 MXS_IOMUX_PAD_NAKED(2, 27, PAD_MUXSEL_GPIO)
+
+#define MX28_PAD_AUART0_RX__GPIO_3_0 MXS_IOMUX_PAD_NAKED(3, 0, PAD_MUXSEL_GPIO)
+#define MX28_PAD_AUART0_TX__GPIO_3_1 MXS_IOMUX_PAD_NAKED(3, 1, PAD_MUXSEL_GPIO)
+#define MX28_PAD_AUART0_CTS__GPIO_3_2 MXS_IOMUX_PAD_NAKED(3, 2, PAD_MUXSEL_GPIO)
+#define MX28_PAD_AUART0_RTS__GPIO_3_3 MXS_IOMUX_PAD_NAKED(3, 3, PAD_MUXSEL_GPIO)
+#define MX28_PAD_AUART1_RX__GPIO_3_4 MXS_IOMUX_PAD_NAKED(3, 4, PAD_MUXSEL_GPIO)
+#define MX28_PAD_AUART1_TX__GPIO_3_5 MXS_IOMUX_PAD_NAKED(3, 5, PAD_MUXSEL_GPIO)
+#define MX28_PAD_AUART1_CTS__GPIO_3_6 MXS_IOMUX_PAD_NAKED(3, 6, PAD_MUXSEL_GPIO)
+#define MX28_PAD_AUART1_RTS__GPIO_3_7 MXS_IOMUX_PAD_NAKED(3, 7, PAD_MUXSEL_GPIO)
+#define MX28_PAD_AUART2_RX__GPIO_3_8 MXS_IOMUX_PAD_NAKED(3, 8, PAD_MUXSEL_GPIO)
+#define MX28_PAD_AUART2_TX__GPIO_3_9 MXS_IOMUX_PAD_NAKED(3, 9, PAD_MUXSEL_GPIO)
+#define MX28_PAD_AUART2_CTS__GPIO_3_10 MXS_IOMUX_PAD_NAKED(3, 10, PAD_MUXSEL_GPIO)
+#define MX28_PAD_AUART2_RTS__GPIO_3_11 MXS_IOMUX_PAD_NAKED(3, 11, PAD_MUXSEL_GPIO)
+#define MX28_PAD_AUART3_RX__GPIO_3_12 MXS_IOMUX_PAD_NAKED(3, 12, PAD_MUXSEL_GPIO)
+#define MX28_PAD_AUART3_TX__GPIO_3_13 MXS_IOMUX_PAD_NAKED(3, 13, PAD_MUXSEL_GPIO)
+#define MX28_PAD_AUART3_CTS__GPIO_3_14 MXS_IOMUX_PAD_NAKED(3, 14, PAD_MUXSEL_GPIO)
+#define MX28_PAD_AUART3_RTS__GPIO_3_15 MXS_IOMUX_PAD_NAKED(3, 15, PAD_MUXSEL_GPIO)
+#define MX28_PAD_PWM0__GPIO_3_16 MXS_IOMUX_PAD_NAKED(3, 16, PAD_MUXSEL_GPIO)
+#define MX28_PAD_PWM1__GPIO_3_17 MXS_IOMUX_PAD_NAKED(3, 17, PAD_MUXSEL_GPIO)
+#define MX28_PAD_PWM2__GPIO_3_18 MXS_IOMUX_PAD_NAKED(3, 18, PAD_MUXSEL_GPIO)
+#define MX28_PAD_SAIF0_MCLK__GPIO_3_20 MXS_IOMUX_PAD_NAKED(3, 20, PAD_MUXSEL_GPIO)
+#define MX28_PAD_SAIF0_LRCLK__GPIO_3_21 MXS_IOMUX_PAD_NAKED(3, 21, PAD_MUXSEL_GPIO)
+#define MX28_PAD_SAIF0_BITCLK__GPIO_3_22 MXS_IOMUX_PAD_NAKED(3, 22, PAD_MUXSEL_GPIO)
+#define MX28_PAD_SAIF0_SDATA0__GPIO_3_23 MXS_IOMUX_PAD_NAKED(3, 23, PAD_MUXSEL_GPIO)
+#define MX28_PAD_I2C0_SCL__GPIO_3_24 MXS_IOMUX_PAD_NAKED(3, 24, PAD_MUXSEL_GPIO)
+#define MX28_PAD_I2C0_SDA__GPIO_3_25 MXS_IOMUX_PAD_NAKED(3, 25, PAD_MUXSEL_GPIO)
+#define MX28_PAD_SAIF1_SDATA0__GPIO_3_26 MXS_IOMUX_PAD_NAKED(3, 26, PAD_MUXSEL_GPIO)
+#define MX28_PAD_SPDIF__GPIO_3_27 MXS_IOMUX_PAD_NAKED(3, 27, PAD_MUXSEL_GPIO)
+#define MX28_PAD_PWM3__GPIO_3_28 MXS_IOMUX_PAD_NAKED(3, 28, PAD_MUXSEL_GPIO)
+#define MX28_PAD_PWM4__GPIO_3_29 MXS_IOMUX_PAD_NAKED(3, 29, PAD_MUXSEL_GPIO)
+#define MX28_PAD_LCD_RESET__GPIO_3_30 MXS_IOMUX_PAD_NAKED(3, 30, PAD_MUXSEL_GPIO)
+
+#define MX28_PAD_ENET0_MDC__GPIO_4_0 MXS_IOMUX_PAD_NAKED(4, 0, PAD_MUXSEL_GPIO)
+#define MX28_PAD_ENET0_MDIO__GPIO_4_1 MXS_IOMUX_PAD_NAKED(4, 1, PAD_MUXSEL_GPIO)
+#define MX28_PAD_ENET0_RX_EN__GPIO_4_2 MXS_IOMUX_PAD_NAKED(4, 2, PAD_MUXSEL_GPIO)
+#define MX28_PAD_ENET0_RXD0__GPIO_4_3 MXS_IOMUX_PAD_NAKED(4, 3, PAD_MUXSEL_GPIO)
+#define MX28_PAD_ENET0_RXD1__GPIO_4_4 MXS_IOMUX_PAD_NAKED(4, 4, PAD_MUXSEL_GPIO)
+#define MX28_PAD_ENET0_TX_CLK__GPIO_4_5 MXS_IOMUX_PAD_NAKED(4, 5, PAD_MUXSEL_GPIO)
+#define MX28_PAD_ENET0_TX_EN__GPIO_4_6 MXS_IOMUX_PAD_NAKED(4, 6, PAD_MUXSEL_GPIO)
+#define MX28_PAD_ENET0_TXD0__GPIO_4_7 MXS_IOMUX_PAD_NAKED(4, 7, PAD_MUXSEL_GPIO)
+#define MX28_PAD_ENET0_TXD1__GPIO_4_8 MXS_IOMUX_PAD_NAKED(4, 8, PAD_MUXSEL_GPIO)
+#define MX28_PAD_ENET0_RXD2__GPIO_4_9 MXS_IOMUX_PAD_NAKED(4, 9, PAD_MUXSEL_GPIO)
+#define MX28_PAD_ENET0_RXD3__GPIO_4_10 MXS_IOMUX_PAD_NAKED(4, 10, PAD_MUXSEL_GPIO)
+#define MX28_PAD_ENET0_TXD2__GPIO_4_11 MXS_IOMUX_PAD_NAKED(4, 11, PAD_MUXSEL_GPIO)
+#define MX28_PAD_ENET0_TXD3__GPIO_4_12 MXS_IOMUX_PAD_NAKED(4, 12, PAD_MUXSEL_GPIO)
+#define MX28_PAD_ENET0_RX_CLK__GPIO_4_13 MXS_IOMUX_PAD_NAKED(4, 13, PAD_MUXSEL_GPIO)
+#define MX28_PAD_ENET0_COL__GPIO_4_14 MXS_IOMUX_PAD_NAKED(4, 14, PAD_MUXSEL_GPIO)
+#define MX28_PAD_ENET0_CRS__GPIO_4_15 MXS_IOMUX_PAD_NAKED(4, 15, PAD_MUXSEL_GPIO)
+#define MX28_PAD_ENET_CLK__GPIO_4_16 MXS_IOMUX_PAD_NAKED(4, 16, PAD_MUXSEL_GPIO)
+#define MX28_PAD_JTAG_RTCK__GPIO_4_20 MXS_IOMUX_PAD_NAKED(4, 20, PAD_MUXSEL_GPIO)
+
+#endif /* __MACH_IOMUX_MX28_H__ */
diff --git a/arch/arm/include/asm/arch-mx28/iomux.h b/arch/arm/include/asm/arch-mx28/iomux.h
new file mode 100644
index 0000000..7abdf58
--- /dev/null
+++ b/arch/arm/include/asm/arch-mx28/iomux.h
@@ -0,0 +1,168 @@
+/*
+ * Copyright (C) 2009 by Jan Weitzel Phytec Messtechnik GmbH,
+ * <armlinux@phytec.de>
+ * Copyright (C) 2010 Freescale Semiconductor, Inc. All Rights Reserved.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * as published by the Free Software Foundation; either version 2
+ * of the License, or (at your option) any later version.
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
+ * MA 02110-1301, USA.
+ */
+
+#ifndef __MACH_MXS_IOMUX_H__
+#define __MACH_MXS_IOMUX_H__
+
+/*
+ * IOMUX/PAD Bit field definitions
+ *
+ * PAD_BANK: 0..2 (3)
+ * PAD_PIN: 3..7 (5)
+ * PAD_MUXSEL: 8..9 (2)
+ * PAD_MA: 10..11 (2)
+ * PAD_MA_VALID: 12 (1)
+ * PAD_VOL: 13 (1)
+ * PAD_VOL_VALID: 14 (1)
+ * PAD_PULL: 15 (1)
+ * PAD_PULL_VALID: 16 (1)
+ * RESERVED: 17..31 (15)
+ */
+typedef u32 iomux_cfg_t;
+
+#define MXS_PAD_BANK_SHIFT 0
+#define MXS_PAD_BANK_MASK ((iomux_cfg_t)0x7 << MXS_PAD_BANK_SHIFT)
+#define MXS_PAD_PIN_SHIFT 3
+#define MXS_PAD_PIN_MASK ((iomux_cfg_t)0x1f << MXS_PAD_PIN_SHIFT)
+#define MXS_PAD_MUXSEL_SHIFT 8
+#define MXS_PAD_MUXSEL_MASK ((iomux_cfg_t)0x3 << MXS_PAD_MUXSEL_SHIFT)
+#define MXS_PAD_MA_SHIFT 10
+#define MXS_PAD_MA_MASK ((iomux_cfg_t)0x3 << MXS_PAD_MA_SHIFT)
+#define MXS_PAD_MA_VALID_SHIFT 12
+#define MXS_PAD_MA_VALID_MASK ((iomux_cfg_t)0x1 << MXS_PAD_MA_VALID_SHIFT)
+#define MXS_PAD_VOL_SHIFT 13
+#define MXS_PAD_VOL_MASK ((iomux_cfg_t)0x1 << MXS_PAD_VOL_SHIFT)
+#define MXS_PAD_VOL_VALID_SHIFT 14
+#define MXS_PAD_VOL_VALID_MASK ((iomux_cfg_t)0x1 << MXS_PAD_VOL_VALID_SHIFT)
+#define MXS_PAD_PULL_SHIFT 15
+#define MXS_PAD_PULL_MASK ((iomux_cfg_t)0x1 << MXS_PAD_PULL_SHIFT)
+#define MXS_PAD_PULL_VALID_SHIFT 16
+#define MXS_PAD_PULL_VALID_MASK ((iomux_cfg_t)0x1 << MXS_PAD_PULL_VALID_SHIFT)
+
+#define PAD_MUXSEL_0 0
+#define PAD_MUXSEL_1 1
+#define PAD_MUXSEL_2 2
+#define PAD_MUXSEL_GPIO 3
+
+#define PAD_4MA 0
+#define PAD_8MA 1
+#define PAD_12MA 2
+#define PAD_16MA 3
+
+#define PAD_1V8 0
+#define PAD_3V3 1
+
+#define PAD_NOPULL 0
+#define PAD_PULLUP 1
+
+#define MXS_PAD_4MA ((PAD_4MA << MXS_PAD_MA_SHIFT) | \
+ MXS_PAD_MA_VALID_MASK)
+#define MXS_PAD_8MA ((PAD_8MA << MXS_PAD_MA_SHIFT) | \
+ MXS_PAD_MA_VALID_MASK)
+#define MXS_PAD_12MA ((PAD_12MA << MXS_PAD_MA_SHIFT) | \
+ MXS_PAD_MA_VALID_MASK)
+#define MXS_PAD_16MA ((PAD_16MA << MXS_PAD_MA_SHIFT) | \
+ MXS_PAD_MA_VALID_MASK)
+
+#define MXS_PAD_1V8 ((PAD_1V8 << MXS_PAD_VOL_SHIFT) | \
+ MXS_PAD_VOL_VALID_MASK)
+#define MXS_PAD_3V3 ((PAD_3V3 << MXS_PAD_VOL_SHIFT) | \
+ MXS_PAD_VOL_VALID_MASK)
+
+#define MXS_PAD_NOPULL ((PAD_NOPULL << MXS_PAD_PULL_SHIFT) | \
+ MXS_PAD_PULL_VALID_MASK)
+#define MXS_PAD_PULLUP ((PAD_PULLUP << MXS_PAD_PULL_SHIFT) | \
+ MXS_PAD_PULL_VALID_MASK)
+
+/* generic pad control used in most cases */
+#define MXS_PAD_CTRL (MXS_PAD_4MA | MXS_PAD_3V3 | MXS_PAD_NOPULL)
+
+#define MXS_IOMUX_PAD(_bank, _pin, _muxsel, _ma, _vol, _pull) \
+ (((iomux_cfg_t)(_bank) << MXS_PAD_BANK_SHIFT) | \
+ ((iomux_cfg_t)(_pin) << MXS_PAD_PIN_SHIFT) | \
+ ((iomux_cfg_t)(_muxsel) << MXS_PAD_MUXSEL_SHIFT) | \
+ ((iomux_cfg_t)(_ma) << MXS_PAD_MA_SHIFT) | \
+ ((iomux_cfg_t)(_vol) << MXS_PAD_VOL_SHIFT) | \
+ ((iomux_cfg_t)(_pull) << MXS_PAD_PULL_SHIFT))
+
+/*
+ * A pad becomes naked, when none of mA, vol or pull
+ * validity bits is set.
+ */
+#define MXS_IOMUX_PAD_NAKED(_bank, _pin, _muxsel) \
+ MXS_IOMUX_PAD(_bank, _pin, _muxsel, 0, 0, 0)
+
+static inline unsigned int PAD_BANK(iomux_cfg_t pad)
+{
+ return (pad & MXS_PAD_BANK_MASK) >> MXS_PAD_BANK_SHIFT;
+}
+
+static inline unsigned int PAD_PIN(iomux_cfg_t pad)
+{
+ return (pad & MXS_PAD_PIN_MASK) >> MXS_PAD_PIN_SHIFT;
+}
+
+static inline unsigned int PAD_MUXSEL(iomux_cfg_t pad)
+{
+ return (pad & MXS_PAD_MUXSEL_MASK) >> MXS_PAD_MUXSEL_SHIFT;
+}
+
+static inline unsigned int PAD_MA(iomux_cfg_t pad)
+{
+ return (pad & MXS_PAD_MA_MASK) >> MXS_PAD_MA_SHIFT;
+}
+
+static inline unsigned int PAD_MA_VALID(iomux_cfg_t pad)
+{
+ return (pad & MXS_PAD_MA_VALID_MASK) >> MXS_PAD_MA_VALID_SHIFT;
+}
+
+static inline unsigned int PAD_VOL(iomux_cfg_t pad)
+{
+ return (pad & MXS_PAD_VOL_MASK) >> MXS_PAD_VOL_SHIFT;
+}
+
+static inline unsigned int PAD_VOL_VALID(iomux_cfg_t pad)
+{
+ return (pad & MXS_PAD_VOL_VALID_MASK) >> MXS_PAD_VOL_VALID_SHIFT;
+}
+
+static inline unsigned int PAD_PULL(iomux_cfg_t pad)
+{
+ return (pad & MXS_PAD_PULL_MASK) >> MXS_PAD_PULL_SHIFT;
+}
+
+static inline unsigned int PAD_PULL_VALID(iomux_cfg_t pad)
+{
+ return (pad & MXS_PAD_PULL_VALID_MASK) >> MXS_PAD_PULL_VALID_SHIFT;
+}
+
+/*
+ * configures a single pad in the iomuxer
+ */
+int mxs_iomux_setup_pad(iomux_cfg_t pad);
+
+/*
+ * configures multiple pads
+ * convenient way to call the above function with tables
+ */
+int mxs_iomux_setup_multiple_pads(const iomux_cfg_t *pad_list, unsigned count);
+
+#endif /* __MACH_MXS_IOMUX_H__*/
diff --git a/arch/arm/include/asm/arch-mx28/regs-apbh.h b/arch/arm/include/asm/arch-mx28/regs-apbh.h
new file mode 100644
index 0000000..a7fa1ec
--- /dev/null
+++ b/arch/arm/include/asm/arch-mx28/regs-apbh.h
@@ -0,0 +1,466 @@
+/*
+ * Freescale i.MX28 APBH Register Definitions
+ *
+ * Copyright (C) 2011 Marek Vasut <marek.vasut@gmail.com>
+ * on behalf of DENX Software Engineering GmbH
+ *
+ * Based on code from LTIB:
+ * Copyright 2008-2010 Freescale Semiconductor, Inc. All Rights Reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
+ *
+ */
+
+#ifndef __REGS_APBH_H__
+#define __REGS_APBH_H__
+
+#include <asm/arch/regs-common.h>
+
+#ifndef __ASSEMBLY__
+struct mx28_apbh_regs {
+ mx28_reg(hw_apbh_ctrl0)
+ mx28_reg(hw_apbh_ctrl1)
+ mx28_reg(hw_apbh_ctrl2)
+ mx28_reg(hw_apbh_channel_ctrl)
+ mx28_reg(hw_apbh_devsel)
+ mx28_reg(hw_apbh_dma_burst_size)
+ mx28_reg(hw_apbh_debug)
+
+ uint32_t reserved[36];
+
+ union {
+ struct {
+ mx28_reg(hw_apbh_ch_curcmdar)
+ mx28_reg(hw_apbh_ch_nxtcmdar)
+ mx28_reg(hw_apbh_ch_cmd)
+ mx28_reg(hw_apbh_ch_bar)
+ mx28_reg(hw_apbh_ch_sema)
+ mx28_reg(hw_apbh_ch_debug1)
+ mx28_reg(hw_apbh_ch_debug2)
+ } ch[16];
+ struct {
+ mx28_reg(hw_apbh_ch0_curcmdar)
+ mx28_reg(hw_apbh_ch0_nxtcmdar)
+ mx28_reg(hw_apbh_ch0_cmd)
+ mx28_reg(hw_apbh_ch0_bar)
+ mx28_reg(hw_apbh_ch0_sema)
+ mx28_reg(hw_apbh_ch0_debug1)
+ mx28_reg(hw_apbh_ch0_debug2)
+ mx28_reg(hw_apbh_ch1_curcmdar)
+ mx28_reg(hw_apbh_ch1_nxtcmdar)
+ mx28_reg(hw_apbh_ch1_cmd)
+ mx28_reg(hw_apbh_ch1_bar)
+ mx28_reg(hw_apbh_ch1_sema)
+ mx28_reg(hw_apbh_ch1_debug1)
+ mx28_reg(hw_apbh_ch1_debug2)
+ mx28_reg(hw_apbh_ch2_curcmdar)
+ mx28_reg(hw_apbh_ch2_nxtcmdar)
+ mx28_reg(hw_apbh_ch2_cmd)
+ mx28_reg(hw_apbh_ch2_bar)
+ mx28_reg(hw_apbh_ch2_sema)
+ mx28_reg(hw_apbh_ch2_debug1)
+ mx28_reg(hw_apbh_ch2_debug2)
+ mx28_reg(hw_apbh_ch3_curcmdar)
+ mx28_reg(hw_apbh_ch3_nxtcmdar)
+ mx28_reg(hw_apbh_ch3_cmd)
+ mx28_reg(hw_apbh_ch3_bar)
+ mx28_reg(hw_apbh_ch3_sema)
+ mx28_reg(hw_apbh_ch3_debug1)
+ mx28_reg(hw_apbh_ch3_debug2)
+ mx28_reg(hw_apbh_ch4_curcmdar)
+ mx28_reg(hw_apbh_ch4_nxtcmdar)
+ mx28_reg(hw_apbh_ch4_cmd)
+ mx28_reg(hw_apbh_ch4_bar)
+ mx28_reg(hw_apbh_ch4_sema)
+ mx28_reg(hw_apbh_ch4_debug1)
+ mx28_reg(hw_apbh_ch4_debug2)
+ mx28_reg(hw_apbh_ch5_curcmdar)
+ mx28_reg(hw_apbh_ch5_nxtcmdar)
+ mx28_reg(hw_apbh_ch5_cmd)
+ mx28_reg(hw_apbh_ch5_bar)
+ mx28_reg(hw_apbh_ch5_sema)
+ mx28_reg(hw_apbh_ch5_debug1)
+ mx28_reg(hw_apbh_ch5_debug2)
+ mx28_reg(hw_apbh_ch6_curcmdar)
+ mx28_reg(hw_apbh_ch6_nxtcmdar)
+ mx28_reg(hw_apbh_ch6_cmd)
+ mx28_reg(hw_apbh_ch6_bar)
+ mx28_reg(hw_apbh_ch6_sema)
+ mx28_reg(hw_apbh_ch6_debug1)
+ mx28_reg(hw_apbh_ch6_debug2)
+ mx28_reg(hw_apbh_ch7_curcmdar)
+ mx28_reg(hw_apbh_ch7_nxtcmdar)
+ mx28_reg(hw_apbh_ch7_cmd)
+ mx28_reg(hw_apbh_ch7_bar)
+ mx28_reg(hw_apbh_ch7_sema)
+ mx28_reg(hw_apbh_ch7_debug1)
+ mx28_reg(hw_apbh_ch7_debug2)
+ mx28_reg(hw_apbh_ch8_curcmdar)
+ mx28_reg(hw_apbh_ch8_nxtcmdar)
+ mx28_reg(hw_apbh_ch8_cmd)
+ mx28_reg(hw_apbh_ch8_bar)
+ mx28_reg(hw_apbh_ch8_sema)
+ mx28_reg(hw_apbh_ch8_debug1)
+ mx28_reg(hw_apbh_ch8_debug2)
+ mx28_reg(hw_apbh_ch9_curcmdar)
+ mx28_reg(hw_apbh_ch9_nxtcmdar)
+ mx28_reg(hw_apbh_ch9_cmd)
+ mx28_reg(hw_apbh_ch9_bar)
+ mx28_reg(hw_apbh_ch9_sema)
+ mx28_reg(hw_apbh_ch9_debug1)
+ mx28_reg(hw_apbh_ch9_debug2)
+ mx28_reg(hw_apbh_ch10_curcmdar)
+ mx28_reg(hw_apbh_ch10_nxtcmdar)
+ mx28_reg(hw_apbh_ch10_cmd)
+ mx28_reg(hw_apbh_ch10_bar)
+ mx28_reg(hw_apbh_ch10_sema)
+ mx28_reg(hw_apbh_ch10_debug1)
+ mx28_reg(hw_apbh_ch10_debug2)
+ mx28_reg(hw_apbh_ch11_curcmdar)
+ mx28_reg(hw_apbh_ch11_nxtcmdar)
+ mx28_reg(hw_apbh_ch11_cmd)
+ mx28_reg(hw_apbh_ch11_bar)
+ mx28_reg(hw_apbh_ch11_sema)
+ mx28_reg(hw_apbh_ch11_debug1)
+ mx28_reg(hw_apbh_ch11_debug2)
+ mx28_reg(hw_apbh_ch12_curcmdar)
+ mx28_reg(hw_apbh_ch12_nxtcmdar)
+ mx28_reg(hw_apbh_ch12_cmd)
+ mx28_reg(hw_apbh_ch12_bar)
+ mx28_reg(hw_apbh_ch12_sema)
+ mx28_reg(hw_apbh_ch12_debug1)
+ mx28_reg(hw_apbh_ch12_debug2)
+ mx28_reg(hw_apbh_ch13_curcmdar)
+ mx28_reg(hw_apbh_ch13_nxtcmdar)
+ mx28_reg(hw_apbh_ch13_cmd)
+ mx28_reg(hw_apbh_ch13_bar)
+ mx28_reg(hw_apbh_ch13_sema)
+ mx28_reg(hw_apbh_ch13_debug1)
+ mx28_reg(hw_apbh_ch13_debug2)
+ mx28_reg(hw_apbh_ch14_curcmdar)
+ mx28_reg(hw_apbh_ch14_nxtcmdar)
+ mx28_reg(hw_apbh_ch14_cmd)
+ mx28_reg(hw_apbh_ch14_bar)
+ mx28_reg(hw_apbh_ch14_sema)
+ mx28_reg(hw_apbh_ch14_debug1)
+ mx28_reg(hw_apbh_ch14_debug2)
+ mx28_reg(hw_apbh_ch15_curcmdar)
+ mx28_reg(hw_apbh_ch15_nxtcmdar)
+ mx28_reg(hw_apbh_ch15_cmd)
+ mx28_reg(hw_apbh_ch15_bar)
+ mx28_reg(hw_apbh_ch15_sema)
+ mx28_reg(hw_apbh_ch15_debug1)
+ mx28_reg(hw_apbh_ch15_debug2)
+ };
+ };
+ mx28_reg(hw_apbh_version)
+};
+#endif
+
+#define APBH_CTRL0_SFTRST (1 << 31)
+#define APBH_CTRL0_CLKGATE (1 << 30)
+#define APBH_CTRL0_AHB_BURST8_EN (1 << 29)
+#define APBH_CTRL0_APB_BURST_EN (1 << 28)
+#define APBH_CTRL0_RSVD0_MASK (0xfff << 16)
+#define APBH_CTRL0_RSVD0_OFFSET 16
+#define APBH_CTRL0_CLKGATE_CHANNEL_MASK 0xffff
+#define APBH_CTRL0_CLKGATE_CHANNEL_OFFSET 0
+#define APBH_CTRL0_CLKGATE_CHANNEL_SSP0 0x0001
+#define APBH_CTRL0_CLKGATE_CHANNEL_SSP1 0x0002
+#define APBH_CTRL0_CLKGATE_CHANNEL_SSP2 0x0004
+#define APBH_CTRL0_CLKGATE_CHANNEL_SSP3 0x0008
+#define APBH_CTRL0_CLKGATE_CHANNEL_NAND0 0x0010
+#define APBH_CTRL0_CLKGATE_CHANNEL_NAND1 0x0020
+#define APBH_CTRL0_CLKGATE_CHANNEL_NAND2 0x0040
+#define APBH_CTRL0_CLKGATE_CHANNEL_NAND3 0x0080
+#define APBH_CTRL0_CLKGATE_CHANNEL_NAND4 0x0100
+#define APBH_CTRL0_CLKGATE_CHANNEL_NAND5 0x0200
+#define APBH_CTRL0_CLKGATE_CHANNEL_NAND6 0x0400
+#define APBH_CTRL0_CLKGATE_CHANNEL_NAND7 0x0800
+#define APBH_CTRL0_CLKGATE_CHANNEL_HSADC 0x1000
+#define APBH_CTRL0_CLKGATE_CHANNEL_LCDIF 0x2000
+
+#define APBH_CTRL1_CH15_CMDCMPLT_IRQ_EN (1 << 31)
+#define APBH_CTRL1_CH14_CMDCMPLT_IRQ_EN (1 << 30)
+#define APBH_CTRL1_CH13_CMDCMPLT_IRQ_EN (1 << 29)
+#define APBH_CTRL1_CH12_CMDCMPLT_IRQ_EN (1 << 28)
+#define APBH_CTRL1_CH11_CMDCMPLT_IRQ_EN (1 << 27)
+#define APBH_CTRL1_CH10_CMDCMPLT_IRQ_EN (1 << 26)
+#define APBH_CTRL1_CH9_CMDCMPLT_IRQ_EN (1 << 25)
+#define APBH_CTRL1_CH8_CMDCMPLT_IRQ_EN (1 << 24)
+#define APBH_CTRL1_CH7_CMDCMPLT_IRQ_EN (1 << 23)
+#define APBH_CTRL1_CH6_CMDCMPLT_IRQ_EN (1 << 22)
+#define APBH_CTRL1_CH5_CMDCMPLT_IRQ_EN (1 << 21)
+#define APBH_CTRL1_CH4_CMDCMPLT_IRQ_EN (1 << 20)
+#define APBH_CTRL1_CH3_CMDCMPLT_IRQ_EN (1 << 19)
+#define APBH_CTRL1_CH2_CMDCMPLT_IRQ_EN (1 << 18)
+#define APBH_CTRL1_CH1_CMDCMPLT_IRQ_EN (1 << 17)
+#define APBH_CTRL1_CH0_CMDCMPLT_IRQ_EN (1 << 16)
+#define APBH_CTRL1_CH_CMDCMPLT_IRQ_EN_OFFSET 16
+#define APBH_CTRL1_CH_CMDCMPLT_IRQ_EN_MASK (0xffff << 16)
+#define APBH_CTRL1_CH15_CMDCMPLT_IRQ (1 << 15)
+#define APBH_CTRL1_CH14_CMDCMPLT_IRQ (1 << 14)
+#define APBH_CTRL1_CH13_CMDCMPLT_IRQ (1 << 13)
+#define APBH_CTRL1_CH12_CMDCMPLT_IRQ (1 << 12)
+#define APBH_CTRL1_CH11_CMDCMPLT_IRQ (1 << 11)
+#define APBH_CTRL1_CH10_CMDCMPLT_IRQ (1 << 10)
+#define APBH_CTRL1_CH9_CMDCMPLT_IRQ (1 << 9)
+#define APBH_CTRL1_CH8_CMDCMPLT_IRQ (1 << 8)
+#define APBH_CTRL1_CH7_CMDCMPLT_IRQ (1 << 7)
+#define APBH_CTRL1_CH6_CMDCMPLT_IRQ (1 << 6)
+#define APBH_CTRL1_CH5_CMDCMPLT_IRQ (1 << 5)
+#define APBH_CTRL1_CH4_CMDCMPLT_IRQ (1 << 4)
+#define APBH_CTRL1_CH3_CMDCMPLT_IRQ (1 << 3)
+#define APBH_CTRL1_CH2_CMDCMPLT_IRQ (1 << 2)
+#define APBH_CTRL1_CH1_CMDCMPLT_IRQ (1 << 1)
+#define APBH_CTRL1_CH0_CMDCMPLT_IRQ (1 << 0)
+
+#define APBH_CTRL2_CH15_ERROR_STATUS (1 << 31)
+#define APBH_CTRL2_CH14_ERROR_STATUS (1 << 30)
+#define APBH_CTRL2_CH13_ERROR_STATUS (1 << 29)
+#define APBH_CTRL2_CH12_ERROR_STATUS (1 << 28)
+#define APBH_CTRL2_CH11_ERROR_STATUS (1 << 27)
+#define APBH_CTRL2_CH10_ERROR_STATUS (1 << 26)
+#define APBH_CTRL2_CH9_ERROR_STATUS (1 << 25)
+#define APBH_CTRL2_CH8_ERROR_STATUS (1 << 24)
+#define APBH_CTRL2_CH7_ERROR_STATUS (1 << 23)
+#define APBH_CTRL2_CH6_ERROR_STATUS (1 << 22)
+#define APBH_CTRL2_CH5_ERROR_STATUS (1 << 21)
+#define APBH_CTRL2_CH4_ERROR_STATUS (1 << 20)
+#define APBH_CTRL2_CH3_ERROR_STATUS (1 << 19)
+#define APBH_CTRL2_CH2_ERROR_STATUS (1 << 18)
+#define APBH_CTRL2_CH1_ERROR_STATUS (1 << 17)
+#define APBH_CTRL2_CH0_ERROR_STATUS (1 << 16)
+#define APBH_CTRL2_CH15_ERROR_IRQ (1 << 15)
+#define APBH_CTRL2_CH14_ERROR_IRQ (1 << 14)
+#define APBH_CTRL2_CH13_ERROR_IRQ (1 << 13)
+#define APBH_CTRL2_CH12_ERROR_IRQ (1 << 12)
+#define APBH_CTRL2_CH11_ERROR_IRQ (1 << 11)
+#define APBH_CTRL2_CH10_ERROR_IRQ (1 << 10)
+#define APBH_CTRL2_CH9_ERROR_IRQ (1 << 9)
+#define APBH_CTRL2_CH8_ERROR_IRQ (1 << 8)
+#define APBH_CTRL2_CH7_ERROR_IRQ (1 << 7)
+#define APBH_CTRL2_CH6_ERROR_IRQ (1 << 6)
+#define APBH_CTRL2_CH5_ERROR_IRQ (1 << 5)
+#define APBH_CTRL2_CH4_ERROR_IRQ (1 << 4)
+#define APBH_CTRL2_CH3_ERROR_IRQ (1 << 3)
+#define APBH_CTRL2_CH2_ERROR_IRQ (1 << 2)
+#define APBH_CTRL2_CH1_ERROR_IRQ (1 << 1)
+#define APBH_CTRL2_CH0_ERROR_IRQ (1 << 0)
+
+#define APBH_CHANNEL_CTRL_RESET_CHANNEL_MASK (0xffff << 16)
+#define APBH_CHANNEL_CTRL_RESET_CHANNEL_OFFSET 16
+#define APBH_CHANNEL_CTRL_RESET_CHANNEL_SSP0 (0x0001 << 16)
+#define APBH_CHANNEL_CTRL_RESET_CHANNEL_SSP1 (0x0002 << 16)
+#define APBH_CHANNEL_CTRL_RESET_CHANNEL_SSP2 (0x0004 << 16)
+#define APBH_CHANNEL_CTRL_RESET_CHANNEL_SSP3 (0x0008 << 16)
+#define APBH_CHANNEL_CTRL_RESET_CHANNEL_NAND0 (0x0010 << 16)
+#define APBH_CHANNEL_CTRL_RESET_CHANNEL_NAND1 (0x0020 << 16)
+#define APBH_CHANNEL_CTRL_RESET_CHANNEL_NAND2 (0x0040 << 16)
+#define APBH_CHANNEL_CTRL_RESET_CHANNEL_NAND3 (0x0080 << 16)
+#define APBH_CHANNEL_CTRL_RESET_CHANNEL_NAND4 (0x0100 << 16)
+#define APBH_CHANNEL_CTRL_RESET_CHANNEL_NAND5 (0x0200 << 16)
+#define APBH_CHANNEL_CTRL_RESET_CHANNEL_NAND6 (0x0400 << 16)
+#define APBH_CHANNEL_CTRL_RESET_CHANNEL_NAND7 (0x0800 << 16)
+#define APBH_CHANNEL_CTRL_RESET_CHANNEL_HSADC (0x1000 << 16)
+#define APBH_CHANNEL_CTRL_RESET_CHANNEL_LCDIF (0x2000 << 16)
+#define APBH_CHANNEL_CTRL_FREEZE_CHANNEL_MASK 0xffff
+#define APBH_CHANNEL_CTRL_FREEZE_CHANNEL_OFFSET 0
+#define APBH_CHANNEL_CTRL_FREEZE_CHANNEL_SSP0 0x0001
+#define APBH_CHANNEL_CTRL_FREEZE_CHANNEL_SSP1 0x0002
+#define APBH_CHANNEL_CTRL_FREEZE_CHANNEL_SSP2 0x0004
+#define APBH_CHANNEL_CTRL_FREEZE_CHANNEL_SSP3 0x0008
+#define APBH_CHANNEL_CTRL_FREEZE_CHANNEL_NAND0 0x0010
+#define APBH_CHANNEL_CTRL_FREEZE_CHANNEL_NAND1 0x0020
+#define APBH_CHANNEL_CTRL_FREEZE_CHANNEL_NAND2 0x0040
+#define APBH_CHANNEL_CTRL_FREEZE_CHANNEL_NAND3 0x0080
+#define APBH_CHANNEL_CTRL_FREEZE_CHANNEL_NAND4 0x0100
+#define APBH_CHANNEL_CTRL_FREEZE_CHANNEL_NAND5 0x0200
+#define APBH_CHANNEL_CTRL_FREEZE_CHANNEL_NAND6 0x0400
+#define APBH_CHANNEL_CTRL_FREEZE_CHANNEL_NAND7 0x0800
+#define APBH_CHANNEL_CTRL_FREEZE_CHANNEL_HSADC 0x1000
+#define APBH_CHANNEL_CTRL_FREEZE_CHANNEL_LCDIF 0x2000
+
+#define APBH_DEVSEL_CH15_MASK (0x3 << 30)
+#define APBH_DEVSEL_CH15_OFFSET 30
+#define APBH_DEVSEL_CH14_MASK (0x3 << 28)
+#define APBH_DEVSEL_CH14_OFFSET 28
+#define APBH_DEVSEL_CH13_MASK (0x3 << 26)
+#define APBH_DEVSEL_CH13_OFFSET 26
+#define APBH_DEVSEL_CH12_MASK (0x3 << 24)
+#define APBH_DEVSEL_CH12_OFFSET 24
+#define APBH_DEVSEL_CH11_MASK (0x3 << 22)
+#define APBH_DEVSEL_CH11_OFFSET 22
+#define APBH_DEVSEL_CH10_MASK (0x3 << 20)
+#define APBH_DEVSEL_CH10_OFFSET 20
+#define APBH_DEVSEL_CH9_MASK (0x3 << 18)
+#define APBH_DEVSEL_CH9_OFFSET 18
+#define APBH_DEVSEL_CH8_MASK (0x3 << 16)
+#define APBH_DEVSEL_CH8_OFFSET 16
+#define APBH_DEVSEL_CH7_MASK (0x3 << 14)
+#define APBH_DEVSEL_CH7_OFFSET 14
+#define APBH_DEVSEL_CH6_MASK (0x3 << 12)
+#define APBH_DEVSEL_CH6_OFFSET 12
+#define APBH_DEVSEL_CH5_MASK (0x3 << 10)
+#define APBH_DEVSEL_CH5_OFFSET 10
+#define APBH_DEVSEL_CH4_MASK (0x3 << 8)
+#define APBH_DEVSEL_CH4_OFFSET 8
+#define APBH_DEVSEL_CH3_MASK (0x3 << 6)
+#define APBH_DEVSEL_CH3_OFFSET 6
+#define APBH_DEVSEL_CH2_MASK (0x3 << 4)
+#define APBH_DEVSEL_CH2_OFFSET 4
+#define APBH_DEVSEL_CH1_MASK (0x3 << 2)
+#define APBH_DEVSEL_CH1_OFFSET 2
+#define APBH_DEVSEL_CH0_MASK (0x3 << 0)
+#define APBH_DEVSEL_CH0_OFFSET 0
+
+#define APBH_DMA_BURST_SIZE_CH15_MASK (0x3 << 30)
+#define APBH_DMA_BURST_SIZE_CH15_OFFSET 30
+#define APBH_DMA_BURST_SIZE_CH14_MASK (0x3 << 28)
+#define APBH_DMA_BURST_SIZE_CH14_OFFSET 28
+#define APBH_DMA_BURST_SIZE_CH13_MASK (0x3 << 26)
+#define APBH_DMA_BURST_SIZE_CH13_OFFSET 26
+#define APBH_DMA_BURST_SIZE_CH12_MASK (0x3 << 24)
+#define APBH_DMA_BURST_SIZE_CH12_OFFSET 24
+#define APBH_DMA_BURST_SIZE_CH11_MASK (0x3 << 22)
+#define APBH_DMA_BURST_SIZE_CH11_OFFSET 22
+#define APBH_DMA_BURST_SIZE_CH10_MASK (0x3 << 20)
+#define APBH_DMA_BURST_SIZE_CH10_OFFSET 20
+#define APBH_DMA_BURST_SIZE_CH9_MASK (0x3 << 18)
+#define APBH_DMA_BURST_SIZE_CH9_OFFSET 18
+#define APBH_DMA_BURST_SIZE_CH8_MASK (0x3 << 16)
+#define APBH_DMA_BURST_SIZE_CH8_OFFSET 16
+#define APBH_DMA_BURST_SIZE_CH8_BURST0 (0x0 << 16)
+#define APBH_DMA_BURST_SIZE_CH8_BURST4 (0x1 << 16)
+#define APBH_DMA_BURST_SIZE_CH8_BURST8 (0x2 << 16)
+#define APBH_DMA_BURST_SIZE_CH7_MASK (0x3 << 14)
+#define APBH_DMA_BURST_SIZE_CH7_OFFSET 14
+#define APBH_DMA_BURST_SIZE_CH6_MASK (0x3 << 12)
+#define APBH_DMA_BURST_SIZE_CH6_OFFSET 12
+#define APBH_DMA_BURST_SIZE_CH5_MASK (0x3 << 10)
+#define APBH_DMA_BURST_SIZE_CH5_OFFSET 10
+#define APBH_DMA_BURST_SIZE_CH4_MASK (0x3 << 8)
+#define APBH_DMA_BURST_SIZE_CH4_OFFSET 8
+#define APBH_DMA_BURST_SIZE_CH3_MASK (0x3 << 6)
+#define APBH_DMA_BURST_SIZE_CH3_OFFSET 6
+#define APBH_DMA_BURST_SIZE_CH3_BURST0 (0x0 << 6)
+#define APBH_DMA_BURST_SIZE_CH3_BURST4 (0x1 << 6)
+#define APBH_DMA_BURST_SIZE_CH3_BURST8 (0x2 << 6)
+
+#define APBH_DMA_BURST_SIZE_CH2_MASK (0x3 << 4)
+#define APBH_DMA_BURST_SIZE_CH2_OFFSET 4
+#define APBH_DMA_BURST_SIZE_CH2_BURST0 (0x0 << 4)
+#define APBH_DMA_BURST_SIZE_CH2_BURST4 (0x1 << 4)
+#define APBH_DMA_BURST_SIZE_CH2_BURST8 (0x2 << 4)
+#define APBH_DMA_BURST_SIZE_CH1_MASK (0x3 << 2)
+#define APBH_DMA_BURST_SIZE_CH1_OFFSET 2
+#define APBH_DMA_BURST_SIZE_CH1_BURST0 (0x0 << 2)
+#define APBH_DMA_BURST_SIZE_CH1_BURST4 (0x1 << 2)
+#define APBH_DMA_BURST_SIZE_CH1_BURST8 (0x2 << 2)
+
+#define APBH_DMA_BURST_SIZE_CH0_MASK 0x3
+#define APBH_DMA_BURST_SIZE_CH0_OFFSET 0
+#define APBH_DMA_BURST_SIZE_CH0_BURST0 0x0
+#define APBH_DMA_BURST_SIZE_CH0_BURST4 0x1
+#define APBH_DMA_BURST_SIZE_CH0_BURST8 0x2
+
+#define APBH_DEBUG_GPMI_ONE_FIFO (1 << 0)
+
+#define APBH_CHn_CURCMDAR_CMD_ADDR_MASK 0xffffffff
+#define APBH_CHn_CURCMDAR_CMD_ADDR_OFFSET 0
+
+#define APBH_CHn_NXTCMDAR_CMD_ADDR_MASK 0xffffffff
+#define APBH_CHn_NXTCMDAR_CMD_ADDR_OFFSET 0
+
+#define APBH_CHn_CMD_XFER_COUNT_MASK (0xffff << 16)
+#define APBH_CHn_CMD_XFER_COUNT_OFFSET 16
+#define APBH_CHn_CMD_CMDWORDS_MASK (0xf << 12)
+#define APBH_CHn_CMD_CMDWORDS_OFFSET 12
+#define APBH_CHn_CMD_HALTONTERMINATE (1 << 8)
+#define APBH_CHn_CMD_WAIT4ENDCMD (1 << 7)
+#define APBH_CHn_CMD_SEMAPHORE (1 << 6)
+#define APBH_CHn_CMD_NANDWAIT4READY (1 << 5)
+#define APBH_CHn_CMD_NANDLOCK (1 << 4)
+#define APBH_CHn_CMD_IRQONCMPLT (1 << 3)
+#define APBH_CHn_CMD_CHAIN (1 << 2)
+#define APBH_CHn_CMD_COMMAND_MASK 0x3
+#define APBH_CHn_CMD_COMMAND_OFFSET 0
+#define APBH_CHn_CMD_COMMAND_NO_DMA_XFER 0x0
+#define APBH_CHn_CMD_COMMAND_DMA_WRITE 0x1
+#define APBH_CHn_CMD_COMMAND_DMA_READ 0x2
+#define APBH_CHn_CMD_COMMAND_DMA_SENSE 0x3
+
+#define APBH_CHn_BAR_ADDRESS_MASK 0xffffffff
+#define APBH_CHn_BAR_ADDRESS_OFFSET 0
+
+#define APBH_CHn_SEMA_RSVD2_MASK (0xff << 24)
+#define APBH_CHn_SEMA_RSVD2_OFFSET 24
+#define APBH_CHn_SEMA_PHORE_MASK (0xff << 16)
+#define APBH_CHn_SEMA_PHORE_OFFSET 16
+#define APBH_CHn_SEMA_RSVD1_MASK (0xff << 8)
+#define APBH_CHn_SEMA_RSVD1_OFFSET 8
+#define APBH_CHn_SEMA_INCREMENT_SEMA_MASK (0xff << 0)
+#define APBH_CHn_SEMA_INCREMENT_SEMA_OFFSET 0
+
+#define APBH_CHn_DEBUG1_REQ (1 << 31)
+#define APBH_CHn_DEBUG1_BURST (1 << 30)
+#define APBH_CHn_DEBUG1_KICK (1 << 29)
+#define APBH_CHn_DEBUG1_END (1 << 28)
+#define APBH_CHn_DEBUG1_SENSE (1 << 27)
+#define APBH_CHn_DEBUG1_READY (1 << 26)
+#define APBH_CHn_DEBUG1_LOCK (1 << 25)
+#define APBH_CHn_DEBUG1_NEXTCMDADDRVALID (1 << 24)
+#define APBH_CHn_DEBUG1_RD_FIFO_EMPTY (1 << 23)
+#define APBH_CHn_DEBUG1_RD_FIFO_FULL (1 << 22)
+#define APBH_CHn_DEBUG1_WR_FIFO_EMPTY (1 << 21)
+#define APBH_CHn_DEBUG1_WR_FIFO_FULL (1 << 20)
+#define APBH_CHn_DEBUG1_RSVD1_MASK (0x7fff << 5)
+#define APBH_CHn_DEBUG1_RSVD1_OFFSET 5
+#define APBH_CHn_DEBUG1_STATEMACHINE_MASK 0x1f
+#define APBH_CHn_DEBUG1_STATEMACHINE_OFFSET 0
+#define APBH_CHn_DEBUG1_STATEMACHINE_IDLE 0x00
+#define APBH_CHn_DEBUG1_STATEMACHINE_REQ_CMD1 0x01
+#define APBH_CHn_DEBUG1_STATEMACHINE_REQ_CMD3 0x02
+#define APBH_CHn_DEBUG1_STATEMACHINE_REQ_CMD2 0x03
+#define APBH_CHn_DEBUG1_STATEMACHINE_XFER_DECODE 0x04
+#define APBH_CHn_DEBUG1_STATEMACHINE_REQ_WAIT 0x05
+#define APBH_CHn_DEBUG1_STATEMACHINE_REQ_CMD4 0x06
+#define APBH_CHn_DEBUG1_STATEMACHINE_PIO_REQ 0x07
+#define APBH_CHn_DEBUG1_STATEMACHINE_READ_FLUSH 0x08
+#define APBH_CHn_DEBUG1_STATEMACHINE_READ_WAIT 0x09
+#define APBH_CHn_DEBUG1_STATEMACHINE_WRITE 0x0c
+#define APBH_CHn_DEBUG1_STATEMACHINE_READ_REQ 0x0d
+#define APBH_CHn_DEBUG1_STATEMACHINE_CHECK_CHAIN 0x0e
+#define APBH_CHn_DEBUG1_STATEMACHINE_XFER_COMPLETE 0x0f
+#define APBH_CHn_DEBUG1_STATEMACHINE_TERMINATE 0x14
+#define APBH_CHn_DEBUG1_STATEMACHINE_WAIT_END 0x15
+#define APBH_CHn_DEBUG1_STATEMACHINE_WRITE_WAIT 0x1c
+#define APBH_CHn_DEBUG1_STATEMACHINE_HALT_AFTER_TERM 0x1d
+#define APBH_CHn_DEBUG1_STATEMACHINE_CHECK_WAIT 0x1e
+#define APBH_CHn_DEBUG1_STATEMACHINE_WAIT_READY 0x1f
+
+#define APBH_CHn_DEBUG2_APB_BYTES_MASK (0xffff << 16)
+#define APBH_CHn_DEBUG2_APB_BYTES_OFFSET 16
+#define APBH_CHn_DEBUG2_AHB_BYTES_MASK 0xffff
+#define APBH_CHn_DEBUG2_AHB_BYTES_OFFSET 0
+
+#define APBH_VERSION_MAJOR_MASK (0xff << 24)
+#define APBH_VERSION_MAJOR_OFFSET 24
+#define APBH_VERSION_MINOR_MASK (0xff << 16)
+#define APBH_VERSION_MINOR_OFFSET 16
+#define APBH_VERSION_STEP_MASK 0xffff
+#define APBH_VERSION_STEP_OFFSET 0
+
+#endif /* __REGS_APBH_H__ */
diff --git a/arch/arm/include/asm/arch-mx28/regs-base.h b/arch/arm/include/asm/arch-mx28/regs-base.h
new file mode 100644
index 0000000..dbdcc2b
--- /dev/null
+++ b/arch/arm/include/asm/arch-mx28/regs-base.h
@@ -0,0 +1,88 @@
+/*
+ * Freescale i.MX28 Peripheral Base Addresses
+ *
+ * Copyright (C) 2011 Marek Vasut <marek.vasut@gmail.com>
+ * on behalf of DENX Software Engineering GmbH
+ *
+ * Based on code from LTIB:
+ * Copyright (C) 2008 Embedded Alley Solutions Inc.
+ *
+ * (C) Copyright 2009-2010 Freescale Semiconductor, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
+ *
+ */
+
+#ifndef __MX28_REGS_BASE_H__
+#define __MX28_REGS_BASE_H__
+
+/*
+ * Register base address
+ */
+#define MXS_ICOL_BASE 0x80000000
+#define MXS_HSADC_BASE 0x80002000
+#define MXS_APBH_BASE 0x80004000
+#define MXS_PERFMON_BASE 0x80006000
+#define MXS_BCH_BASE 0x8000A000
+#define MXS_GPMI_BASE 0x8000C000
+#define MXS_SSP0_BASE 0x80010000
+#define MXS_SSP1_BASE 0x80012000
+#define MXS_SSP2_BASE 0x80014000
+#define MXS_SSP3_BASE 0x80016000
+#define MXS_PINCTRL_BASE 0x80018000
+#define MXS_DIGCTL_BASE 0x8001C000
+#define MXS_ETM_BASE 0x80022000
+#define MXS_APBX_BASE 0x80024000
+#define MXS_DCP_BASE 0x80028000
+#define MXS_PXP_BASE 0x8002A000
+#define MXS_OCOTP_BASE 0x8002C000
+#define MXS_AXI_AHB0_BASE 0x8002E000
+#define MXS_LCDIF_BASE 0x80030000
+#define MXS_CAN0_BASE 0x80032000
+#define MXS_CAN1_BASE 0x80034000
+#define MXS_SIMDBG_BASE 0x8003C000
+#define MXS_SIMGPMISEL_BASE 0x8003C200
+#define MXS_SIMSSPSEL_BASE 0x8003C300
+#define MXS_SIMMEMSEL_BASE 0x8003C400
+#define MXS_GPIOMON_BASE 0x8003C500
+#define MXS_SIMENET_BASE 0x8003C700
+#define MXS_ARMJTAG_BASE 0x8003C800
+#define MXS_CLKCTRL_BASE 0x80040000
+#define MXS_SAIF0_BASE 0x80042000
+#define MXS_POWER_BASE 0x80044000
+#define MXS_SAIF1_BASE 0x80046000
+#define MXS_LRADC_BASE 0x80050000
+#define MXS_SPDIF_BASE 0x80054000
+#define MXS_RTC_BASE 0x80056000
+#define MXS_I2C0_BASE 0x80058000
+#define MXS_I2C1_BASE 0x8005A000
+#define MXS_PWM_BASE 0x80064000
+#define MXS_TIMROT_BASE 0x80068000
+#define MXS_UARTAPP0_BASE 0x8006A000
+#define MXS_UARTAPP1_BASE 0x8006C000
+#define MXS_UARTAPP2_BASE 0x8006E000
+#define MXS_UARTAPP3_BASE 0x80070000
+#define MXS_UARTAPP4_BASE 0x80072000
+#define MXS_UARTDBG_BASE 0x80074000
+#define MXS_USBPHY0_BASE 0x8007C000
+#define MXS_USBPHY1_BASE 0x8007E000
+#define MXS_USBCTRL0_BASE 0x80080000
+#define MXS_USBCTRL1_BASE 0x80090000
+#define MXS_DFLPT_BASE 0x800C0000
+#define MXS_DRAM_BASE 0x800E0000
+#define MXS_ENET0_BASE 0x800F0000
+#define MXS_ENET1_BASE 0x800F4000
+
+#endif /* __MX28_REGS_BASE_H__ */
diff --git a/arch/arm/include/asm/arch-mx28/regs-bch.h b/arch/arm/include/asm/arch-mx28/regs-bch.h
new file mode 100644
index 0000000..cac0470
--- /dev/null
+++ b/arch/arm/include/asm/arch-mx28/regs-bch.h
@@ -0,0 +1,230 @@
+/*
+ * Freescale i.MX28 BCH Register Definitions
+ *
+ * Copyright (C) 2011 Marek Vasut <marek.vasut@gmail.com>
+ * on behalf of DENX Software Engineering GmbH
+ *
+ * Based on code from LTIB:
+ * Copyright 2008-2010 Freescale Semiconductor, Inc. All Rights Reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
+ *
+ */
+
+#ifndef __MX28_REGS_BCH_H__
+#define __MX28_REGS_BCH_H__
+
+#include <asm/arch/regs-common.h>
+
+#ifndef __ASSEMBLY__
+struct mx28_bch_regs {
+ mx28_reg(hw_bch_ctrl)
+ mx28_reg(hw_bch_status0)
+ mx28_reg(hw_bch_mode)
+ mx28_reg(hw_bch_encodeptr)
+ mx28_reg(hw_bch_dataptr)
+ mx28_reg(hw_bch_metaptr)
+
+ uint32_t reserved[4];
+
+ mx28_reg(hw_bch_layoutselect)
+ mx28_reg(hw_bch_flash0layout0)
+ mx28_reg(hw_bch_flash0layout1)
+ mx28_reg(hw_bch_flash1layout0)
+ mx28_reg(hw_bch_flash1layout1)
+ mx28_reg(hw_bch_flash2layout0)
+ mx28_reg(hw_bch_flash2layout1)
+ mx28_reg(hw_bch_flash3layout0)
+ mx28_reg(hw_bch_flash3layout1)
+ mx28_reg(hw_bch_dbgkesread)
+ mx28_reg(hw_bch_dbgcsferead)
+ mx28_reg(hw_bch_dbgsyndegread)
+ mx28_reg(hw_bch_dbgahbmread)
+ mx28_reg(hw_bch_blockname)
+ mx28_reg(hw_bch_version)
+};
+#endif
+
+#define BCH_CTRL_SFTRST (1 << 31)
+#define BCH_CTRL_CLKGATE (1 << 30)
+#define BCH_CTRL_DEBUGSYNDROME (1 << 22)
+#define BCH_CTRL_M2M_LAYOUT_MASK (0x3 << 18)
+#define BCH_CTRL_M2M_LAYOUT_OFFSET 18
+#define BCH_CTRL_M2M_ENCODE (1 << 17)
+#define BCH_CTRL_M2M_ENABLE (1 << 16)
+#define BCH_CTRL_DEBUG_STALL_IRQ_EN (1 << 10)
+#define BCH_CTRL_COMPLETE_IRQ_EN (1 << 8)
+#define BCH_CTRL_BM_ERROR_IRQ (1 << 3)
+#define BCH_CTRL_DEBUG_STALL_IRQ (1 << 2)
+#define BCH_CTRL_COMPLETE_IRQ (1 << 0)
+
+#define BCH_STATUS0_HANDLE_MASK (0xfff << 20)
+#define BCH_STATUS0_HANDLE_OFFSET 20
+#define BCH_STATUS0_COMPLETED_CE_MASK (0xf << 16)
+#define BCH_STATUS0_COMPLETED_CE_OFFSET 16
+#define BCH_STATUS0_STATUS_BLK0_MASK (0xff << 8)
+#define BCH_STATUS0_STATUS_BLK0_OFFSET 8
+#define BCH_STATUS0_STATUS_BLK0_ZERO (0x00 << 8)
+#define BCH_STATUS0_STATUS_BLK0_ERROR1 (0x01 << 8)
+#define BCH_STATUS0_STATUS_BLK0_ERROR2 (0x02 << 8)
+#define BCH_STATUS0_STATUS_BLK0_ERROR3 (0x03 << 8)
+#define BCH_STATUS0_STATUS_BLK0_ERROR4 (0x04 << 8)
+#define BCH_STATUS0_STATUS_BLK0_UNCORRECTABLE (0xfe << 8)
+#define BCH_STATUS0_STATUS_BLK0_ERASED (0xff << 8)
+#define BCH_STATUS0_ALLONES (1 << 4)
+#define BCH_STATUS0_CORRECTED (1 << 3)
+#define BCH_STATUS0_UNCORRECTABLE (1 << 2)
+
+#define BCH_MODE_ERASE_THRESHOLD_MASK 0xff
+#define BCH_MODE_ERASE_THRESHOLD_OFFSET 0
+
+#define BCH_ENCODEPTR_ADDR_MASK 0xffffffff
+#define BCH_ENCODEPTR_ADDR_OFFSET 0
+
+#define BCH_DATAPTR_ADDR_MASK 0xffffffff
+#define BCH_DATAPTR_ADDR_OFFSET 0
+
+#define BCH_METAPTR_ADDR_MASK 0xffffffff
+#define BCH_METAPTR_ADDR_OFFSET 0
+
+#define BCH_LAYOUTSELECT_CS15_SELECT_MASK (0x3 << 30)
+#define BCH_LAYOUTSELECT_CS15_SELECT_OFFSET 30
+#define BCH_LAYOUTSELECT_CS14_SELECT_MASK (0x3 << 28)
+#define BCH_LAYOUTSELECT_CS14_SELECT_OFFSET 28
+#define BCH_LAYOUTSELECT_CS13_SELECT_MASK (0x3 << 26)
+#define BCH_LAYOUTSELECT_CS13_SELECT_OFFSET 26
+#define BCH_LAYOUTSELECT_CS12_SELECT_MASK (0x3 << 24)
+#define BCH_LAYOUTSELECT_CS12_SELECT_OFFSET 24
+#define BCH_LAYOUTSELECT_CS11_SELECT_MASK (0x3 << 22)
+#define BCH_LAYOUTSELECT_CS11_SELECT_OFFSET 22
+#define BCH_LAYOUTSELECT_CS10_SELECT_MASK (0x3 << 20)
+#define BCH_LAYOUTSELECT_CS10_SELECT_OFFSET 20
+#define BCH_LAYOUTSELECT_CS9_SELECT_MASK (0x3 << 18)
+#define BCH_LAYOUTSELECT_CS9_SELECT_OFFSET 18
+#define BCH_LAYOUTSELECT_CS8_SELECT_MASK (0x3 << 16)
+#define BCH_LAYOUTSELECT_CS8_SELECT_OFFSET 16
+#define BCH_LAYOUTSELECT_CS7_SELECT_MASK (0x3 << 14)
+#define BCH_LAYOUTSELECT_CS7_SELECT_OFFSET 14
+#define BCH_LAYOUTSELECT_CS6_SELECT_MASK (0x3 << 12)
+#define BCH_LAYOUTSELECT_CS6_SELECT_OFFSET 12
+#define BCH_LAYOUTSELECT_CS5_SELECT_MASK (0x3 << 10)
+#define BCH_LAYOUTSELECT_CS5_SELECT_OFFSET 10
+#define BCH_LAYOUTSELECT_CS4_SELECT_MASK (0x3 << 8)
+#define BCH_LAYOUTSELECT_CS4_SELECT_OFFSET 8
+#define BCH_LAYOUTSELECT_CS3_SELECT_MASK (0x3 << 6)
+#define BCH_LAYOUTSELECT_CS3_SELECT_OFFSET 6
+#define BCH_LAYOUTSELECT_CS2_SELECT_MASK (0x3 << 4)
+#define BCH_LAYOUTSELECT_CS2_SELECT_OFFSET 4
+#define BCH_LAYOUTSELECT_CS1_SELECT_MASK (0x3 << 2)
+#define BCH_LAYOUTSELECT_CS1_SELECT_OFFSET 2
+#define BCH_LAYOUTSELECT_CS0_SELECT_MASK (0x3 << 0)
+#define BCH_LAYOUTSELECT_CS0_SELECT_OFFSET 0
+
+#define BCH_FLASHLAYOUT0_NBLOCKS_MASK (0xff << 24)
+#define BCH_FLASHLAYOUT0_NBLOCKS_OFFSET 24
+#define BCH_FLASHLAYOUT0_META_SIZE_MASK (0xff << 16)
+#define BCH_FLASHLAYOUT0_META_SIZE_OFFSET 16
+#define BCH_FLASHLAYOUT0_ECC0_MASK (0xf << 12)
+#define BCH_FLASHLAYOUT0_ECC0_OFFSET 12
+#define BCH_FLASHLAYOUT0_ECC0_NONE (0x0 << 12)
+#define BCH_FLASHLAYOUT0_ECC0_ECC2 (0x1 << 12)
+#define BCH_FLASHLAYOUT0_ECC0_ECC4 (0x2 << 12)
+#define BCH_FLASHLAYOUT0_ECC0_ECC6 (0x3 << 12)
+#define BCH_FLASHLAYOUT0_ECC0_ECC8 (0x4 << 12)
+#define BCH_FLASHLAYOUT0_ECC0_ECC10 (0x5 << 12)
+#define BCH_FLASHLAYOUT0_ECC0_ECC12 (0x6 << 12)
+#define BCH_FLASHLAYOUT0_ECC0_ECC14 (0x7 << 12)
+#define BCH_FLASHLAYOUT0_ECC0_ECC16 (0x8 << 12)
+#define BCH_FLASHLAYOUT0_ECC0_ECC18 (0x9 << 12)
+#define BCH_FLASHLAYOUT0_ECC0_ECC20 (0xa << 12)
+#define BCH_FLASHLAYOUT0_ECC0_ECC22 (0xb << 12)
+#define BCH_FLASHLAYOUT0_ECC0_ECC24 (0xc << 12)
+#define BCH_FLASHLAYOUT0_ECC0_ECC26 (0xd << 12)
+#define BCH_FLASHLAYOUT0_ECC0_ECC28 (0xe << 12)
+#define BCH_FLASHLAYOUT0_ECC0_ECC30 (0xf << 12)
+#define BCH_FLASHLAYOUT0_ECC0_ECC32 (0x10 << 12)
+#define BCH_FLASHLAYOUT0_GF13_0_GF14_1 (1 << 10)
+#define BCH_FLASHLAYOUT0_DATA0_SIZE_MASK 0xfff
+#define BCH_FLASHLAYOUT0_DATA0_SIZE_OFFSET 0
+
+#define BCH_FLASHLAYOUT1_PAGE_SIZE_MASK (0xffff << 16)
+#define BCH_FLASHLAYOUT1_PAGE_SIZE_OFFSET 16
+#define BCH_FLASHLAYOUT1_ECCN_MASK (0xf << 12)
+#define BCH_FLASHLAYOUT1_ECCN_OFFSET 12
+#define BCH_FLASHLAYOUT1_ECCN_NONE (0x0 << 12)
+#define BCH_FLASHLAYOUT1_ECCN_ECC2 (0x1 << 12)
+#define BCH_FLASHLAYOUT1_ECCN_ECC4 (0x2 << 12)
+#define BCH_FLASHLAYOUT1_ECCN_ECC6 (0x3 << 12)
+#define BCH_FLASHLAYOUT1_ECCN_ECC8 (0x4 << 12)
+#define BCH_FLASHLAYOUT1_ECCN_ECC10 (0x5 << 12)
+#define BCH_FLASHLAYOUT1_ECCN_ECC12 (0x6 << 12)
+#define BCH_FLASHLAYOUT1_ECCN_ECC14 (0x7 << 12)
+#define BCH_FLASHLAYOUT1_ECCN_ECC16 (0x8 << 12)
+#define BCH_FLASHLAYOUT1_ECCN_ECC18 (0x9 << 12)
+#define BCH_FLASHLAYOUT1_ECCN_ECC20 (0xa << 12)
+#define BCH_FLASHLAYOUT1_ECCN_ECC22 (0xb << 12)
+#define BCH_FLASHLAYOUT1_ECCN_ECC24 (0xc << 12)
+#define BCH_FLASHLAYOUT1_ECCN_ECC26 (0xd << 12)
+#define BCH_FLASHLAYOUT1_ECCN_ECC28 (0xe << 12)
+#define BCH_FLASHLAYOUT1_ECCN_ECC30 (0xf << 12)
+#define BCH_FLASHLAYOUT1_ECCN_ECC32 (0x10 << 12)
+#define BCH_FLASHLAYOUT1_GF13_0_GF14_1 (1 << 10)
+#define BCH_FLASHLAYOUT1_DATAN_SIZE_MASK 0xfff
+#define BCH_FLASHLAYOUT1_DATAN_SIZE_OFFSET 0
+
+#define BCH_DEBUG0_RSVD1_MASK (0x1f << 27)
+#define BCH_DEBUG0_RSVD1_OFFSET 27
+#define BCH_DEBUG0_ROM_BIST_ENABLE (1 << 26)
+#define BCH_DEBUG0_ROM_BIST_COMPLETE (1 << 25)
+#define BCH_DEBUG0_KES_DEBUG_SYNDROME_SYMBOL_MASK (0x1ff << 16)
+#define BCH_DEBUG0_KES_DEBUG_SYNDROME_SYMBOL_OFFSET 16
+#define BCH_DEBUG0_KES_DEBUG_SYNDROME_SYMBOL_NORMAL (0x0 << 16)
+#define BCH_DEBUG0_KES_DEBUG_SYNDROME_SYMBOL_TEST_MODE (0x1 << 16)
+#define BCH_DEBUG0_KES_DEBUG_SHIFT_SYND (1 << 15)
+#define BCH_DEBUG0_KES_DEBUG_PAYLOAD_FLAG (1 << 14)
+#define BCH_DEBUG0_KES_DEBUG_MODE4K (1 << 13)
+#define BCH_DEBUG0_KES_DEBUG_KICK (1 << 12)
+#define BCH_DEBUG0_KES_STANDALONE (1 << 11)
+#define BCH_DEBUG0_KES_DEBUG_STEP (1 << 10)
+#define BCH_DEBUG0_KES_DEBUG_STALL (1 << 9)
+#define BCH_DEBUG0_BM_KES_TEST_BYPASS (1 << 8)
+#define BCH_DEBUG0_RSVD0_MASK (0x3 << 6)
+#define BCH_DEBUG0_RSVD0_OFFSET 6
+#define BCH_DEBUG0_DEBUG_REG_SELECT_MASK 0x3f
+#define BCH_DEBUG0_DEBUG_REG_SELECT_OFFSET 0
+
+#define BCH_DBGKESREAD_VALUES_MASK 0xffffffff
+#define BCH_DBGKESREAD_VALUES_OFFSET 0
+
+#define BCH_DBGCSFEREAD_VALUES_MASK 0xffffffff
+#define BCH_DBGCSFEREAD_VALUES_OFFSET 0
+
+#define BCH_DBGSYNDGENREAD_VALUES_MASK 0xffffffff
+#define BCH_DBGSYNDGENREAD_VALUES_OFFSET 0
+
+#define BCH_DBGAHBMREAD_VALUES_MASK 0xffffffff
+#define BCH_DBGAHBMREAD_VALUES_OFFSET 0
+
+#define BCH_BLOCKNAME_NAME_MASK 0xffffffff
+#define BCH_BLOCKNAME_NAME_OFFSET 0
+
+#define BCH_VERSION_MAJOR_MASK (0xff << 24)
+#define BCH_VERSION_MAJOR_OFFSET 24
+#define BCH_VERSION_MINOR_MASK (0xff << 16)
+#define BCH_VERSION_MINOR_OFFSET 16
+#define BCH_VERSION_STEP_MASK 0xffff
+#define BCH_VERSION_STEP_OFFSET 0
+
+#endif /* __MX28_REGS_BCH_H__ */
diff --git a/arch/arm/include/asm/arch-mx28/regs-clkctrl.h b/arch/arm/include/asm/arch-mx28/regs-clkctrl.h
new file mode 100644
index 0000000..93d0397
--- /dev/null
+++ b/arch/arm/include/asm/arch-mx28/regs-clkctrl.h
@@ -0,0 +1,312 @@
+/*
+ * Freescale i.MX28 CLKCTRL Register Definitions
+ *
+ * Copyright (C) 2011 Marek Vasut <marek.vasut@gmail.com>
+ * on behalf of DENX Software Engineering GmbH
+ *
+ * Based on code from LTIB:
+ * Copyright 2008-2010 Freescale Semiconductor, Inc. All Rights Reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
+ *
+ */
+
+#ifndef __MX28_REGS_CLKCTRL_H__
+#define __MX28_REGS_CLKCTRL_H__
+
+#include <asm/arch/regs-common.h>
+
+#ifndef __ASSEMBLY__
+struct mx28_clkctrl_regs {
+ mx28_reg(hw_clkctrl_pll0ctrl0) /* 0x00 */
+ mx28_reg(hw_clkctrl_pll0ctrl1) /* 0x10 */
+ mx28_reg(hw_clkctrl_pll1ctrl0) /* 0x20 */
+ mx28_reg(hw_clkctrl_pll1ctrl1) /* 0x30 */
+ mx28_reg(hw_clkctrl_pll2ctrl0) /* 0x40 */
+ mx28_reg(hw_clkctrl_cpu) /* 0x50 */
+ mx28_reg(hw_clkctrl_hbus) /* 0x60 */
+ mx28_reg(hw_clkctrl_xbus) /* 0x70 */
+ mx28_reg(hw_clkctrl_xtal) /* 0x80 */
+ mx28_reg(hw_clkctrl_ssp0) /* 0x90 */
+ mx28_reg(hw_clkctrl_ssp1) /* 0xa0 */
+ mx28_reg(hw_clkctrl_ssp2) /* 0xb0 */
+ mx28_reg(hw_clkctrl_ssp3) /* 0xc0 */
+ mx28_reg(hw_clkctrl_gpmi) /* 0xd0 */
+ mx28_reg(hw_clkctrl_spdif) /* 0xe0 */
+ mx28_reg(hw_clkctrl_emi) /* 0xf0 */
+ mx28_reg(hw_clkctrl_saif0) /* 0x100 */
+ mx28_reg(hw_clkctrl_saif1) /* 0x110 */
+ mx28_reg(hw_clkctrl_lcdif) /* 0x120 */
+ mx28_reg(hw_clkctrl_etm) /* 0x130 */
+ mx28_reg(hw_clkctrl_enet) /* 0x140 */
+ mx28_reg(hw_clkctrl_hsadc) /* 0x150 */
+ mx28_reg(hw_clkctrl_flexcan) /* 0x160 */
+
+ uint32_t reserved[16];
+
+ mx28_reg(hw_clkctrl_frac0) /* 0x1b0 */
+ mx28_reg(hw_clkctrl_frac1) /* 0x1c0 */
+ mx28_reg(hw_clkctrl_clkseq) /* 0x1d0 */
+ mx28_reg(hw_clkctrl_reset) /* 0x1e0 */
+ mx28_reg(hw_clkctrl_status) /* 0x1f0 */
+ mx28_reg(hw_clkctrl_version) /* 0x200 */
+};
+#endif
+
+#define CLKCTRL_PLL0CTRL0_LFR_SEL_MASK (0x3 << 28)
+#define CLKCTRL_PLL0CTRL0_LFR_SEL_OFFSET 28
+#define CLKCTRL_PLL0CTRL0_LFR_SEL_DEFAULT (0x0 << 28)
+#define CLKCTRL_PLL0CTRL0_LFR_SEL_TIMES_2 (0x1 << 28)
+#define CLKCTRL_PLL0CTRL0_LFR_SEL_TIMES_05 (0x2 << 28)
+#define CLKCTRL_PLL0CTRL0_LFR_SEL_UNDEFINED (0x3 << 28)
+#define CLKCTRL_PLL0CTRL0_CP_SEL_MASK (0x3 << 24)
+#define CLKCTRL_PLL0CTRL0_CP_SEL_OFFSET 24
+#define CLKCTRL_PLL0CTRL0_CP_SEL_DEFAULT (0x0 << 24)
+#define CLKCTRL_PLL0CTRL0_CP_SEL_TIMES_2 (0x1 << 24)
+#define CLKCTRL_PLL0CTRL0_CP_SEL_TIMES_05 (0x2 << 24)
+#define CLKCTRL_PLL0CTRL0_CP_SEL_UNDEFINED (0x3 << 24)
+#define CLKCTRL_PLL0CTRL0_DIV_SEL_MASK (0x3 << 20)
+#define CLKCTRL_PLL0CTRL0_DIV_SEL_OFFSET 20
+#define CLKCTRL_PLL0CTRL0_DIV_SEL_DEFAULT (0x0 << 20)
+#define CLKCTRL_PLL0CTRL0_DIV_SEL_LOWER (0x1 << 20)
+#define CLKCTRL_PLL0CTRL0_DIV_SEL_LOWEST (0x2 << 20)
+#define CLKCTRL_PLL0CTRL0_DIV_SEL_UNDEFINED (0x3 << 20)
+#define CLKCTRL_PLL0CTRL0_EN_USB_CLKS (1 << 18)
+#define CLKCTRL_PLL0CTRL0_POWER (1 << 17)
+
+#define CLKCTRL_PLL0CTRL1_LOCK (1 << 31)
+#define CLKCTRL_PLL0CTRL1_FORCE_LOCK (1 << 30)
+#define CLKCTRL_PLL0CTRL1_LOCK_COUNT_MASK 0xffff
+#define CLKCTRL_PLL0CTRL1_LOCK_COUNT_OFFSET 0
+
+#define CLKCTRL_PLL1CTRL0_CLKGATEEMI (1 << 31)
+#define CLKCTRL_PLL1CTRL0_LFR_SEL_MASK (0x3 << 28)
+#define CLKCTRL_PLL1CTRL0_LFR_SEL_OFFSET 28
+#define CLKCTRL_PLL1CTRL0_LFR_SEL_DEFAULT (0x0 << 28)
+#define CLKCTRL_PLL1CTRL0_LFR_SEL_TIMES_2 (0x1 << 28)
+#define CLKCTRL_PLL1CTRL0_LFR_SEL_TIMES_05 (0x2 << 28)
+#define CLKCTRL_PLL1CTRL0_LFR_SEL_UNDEFINED (0x3 << 28)
+#define CLKCTRL_PLL1CTRL0_CP_SEL_MASK (0x3 << 24)
+#define CLKCTRL_PLL1CTRL0_CP_SEL_OFFSET 24
+#define CLKCTRL_PLL1CTRL0_CP_SEL_DEFAULT (0x0 << 24)
+#define CLKCTRL_PLL1CTRL0_CP_SEL_TIMES_2 (0x1 << 24)
+#define CLKCTRL_PLL1CTRL0_CP_SEL_TIMES_05 (0x2 << 24)
+#define CLKCTRL_PLL1CTRL0_CP_SEL_UNDEFINED (0x3 << 24)
+#define CLKCTRL_PLL1CTRL0_DIV_SEL_MASK (0x3 << 20)
+#define CLKCTRL_PLL1CTRL0_DIV_SEL_OFFSET 20
+#define CLKCTRL_PLL1CTRL0_DIV_SEL_DEFAULT (0x0 << 20)
+#define CLKCTRL_PLL1CTRL0_DIV_SEL_LOWER (0x1 << 20)
+#define CLKCTRL_PLL1CTRL0_DIV_SEL_LOWEST (0x2 << 20)
+#define CLKCTRL_PLL1CTRL0_DIV_SEL_UNDEFINED (0x3 << 20)
+#define CLKCTRL_PLL1CTRL0_EN_USB_CLKS (1 << 18)
+#define CLKCTRL_PLL1CTRL0_POWER (1 << 17)
+
+#define CLKCTRL_PLL1CTRL1_LOCK (1 << 31)
+#define CLKCTRL_PLL1CTRL1_FORCE_LOCK (1 << 30)
+#define CLKCTRL_PLL1CTRL1_LOCK_COUNT_MASK 0xffff
+#define CLKCTRL_PLL1CTRL1_LOCK_COUNT_OFFSET 0
+
+#define CLKCTRL_PLL2CTRL0_CLKGATE (1 << 31)
+#define CLKCTRL_PLL2CTRL0_LFR_SEL_MASK (0x3 << 28)
+#define CLKCTRL_PLL2CTRL0_LFR_SEL_OFFSET 28
+#define CLKCTRL_PLL2CTRL0_HOLD_RING_OFF_B (1 << 26)
+#define CLKCTRL_PLL2CTRL0_CP_SEL_MASK (0x3 << 24)
+#define CLKCTRL_PLL2CTRL0_CP_SEL_OFFSET 24
+#define CLKCTRL_PLL2CTRL0_POWER (1 << 23)
+
+#define CLKCTRL_CPU_BUSY_REF_XTAL (1 << 29)
+#define CLKCTRL_CPU_BUSY_REF_CPU (1 << 28)
+#define CLKCTRL_CPU_DIV_XTAL_FRAC_EN (1 << 26)
+#define CLKCTRL_CPU_DIV_XTAL_MASK (0x3ff << 16)
+#define CLKCTRL_CPU_DIV_XTAL_OFFSET 16
+#define CLKCTRL_CPU_INTERRUPT_WAIT (1 << 12)
+#define CLKCTRL_CPU_DIV_CPU_FRAC_EN (1 << 10)
+#define CLKCTRL_CPU_DIV_CPU_MASK 0x3f
+#define CLKCTRL_CPU_DIV_CPU_OFFSET 0
+
+#define CLKCTRL_HBUS_ASM_BUSY (1 << 31)
+#define CLKCTRL_HBUS_DCP_AS_ENABLE (1 << 30)
+#define CLKCTRL_HBUS_PXP_AS_ENABLE (1 << 29)
+#define CLKCTRL_HBUS_ASM_EMIPORT_AS_ENABLE (1 << 27)
+#define CLKCTRL_HBUS_APBHDMA_AS_ENABLE (1 << 26)
+#define CLKCTRL_HBUS_APBXDMA_AS_ENABLE (1 << 25)
+#define CLKCTRL_HBUS_TRAFFIC_JAM_AS_ENABLE (1 << 24)
+#define CLKCTRL_HBUS_TRAFFIC_AS_ENABLE (1 << 23)
+#define CLKCTRL_HBUS_CPU_DATA_AS_ENABLE (1 << 22)
+#define CLKCTRL_HBUS_CPU_INSTR_AS_ENABLE (1 << 21)
+#define CLKCTRL_HBUS_ASM_ENABLE (1 << 20)
+#define CLKCTRL_HBUS_AUTO_CLEAR_DIV_ENABLE (1 << 19)
+#define CLKCTRL_HBUS_SLOW_DIV_MASK (0x7 << 16)
+#define CLKCTRL_HBUS_SLOW_DIV_OFFSET 16
+#define CLKCTRL_HBUS_SLOW_DIV_BY1 (0x0 << 16)
+#define CLKCTRL_HBUS_SLOW_DIV_BY2 (0x1 << 16)
+#define CLKCTRL_HBUS_SLOW_DIV_BY4 (0x2 << 16)
+#define CLKCTRL_HBUS_SLOW_DIV_BY8 (0x3 << 16)
+#define CLKCTRL_HBUS_SLOW_DIV_BY16 (0x4 << 16)
+#define CLKCTRL_HBUS_SLOW_DIV_BY32 (0x5 << 16)
+#define CLKCTRL_HBUS_DIV_FRAC_EN (1 << 5)
+#define CLKCTRL_HBUS_DIV_MASK 0x1f
+#define CLKCTRL_HBUS_DIV_OFFSET 0
+
+#define CLKCTRL_XBUS_BUSY (1 << 31)
+#define CLKCTRL_XBUS_AUTO_CLEAR_DIV_ENABLE (1 << 11)
+#define CLKCTRL_XBUS_DIV_FRAC_EN (1 << 10)
+#define CLKCTRL_XBUS_DIV_MASK 0x3ff
+#define CLKCTRL_XBUS_DIV_OFFSET 0
+
+#define CLKCTRL_XTAL_UART_CLK_GATE (1 << 31)
+#define CLKCTRL_XTAL_PWM_CLK24M_GATE (1 << 29)
+#define CLKCTRL_XTAL_TIMROT_CLK32K_GATE (1 << 26)
+#define CLKCTRL_XTAL_DIV_UART_MASK 0x3
+#define CLKCTRL_XTAL_DIV_UART_OFFSET 0
+
+#define CLKCTRL_SSP_CLKGATE (1 << 31)
+#define CLKCTRL_SSP_BUSY (1 << 29)
+#define CLKCTRL_SSP_DIV_FRAC_EN (1 << 9)
+#define CLKCTRL_SSP_DIV_MASK 0x1ff
+#define CLKCTRL_SSP_DIV_OFFSET 0
+
+#define CLKCTRL_GPMI_CLKGATE (1 << 31)
+#define CLKCTRL_GPMI_BUSY (1 << 29)
+#define CLKCTRL_GPMI_DIV_FRAC_EN (1 << 10)
+#define CLKCTRL_GPMI_DIV_MASK 0x3ff
+#define CLKCTRL_GPMI_DIV_OFFSET 0
+
+#define CLKCTRL_SPDIF_CLKGATE (1 << 31)
+
+#define CLKCTRL_EMI_CLKGATE (1 << 31)
+#define CLKCTRL_EMI_SYNC_MODE_EN (1 << 30)
+#define CLKCTRL_EMI_BUSY_REF_XTAL (1 << 29)
+#define CLKCTRL_EMI_BUSY_REF_EMI (1 << 28)
+#define CLKCTRL_EMI_BUSY_REF_CPU (1 << 27)
+#define CLKCTRL_EMI_BUSY_SYNC_MODE (1 << 26)
+#define CLKCTRL_EMI_BUSY_DCC_RESYNC (1 << 17)
+#define CLKCTRL_EMI_DCC_RESYNC_ENABLE (1 << 16)
+#define CLKCTRL_EMI_DIV_XTAL_MASK (0xf << 8)
+#define CLKCTRL_EMI_DIV_XTAL_OFFSET 8
+#define CLKCTRL_EMI_DIV_EMI_MASK 0x3f
+#define CLKCTRL_EMI_DIV_EMI_OFFSET 0
+
+#define CLKCTRL_SAIF0_CLKGATE (1 << 31)
+#define CLKCTRL_SAIF0_BUSY (1 << 29)
+#define CLKCTRL_SAIF0_DIV_FRAC_EN (1 << 16)
+#define CLKCTRL_SAIF0_DIV_MASK 0xffff
+#define CLKCTRL_SAIF0_DIV_OFFSET 0
+
+#define CLKCTRL_SAIF1_CLKGATE (1 << 31)
+#define CLKCTRL_SAIF1_BUSY (1 << 29)
+#define CLKCTRL_SAIF1_DIV_FRAC_EN (1 << 16)
+#define CLKCTRL_SAIF1_DIV_MASK 0xffff
+#define CLKCTRL_SAIF1_DIV_OFFSET 0
+
+#define CLKCTRL_DIS_LCDIF_CLKGATE (1 << 31)
+#define CLKCTRL_DIS_LCDIF_BUSY (1 << 29)
+#define CLKCTRL_DIS_LCDIF_DIV_FRAC_EN (1 << 13)
+#define CLKCTRL_DIS_LCDIF_DIV_MASK 0x1fff
+#define CLKCTRL_DIS_LCDIF_DIV_OFFSET 0
+
+#define CLKCTRL_ETM_CLKGATE (1 << 31)
+#define CLKCTRL_ETM_BUSY (1 << 29)
+#define CLKCTRL_ETM_DIV_FRAC_EN (1 << 7)
+#define CLKCTRL_ETM_DIV_MASK 0x7f
+#define CLKCTRL_ETM_DIV_OFFSET 0
+
+#define CLKCTRL_ENET_SLEEP (1 << 31)
+#define CLKCTRL_ENET_DISABLE (1 << 30)
+#define CLKCTRL_ENET_STATUS (1 << 29)
+#define CLKCTRL_ENET_BUSY_TIME (1 << 27)
+#define CLKCTRL_ENET_DIV_TIME_MASK (0x3f << 21)
+#define CLKCTRL_ENET_DIV_TIME_OFFSET 21
+#define CLKCTRL_ENET_TIME_SEL_MASK (0x3 << 19)
+#define CLKCTRL_ENET_TIME_SEL_OFFSET 19
+#define CLKCTRL_ENET_TIME_SEL_XTAL (0x0 << 19)
+#define CLKCTRL_ENET_TIME_SEL_PLL (0x1 << 19)
+#define CLKCTRL_ENET_TIME_SEL_RMII_CLK (0x2 << 19)
+#define CLKCTRL_ENET_TIME_SEL_UNDEFINED (0x3 << 19)
+#define CLKCTRL_ENET_CLK_OUT_EN (1 << 18)
+#define CLKCTRL_ENET_RESET_BY_SW_CHIP (1 << 17)
+#define CLKCTRL_ENET_RESET_BY_SW (1 << 16)
+
+#define CLKCTRL_HSADC_RESETB (1 << 30)
+#define CLKCTRL_HSADC_FREQDIV_MASK (0x3 << 28)
+#define CLKCTRL_HSADC_FREQDIV_OFFSET 28
+
+#define CLKCTRL_FLEXCAN_STOP_CAN0 (1 << 30)
+#define CLKCTRL_FLEXCAN_CAN0_STATUS (1 << 29)
+#define CLKCTRL_FLEXCAN_STOP_CAN1 (1 << 28)
+#define CLKCTRL_FLEXCAN_CAN1_STATUS (1 << 27)
+
+#define CLKCTRL_FRAC0_CLKGATEIO0 (1 << 31)
+#define CLKCTRL_FRAC0_IO0_STABLE (1 << 30)
+#define CLKCTRL_FRAC0_IO0FRAC_MASK (0x3f << 24)
+#define CLKCTRL_FRAC0_IO0FRAC_OFFSET 24
+#define CLKCTRL_FRAC0_CLKGATEIO1 (1 << 23)
+#define CLKCTRL_FRAC0_IO1_STABLE (1 << 22)
+#define CLKCTRL_FRAC0_IO1FRAC_MASK (0x3f << 16)
+#define CLKCTRL_FRAC0_IO1FRAC_OFFSET 16
+#define CLKCTRL_FRAC0_CLKGATEEMI (1 << 15)
+#define CLKCTRL_FRAC0_EMI_STABLE (1 << 14)
+#define CLKCTRL_FRAC0_EMIFRAC_MASK (0x3f << 8)
+#define CLKCTRL_FRAC0_EMIFRAC_OFFSET 8
+#define CLKCTRL_FRAC0_CLKGATECPU (1 << 7)
+#define CLKCTRL_FRAC0_CPU_STABLE (1 << 6)
+#define CLKCTRL_FRAC0_CPUFRAC_MASK 0x3f
+#define CLKCTRL_FRAC0_CPUFRAC_OFFSET 0
+
+#define CLKCTRL_FRAC1_CLKGATEGPMI (1 << 23)
+#define CLKCTRL_FRAC1_GPMI_STABLE (1 << 22)
+#define CLKCTRL_FRAC1_GPMIFRAC_MASK (0x3f << 16)
+#define CLKCTRL_FRAC1_GPMIFRAC_OFFSET 16
+#define CLKCTRL_FRAC1_CLKGATEHSADC (1 << 15)
+#define CLKCTRL_FRAC1_HSADC_STABLE (1 << 14)
+#define CLKCTRL_FRAC1_HSADCFRAC_MASK (0x3f << 8)
+#define CLKCTRL_FRAC1_HSADCFRAC_OFFSET 8
+#define CLKCTRL_FRAC1_CLKGATEPIX (1 << 7)
+#define CLKCTRL_FRAC1_PIX_STABLE (1 << 6)
+#define CLKCTRL_FRAC1_PIXFRAC_MASK 0x3f
+#define CLKCTRL_FRAC1_PIXFRAC_OFFSET 0
+
+#define CLKCTRL_CLKSEQ_BYPASS_CPU (1 << 18)
+#define CLKCTRL_CLKSEQ_BYPASS_DIS_LCDIF (1 << 14)
+#define CLKCTRL_CLKSEQ_BYPASS_DIS_LCDIF_BYPASS (0x1 << 14)
+#define CLKCTRL_CLKSEQ_BYPASS_DIS_LCDIF_PFD (0x0 << 14)
+#define CLKCTRL_CLKSEQ_BYPASS_ETM (1 << 8)
+#define CLKCTRL_CLKSEQ_BYPASS_EMI (1 << 7)
+#define CLKCTRL_CLKSEQ_BYPASS_SSP3 (1 << 6)
+#define CLKCTRL_CLKSEQ_BYPASS_SSP2 (1 << 5)
+#define CLKCTRL_CLKSEQ_BYPASS_SSP1 (1 << 4)
+#define CLKCTRL_CLKSEQ_BYPASS_SSP0 (1 << 3)
+#define CLKCTRL_CLKSEQ_BYPASS_GPMI (1 << 2)
+#define CLKCTRL_CLKSEQ_BYPASS_SAIF1 (1 << 1)
+#define CLKCTRL_CLKSEQ_BYPASS_SAIF0 (1 << 0)
+
+#define CLKCTRL_RESET_WDOG_POR_DISABLE (1 << 5)
+#define CLKCTRL_RESET_EXTERNAL_RESET_ENABLE (1 << 4)
+#define CLKCTRL_RESET_THERMAL_RESET_ENABLE (1 << 3)
+#define CLKCTRL_RESET_THERMAL_RESET_DEFAULT (1 << 2)
+#define CLKCTRL_RESET_CHIP (1 << 1)
+#define CLKCTRL_RESET_DIG (1 << 0)
+
+#define CLKCTRL_STATUS_CPU_LIMIT_MASK (0x3 << 30)
+#define CLKCTRL_STATUS_CPU_LIMIT_OFFSET 30
+
+#define CLKCTRL_VERSION_MAJOR_MASK (0xff << 24)
+#define CLKCTRL_VERSION_MAJOR_OFFSET 24
+#define CLKCTRL_VERSION_MINOR_MASK (0xff << 16)
+#define CLKCTRL_VERSION_MINOR_OFFSET 16
+#define CLKCTRL_VERSION_STEP_MASK 0xffff
+#define CLKCTRL_VERSION_STEP_OFFSET 0
+
+#endif /* __MX28_REGS_CLKCTRL_H__ */
diff --git a/arch/arm/include/asm/arch-mx28/regs-common.h b/arch/arm/include/asm/arch-mx28/regs-common.h
new file mode 100644
index 0000000..efe975b
--- /dev/null
+++ b/arch/arm/include/asm/arch-mx28/regs-common.h
@@ -0,0 +1,66 @@
+/*
+ * Freescale i.MX28 Register Accessors
+ *
+ * Copyright (C) 2011 Marek Vasut <marek.vasut@gmail.com>
+ * on behalf of DENX Software Engineering GmbH
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
+ *
+ */
+
+#ifndef __MX28_REGS_COMMON_H__
+#define __MX28_REGS_COMMON_H__
+
+/*
+ * The i.MX28 has interesting feature when it comes to register access. There
+ * are four kinds of access to one particular register. Those are:
+ *
+ * 1) Common read/write access. To use this mode, just write to the address of
+ * the register.
+ * 2) Set bits only access. To set bits, write which bits you want to set to the
+ * address of the register + 0x4.
+ * 3) Clear bits only access. To clear bits, write which bits you want to clear
+ * to the address of the register + 0x8.
+ * 4) Toggle bits only access. To toggle bits, write which bits you want to
+ * toggle to the address of the register + 0xc.
+ *
+ * IMPORTANT NOTE: Not all registers support accesses 2-4! Also, not all bits
+ * can be set/cleared by pure write as in access type 1, some need to be
+ * explicitly set/cleared by using access type 2-3.
+ *
+ * The following macros and structures allow the user to either access the
+ * register in all aforementioned modes (by accessing reg_name, reg_name_set,
+ * reg_name_clr, reg_name_tog) or pass the register structure further into
+ * various functions with correct type information (by accessing reg_name_reg).
+ *
+ */
+
+#define __mx28_reg(name) \
+ uint32_t name; \
+ uint32_t name##_set; \
+ uint32_t name##_clr; \
+ uint32_t name##_tog;
+
+struct mx28_register {
+ __mx28_reg(reg)
+};
+
+#define mx28_reg(name) \
+ union { \
+ struct { __mx28_reg(name) }; \
+ struct mx28_register name##_reg; \
+ };
+
+#endif /* __MX28_REGS_COMMON_H__ */
diff --git a/arch/arm/include/asm/arch-mx28/regs-gpmi.h b/arch/arm/include/asm/arch-mx28/regs-gpmi.h
new file mode 100644
index 0000000..0096793
--- /dev/null
+++ b/arch/arm/include/asm/arch-mx28/regs-gpmi.h
@@ -0,0 +1,222 @@
+/*
+ * Freescale i.MX28 GPMI Register Definitions
+ *
+ * Copyright (C) 2011 Marek Vasut <marek.vasut@gmail.com>
+ * on behalf of DENX Software Engineering GmbH
+ *
+ * Based on code from LTIB:
+ * Copyright 2008-2010 Freescale Semiconductor, Inc. All Rights Reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
+ *
+ */
+
+#ifndef __MX28_REGS_GPMI_H__
+#define __MX28_REGS_GPMI_H__
+
+#include <asm/arch/regs-common.h>
+
+#ifndef __ASSEMBLY__
+struct mx28_gpmi_regs {
+ mx28_reg(hw_gpmi_ctrl0)
+ mx28_reg(hw_gpmi_compare)
+ mx28_reg(hw_gpmi_eccctrl)
+ mx28_reg(hw_gpmi_ecccount)
+ mx28_reg(hw_gpmi_payload)
+ mx28_reg(hw_gpmi_auxiliary)
+ mx28_reg(hw_gpmi_ctrl1)
+ mx28_reg(hw_gpmi_timing0)
+ mx28_reg(hw_gpmi_timing1)
+
+ uint32_t reserved[4];
+
+ mx28_reg(hw_gpmi_data)
+ mx28_reg(hw_gpmi_stat)
+ mx28_reg(hw_gpmi_debug)
+ mx28_reg(hw_gpmi_version)
+};
+#endif
+
+#define GPMI_CTRL0_SFTRST (1 << 31)
+#define GPMI_CTRL0_CLKGATE (1 << 30)
+#define GPMI_CTRL0_RUN (1 << 29)
+#define GPMI_CTRL0_DEV_IRQ_EN (1 << 28)
+#define GPMI_CTRL0_LOCK_CS (1 << 27)
+#define GPMI_CTRL0_UDMA (1 << 26)
+#define GPMI_CTRL0_COMMAND_MODE_MASK (0x3 << 24)
+#define GPMI_CTRL0_COMMAND_MODE_OFFSET 24
+#define GPMI_CTRL0_COMMAND_MODE_WRITE (0x0 << 24)
+#define GPMI_CTRL0_COMMAND_MODE_READ (0x1 << 24)
+#define GPMI_CTRL0_COMMAND_MODE_READ_AND_COMPARE (0x2 << 24)
+#define GPMI_CTRL0_COMMAND_MODE_WAIT_FOR_READY (0x3 << 24)
+#define GPMI_CTRL0_WORD_LENGTH (1 << 23)
+#define GPMI_CTRL0_CS_MASK (0x7 << 20)
+#define GPMI_CTRL0_CS_OFFSET 20
+#define GPMI_CTRL0_ADDRESS_MASK (0x7 << 17)
+#define GPMI_CTRL0_ADDRESS_OFFSET 17
+#define GPMI_CTRL0_ADDRESS_NAND_DATA (0x0 << 17)
+#define GPMI_CTRL0_ADDRESS_NAND_CLE (0x1 << 17)
+#define GPMI_CTRL0_ADDRESS_NAND_ALE (0x2 << 17)
+#define GPMI_CTRL0_ADDRESS_INCREMENT (1 << 16)
+#define GPMI_CTRL0_XFER_COUNT_MASK 0xffff
+#define GPMI_CTRL0_XFER_COUNT_OFFSET 0
+
+#define GPMI_COMPARE_MASK_MASK (0xffff << 16)
+#define GPMI_COMPARE_MASK_OFFSET 16
+#define GPMI_COMPARE_REFERENCE_MASK 0xffff
+#define GPMI_COMPARE_REFERENCE_OFFSET 0
+
+#define GPMI_ECCCTRL_HANDLE_MASK (0xffff << 16)
+#define GPMI_ECCCTRL_HANDLE_OFFSET 16
+#define GPMI_ECCCTRL_ECC_CMD_MASK (0x3 << 13)
+#define GPMI_ECCCTRL_ECC_CMD_OFFSET 13
+#define GPMI_ECCCTRL_ECC_CMD_DECODE (0x0 << 13)
+#define GPMI_ECCCTRL_ECC_CMD_ENCODE (0x1 << 13)
+#define GPMI_ECCCTRL_ENABLE_ECC (1 << 12)
+#define GPMI_ECCCTRL_BUFFER_MASK_MASK 0x1ff
+#define GPMI_ECCCTRL_BUFFER_MASK_OFFSET 0
+#define GPMI_ECCCTRL_BUFFER_MASK_BCH_AUXONLY 0x100
+#define GPMI_ECCCTRL_BUFFER_MASK_BCH_PAGE 0x1ff
+
+#define GPMI_ECCCOUNT_COUNT_MASK 0xffff
+#define GPMI_ECCCOUNT_COUNT_OFFSET 0
+
+#define GPMI_PAYLOAD_ADDRESS_MASK (0x3fffffff << 2)
+#define GPMI_PAYLOAD_ADDRESS_OFFSET 2
+
+#define GPMI_AUXILIARY_ADDRESS_MASK (0x3fffffff << 2)
+#define GPMI_AUXILIARY_ADDRESS_OFFSET 2
+
+#define GPMI_CTRL1_DECOUPLE_CS (1 << 24)
+#define GPMI_CTRL1_WRN_DLY_SEL_MASK (0x3 << 22)
+#define GPMI_CTRL1_WRN_DLY_SEL_OFFSET 22
+#define GPMI_CTRL1_TIMEOUT_IRQ_EN (1 << 20)
+#define GPMI_CTRL1_GANGED_RDYBUSY (1 << 19)
+#define GPMI_CTRL1_BCH_MODE (1 << 18)
+#define GPMI_CTRL1_DLL_ENABLE (1 << 17)
+#define GPMI_CTRL1_HALF_PERIOD (1 << 16)
+#define GPMI_CTRL1_RDN_DELAY_MASK (0xf << 12)
+#define GPMI_CTRL1_RDN_DELAY_OFFSET 12
+#define GPMI_CTRL1_DMA2ECC_MODE (1 << 11)
+#define GPMI_CTRL1_DEV_IRQ (1 << 10)
+#define GPMI_CTRL1_TIMEOUT_IRQ (1 << 9)
+#define GPMI_CTRL1_BURST_EN (1 << 8)
+#define GPMI_CTRL1_ABORT_WAIT_REQUEST (1 << 7)
+#define GPMI_CTRL1_ABORT_WAIT_FOR_READY_CHANNEL_MASK (0x7 << 4)
+#define GPMI_CTRL1_ABORT_WAIT_FOR_READY_CHANNEL_OFFSET 4
+#define GPMI_CTRL1_DEV_RESET (1 << 3)
+#define GPMI_CTRL1_ATA_IRQRDY_POLARITY (1 << 2)
+#define GPMI_CTRL1_CAMERA_MODE (1 << 1)
+#define GPMI_CTRL1_GPMI_MODE (1 << 0)
+
+#define GPMI_TIMING0_ADDRESS_SETUP_MASK (0xff << 16)
+#define GPMI_TIMING0_ADDRESS_SETUP_OFFSET 16
+#define GPMI_TIMING0_DATA_HOLD_MASK (0xff << 8)
+#define GPMI_TIMING0_DATA_HOLD_OFFSET 8
+#define GPMI_TIMING0_DATA_SETUP_MASK 0xff
+#define GPMI_TIMING0_DATA_SETUP_OFFSET 0
+
+#define GPMI_TIMING1_DEVICE_BUSY_TIMEOUT_MASK (0xffff << 16)
+#define GPMI_TIMING1_DEVICE_BUSY_TIMEOUT_OFFSET 16
+
+#define GPMI_TIMING2_UDMA_TRP_MASK (0xff << 24)
+#define GPMI_TIMING2_UDMA_TRP_OFFSET 24
+#define GPMI_TIMING2_UDMA_ENV_MASK (0xff << 16)
+#define GPMI_TIMING2_UDMA_ENV_OFFSET 16
+#define GPMI_TIMING2_UDMA_HOLD_MASK (0xff << 8)
+#define GPMI_TIMING2_UDMA_HOLD_OFFSET 8
+#define GPMI_TIMING2_UDMA_SETUP_MASK 0xff
+#define GPMI_TIMING2_UDMA_SETUP_OFFSET 0
+
+#define GPMI_DATA_DATA_MASK 0xffffffff
+#define GPMI_DATA_DATA_OFFSET 0
+
+#define GPMI_STAT_READY_BUSY_MASK (0xff << 24)
+#define GPMI_STAT_READY_BUSY_OFFSET 24
+#define GPMI_STAT_RDY_TIMEOUT_MASK (0xff << 16)
+#define GPMI_STAT_RDY_TIMEOUT_OFFSET 16
+#define GPMI_STAT_DEV7_ERROR (1 << 15)
+#define GPMI_STAT_DEV6_ERROR (1 << 14)
+#define GPMI_STAT_DEV5_ERROR (1 << 13)
+#define GPMI_STAT_DEV4_ERROR (1 << 12)
+#define GPMI_STAT_DEV3_ERROR (1 << 11)
+#define GPMI_STAT_DEV2_ERROR (1 << 10)
+#define GPMI_STAT_DEV1_ERROR (1 << 9)
+#define GPMI_STAT_DEV0_ERROR (1 << 8)
+#define GPMI_STAT_ATA_IRQ (1 << 4)
+#define GPMI_STAT_INVALID_BUFFER_MASK (1 << 3)
+#define GPMI_STAT_FIFO_EMPTY (1 << 2)
+#define GPMI_STAT_FIFO_FULL (1 << 1)
+#define GPMI_STAT_PRESENT (1 << 0)
+
+#define GPMI_DEBUG_WAIT_FOR_READY_END_MASK (0xff << 24)
+#define GPMI_DEBUG_WAIT_FOR_READY_END_OFFSET 24
+#define GPMI_DEBUG_DMA_SENSE_MASK (0xff << 16)
+#define GPMI_DEBUG_DMA_SENSE_OFFSET 16
+#define GPMI_DEBUG_DMAREQ_MASK (0xff << 8)
+#define GPMI_DEBUG_DMAREQ_OFFSET 8
+#define GPMI_DEBUG_CMD_END_MASK 0xff
+#define GPMI_DEBUG_CMD_END_OFFSET 0
+
+#define GPMI_VERSION_MAJOR_MASK (0xff << 24)
+#define GPMI_VERSION_MAJOR_OFFSET 24
+#define GPMI_VERSION_MINOR_MASK (0xff << 16)
+#define GPMI_VERSION_MINOR_OFFSET 16
+#define GPMI_VERSION_STEP_MASK 0xffff
+#define GPMI_VERSION_STEP_OFFSET 0
+
+#define GPMI_DEBUG2_UDMA_STATE_MASK (0xf << 24)
+#define GPMI_DEBUG2_UDMA_STATE_OFFSET 24
+#define GPMI_DEBUG2_BUSY (1 << 23)
+#define GPMI_DEBUG2_PIN_STATE_MASK (0x7 << 20)
+#define GPMI_DEBUG2_PIN_STATE_OFFSET 20
+#define GPMI_DEBUG2_PIN_STATE_PSM_IDLE (0x0 << 20)
+#define GPMI_DEBUG2_PIN_STATE_PSM_BYTCNT (0x1 << 20)
+#define GPMI_DEBUG2_PIN_STATE_PSM_ADDR (0x2 << 20)
+#define GPMI_DEBUG2_PIN_STATE_PSM_STALL (0x3 << 20)
+#define GPMI_DEBUG2_PIN_STATE_PSM_STROBE (0x4 << 20)
+#define GPMI_DEBUG2_PIN_STATE_PSM_ATARDY (0x5 << 20)
+#define GPMI_DEBUG2_PIN_STATE_PSM_DHOLD (0x6 << 20)
+#define GPMI_DEBUG2_PIN_STATE_PSM_DONE (0x7 << 20)
+#define GPMI_DEBUG2_MAIN_STATE_MASK (0xf << 16)
+#define GPMI_DEBUG2_MAIN_STATE_OFFSET 16
+#define GPMI_DEBUG2_MAIN_STATE_MSM_IDLE (0x0 << 16)
+#define GPMI_DEBUG2_MAIN_STATE_MSM_BYTCNT (0x1 << 16)
+#define GPMI_DEBUG2_MAIN_STATE_MSM_WAITFE (0x2 << 16)
+#define GPMI_DEBUG2_MAIN_STATE_MSM_WAITFR (0x3 << 16)
+#define GPMI_DEBUG2_MAIN_STATE_MSM_DMAREQ (0x4 << 16)
+#define GPMI_DEBUG2_MAIN_STATE_MSM_DMAACK (0x5 << 16)
+#define GPMI_DEBUG2_MAIN_STATE_MSM_WAITFF (0x6 << 16)
+#define GPMI_DEBUG2_MAIN_STATE_MSM_LDFIFO (0x7 << 16)
+#define GPMI_DEBUG2_MAIN_STATE_MSM_LDDMAR (0x8 << 16)
+#define GPMI_DEBUG2_MAIN_STATE_MSM_RDCMP (0x9 << 16)
+#define GPMI_DEBUG2_MAIN_STATE_MSM_DONE (0xa << 16)
+#define GPMI_DEBUG2_SYND2GPMI_BE_MASK (0xf << 12)
+#define GPMI_DEBUG2_SYND2GPMI_BE_OFFSET 12
+#define GPMI_DEBUG2_GPMI2SYND_VALID (1 << 11)
+#define GPMI_DEBUG2_GPMI2SYND_READY (1 << 10)
+#define GPMI_DEBUG2_SYND2GPMI_VALID (1 << 9)
+#define GPMI_DEBUG2_SYND2GPMI_READY (1 << 8)
+#define GPMI_DEBUG2_VIEW_DELAYED_RDN (1 << 7)
+#define GPMI_DEBUG2_UPDATE_WINDOW (1 << 6)
+#define GPMI_DEBUG2_RDN_TAP_MASK 0x3f
+#define GPMI_DEBUG2_RDN_TAP_OFFSET 0
+
+#define GPMI_DEBUG3_APB_WORD_CNTR_MASK (0xffff << 16)
+#define GPMI_DEBUG3_APB_WORD_CNTR_OFFSET 16
+#define GPMI_DEBUG3_DEV_WORD_CNTR_MASK 0xffff
+#define GPMI_DEBUG3_DEV_WORD_CNTR_OFFSET 0
+
+#endif /* __MX28_REGS_GPMI_H__ */
diff --git a/arch/arm/include/asm/arch-mx28/regs-i2c.h b/arch/arm/include/asm/arch-mx28/regs-i2c.h
new file mode 100644
index 0000000..30e0ed7
--- /dev/null
+++ b/arch/arm/include/asm/arch-mx28/regs-i2c.h
@@ -0,0 +1,207 @@
+/*
+ * Freescale i.MX28 I2C Register Definitions
+ *
+ * Copyright (C) 2011 Marek Vasut <marek.vasut@gmail.com>
+ * on behalf of DENX Software Engineering GmbH
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
+ *
+ */
+
+#ifndef __MX28_REGS_I2C_H__
+#define __MX28_REGS_I2C_H__
+
+#include <asm/arch/regs-common.h>
+
+#ifndef __ASSEMBLY__
+struct mx28_i2c_regs {
+ mx28_reg(hw_i2c_ctrl0)
+ mx28_reg(hw_i2c_timing0)
+ mx28_reg(hw_i2c_timing1)
+ mx28_reg(hw_i2c_timing2)
+ mx28_reg(hw_i2c_ctrl1)
+ mx28_reg(hw_i2c_stat)
+ mx28_reg(hw_i2c_queuectrl)
+ mx28_reg(hw_i2c_queuestat)
+ mx28_reg(hw_i2c_queuecmd)
+ mx28_reg(hw_i2c_queuedata)
+ mx28_reg(hw_i2c_data)
+ mx28_reg(hw_i2c_debug0)
+ mx28_reg(hw_i2c_debug1)
+ mx28_reg(hw_i2c_version)
+};
+#endif
+
+#define I2C_CTRL_SFTRST (1 << 31)
+#define I2C_CTRL_CLKGATE (1 << 30)
+#define I2C_CTRL_RUN (1 << 29)
+#define I2C_CTRL_PREACK (1 << 27)
+#define I2C_CTRL_ACKNOWLEDGE (1 << 26)
+#define I2C_CTRL_SEND_NAK_ON_LAST (1 << 25)
+#define I2C_CTRL_MULTI_MASTER (1 << 23)
+#define I2C_CTRL_CLOCK_HELD (1 << 22)
+#define I2C_CTRL_RETAIN_CLOCK (1 << 21)
+#define I2C_CTRL_POST_SEND_STOP (1 << 20)
+#define I2C_CTRL_PRE_SEND_START (1 << 19)
+#define I2C_CTRL_SLAVE_ADDRESS_ENABLE (1 << 18)
+#define I2C_CTRL_MASTER_MODE (1 << 17)
+#define I2C_CTRL_DIRECTION (1 << 16)
+#define I2C_CTRL_XFER_COUNT_MASK 0xffff
+#define I2C_CTRL_XFER_COUNT_OFFSET 0
+
+#define I2C_TIMING0_HIGH_COUNT_MASK (0x3ff << 16)
+#define I2C_TIMING0_HIGH_COUNT_OFFSET 16
+#define I2C_TIMING0_RCV_COUNT_MASK 0x3ff
+#define I2C_TIMING0_RCV_COUNT_OFFSET 0
+
+#define I2C_TIMING1_LOW_COUNT_MASK (0x3ff << 16)
+#define I2C_TIMING1_LOW_COUNT_OFFSET 16
+#define I2C_TIMING1_XMIT_COUNT_MASK 0x3ff
+#define I2C_TIMING1_XMIT_COUNT_OFFSET 0
+
+#define I2C_TIMING2_BUS_FREE_MASK (0x3ff << 16)
+#define I2C_TIMING2_BUS_FREE_OFFSET 16
+#define I2C_TIMING2_LEADIN_COUNT_MASK 0x3ff
+#define I2C_TIMING2_LEADIN_COUNT_OFFSET 0
+
+#define I2C_CTRL1_RD_QUEUE_IRQ (1 << 30)
+#define I2C_CTRL1_WR_QUEUE_IRQ (1 << 29)
+#define I2C_CTRL1_CLR_GOT_A_NAK (1 << 28)
+#define I2C_CTRL1_ACK_MODE (1 << 27)
+#define I2C_CTRL1_FORCE_DATA_IDLE (1 << 26)
+#define I2C_CTRL1_FORCE_CLK_IDLE (1 << 25)
+#define I2C_CTRL1_BCAST_SLAVE_EN (1 << 24)
+#define I2C_CTRL1_SLAVE_ADDRESS_BYTE_MASK (0xff << 16)
+#define I2C_CTRL1_SLAVE_ADDRESS_BYTE_OFFSET 16
+#define I2C_CTRL1_BUS_FREE_IRQ_EN (1 << 15)
+#define I2C_CTRL1_DATA_ENGINE_CMPLT_IRQ_EN (1 << 14)
+#define I2C_CTRL1_NO_SLAVE_ACK_IRQ_EN (1 << 13)
+#define I2C_CTRL1_OVERSIZE_XFER_TERM_IRQ_EN (1 << 12)
+#define I2C_CTRL1_EARLY_TERM_IRQ_EN (1 << 11)
+#define I2C_CTRL1_MASTER_LOSS_IRQ_EN (1 << 10)
+#define I2C_CTRL1_SLAVE_STOP_IRQ_EN (1 << 9)
+#define I2C_CTRL1_SLAVE_IRQ_EN (1 << 8)
+#define I2C_CTRL1_BUS_FREE_IRQ (1 << 7)
+#define I2C_CTRL1_DATA_ENGINE_CMPLT_IRQ (1 << 6)
+#define I2C_CTRL1_NO_SLAVE_ACK_IRQ (1 << 5)
+#define I2C_CTRL1_OVERSIZE_XFER_TERM_IRQ (1 << 4)
+#define I2C_CTRL1_EARLY_TERM_IRQ (1 << 3)
+#define I2C_CTRL1_MASTER_LOSS_IRQ (1 << 2)
+#define I2C_CTRL1_SLAVE_STOP_IRQ (1 << 1)
+#define I2C_CTRL1_SLAVE_IRQ (1 << 0)
+
+#define I2C_STAT_MASTER_PRESENT (1 << 31)
+#define I2C_STAT_SLAVE_PRESENT (1 << 30)
+#define I2C_STAT_ANY_ENABLED_IRQ (1 << 29)
+#define I2C_STAT_GOT_A_NAK (1 << 28)
+#define I2C_STAT_RCVD_SLAVE_ADDR_MASK (0xff << 16)
+#define I2C_STAT_RCVD_SLAVE_ADDR_OFFSET 16
+#define I2C_STAT_SLAVE_ADDR_EQ_ZERO (1 << 15)
+#define I2C_STAT_SLAVE_FOUND (1 << 14)
+#define I2C_STAT_SLAVE_SEARCHING (1 << 13)
+#define I2C_STAT_DATA_ENGING_DMA_WAIT (1 << 12)
+#define I2C_STAT_BUS_BUSY (1 << 11)
+#define I2C_STAT_CLK_GEN_BUSY (1 << 10)
+#define I2C_STAT_DATA_ENGINE_BUSY (1 << 9)
+#define I2C_STAT_SLAVE_BUSY (1 << 8)
+#define I2C_STAT_BUS_FREE_IRQ_SUMMARY (1 << 7)
+#define I2C_STAT_DATA_ENGINE_CMPLT_IRQ_SUMMARY (1 << 6)
+#define I2C_STAT_NO_SLAVE_ACK_IRQ_SUMMARY (1 << 5)
+#define I2C_STAT_OVERSIZE_XFER_TERM_IRQ_SUMMARY (1 << 4)
+#define I2C_STAT_EARLY_TERM_IRQ_SUMMARY (1 << 3)
+#define I2C_STAT_MASTER_LOSS_IRQ_SUMMARY (1 << 2)
+#define I2C_STAT_SLAVE_STOP_IRQ_SUMMARY (1 << 1)
+#define I2C_STAT_SLAVE_IRQ_SUMMARY (1 << 0)
+
+#define I2C_QUEUECTRL_RD_THRESH_MASK (0x1f << 16)
+#define I2C_QUEUECTRL_RD_THRESH_OFFSET 16
+#define I2C_QUEUECTRL_WR_THRESH_MASK (0x1f << 8)
+#define I2C_QUEUECTRL_WR_THRESH_OFFSET 8
+#define I2C_QUEUECTRL_QUEUE_RUN (1 << 5)
+#define I2C_QUEUECTRL_RD_CLEAR (1 << 4)
+#define I2C_QUEUECTRL_WR_CLEAR (1 << 3)
+#define I2C_QUEUECTRL_PIO_QUEUE_MODE (1 << 2)
+#define I2C_QUEUECTRL_RD_QUEUE_IRQ_EN (1 << 1)
+#define I2C_QUEUECTRL_WR_QUEUE_IRQ_EN (1 << 0)
+
+#define I2C_QUEUESTAT_RD_QUEUE_FULL (1 << 14)
+#define I2C_QUEUESTAT_RD_QUEUE_EMPTY (1 << 13)
+#define I2C_QUEUESTAT_RD_QUEUE_CNT_MASK (0x1f << 8)
+#define I2C_QUEUESTAT_RD_QUEUE_CNT_OFFSET 8
+#define I2C_QUEUESTAT_WR_QUEUE_FULL (1 << 6)
+#define I2C_QUEUESTAT_WR_QUEUE_EMPTY (1 << 5)
+#define I2C_QUEUESTAT_WR_QUEUE_CNT_MASK 0x1f
+#define I2C_QUEUESTAT_WR_QUEUE_CNT_OFFSET 0
+
+#define I2C_QUEUECMD_PREACK (1 << 27)
+#define I2C_QUEUECMD_ACKNOWLEDGE (1 << 26)
+#define I2C_QUEUECMD_SEND_NAK_ON_LAST (1 << 25)
+#define I2C_QUEUECMD_MULTI_MASTER (1 << 23)
+#define I2C_QUEUECMD_CLOCK_HELD (1 << 22)
+#define I2C_QUEUECMD_RETAIN_CLOCK (1 << 21)
+#define I2C_QUEUECMD_POST_SEND_STOP (1 << 20)
+#define I2C_QUEUECMD_PRE_SEND_START (1 << 19)
+#define I2C_QUEUECMD_SLAVE_ADDRESS_ENABLE (1 << 18)
+#define I2C_QUEUECMD_MASTER_MODE (1 << 17)
+#define I2C_QUEUECMD_DIRECTION (1 << 16)
+#define I2C_QUEUECMD_XFER_COUNT_MASK 0xffff
+#define I2C_QUEUECMD_XFER_COUNT_OFFSET 0
+
+#define I2C_QUEUEDATA_DATA_MASK 0xffffffff
+#define I2C_QUEUEDATA_DATA_OFFSET 0
+
+#define I2C_DATA_DATA_MASK 0xffffffff
+#define I2C_DATA_DATA_OFFSET 0
+
+#define I2C_DEBUG0_DMAREQ (1 << 31)
+#define I2C_DEBUG0_DMAENDCMD (1 << 30)
+#define I2C_DEBUG0_DMAKICK (1 << 29)
+#define I2C_DEBUG0_DMATERMINATE (1 << 28)
+#define I2C_DEBUG0_STATE_VALUE_MASK (0x3 << 26)
+#define I2C_DEBUG0_STATE_VALUE_OFFSET 26
+#define I2C_DEBUG0_DMA_STATE_MASK (0x3ff << 16)
+#define I2C_DEBUG0_DMA_STATE_OFFSET 16
+#define I2C_DEBUG0_START_TOGGLE (1 << 15)
+#define I2C_DEBUG0_STOP_TOGGLE (1 << 14)
+#define I2C_DEBUG0_GRAB_TOGGLE (1 << 13)
+#define I2C_DEBUG0_CHANGE_TOGGLE (1 << 12)
+#define I2C_DEBUG0_STATE_LATCH (1 << 11)
+#define I2C_DEBUG0_SLAVE_HOLD_CLK (1 << 10)
+#define I2C_DEBUG0_STATE_STATE_MASK 0x3ff
+#define I2C_DEBUG0_STATE_STATE_OFFSET 0
+
+#define I2C_DEBUG1_I2C_CLK_IN (1 << 31)
+#define I2C_DEBUG1_I2C_DATA_IN (1 << 30)
+#define I2C_DEBUG1_DMA_BYTE_ENABLES_MASK (0xf << 24)
+#define I2C_DEBUG1_DMA_BYTE_ENABLES_OFFSET 24
+#define I2C_DEBUG1_CLK_GEN_STATE_MASK (0xff << 16)
+#define I2C_DEBUG1_CLK_GEN_STATE_OFFSET 16
+#define I2C_DEBUG1_LST_MODE_MASK (0x3 << 9)
+#define I2C_DEBUG1_LST_MODE_OFFSET 9
+#define I2C_DEBUG1_LOCAL_SLAVE_TEST (1 << 8)
+#define I2C_DEBUG1_FORCE_CLK_ON (1 << 4)
+#define I2C_DEBUG1_FORCE_ABR_LOSS (1 << 3)
+#define I2C_DEBUG1_FORCE_RCV_ACK (1 << 2)
+#define I2C_DEBUG1_FORCE_I2C_DATA_OE (1 << 1)
+#define I2C_DEBUG1_FORCE_I2C_CLK_OE (1 << 0)
+
+#define I2C_VERSION_MAJOR_MASK (0xff << 24)
+#define I2C_VERSION_MAJOR_OFFSET 24
+#define I2C_VERSION_MINOR_MASK (0xff << 16)
+#define I2C_VERSION_MINOR_OFFSET 16
+#define I2C_VERSION_STEP_MASK 0xffff
+#define I2C_VERSION_STEP_OFFSET 0
+
+#endif /* __MX28_REGS_I2C_H__ */
diff --git a/arch/arm/include/asm/arch-mx28/regs-ocotp.h b/arch/arm/include/asm/arch-mx28/regs-ocotp.h
new file mode 100644
index 0000000..ea2fd7b
--- /dev/null
+++ b/arch/arm/include/asm/arch-mx28/regs-ocotp.h
@@ -0,0 +1,173 @@
+/*
+ * Freescale i.MX28 OCOTP Register Definitions
+ *
+ * Copyright (C) 2011 Marek Vasut <marek.vasut@gmail.com>
+ * on behalf of DENX Software Engineering GmbH
+ *
+ * Based on code from LTIB:
+ * Copyright 2008-2010 Freescale Semiconductor, Inc. All Rights Reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
+ *
+ */
+
+#ifndef __MX28_REGS_OCOTP_H__
+#define __MX28_REGS_OCOTP_H__
+
+#include <asm/arch/regs-common.h>
+
+#ifndef __ASSEMBLY__
+struct mx28_ocotp_regs {
+ mx28_reg(hw_ocotp_ctrl) /* 0x0 */
+ mx28_reg(hw_ocotp_data) /* 0x10 */
+ mx28_reg(hw_ocotp_cust0) /* 0x20 */
+ mx28_reg(hw_ocotp_cust1) /* 0x30 */
+ mx28_reg(hw_ocotp_cust2) /* 0x40 */
+ mx28_reg(hw_ocotp_cust3) /* 0x50 */
+ mx28_reg(hw_ocotp_crypto0) /* 0x60 */
+ mx28_reg(hw_ocotp_crypto1) /* 0x70 */
+ mx28_reg(hw_ocotp_crypto2) /* 0x80 */
+ mx28_reg(hw_ocotp_crypto3) /* 0x90 */
+ mx28_reg(hw_ocotp_hwcap0) /* 0xa0 */
+ mx28_reg(hw_ocotp_hwcap1) /* 0xb0 */
+ mx28_reg(hw_ocotp_hwcap2) /* 0xc0 */
+ mx28_reg(hw_ocotp_hwcap3) /* 0xd0 */
+ mx28_reg(hw_ocotp_hwcap4) /* 0xe0 */
+ mx28_reg(hw_ocotp_hwcap5) /* 0xf0 */
+ mx28_reg(hw_ocotp_swcap) /* 0x100 */
+ mx28_reg(hw_ocotp_custcap) /* 0x110 */
+ mx28_reg(hw_ocotp_lock) /* 0x120 */
+ mx28_reg(hw_ocotp_ops0) /* 0x130 */
+ mx28_reg(hw_ocotp_ops1) /* 0x140 */
+ mx28_reg(hw_ocotp_ops2) /* 0x150 */
+ mx28_reg(hw_ocotp_ops3) /* 0x160 */
+ mx28_reg(hw_ocotp_un0) /* 0x170 */
+ mx28_reg(hw_ocotp_un1) /* 0x180 */
+ mx28_reg(hw_ocotp_un2) /* 0x190 */
+ mx28_reg(hw_ocotp_rom0) /* 0x1a0 */
+ mx28_reg(hw_ocotp_rom1) /* 0x1b0 */
+ mx28_reg(hw_ocotp_rom2) /* 0x1c0 */
+ mx28_reg(hw_ocotp_rom3) /* 0x1d0 */
+ mx28_reg(hw_ocotp_rom4) /* 0x1e0 */
+ mx28_reg(hw_ocotp_rom5) /* 0x1f0 */
+ mx28_reg(hw_ocotp_rom6) /* 0x200 */
+ mx28_reg(hw_ocotp_rom7) /* 0x210 */
+ mx28_reg(hw_ocotp_srk0) /* 0x220 */
+ mx28_reg(hw_ocotp_srk1) /* 0x230 */
+ mx28_reg(hw_ocotp_srk2) /* 0x240 */
+ mx28_reg(hw_ocotp_srk3) /* 0x250 */
+ mx28_reg(hw_ocotp_srk4) /* 0x260 */
+ mx28_reg(hw_ocotp_srk5) /* 0x270 */
+ mx28_reg(hw_ocotp_srk6) /* 0x280 */
+ mx28_reg(hw_ocotp_srk7) /* 0x290 */
+ mx28_reg(hw_ocotp_version) /* 0x2a0 */
+};
+#endif
+
+#define OCOTP_CTRL_WR_UNLOCK_MASK (0xffff << 16)
+#define OCOTP_CTRL_WR_UNLOCK_OFFSET 16
+#define OCOTP_CTRL_WR_UNLOCK_KEY (0x3e77 << 16)
+#define OCOTP_CTRL_RELOAD_SHADOWS (1 << 13)
+#define OCOTP_CTRL_RD_BANK_OPEN (1 << 12)
+#define OCOTP_CTRL_ERROR (1 << 9)
+#define OCOTP_CTRL_BUSY (1 << 8)
+#define OCOTP_CTRL_ADDR_MASK 0x3f
+#define OCOTP_CTRL_ADDR_OFFSET 0
+
+#define OCOTP_DATA_DATA_MASK 0xffffffff
+#define OCOTP_DATA_DATA_OFFSET 0
+
+#define OCOTP_CUST_BITS_MASK 0xffffffff
+#define OCOTP_CUST_BITS_OFFSET 0
+
+#define OCOTP_CRYPTO_BITS_MASK 0xffffffff
+#define OCOTP_CRYPTO_BITS_OFFSET 0
+
+#define OCOTP_HWCAP_BITS_MASK 0xffffffff
+#define OCOTP_HWCAP_BITS_OFFSET 0
+
+#define OCOTP_SWCAP_BITS_MASK 0xffffffff
+#define OCOTP_SWCAP_BITS_OFFSET 0
+
+#define OCOTP_CUSTCAP_RTC_XTAL_32768_PRESENT (1 << 2)
+#define OCOTP_CUSTCAP_RTC_XTAL_32000_PRESENT (1 << 1)
+
+#define OCOTP_LOCK_ROM7 (1 << 31)
+#define OCOTP_LOCK_ROM6 (1 << 30)
+#define OCOTP_LOCK_ROM5 (1 << 29)
+#define OCOTP_LOCK_ROM4 (1 << 28)
+#define OCOTP_LOCK_ROM3 (1 << 27)
+#define OCOTP_LOCK_ROM2 (1 << 26)
+#define OCOTP_LOCK_ROM1 (1 << 25)
+#define OCOTP_LOCK_ROM0 (1 << 24)
+#define OCOTP_LOCK_HWSW_SHADOW_ALT (1 << 23)
+#define OCOTP_LOCK_CRYPTODCP_ALT (1 << 22)
+#define OCOTP_LOCK_CRYPTOKEY_ALT (1 << 21)
+#define OCOTP_LOCK_PIN (1 << 20)
+#define OCOTP_LOCK_OPS (1 << 19)
+#define OCOTP_LOCK_UN2 (1 << 18)
+#define OCOTP_LOCK_UN1 (1 << 17)
+#define OCOTP_LOCK_UN0 (1 << 16)
+#define OCOTP_LOCK_SRK (1 << 15)
+#define OCOTP_LOCK_UNALLOCATED_MASK (0x7 << 12)
+#define OCOTP_LOCK_UNALLOCATED_OFFSET 12
+#define OCOTP_LOCK_SRK_SHADOW (1 << 11)
+#define OCOTP_LOCK_ROM_SHADOW (1 << 10)
+#define OCOTP_LOCK_CUSTCAP (1 << 9)
+#define OCOTP_LOCK_HWSW (1 << 8)
+#define OCOTP_LOCK_CUSTCAP_SHADOW (1 << 7)
+#define OCOTP_LOCK_HWSW_SHADOW (1 << 6)
+#define OCOTP_LOCK_CRYPTODCP (1 << 5)
+#define OCOTP_LOCK_CRYPTOKEY (1 << 4)
+#define OCOTP_LOCK_CUST3 (1 << 3)
+#define OCOTP_LOCK_CUST2 (1 << 2)
+#define OCOTP_LOCK_CUST1 (1 << 1)
+#define OCOTP_LOCK_CUST0 (1 << 0)
+
+#define OCOTP_OPS_BITS_MASK 0xffffffff
+#define OCOTP_OPS_BITS_OFFSET 0
+
+#define OCOTP_UN_BITS_MASK 0xffffffff
+#define OCOTP_UN_BITS_OFFSET 0
+
+#define OCOTP_ROM_BOOT_MODE_MASK (0xff << 24)
+#define OCOTP_ROM_BOOT_MODE_OFFSET 24
+#define OCOTP_ROM_SD_MMC_MODE_MASK (0x3 << 22)
+#define OCOTP_ROM_SD_MMC_MODE_OFFSET 22
+#define OCOTP_ROM_SD_POWER_GATE_GPIO_MASK (0x3 << 20)
+#define OCOTP_ROM_SD_POWER_GATE_GPIO_OFFSET 20
+#define OCOTP_ROM_SD_POWER_UP_DELAY_MASK (0x3f << 14)
+#define OCOTP_ROM_SD_POWER_UP_DELAY_OFFSET 14
+#define OCOTP_ROM_SD_BUS_WIDTH_MASK (0x3 << 12)
+#define OCOTP_ROM_SD_BUS_WIDTH_OFFSET 12
+#define OCOTP_ROM_SSP_SCK_INDEX_MASK (0xf << 8)
+#define OCOTP_ROM_SSP_SCK_INDEX_OFFSET 8
+#define OCOTP_ROM_EMMC_USE_DDR (1 << 7)
+#define OCOTP_ROM_DISABLE_SPI_NOR_FAST_READ (1 << 6)
+#define OCOTP_ROM_ENABLE_USB_BOOT_SERIAL_NUM (1 << 5)
+#define OCOTP_ROM_ENABLE_UNENCRYPTED_BOOT (1 << 4)
+#define OCOTP_ROM_SD_MBR_BOOT (1 << 3)
+
+#define OCOTP_SRK_BITS_MASK 0xffffffff
+#define OCOTP_SRK_BITS_OFFSET 0
+
+#define OCOTP_VERSION_MAJOR_MASK (0xff << 24)
+#define OCOTP_VERSION_MAJOR_OFFSET 24
+#define OCOTP_VERSION_MINOR_MASK (0xff << 16)
+#define OCOTP_VERSION_MINOR_OFFSET 16
+#define OCOTP_VERSION_STEP_MASK 0xffff
+#define OCOTP_VERSION_STEP_OFFSET 0
+
+#endif /* __MX28_REGS_OCOTP_H__ */
diff --git a/arch/arm/include/asm/arch-mx28/regs-pinctrl.h b/arch/arm/include/asm/arch-mx28/regs-pinctrl.h
new file mode 100644
index 0000000..73739ca
--- /dev/null
+++ b/arch/arm/include/asm/arch-mx28/regs-pinctrl.h
@@ -0,0 +1,1284 @@
+/*
+ * Freescale i.MX28 PINCTRL Register Definitions
+ *
+ * Copyright (C) 2011 Marek Vasut <marek.vasut@gmail.com>
+ * on behalf of DENX Software Engineering GmbH
+ *
+ * Based on code from LTIB:
+ * Copyright 2008-2010 Freescale Semiconductor, Inc. All Rights Reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
+ *
+ */
+
+#ifndef __MX28_REGS_PINCTRL_H__
+#define __MX28_REGS_PINCTRL_H__
+
+#include <asm/arch/regs-common.h>
+
+#ifndef __ASSEMBLY__
+struct mx28_pinctrl_regs {
+ mx28_reg(hw_pinctrl_ctrl) /* 0x0 */
+
+ uint32_t reserved1[60];
+
+ mx28_reg(hw_pinctrl_muxsel0) /* 0x100 */
+ mx28_reg(hw_pinctrl_muxsel1) /* 0x110 */
+ mx28_reg(hw_pinctrl_muxsel2) /* 0x120 */
+ mx28_reg(hw_pinctrl_muxsel3) /* 0x130 */
+ mx28_reg(hw_pinctrl_muxsel4) /* 0x140 */
+ mx28_reg(hw_pinctrl_muxsel5) /* 0x150 */
+ mx28_reg(hw_pinctrl_muxsel6) /* 0x160 */
+ mx28_reg(hw_pinctrl_muxsel7) /* 0x170 */
+ mx28_reg(hw_pinctrl_muxsel8) /* 0x180 */
+ mx28_reg(hw_pinctrl_muxsel9) /* 0x190 */
+ mx28_reg(hw_pinctrl_muxsel10) /* 0x1a0 */
+ mx28_reg(hw_pinctrl_muxsel11) /* 0x1b0 */
+ mx28_reg(hw_pinctrl_muxsel12) /* 0x1c0 */
+ mx28_reg(hw_pinctrl_muxsel13) /* 0x1d0 */
+
+ uint32_t reserved2[72];
+
+ mx28_reg(hw_pinctrl_drive0) /* 0x300 */
+ mx28_reg(hw_pinctrl_drive1) /* 0x310 */
+ mx28_reg(hw_pinctrl_drive2) /* 0x320 */
+ mx28_reg(hw_pinctrl_drive3) /* 0x330 */
+ mx28_reg(hw_pinctrl_drive4) /* 0x340 */
+ mx28_reg(hw_pinctrl_drive5) /* 0x350 */
+ mx28_reg(hw_pinctrl_drive6) /* 0x360 */
+ mx28_reg(hw_pinctrl_drive7) /* 0x370 */
+ mx28_reg(hw_pinctrl_drive8) /* 0x380 */
+ mx28_reg(hw_pinctrl_drive9) /* 0x390 */
+ mx28_reg(hw_pinctrl_drive10) /* 0x3a0 */
+ mx28_reg(hw_pinctrl_drive11) /* 0x3b0 */
+ mx28_reg(hw_pinctrl_drive12) /* 0x3c0 */
+ mx28_reg(hw_pinctrl_drive13) /* 0x3d0 */
+ mx28_reg(hw_pinctrl_drive14) /* 0x3e0 */
+ mx28_reg(hw_pinctrl_drive15) /* 0x3f0 */
+ mx28_reg(hw_pinctrl_drive16) /* 0x400 */
+ mx28_reg(hw_pinctrl_drive17) /* 0x410 */
+ mx28_reg(hw_pinctrl_drive18) /* 0x420 */
+ mx28_reg(hw_pinctrl_drive19) /* 0x430 */
+
+ uint32_t reserved3[112];
+
+ mx28_reg(hw_pinctrl_pull0) /* 0x600 */
+ mx28_reg(hw_pinctrl_pull1) /* 0x610 */
+ mx28_reg(hw_pinctrl_pull2) /* 0x620 */
+ mx28_reg(hw_pinctrl_pull3) /* 0x630 */
+ mx28_reg(hw_pinctrl_pull4) /* 0x640 */
+ mx28_reg(hw_pinctrl_pull5) /* 0x650 */
+ mx28_reg(hw_pinctrl_pull6) /* 0x660 */
+
+ uint32_t reserved4[36];
+
+ mx28_reg(hw_pinctrl_dout0) /* 0x700 */
+ mx28_reg(hw_pinctrl_dout1) /* 0x710 */
+ mx28_reg(hw_pinctrl_dout2) /* 0x720 */
+ mx28_reg(hw_pinctrl_dout3) /* 0x730 */
+ mx28_reg(hw_pinctrl_dout4) /* 0x740 */
+
+ uint32_t reserved5[108];
+
+ mx28_reg(hw_pinctrl_din0) /* 0x900 */
+ mx28_reg(hw_pinctrl_din1) /* 0x910 */
+ mx28_reg(hw_pinctrl_din2) /* 0x920 */
+ mx28_reg(hw_pinctrl_din3) /* 0x930 */
+ mx28_reg(hw_pinctrl_din4) /* 0x940 */
+
+ uint32_t reserved6[108];
+
+ mx28_reg(hw_pinctrl_doe0) /* 0xb00 */
+ mx28_reg(hw_pinctrl_doe1) /* 0xb10 */
+ mx28_reg(hw_pinctrl_doe2) /* 0xb20 */
+ mx28_reg(hw_pinctrl_doe3) /* 0xb30 */
+ mx28_reg(hw_pinctrl_doe4) /* 0xb40 */
+
+ uint32_t reserved7[300];
+
+ mx28_reg(hw_pinctrl_pin2irq0) /* 0x1000 */
+ mx28_reg(hw_pinctrl_pin2irq1) /* 0x1010 */
+ mx28_reg(hw_pinctrl_pin2irq2) /* 0x1020 */
+ mx28_reg(hw_pinctrl_pin2irq3) /* 0x1030 */
+ mx28_reg(hw_pinctrl_pin2irq4) /* 0x1040 */
+
+ uint32_t reserved8[44];
+
+ mx28_reg(hw_pinctrl_irqen0) /* 0x1100 */
+ mx28_reg(hw_pinctrl_irqen1) /* 0x1110 */
+ mx28_reg(hw_pinctrl_irqen2) /* 0x1120 */
+ mx28_reg(hw_pinctrl_irqen3) /* 0x1130 */
+ mx28_reg(hw_pinctrl_irqen4) /* 0x1140 */
+
+ uint32_t reserved9[44];
+
+ mx28_reg(hw_pinctrl_irqlevel0) /* 0x1200 */
+ mx28_reg(hw_pinctrl_irqlevel1) /* 0x1210 */
+ mx28_reg(hw_pinctrl_irqlevel2) /* 0x1220 */
+ mx28_reg(hw_pinctrl_irqlevel3) /* 0x1230 */
+ mx28_reg(hw_pinctrl_irqlevel4) /* 0x1240 */
+
+ uint32_t reserved10[44];
+
+ mx28_reg(hw_pinctrl_irqpol0) /* 0x1300 */
+ mx28_reg(hw_pinctrl_irqpol1) /* 0x1310 */
+ mx28_reg(hw_pinctrl_irqpol2) /* 0x1320 */
+ mx28_reg(hw_pinctrl_irqpol3) /* 0x1330 */
+ mx28_reg(hw_pinctrl_irqpol4) /* 0x1340 */
+
+ uint32_t reserved11[44];
+
+ mx28_reg(hw_pinctrl_irqstat0) /* 0x1400 */
+ mx28_reg(hw_pinctrl_irqstat1) /* 0x1410 */
+ mx28_reg(hw_pinctrl_irqstat2) /* 0x1420 */
+ mx28_reg(hw_pinctrl_irqstat3) /* 0x1430 */
+ mx28_reg(hw_pinctrl_irqstat4) /* 0x1440 */
+
+ uint32_t reserved12[380];
+
+ mx28_reg(hw_pinctrl_emi_odt_ctrl) /* 0x1a40 */
+
+ uint32_t reserved13[76];
+
+ mx28_reg(hw_pinctrl_emi_ds_ctrl) /* 0x1b80 */
+};
+#endif
+
+#define PINCTRL_CTRL_SFTRST (1 << 31)
+#define PINCTRL_CTRL_CLKGATE (1 << 30)
+#define PINCTRL_CTRL_PRESENT4 (1 << 24)
+#define PINCTRL_CTRL_PRESENT3 (1 << 23)
+#define PINCTRL_CTRL_PRESENT2 (1 << 22)
+#define PINCTRL_CTRL_PRESENT1 (1 << 21)
+#define PINCTRL_CTRL_PRESENT0 (1 << 20)
+#define PINCTRL_CTRL_IRQOUT4 (1 << 4)
+#define PINCTRL_CTRL_IRQOUT3 (1 << 3)
+#define PINCTRL_CTRL_IRQOUT2 (1 << 2)
+#define PINCTRL_CTRL_IRQOUT1 (1 << 1)
+#define PINCTRL_CTRL_IRQOUT0 (1 << 0)
+
+#define PINCTRL_MUXSEL0_BANK0_PIN07_MASK (0x3 << 14)
+#define PINCTRL_MUXSEL0_BANK0_PIN07_OFFSET 14
+#define PINCTRL_MUXSEL0_BANK0_PIN06_MASK (0x3 << 12)
+#define PINCTRL_MUXSEL0_BANK0_PIN06_OFFSET 12
+#define PINCTRL_MUXSEL0_BANK0_PIN05_MASK (0x3 << 10)
+#define PINCTRL_MUXSEL0_BANK0_PIN05_OFFSET 10
+#define PINCTRL_MUXSEL0_BANK0_PIN04_MASK (0x3 << 8)
+#define PINCTRL_MUXSEL0_BANK0_PIN04_OFFSET 8
+#define PINCTRL_MUXSEL0_BANK0_PIN03_MASK (0x3 << 6)
+#define PINCTRL_MUXSEL0_BANK0_PIN03_OFFSET 6
+#define PINCTRL_MUXSEL0_BANK0_PIN02_MASK (0x3 << 4)
+#define PINCTRL_MUXSEL0_BANK0_PIN02_OFFSET 4
+#define PINCTRL_MUXSEL0_BANK0_PIN01_MASK (0x3 << 2)
+#define PINCTRL_MUXSEL0_BANK0_PIN01_OFFSET 2
+#define PINCTRL_MUXSEL0_BANK0_PIN00_MASK (0x3 << 0)
+#define PINCTRL_MUXSEL0_BANK0_PIN00_OFFSET 0
+
+#define PINCTRL_MUXSEL1_BANK0_PIN28_MASK (0x3 << 24)
+#define PINCTRL_MUXSEL1_BANK0_PIN28_OFFSET 24
+#define PINCTRL_MUXSEL1_BANK0_PIN27_MASK (0x3 << 22)
+#define PINCTRL_MUXSEL1_BANK0_PIN27_OFFSET 22
+#define PINCTRL_MUXSEL1_BANK0_PIN26_MASK (0x3 << 20)
+#define PINCTRL_MUXSEL1_BANK0_PIN26_OFFSET 20
+#define PINCTRL_MUXSEL1_BANK0_PIN25_MASK (0x3 << 18)
+#define PINCTRL_MUXSEL1_BANK0_PIN25_OFFSET 18
+#define PINCTRL_MUXSEL1_BANK0_PIN24_MASK (0x3 << 16)
+#define PINCTRL_MUXSEL1_BANK0_PIN24_OFFSET 16
+#define PINCTRL_MUXSEL1_BANK0_PIN23_MASK (0x3 << 14)
+#define PINCTRL_MUXSEL1_BANK0_PIN23_OFFSET 14
+#define PINCTRL_MUXSEL1_BANK0_PIN22_MASK (0x3 << 12)
+#define PINCTRL_MUXSEL1_BANK0_PIN22_OFFSET 12
+#define PINCTRL_MUXSEL1_BANK0_PIN21_MASK (0x3 << 10)
+#define PINCTRL_MUXSEL1_BANK0_PIN21_OFFSET 10
+#define PINCTRL_MUXSEL1_BANK0_PIN20_MASK (0x3 << 8)
+#define PINCTRL_MUXSEL1_BANK0_PIN20_OFFSET 8
+#define PINCTRL_MUXSEL1_BANK0_PIN19_MASK (0x3 << 6)
+#define PINCTRL_MUXSEL1_BANK0_PIN19_OFFSET 6
+#define PINCTRL_MUXSEL1_BANK0_PIN18_MASK (0x3 << 4)
+#define PINCTRL_MUXSEL1_BANK0_PIN18_OFFSET 4
+#define PINCTRL_MUXSEL1_BANK0_PIN17_MASK (0x3 << 2)
+#define PINCTRL_MUXSEL1_BANK0_PIN17_OFFSET 2
+#define PINCTRL_MUXSEL1_BANK0_PIN16_MASK (0x3 << 0)
+#define PINCTRL_MUXSEL1_BANK0_PIN16_OFFSET 0
+
+#define PINCTRL_MUXSEL2_BANK1_PIN15_MASK (0x3 << 30)
+#define PINCTRL_MUXSEL2_BANK1_PIN15_OFFSET 30
+#define PINCTRL_MUXSEL2_BANK1_PIN14_MASK (0x3 << 28)
+#define PINCTRL_MUXSEL2_BANK1_PIN14_OFFSET 28
+#define PINCTRL_MUXSEL2_BANK1_PIN13_MASK (0x3 << 26)
+#define PINCTRL_MUXSEL2_BANK1_PIN13_OFFSET 26
+#define PINCTRL_MUXSEL2_BANK1_PIN12_MASK (0x3 << 24)
+#define PINCTRL_MUXSEL2_BANK1_PIN12_OFFSET 24
+#define PINCTRL_MUXSEL2_BANK1_PIN11_MASK (0x3 << 22)
+#define PINCTRL_MUXSEL2_BANK1_PIN11_OFFSET 22
+#define PINCTRL_MUXSEL2_BANK1_PIN10_MASK (0x3 << 20)
+#define PINCTRL_MUXSEL2_BANK1_PIN10_OFFSET 20
+#define PINCTRL_MUXSEL2_BANK1_PIN09_MASK (0x3 << 18)
+#define PINCTRL_MUXSEL2_BANK1_PIN09_OFFSET 18
+#define PINCTRL_MUXSEL2_BANK1_PIN08_MASK (0x3 << 16)
+#define PINCTRL_MUXSEL2_BANK1_PIN08_OFFSET 16
+#define PINCTRL_MUXSEL2_BANK1_PIN07_MASK (0x3 << 14)
+#define PINCTRL_MUXSEL2_BANK1_PIN07_OFFSET 14
+#define PINCTRL_MUXSEL2_BANK1_PIN06_MASK (0x3 << 12)
+#define PINCTRL_MUXSEL2_BANK1_PIN06_OFFSET 12
+#define PINCTRL_MUXSEL2_BANK1_PIN05_MASK (0x3 << 10)
+#define PINCTRL_MUXSEL2_BANK1_PIN05_OFFSET 10
+#define PINCTRL_MUXSEL2_BANK1_PIN04_MASK (0x3 << 8)
+#define PINCTRL_MUXSEL2_BANK1_PIN04_OFFSET 8
+#define PINCTRL_MUXSEL2_BANK1_PIN03_MASK (0x3 << 6)
+#define PINCTRL_MUXSEL2_BANK1_PIN03_OFFSET 6
+#define PINCTRL_MUXSEL2_BANK1_PIN02_MASK (0x3 << 4)
+#define PINCTRL_MUXSEL2_BANK1_PIN02_OFFSET 4
+#define PINCTRL_MUXSEL2_BANK1_PIN01_MASK (0x3 << 2)
+#define PINCTRL_MUXSEL2_BANK1_PIN01_OFFSET 2
+#define PINCTRL_MUXSEL2_BANK1_PIN00_MASK (0x3 << 0)
+#define PINCTRL_MUXSEL2_BANK1_PIN00_OFFSET 0
+
+#define PINCTRL_MUXSEL3_BANK1_PIN31_MASK (0x3 << 30)
+#define PINCTRL_MUXSEL3_BANK1_PIN31_OFFSET 30
+#define PINCTRL_MUXSEL3_BANK1_PIN30_MASK (0x3 << 28)
+#define PINCTRL_MUXSEL3_BANK1_PIN30_OFFSET 28
+#define PINCTRL_MUXSEL3_BANK1_PIN29_MASK (0x3 << 26)
+#define PINCTRL_MUXSEL3_BANK1_PIN29_OFFSET 26
+#define PINCTRL_MUXSEL3_BANK1_PIN28_MASK (0x3 << 24)
+#define PINCTRL_MUXSEL3_BANK1_PIN28_OFFSET 24
+#define PINCTRL_MUXSEL3_BANK1_PIN27_MASK (0x3 << 22)
+#define PINCTRL_MUXSEL3_BANK1_PIN27_OFFSET 22
+#define PINCTRL_MUXSEL3_BANK1_PIN26_MASK (0x3 << 20)
+#define PINCTRL_MUXSEL3_BANK1_PIN26_OFFSET 20
+#define PINCTRL_MUXSEL3_BANK1_PIN25_MASK (0x3 << 18)
+#define PINCTRL_MUXSEL3_BANK1_PIN25_OFFSET 18
+#define PINCTRL_MUXSEL3_BANK1_PIN24_MASK (0x3 << 16)
+#define PINCTRL_MUXSEL3_BANK1_PIN24_OFFSET 16
+#define PINCTRL_MUXSEL3_BANK1_PIN23_MASK (0x3 << 14)
+#define PINCTRL_MUXSEL3_BANK1_PIN23_OFFSET 14
+#define PINCTRL_MUXSEL3_BANK1_PIN22_MASK (0x3 << 12)
+#define PINCTRL_MUXSEL3_BANK1_PIN22_OFFSET 12
+#define PINCTRL_MUXSEL3_BANK1_PIN21_MASK (0x3 << 10)
+#define PINCTRL_MUXSEL3_BANK1_PIN21_OFFSET 10
+#define PINCTRL_MUXSEL3_BANK1_PIN20_MASK (0x3 << 8)
+#define PINCTRL_MUXSEL3_BANK1_PIN20_OFFSET 8
+#define PINCTRL_MUXSEL3_BANK1_PIN19_MASK (0x3 << 6)
+#define PINCTRL_MUXSEL3_BANK1_PIN19_OFFSET 6
+#define PINCTRL_MUXSEL3_BANK1_PIN18_MASK (0x3 << 4)
+#define PINCTRL_MUXSEL3_BANK1_PIN18_OFFSET 4
+#define PINCTRL_MUXSEL3_BANK1_PIN17_MASK (0x3 << 2)
+#define PINCTRL_MUXSEL3_BANK1_PIN17_OFFSET 2
+#define PINCTRL_MUXSEL3_BANK1_PIN16_MASK (0x3 << 0)
+#define PINCTRL_MUXSEL3_BANK1_PIN16_OFFSET 0
+
+#define PINCTRL_MUXSEL4_BANK2_PIN15_MASK (0x3 << 30)
+#define PINCTRL_MUXSEL4_BANK2_PIN15_OFFSET 30
+#define PINCTRL_MUXSEL4_BANK2_PIN14_MASK (0x3 << 28)
+#define PINCTRL_MUXSEL4_BANK2_PIN14_OFFSET 28
+#define PINCTRL_MUXSEL4_BANK2_PIN13_MASK (0x3 << 26)
+#define PINCTRL_MUXSEL4_BANK2_PIN13_OFFSET 26
+#define PINCTRL_MUXSEL4_BANK2_PIN12_MASK (0x3 << 24)
+#define PINCTRL_MUXSEL4_BANK2_PIN12_OFFSET 24
+#define PINCTRL_MUXSEL4_BANK2_PIN10_MASK (0x3 << 20)
+#define PINCTRL_MUXSEL4_BANK2_PIN10_OFFSET 20
+#define PINCTRL_MUXSEL4_BANK2_PIN09_MASK (0x3 << 18)
+#define PINCTRL_MUXSEL4_BANK2_PIN09_OFFSET 18
+#define PINCTRL_MUXSEL4_BANK2_PIN08_MASK (0x3 << 16)
+#define PINCTRL_MUXSEL4_BANK2_PIN08_OFFSET 16
+#define PINCTRL_MUXSEL4_BANK2_PIN07_MASK (0x3 << 14)
+#define PINCTRL_MUXSEL4_BANK2_PIN07_OFFSET 14
+#define PINCTRL_MUXSEL4_BANK2_PIN06_MASK (0x3 << 12)
+#define PINCTRL_MUXSEL4_BANK2_PIN06_OFFSET 12
+#define PINCTRL_MUXSEL4_BANK2_PIN05_MASK (0x3 << 10)
+#define PINCTRL_MUXSEL4_BANK2_PIN05_OFFSET 10
+#define PINCTRL_MUXSEL4_BANK2_PIN04_MASK (0x3 << 8)
+#define PINCTRL_MUXSEL4_BANK2_PIN04_OFFSET 8
+#define PINCTRL_MUXSEL4_BANK2_PIN03_MASK (0x3 << 6)
+#define PINCTRL_MUXSEL4_BANK2_PIN03_OFFSET 6
+#define PINCTRL_MUXSEL4_BANK2_PIN02_MASK (0x3 << 4)
+#define PINCTRL_MUXSEL4_BANK2_PIN02_OFFSET 4
+#define PINCTRL_MUXSEL4_BANK2_PIN01_MASK (0x3 << 2)
+#define PINCTRL_MUXSEL4_BANK2_PIN01_OFFSET 2
+#define PINCTRL_MUXSEL4_BANK2_PIN00_MASK (0x3 << 0)
+#define PINCTRL_MUXSEL4_BANK2_PIN00_OFFSET 0
+
+#define PINCTRL_MUXSEL5_BANK2_PIN27_MASK (0x3 << 22)
+#define PINCTRL_MUXSEL5_BANK2_PIN27_OFFSET 22
+#define PINCTRL_MUXSEL5_BANK2_PIN26_MASK (0x3 << 20)
+#define PINCTRL_MUXSEL5_BANK2_PIN26_OFFSET 20
+#define PINCTRL_MUXSEL5_BANK2_PIN25_MASK (0x3 << 18)
+#define PINCTRL_MUXSEL5_BANK2_PIN25_OFFSET 18
+#define PINCTRL_MUXSEL5_BANK2_PIN24_MASK (0x3 << 16)
+#define PINCTRL_MUXSEL5_BANK2_PIN24_OFFSET 16
+#define PINCTRL_MUXSEL5_BANK2_PIN21_MASK (0x3 << 10)
+#define PINCTRL_MUXSEL5_BANK2_PIN21_OFFSET 10
+#define PINCTRL_MUXSEL5_BANK2_PIN20_MASK (0x3 << 8)
+#define PINCTRL_MUXSEL5_BANK2_PIN20_OFFSET 8
+#define PINCTRL_MUXSEL5_BANK2_PIN19_MASK (0x3 << 6)
+#define PINCTRL_MUXSEL5_BANK2_PIN19_OFFSET 6
+#define PINCTRL_MUXSEL5_BANK2_PIN18_MASK (0x3 << 4)
+#define PINCTRL_MUXSEL5_BANK2_PIN18_OFFSET 4
+#define PINCTRL_MUXSEL5_BANK2_PIN17_MASK (0x3 << 2)
+#define PINCTRL_MUXSEL5_BANK2_PIN17_OFFSET 2
+#define PINCTRL_MUXSEL5_BANK2_PIN16_MASK (0x3 << 0)
+#define PINCTRL_MUXSEL5_BANK2_PIN16_OFFSET 0
+
+#define PINCTRL_MUXSEL6_BANK3_PIN15_MASK (0x3 << 30)
+#define PINCTRL_MUXSEL6_BANK3_PIN15_OFFSET 30
+#define PINCTRL_MUXSEL6_BANK3_PIN14_MASK (0x3 << 28)
+#define PINCTRL_MUXSEL6_BANK3_PIN14_OFFSET 28
+#define PINCTRL_MUXSEL6_BANK3_PIN13_MASK (0x3 << 26)
+#define PINCTRL_MUXSEL6_BANK3_PIN13_OFFSET 26
+#define PINCTRL_MUXSEL6_BANK3_PIN12_MASK (0x3 << 24)
+#define PINCTRL_MUXSEL6_BANK3_PIN12_OFFSET 24
+#define PINCTRL_MUXSEL6_BANK3_PIN11_MASK (0x3 << 22)
+#define PINCTRL_MUXSEL6_BANK3_PIN11_OFFSET 22
+#define PINCTRL_MUXSEL6_BANK3_PIN10_MASK (0x3 << 20)
+#define PINCTRL_MUXSEL6_BANK3_PIN10_OFFSET 20
+#define PINCTRL_MUXSEL6_BANK3_PIN09_MASK (0x3 << 18)
+#define PINCTRL_MUXSEL6_BANK3_PIN09_OFFSET 18
+#define PINCTRL_MUXSEL6_BANK3_PIN08_MASK (0x3 << 16)
+#define PINCTRL_MUXSEL6_BANK3_PIN08_OFFSET 16
+#define PINCTRL_MUXSEL6_BANK3_PIN07_MASK (0x3 << 14)
+#define PINCTRL_MUXSEL6_BANK3_PIN07_OFFSET 14
+#define PINCTRL_MUXSEL6_BANK3_PIN06_MASK (0x3 << 12)
+#define PINCTRL_MUXSEL6_BANK3_PIN06_OFFSET 12
+#define PINCTRL_MUXSEL6_BANK3_PIN05_MASK (0x3 << 10)
+#define PINCTRL_MUXSEL6_BANK3_PIN05_OFFSET 10
+#define PINCTRL_MUXSEL6_BANK3_PIN04_MASK (0x3 << 8)
+#define PINCTRL_MUXSEL6_BANK3_PIN04_OFFSET 8
+#define PINCTRL_MUXSEL6_BANK3_PIN03_MASK (0x3 << 6)
+#define PINCTRL_MUXSEL6_BANK3_PIN03_OFFSET 6
+#define PINCTRL_MUXSEL6_BANK3_PIN02_MASK (0x3 << 4)
+#define PINCTRL_MUXSEL6_BANK3_PIN02_OFFSET 4
+#define PINCTRL_MUXSEL6_BANK3_PIN01_MASK (0x3 << 2)
+#define PINCTRL_MUXSEL6_BANK3_PIN01_OFFSET 2
+#define PINCTRL_MUXSEL6_BANK3_PIN00_MASK (0x3 << 0)
+#define PINCTRL_MUXSEL6_BANK3_PIN00_OFFSET 0
+
+#define PINCTRL_MUXSEL7_BANK3_PIN30_MASK (0x3 << 28)
+#define PINCTRL_MUXSEL7_BANK3_PIN30_OFFSET 28
+#define PINCTRL_MUXSEL7_BANK3_PIN29_MASK (0x3 << 26)
+#define PINCTRL_MUXSEL7_BANK3_PIN29_OFFSET 26
+#define PINCTRL_MUXSEL7_BANK3_PIN28_MASK (0x3 << 24)
+#define PINCTRL_MUXSEL7_BANK3_PIN28_OFFSET 24
+#define PINCTRL_MUXSEL7_BANK3_PIN27_MASK (0x3 << 22)
+#define PINCTRL_MUXSEL7_BANK3_PIN27_OFFSET 22
+#define PINCTRL_MUXSEL7_BANK3_PIN26_MASK (0x3 << 20)
+#define PINCTRL_MUXSEL7_BANK3_PIN26_OFFSET 20
+#define PINCTRL_MUXSEL7_BANK3_PIN25_MASK (0x3 << 18)
+#define PINCTRL_MUXSEL7_BANK3_PIN25_OFFSET 18
+#define PINCTRL_MUXSEL7_BANK3_PIN24_MASK (0x3 << 16)
+#define PINCTRL_MUXSEL7_BANK3_PIN24_OFFSET 16
+#define PINCTRL_MUXSEL7_BANK3_PIN23_MASK (0x3 << 14)
+#define PINCTRL_MUXSEL7_BANK3_PIN23_OFFSET 14
+#define PINCTRL_MUXSEL7_BANK3_PIN22_MASK (0x3 << 12)
+#define PINCTRL_MUXSEL7_BANK3_PIN22_OFFSET 12
+#define PINCTRL_MUXSEL7_BANK3_PIN21_MASK (0x3 << 10)
+#define PINCTRL_MUXSEL7_BANK3_PIN21_OFFSET 10
+#define PINCTRL_MUXSEL7_BANK3_PIN20_MASK (0x3 << 8)
+#define PINCTRL_MUXSEL7_BANK3_PIN20_OFFSET 8
+#define PINCTRL_MUXSEL7_BANK3_PIN18_MASK (0x3 << 4)
+#define PINCTRL_MUXSEL7_BANK3_PIN18_OFFSET 4
+#define PINCTRL_MUXSEL7_BANK3_PIN17_MASK (0x3 << 2)
+#define PINCTRL_MUXSEL7_BANK3_PIN17_OFFSET 2
+#define PINCTRL_MUXSEL7_BANK3_PIN16_MASK (0x3 << 0)
+#define PINCTRL_MUXSEL7_BANK3_PIN16_OFFSET 0
+
+#define PINCTRL_MUXSEL8_BANK4_PIN15_MASK (0x3 << 30)
+#define PINCTRL_MUXSEL8_BANK4_PIN15_OFFSET 30
+#define PINCTRL_MUXSEL8_BANK4_PIN14_MASK (0x3 << 28)
+#define PINCTRL_MUXSEL8_BANK4_PIN14_OFFSET 28
+#define PINCTRL_MUXSEL8_BANK4_PIN13_MASK (0x3 << 26)
+#define PINCTRL_MUXSEL8_BANK4_PIN13_OFFSET 26
+#define PINCTRL_MUXSEL8_BANK4_PIN12_MASK (0x3 << 24)
+#define PINCTRL_MUXSEL8_BANK4_PIN12_OFFSET 24
+#define PINCTRL_MUXSEL8_BANK4_PIN11_MASK (0x3 << 22)
+#define PINCTRL_MUXSEL8_BANK4_PIN11_OFFSET 22
+#define PINCTRL_MUXSEL8_BANK4_PIN10_MASK (0x3 << 20)
+#define PINCTRL_MUXSEL8_BANK4_PIN10_OFFSET 20
+#define PINCTRL_MUXSEL8_BANK4_PIN09_MASK (0x3 << 18)
+#define PINCTRL_MUXSEL8_BANK4_PIN09_OFFSET 18
+#define PINCTRL_MUXSEL8_BANK4_PIN08_MASK (0x3 << 16)
+#define PINCTRL_MUXSEL8_BANK4_PIN08_OFFSET 16
+#define PINCTRL_MUXSEL8_BANK4_PIN07_MASK (0x3 << 14)
+#define PINCTRL_MUXSEL8_BANK4_PIN07_OFFSET 14
+#define PINCTRL_MUXSEL8_BANK4_PIN06_MASK (0x3 << 12)
+#define PINCTRL_MUXSEL8_BANK4_PIN06_OFFSET 12
+#define PINCTRL_MUXSEL8_BANK4_PIN05_MASK (0x3 << 10)
+#define PINCTRL_MUXSEL8_BANK4_PIN05_OFFSET 10
+#define PINCTRL_MUXSEL8_BANK4_PIN04_MASK (0x3 << 8)
+#define PINCTRL_MUXSEL8_BANK4_PIN04_OFFSET 8
+#define PINCTRL_MUXSEL8_BANK4_PIN03_MASK (0x3 << 6)
+#define PINCTRL_MUXSEL8_BANK4_PIN03_OFFSET 6
+#define PINCTRL_MUXSEL8_BANK4_PIN02_MASK (0x3 << 4)
+#define PINCTRL_MUXSEL8_BANK4_PIN02_OFFSET 4
+#define PINCTRL_MUXSEL8_BANK4_PIN01_MASK (0x3 << 2)
+#define PINCTRL_MUXSEL8_BANK4_PIN01_OFFSET 2
+#define PINCTRL_MUXSEL8_BANK4_PIN00_MASK (0x3 << 0)
+#define PINCTRL_MUXSEL8_BANK4_PIN00_OFFSET 0
+
+#define PINCTRL_MUXSEL9_BANK4_PIN20_MASK (0x3 << 8)
+#define PINCTRL_MUXSEL9_BANK4_PIN20_OFFSET 8
+#define PINCTRL_MUXSEL9_BANK4_PIN16_MASK (0x3 << 0)
+#define PINCTRL_MUXSEL9_BANK4_PIN16_OFFSET 0
+
+#define PINCTRL_MUXSEL10_BANK5_PIN15_MASK (0x3 << 30)
+#define PINCTRL_MUXSEL10_BANK5_PIN15_OFFSET 30
+#define PINCTRL_MUXSEL10_BANK5_PIN14_MASK (0x3 << 28)
+#define PINCTRL_MUXSEL10_BANK5_PIN14_OFFSET 28
+#define PINCTRL_MUXSEL10_BANK5_PIN13_MASK (0x3 << 26)
+#define PINCTRL_MUXSEL10_BANK5_PIN13_OFFSET 26
+#define PINCTRL_MUXSEL10_BANK5_PIN12_MASK (0x3 << 24)
+#define PINCTRL_MUXSEL10_BANK5_PIN12_OFFSET 24
+#define PINCTRL_MUXSEL10_BANK5_PIN11_MASK (0x3 << 22)
+#define PINCTRL_MUXSEL10_BANK5_PIN11_OFFSET 22
+#define PINCTRL_MUXSEL10_BANK5_PIN10_MASK (0x3 << 20)
+#define PINCTRL_MUXSEL10_BANK5_PIN10_OFFSET 20
+#define PINCTRL_MUXSEL10_BANK5_PIN09_MASK (0x3 << 18)
+#define PINCTRL_MUXSEL10_BANK5_PIN09_OFFSET 18
+#define PINCTRL_MUXSEL10_BANK5_PIN08_MASK (0x3 << 16)
+#define PINCTRL_MUXSEL10_BANK5_PIN08_OFFSET 16
+#define PINCTRL_MUXSEL10_BANK5_PIN07_MASK (0x3 << 14)
+#define PINCTRL_MUXSEL10_BANK5_PIN07_OFFSET 14
+#define PINCTRL_MUXSEL10_BANK5_PIN06_MASK (0x3 << 12)
+#define PINCTRL_MUXSEL10_BANK5_PIN06_OFFSET 12
+#define PINCTRL_MUXSEL10_BANK5_PIN05_MASK (0x3 << 10)
+#define PINCTRL_MUXSEL10_BANK5_PIN05_OFFSET 10
+#define PINCTRL_MUXSEL10_BANK5_PIN04_MASK (0x3 << 8)
+#define PINCTRL_MUXSEL10_BANK5_PIN04_OFFSET 8
+#define PINCTRL_MUXSEL10_BANK5_PIN03_MASK (0x3 << 6)
+#define PINCTRL_MUXSEL10_BANK5_PIN03_OFFSET 6
+#define PINCTRL_MUXSEL10_BANK5_PIN02_MASK (0x3 << 4)
+#define PINCTRL_MUXSEL10_BANK5_PIN02_OFFSET 4
+#define PINCTRL_MUXSEL10_BANK5_PIN01_MASK (0x3 << 2)
+#define PINCTRL_MUXSEL10_BANK5_PIN01_OFFSET 2
+#define PINCTRL_MUXSEL10_BANK5_PIN00_MASK (0x3 << 0)
+#define PINCTRL_MUXSEL10_BANK5_PIN00_OFFSET 0
+
+#define PINCTRL_MUXSEL11_BANK5_PIN26_MASK (0x3 << 20)
+#define PINCTRL_MUXSEL11_BANK5_PIN26_OFFSET 20
+#define PINCTRL_MUXSEL11_BANK5_PIN23_MASK (0x3 << 14)
+#define PINCTRL_MUXSEL11_BANK5_PIN23_OFFSET 14
+#define PINCTRL_MUXSEL11_BANK5_PIN22_MASK (0x3 << 12)
+#define PINCTRL_MUXSEL11_BANK5_PIN22_OFFSET 12
+#define PINCTRL_MUXSEL11_BANK5_PIN21_MASK (0x3 << 10)
+#define PINCTRL_MUXSEL11_BANK5_PIN21_OFFSET 10
+#define PINCTRL_MUXSEL11_BANK5_PIN20_MASK (0x3 << 8)
+#define PINCTRL_MUXSEL11_BANK5_PIN20_OFFSET 8
+#define PINCTRL_MUXSEL11_BANK5_PIN19_MASK (0x3 << 6)
+#define PINCTRL_MUXSEL11_BANK5_PIN19_OFFSET 6
+#define PINCTRL_MUXSEL11_BANK5_PIN18_MASK (0x3 << 4)
+#define PINCTRL_MUXSEL11_BANK5_PIN18_OFFSET 4
+#define PINCTRL_MUXSEL11_BANK5_PIN17_MASK (0x3 << 2)
+#define PINCTRL_MUXSEL11_BANK5_PIN17_OFFSET 2
+#define PINCTRL_MUXSEL11_BANK5_PIN16_MASK (0x3 << 0)
+#define PINCTRL_MUXSEL11_BANK5_PIN16_OFFSET 0
+
+#define PINCTRL_MUXSEL12_BANK6_PIN14_MASK (0x3 << 28)
+#define PINCTRL_MUXSEL12_BANK6_PIN14_OFFSET 28
+#define PINCTRL_MUXSEL12_BANK6_PIN13_MASK (0x3 << 26)
+#define PINCTRL_MUXSEL12_BANK6_PIN13_OFFSET 26
+#define PINCTRL_MUXSEL12_BANK6_PIN12_MASK (0x3 << 24)
+#define PINCTRL_MUXSEL12_BANK6_PIN12_OFFSET 24
+#define PINCTRL_MUXSEL12_BANK6_PIN11_MASK (0x3 << 22)
+#define PINCTRL_MUXSEL12_BANK6_PIN11_OFFSET 22
+#define PINCTRL_MUXSEL12_BANK6_PIN10_MASK (0x3 << 20)
+#define PINCTRL_MUXSEL12_BANK6_PIN10_OFFSET 20
+#define PINCTRL_MUXSEL12_BANK6_PIN09_MASK (0x3 << 18)
+#define PINCTRL_MUXSEL12_BANK6_PIN09_OFFSET 18
+#define PINCTRL_MUXSEL12_BANK6_PIN08_MASK (0x3 << 16)
+#define PINCTRL_MUXSEL12_BANK6_PIN08_OFFSET 16
+#define PINCTRL_MUXSEL12_BANK6_PIN07_MASK (0x3 << 14)
+#define PINCTRL_MUXSEL12_BANK6_PIN07_OFFSET 14
+#define PINCTRL_MUXSEL12_BANK6_PIN06_MASK (0x3 << 12)
+#define PINCTRL_MUXSEL12_BANK6_PIN06_OFFSET 12
+#define PINCTRL_MUXSEL12_BANK6_PIN05_MASK (0x3 << 10)
+#define PINCTRL_MUXSEL12_BANK6_PIN05_OFFSET 10
+#define PINCTRL_MUXSEL12_BANK6_PIN04_MASK (0x3 << 8)
+#define PINCTRL_MUXSEL12_BANK6_PIN04_OFFSET 8
+#define PINCTRL_MUXSEL12_BANK6_PIN03_MASK (0x3 << 6)
+#define PINCTRL_MUXSEL12_BANK6_PIN03_OFFSET 6
+#define PINCTRL_MUXSEL12_BANK6_PIN02_MASK (0x3 << 4)
+#define PINCTRL_MUXSEL12_BANK6_PIN02_OFFSET 4
+#define PINCTRL_MUXSEL12_BANK6_PIN01_MASK (0x3 << 2)
+#define PINCTRL_MUXSEL12_BANK6_PIN01_OFFSET 2
+#define PINCTRL_MUXSEL12_BANK6_PIN00_MASK (0x3 << 0)
+#define PINCTRL_MUXSEL12_BANK6_PIN00_OFFSET 0
+
+#define PINCTRL_MUXSEL13_BANK6_PIN24_MASK (0x3 << 16)
+#define PINCTRL_MUXSEL13_BANK6_PIN24_OFFSET 16
+#define PINCTRL_MUXSEL13_BANK6_PIN23_MASK (0x3 << 14)
+#define PINCTRL_MUXSEL13_BANK6_PIN23_OFFSET 14
+#define PINCTRL_MUXSEL13_BANK6_PIN22_MASK (0x3 << 12)
+#define PINCTRL_MUXSEL13_BANK6_PIN22_OFFSET 12
+#define PINCTRL_MUXSEL13_BANK6_PIN21_MASK (0x3 << 10)
+#define PINCTRL_MUXSEL13_BANK6_PIN21_OFFSET 10
+#define PINCTRL_MUXSEL13_BANK6_PIN20_MASK (0x3 << 8)
+#define PINCTRL_MUXSEL13_BANK6_PIN20_OFFSET 8
+#define PINCTRL_MUXSEL13_BANK6_PIN19_MASK (0x3 << 6)
+#define PINCTRL_MUXSEL13_BANK6_PIN19_OFFSET 6
+#define PINCTRL_MUXSEL13_BANK6_PIN18_MASK (0x3 << 4)
+#define PINCTRL_MUXSEL13_BANK6_PIN18_OFFSET 4
+#define PINCTRL_MUXSEL13_BANK6_PIN17_MASK (0x3 << 2)
+#define PINCTRL_MUXSEL13_BANK6_PIN17_OFFSET 2
+#define PINCTRL_MUXSEL13_BANK6_PIN16_MASK (0x3 << 0)
+#define PINCTRL_MUXSEL13_BANK6_PIN16_OFFSET 0
+
+#define PINCTRL_DRIVE0_BANK0_PIN07_V (1 << 30)
+#define PINCTRL_DRIVE0_BANK0_PIN07_MA_MASK (0x3 << 28)
+#define PINCTRL_DRIVE0_BANK0_PIN07_MA_OFFSET 28
+#define PINCTRL_DRIVE0_BANK0_PIN06_V (1 << 26)
+#define PINCTRL_DRIVE0_BANK0_PIN06_MA_MASK (0x3 << 24)
+#define PINCTRL_DRIVE0_BANK0_PIN06_MA_OFFSET 24
+#define PINCTRL_DRIVE0_BANK0_PIN05_V (1 << 22)
+#define PINCTRL_DRIVE0_BANK0_PIN05_MA_MASK (0x3 << 20)
+#define PINCTRL_DRIVE0_BANK0_PIN05_MA_OFFSET 20
+#define PINCTRL_DRIVE0_BANK0_PIN04_V (1 << 18)
+#define PINCTRL_DRIVE0_BANK0_PIN04_MA_MASK (0x3 << 16)
+#define PINCTRL_DRIVE0_BANK0_PIN04_MA_OFFSET 16
+#define PINCTRL_DRIVE0_BANK0_PIN03_V (1 << 14)
+#define PINCTRL_DRIVE0_BANK0_PIN03_MA_MASK (0x3 << 12)
+#define PINCTRL_DRIVE0_BANK0_PIN03_MA_OFFSET 12
+#define PINCTRL_DRIVE0_BANK0_PIN02_V (1 << 10)
+#define PINCTRL_DRIVE0_BANK0_PIN02_MA_MASK (0x3 << 8)
+#define PINCTRL_DRIVE0_BANK0_PIN02_MA_OFFSET 8
+#define PINCTRL_DRIVE0_BANK0_PIN01_V (1 << 6)
+#define PINCTRL_DRIVE0_BANK0_PIN01_MA_MASK (0x3 << 4)
+#define PINCTRL_DRIVE0_BANK0_PIN01_MA_OFFSET 4
+#define PINCTRL_DRIVE0_BANK0_PIN00_V (1 << 2)
+#define PINCTRL_DRIVE0_BANK0_PIN00_MA_MASK (0x3 << 0)
+#define PINCTRL_DRIVE0_BANK0_PIN00_MA_OFFSET 0
+
+#define PINCTRL_DRIVE2_BANK0_PIN23_V (1 << 30)
+#define PINCTRL_DRIVE2_BANK0_PIN23_MA_MASK (0x3 << 28)
+#define PINCTRL_DRIVE2_BANK0_PIN23_MA_OFFSET 28
+#define PINCTRL_DRIVE2_BANK0_PIN22_V (1 << 26)
+#define PINCTRL_DRIVE2_BANK0_PIN22_MA_MASK (0x3 << 24)
+#define PINCTRL_DRIVE2_BANK0_PIN22_MA_OFFSET 24
+#define PINCTRL_DRIVE2_BANK0_PIN21_V (1 << 22)
+#define PINCTRL_DRIVE2_BANK0_PIN21_MA_MASK (0x3 << 20)
+#define PINCTRL_DRIVE2_BANK0_PIN21_MA_OFFSET 20
+#define PINCTRL_DRIVE2_BANK0_PIN20_V (1 << 18)
+#define PINCTRL_DRIVE2_BANK0_PIN20_MA_MASK (0x3 << 16)
+#define PINCTRL_DRIVE2_BANK0_PIN20_MA_OFFSET 16
+#define PINCTRL_DRIVE2_BANK0_PIN19_V (1 << 14)
+#define PINCTRL_DRIVE2_BANK0_PIN19_MA_MASK (0x3 << 12)
+#define PINCTRL_DRIVE2_BANK0_PIN19_MA_OFFSET 12
+#define PINCTRL_DRIVE2_BANK0_PIN18_V (1 << 10)
+#define PINCTRL_DRIVE2_BANK0_PIN18_MA_MASK (0x3 << 8)
+#define PINCTRL_DRIVE2_BANK0_PIN18_MA_OFFSET 8
+#define PINCTRL_DRIVE2_BANK0_PIN17_V (1 << 6)
+#define PINCTRL_DRIVE2_BANK0_PIN17_MA_MASK (0x3 << 4)
+#define PINCTRL_DRIVE2_BANK0_PIN17_MA_OFFSET 4
+#define PINCTRL_DRIVE2_BANK0_PIN16_V (1 << 2)
+#define PINCTRL_DRIVE2_BANK0_PIN16_MA_MASK (0x3 << 0)
+#define PINCTRL_DRIVE2_BANK0_PIN16_MA_OFFSET 0
+
+#define PINCTRL_DRIVE3_BANK0_PIN28_V (1 << 18)
+#define PINCTRL_DRIVE3_BANK0_PIN28_MA_MASK (0x3 << 16)
+#define PINCTRL_DRIVE3_BANK0_PIN28_MA_OFFSET 16
+#define PINCTRL_DRIVE3_BANK0_PIN27_V (1 << 14)
+#define PINCTRL_DRIVE3_BANK0_PIN27_MA_MASK (0x3 << 12)
+#define PINCTRL_DRIVE3_BANK0_PIN27_MA_OFFSET 12
+#define PINCTRL_DRIVE3_BANK0_PIN26_V (1 << 10)
+#define PINCTRL_DRIVE3_BANK0_PIN26_MA_MASK (0x3 << 8)
+#define PINCTRL_DRIVE3_BANK0_PIN26_MA_OFFSET 8
+#define PINCTRL_DRIVE3_BANK0_PIN25_V (1 << 6)
+#define PINCTRL_DRIVE3_BANK0_PIN25_MA_MASK (0x3 << 4)
+#define PINCTRL_DRIVE3_BANK0_PIN25_MA_OFFSET 4
+#define PINCTRL_DRIVE3_BANK0_PIN24_V (1 << 2)
+#define PINCTRL_DRIVE3_BANK0_PIN24_MA_MASK (0x3 << 0)
+#define PINCTRL_DRIVE3_BANK0_PIN24_MA_OFFSET 0
+
+#define PINCTRL_DRIVE4_BANK1_PIN07_V (1 << 30)
+#define PINCTRL_DRIVE4_BANK1_PIN07_MA_MASK (0x3 << 28)
+#define PINCTRL_DRIVE4_BANK1_PIN07_MA_OFFSET 28
+#define PINCTRL_DRIVE4_BANK1_PIN06_V (1 << 26)
+#define PINCTRL_DRIVE4_BANK1_PIN06_MA_MASK (0x3 << 24)
+#define PINCTRL_DRIVE4_BANK1_PIN06_MA_OFFSET 24
+#define PINCTRL_DRIVE4_BANK1_PIN05_V (1 << 22)
+#define PINCTRL_DRIVE4_BANK1_PIN05_MA_MASK (0x3 << 20)
+#define PINCTRL_DRIVE4_BANK1_PIN05_MA_OFFSET 20
+#define PINCTRL_DRIVE4_BANK1_PIN04_V (1 << 18)
+#define PINCTRL_DRIVE4_BANK1_PIN04_MA_MASK (0x3 << 16)
+#define PINCTRL_DRIVE4_BANK1_PIN04_MA_OFFSET 16
+#define PINCTRL_DRIVE4_BANK1_PIN03_V (1 << 14)
+#define PINCTRL_DRIVE4_BANK1_PIN03_MA_MASK (0x3 << 12)
+#define PINCTRL_DRIVE4_BANK1_PIN03_MA_OFFSET 12
+#define PINCTRL_DRIVE4_BANK1_PIN02_V (1 << 10)
+#define PINCTRL_DRIVE4_BANK1_PIN02_MA_MASK (0x3 << 8)
+#define PINCTRL_DRIVE4_BANK1_PIN02_MA_OFFSET 8
+#define PINCTRL_DRIVE4_BANK1_PIN01_V (1 << 6)
+#define PINCTRL_DRIVE4_BANK1_PIN01_MA_MASK (0x3 << 4)
+#define PINCTRL_DRIVE4_BANK1_PIN01_MA_OFFSET 4
+#define PINCTRL_DRIVE4_BANK1_PIN00_V (1 << 2)
+#define PINCTRL_DRIVE4_BANK1_PIN00_MA_MASK (0x3 << 0)
+#define PINCTRL_DRIVE4_BANK1_PIN00_MA_OFFSET 0
+
+#define PINCTRL_DRIVE5_BANK1_PIN15_V (1 << 30)
+#define PINCTRL_DRIVE5_BANK1_PIN15_MA_MASK (0x3 << 28)
+#define PINCTRL_DRIVE5_BANK1_PIN15_MA_OFFSET 28
+#define PINCTRL_DRIVE5_BANK1_PIN14_V (1 << 26)
+#define PINCTRL_DRIVE5_BANK1_PIN14_MA_MASK (0x3 << 24)
+#define PINCTRL_DRIVE5_BANK1_PIN14_MA_OFFSET 24
+#define PINCTRL_DRIVE5_BANK1_PIN13_V (1 << 22)
+#define PINCTRL_DRIVE5_BANK1_PIN13_MA_MASK (0x3 << 20)
+#define PINCTRL_DRIVE5_BANK1_PIN13_MA_OFFSET 20
+#define PINCTRL_DRIVE5_BANK1_PIN12_V (1 << 18)
+#define PINCTRL_DRIVE5_BANK1_PIN12_MA_MASK (0x3 << 16)
+#define PINCTRL_DRIVE5_BANK1_PIN12_MA_OFFSET 16
+#define PINCTRL_DRIVE5_BANK1_PIN11_V (1 << 14)
+#define PINCTRL_DRIVE5_BANK1_PIN11_MA_MASK (0x3 << 12)
+#define PINCTRL_DRIVE5_BANK1_PIN11_MA_OFFSET 12
+#define PINCTRL_DRIVE5_BANK1_PIN10_V (1 << 10)
+#define PINCTRL_DRIVE5_BANK1_PIN10_MA_MASK (0x3 << 8)
+#define PINCTRL_DRIVE5_BANK1_PIN10_MA_OFFSET 8
+#define PINCTRL_DRIVE5_BANK1_PIN09_V (1 << 6)
+#define PINCTRL_DRIVE5_BANK1_PIN09_MA_MASK (0x3 << 4)
+#define PINCTRL_DRIVE5_BANK1_PIN09_MA_OFFSET 4
+#define PINCTRL_DRIVE5_BANK1_PIN08_V (1 << 2)
+#define PINCTRL_DRIVE5_BANK1_PIN08_MA_MASK (0x3 << 0)
+#define PINCTRL_DRIVE5_BANK1_PIN08_MA_OFFSET 0
+
+#define PINCTRL_DRIVE6_BANK1_PIN23_V (1 << 30)
+#define PINCTRL_DRIVE6_BANK1_PIN23_MA_MASK (0x3 << 28)
+#define PINCTRL_DRIVE6_BANK1_PIN23_MA_OFFSET 28
+#define PINCTRL_DRIVE6_BANK1_PIN22_V (1 << 26)
+#define PINCTRL_DRIVE6_BANK1_PIN22_MA_MASK (0x3 << 24)
+#define PINCTRL_DRIVE6_BANK1_PIN22_MA_OFFSET 24
+#define PINCTRL_DRIVE6_BANK1_PIN21_V (1 << 22)
+#define PINCTRL_DRIVE6_BANK1_PIN21_MA_MASK (0x3 << 20)
+#define PINCTRL_DRIVE6_BANK1_PIN21_MA_OFFSET 20
+#define PINCTRL_DRIVE6_BANK1_PIN20_V (1 << 18)
+#define PINCTRL_DRIVE6_BANK1_PIN20_MA_MASK (0x3 << 16)
+#define PINCTRL_DRIVE6_BANK1_PIN20_MA_OFFSET 16
+#define PINCTRL_DRIVE6_BANK1_PIN19_V (1 << 14)
+#define PINCTRL_DRIVE6_BANK1_PIN19_MA_MASK (0x3 << 12)
+#define PINCTRL_DRIVE6_BANK1_PIN19_MA_OFFSET 12
+#define PINCTRL_DRIVE6_BANK1_PIN18_V (1 << 10)
+#define PINCTRL_DRIVE6_BANK1_PIN18_MA_MASK (0x3 << 8)
+#define PINCTRL_DRIVE6_BANK1_PIN18_MA_OFFSET 8
+#define PINCTRL_DRIVE6_BANK1_PIN17_V (1 << 6)
+#define PINCTRL_DRIVE6_BANK1_PIN17_MA_MASK (0x3 << 4)
+#define PINCTRL_DRIVE6_BANK1_PIN17_MA_OFFSET 4
+#define PINCTRL_DRIVE6_BANK1_PIN16_V (1 << 2)
+#define PINCTRL_DRIVE6_BANK1_PIN16_MA_MASK (0x3 << 0)
+#define PINCTRL_DRIVE6_BANK1_PIN16_MA_OFFSET 0
+
+#define PINCTRL_DRIVE7_BANK1_PIN31_V (1 << 30)
+#define PINCTRL_DRIVE7_BANK1_PIN31_MA_MASK (0x3 << 28)
+#define PINCTRL_DRIVE7_BANK1_PIN31_MA_OFFSET 28
+#define PINCTRL_DRIVE7_BANK1_PIN30_V (1 << 26)
+#define PINCTRL_DRIVE7_BANK1_PIN30_MA_MASK (0x3 << 24)
+#define PINCTRL_DRIVE7_BANK1_PIN30_MA_OFFSET 24
+#define PINCTRL_DRIVE7_BANK1_PIN29_V (1 << 22)
+#define PINCTRL_DRIVE7_BANK1_PIN29_MA_MASK (0x3 << 20)
+#define PINCTRL_DRIVE7_BANK1_PIN29_MA_OFFSET 20
+#define PINCTRL_DRIVE7_BANK1_PIN28_V (1 << 18)
+#define PINCTRL_DRIVE7_BANK1_PIN28_MA_MASK (0x3 << 16)
+#define PINCTRL_DRIVE7_BANK1_PIN28_MA_OFFSET 16
+#define PINCTRL_DRIVE7_BANK1_PIN27_V (1 << 14)
+#define PINCTRL_DRIVE7_BANK1_PIN27_MA_MASK (0x3 << 12)
+#define PINCTRL_DRIVE7_BANK1_PIN27_MA_OFFSET 12
+#define PINCTRL_DRIVE7_BANK1_PIN26_V (1 << 10)
+#define PINCTRL_DRIVE7_BANK1_PIN26_MA_MASK (0x3 << 8)
+#define PINCTRL_DRIVE7_BANK1_PIN26_MA_OFFSET 8
+#define PINCTRL_DRIVE7_BANK1_PIN25_V (1 << 6)
+#define PINCTRL_DRIVE7_BANK1_PIN25_MA_MASK (0x3 << 4)
+#define PINCTRL_DRIVE7_BANK1_PIN25_MA_OFFSET 4
+#define PINCTRL_DRIVE7_BANK1_PIN24_V (1 << 2)
+#define PINCTRL_DRIVE7_BANK1_PIN24_MA_MASK (0x3 << 0)
+#define PINCTRL_DRIVE7_BANK1_PIN24_MA_OFFSET 0
+
+#define PINCTRL_DRIVE8_BANK2_PIN07_V (1 << 30)
+#define PINCTRL_DRIVE8_BANK2_PIN07_MA_MASK (0x3 << 28)
+#define PINCTRL_DRIVE8_BANK2_PIN07_MA_OFFSET 28
+#define PINCTRL_DRIVE8_BANK2_PIN06_V (1 << 26)
+#define PINCTRL_DRIVE8_BANK2_PIN06_MA_MASK (0x3 << 24)
+#define PINCTRL_DRIVE8_BANK2_PIN06_MA_OFFSET 24
+#define PINCTRL_DRIVE8_BANK2_PIN05_V (1 << 22)
+#define PINCTRL_DRIVE8_BANK2_PIN05_MA_MASK (0x3 << 20)
+#define PINCTRL_DRIVE8_BANK2_PIN05_MA_OFFSET 20
+#define PINCTRL_DRIVE8_BANK2_PIN04_V (1 << 18)
+#define PINCTRL_DRIVE8_BANK2_PIN04_MA_MASK (0x3 << 16)
+#define PINCTRL_DRIVE8_BANK2_PIN04_MA_OFFSET 16
+#define PINCTRL_DRIVE8_BANK2_PIN03_V (1 << 14)
+#define PINCTRL_DRIVE8_BANK2_PIN03_MA_MASK (0x3 << 12)
+#define PINCTRL_DRIVE8_BANK2_PIN03_MA_OFFSET 12
+#define PINCTRL_DRIVE8_BANK2_PIN02_V (1 << 10)
+#define PINCTRL_DRIVE8_BANK2_PIN02_MA_MASK (0x3 << 8)
+#define PINCTRL_DRIVE8_BANK2_PIN02_MA_OFFSET 8
+#define PINCTRL_DRIVE8_BANK2_PIN01_V (1 << 6)
+#define PINCTRL_DRIVE8_BANK2_PIN01_MA_MASK (0x3 << 4)
+#define PINCTRL_DRIVE8_BANK2_PIN01_MA_OFFSET 4
+#define PINCTRL_DRIVE8_BANK2_PIN00_V (1 << 2)
+#define PINCTRL_DRIVE8_BANK2_PIN00_MA_MASK (0x3 << 0)
+#define PINCTRL_DRIVE8_BANK2_PIN00_MA_OFFSET 0
+
+#define PINCTRL_DRIVE9_BANK2_PIN15_V (1 << 30)
+#define PINCTRL_DRIVE9_BANK2_PIN15_MA_MASK (0x3 << 28)
+#define PINCTRL_DRIVE9_BANK2_PIN15_MA_OFFSET 28
+#define PINCTRL_DRIVE9_BANK2_PIN14_V (1 << 26)
+#define PINCTRL_DRIVE9_BANK2_PIN14_MA_MASK (0x3 << 24)
+#define PINCTRL_DRIVE9_BANK2_PIN14_MA_OFFSET 24
+#define PINCTRL_DRIVE9_BANK2_PIN13_V (1 << 22)
+#define PINCTRL_DRIVE9_BANK2_PIN13_MA_MASK (0x3 << 20)
+#define PINCTRL_DRIVE9_BANK2_PIN13_MA_OFFSET 20
+#define PINCTRL_DRIVE9_BANK2_PIN12_V (1 << 18)
+#define PINCTRL_DRIVE9_BANK2_PIN12_MA_MASK (0x3 << 16)
+#define PINCTRL_DRIVE9_BANK2_PIN12_MA_OFFSET 16
+#define PINCTRL_DRIVE9_BANK2_PIN10_V (1 << 10)
+#define PINCTRL_DRIVE9_BANK2_PIN10_MA_MASK (0x3 << 8)
+#define PINCTRL_DRIVE9_BANK2_PIN10_MA_OFFSET 8
+#define PINCTRL_DRIVE9_BANK2_PIN09_V (1 << 6)
+#define PINCTRL_DRIVE9_BANK2_PIN09_MA_MASK (0x3 << 4)
+#define PINCTRL_DRIVE9_BANK2_PIN09_MA_OFFSET 4
+#define PINCTRL_DRIVE9_BANK2_PIN08_V (1 << 2)
+#define PINCTRL_DRIVE9_BANK2_PIN08_MA_MASK (0x3 << 0)
+#define PINCTRL_DRIVE9_BANK2_PIN08_MA_OFFSET 0
+
+#define PINCTRL_DRIVE10_BANK2_PIN21_V (1 << 22)
+#define PINCTRL_DRIVE10_BANK2_PIN21_MA_MASK (0x3 << 20)
+#define PINCTRL_DRIVE10_BANK2_PIN21_MA_OFFSET 20
+#define PINCTRL_DRIVE10_BANK2_PIN20_V (1 << 18)
+#define PINCTRL_DRIVE10_BANK2_PIN20_MA_MASK (0x3 << 16)
+#define PINCTRL_DRIVE10_BANK2_PIN20_MA_OFFSET 16
+#define PINCTRL_DRIVE10_BANK2_PIN19_V (1 << 14)
+#define PINCTRL_DRIVE10_BANK2_PIN19_MA_MASK (0x3 << 12)
+#define PINCTRL_DRIVE10_BANK2_PIN19_MA_OFFSET 12
+#define PINCTRL_DRIVE10_BANK2_PIN18_V (1 << 10)
+#define PINCTRL_DRIVE10_BANK2_PIN18_MA_MASK (0x3 << 8)
+#define PINCTRL_DRIVE10_BANK2_PIN18_MA_OFFSET 8
+#define PINCTRL_DRIVE10_BANK2_PIN17_V (1 << 6)
+#define PINCTRL_DRIVE10_BANK2_PIN17_MA_MASK (0x3 << 4)
+#define PINCTRL_DRIVE10_BANK2_PIN17_MA_OFFSET 4
+#define PINCTRL_DRIVE10_BANK2_PIN16_V (1 << 2)
+#define PINCTRL_DRIVE10_BANK2_PIN16_MA_MASK (0x3 << 0)
+#define PINCTRL_DRIVE10_BANK2_PIN16_MA_OFFSET 0
+
+#define PINCTRL_DRIVE11_BANK2_PIN27_V (1 << 14)
+#define PINCTRL_DRIVE11_BANK2_PIN27_MA_MASK (0x3 << 12)
+#define PINCTRL_DRIVE11_BANK2_PIN27_MA_OFFSET 12
+#define PINCTRL_DRIVE11_BANK2_PIN26_V (1 << 10)
+#define PINCTRL_DRIVE11_BANK2_PIN26_MA_MASK (0x3 << 8)
+#define PINCTRL_DRIVE11_BANK2_PIN26_MA_OFFSET 8
+#define PINCTRL_DRIVE11_BANK2_PIN25_V (1 << 6)
+#define PINCTRL_DRIVE11_BANK2_PIN25_MA_MASK (0x3 << 4)
+#define PINCTRL_DRIVE11_BANK2_PIN25_MA_OFFSET 4
+#define PINCTRL_DRIVE11_BANK2_PIN24_V (1 << 2)
+#define PINCTRL_DRIVE11_BANK2_PIN24_MA_MASK (0x3 << 0)
+#define PINCTRL_DRIVE11_BANK2_PIN24_MA_OFFSET 0
+
+#define PINCTRL_DRIVE12_BANK3_PIN07_V (1 << 30)
+#define PINCTRL_DRIVE12_BANK3_PIN07_MA_MASK (0x3 << 28)
+#define PINCTRL_DRIVE12_BANK3_PIN07_MA_OFFSET 28
+#define PINCTRL_DRIVE12_BANK3_PIN06_V (1 << 26)
+#define PINCTRL_DRIVE12_BANK3_PIN06_MA_MASK (0x3 << 24)
+#define PINCTRL_DRIVE12_BANK3_PIN06_MA_OFFSET 24
+#define PINCTRL_DRIVE12_BANK3_PIN05_V (1 << 22)
+#define PINCTRL_DRIVE12_BANK3_PIN05_MA_MASK (0x3 << 20)
+#define PINCTRL_DRIVE12_BANK3_PIN05_MA_OFFSET 20
+#define PINCTRL_DRIVE12_BANK3_PIN04_V (1 << 18)
+#define PINCTRL_DRIVE12_BANK3_PIN04_MA_MASK (0x3 << 16)
+#define PINCTRL_DRIVE12_BANK3_PIN04_MA_OFFSET 16
+#define PINCTRL_DRIVE12_BANK3_PIN03_V (1 << 14)
+#define PINCTRL_DRIVE12_BANK3_PIN03_MA_MASK (0x3 << 12)
+#define PINCTRL_DRIVE12_BANK3_PIN03_MA_OFFSET 12
+#define PINCTRL_DRIVE12_BANK3_PIN02_V (1 << 10)
+#define PINCTRL_DRIVE12_BANK3_PIN02_MA_MASK (0x3 << 8)
+#define PINCTRL_DRIVE12_BANK3_PIN02_MA_OFFSET 8
+#define PINCTRL_DRIVE12_BANK3_PIN01_V (1 << 6)
+#define PINCTRL_DRIVE12_BANK3_PIN01_MA_MASK (0x3 << 4)
+#define PINCTRL_DRIVE12_BANK3_PIN01_MA_OFFSET 4
+#define PINCTRL_DRIVE12_BANK3_PIN00_V (1 << 2)
+#define PINCTRL_DRIVE12_BANK3_PIN00_MA_MASK (0x3 << 0)
+#define PINCTRL_DRIVE12_BANK3_PIN00_MA_OFFSET 0
+
+#define PINCTRL_DRIVE13_BANK3_PIN15_V (1 << 30)
+#define PINCTRL_DRIVE13_BANK3_PIN15_MA_MASK (0x3 << 28)
+#define PINCTRL_DRIVE13_BANK3_PIN15_MA_OFFSET 28
+#define PINCTRL_DRIVE13_BANK3_PIN14_V (1 << 26)
+#define PINCTRL_DRIVE13_BANK3_PIN14_MA_MASK (0x3 << 24)
+#define PINCTRL_DRIVE13_BANK3_PIN14_MA_OFFSET 24
+#define PINCTRL_DRIVE13_BANK3_PIN13_V (1 << 22)
+#define PINCTRL_DRIVE13_BANK3_PIN13_MA_MASK (0x3 << 20)
+#define PINCTRL_DRIVE13_BANK3_PIN13_MA_OFFSET 20
+#define PINCTRL_DRIVE13_BANK3_PIN12_V (1 << 18)
+#define PINCTRL_DRIVE13_BANK3_PIN12_MA_MASK (0x3 << 16)
+#define PINCTRL_DRIVE13_BANK3_PIN12_MA_OFFSET 16
+#define PINCTRL_DRIVE13_BANK3_PIN11_V (1 << 14)
+#define PINCTRL_DRIVE13_BANK3_PIN11_MA_MASK (0x3 << 12)
+#define PINCTRL_DRIVE13_BANK3_PIN11_MA_OFFSET 12
+#define PINCTRL_DRIVE13_BANK3_PIN10_V (1 << 10)
+#define PINCTRL_DRIVE13_BANK3_PIN10_MA_MASK (0x3 << 8)
+#define PINCTRL_DRIVE13_BANK3_PIN10_MA_OFFSET 8
+#define PINCTRL_DRIVE13_BANK3_PIN09_V (1 << 6)
+#define PINCTRL_DRIVE13_BANK3_PIN09_MA_MASK (0x3 << 4)
+#define PINCTRL_DRIVE13_BANK3_PIN09_MA_OFFSET 4
+#define PINCTRL_DRIVE13_BANK3_PIN08_V (1 << 2)
+#define PINCTRL_DRIVE13_BANK3_PIN08_MA_MASK (0x3 << 0)
+#define PINCTRL_DRIVE13_BANK3_PIN08_MA_OFFSET 0
+
+#define PINCTRL_DRIVE14_BANK3_PIN23_V (1 << 30)
+#define PINCTRL_DRIVE14_BANK3_PIN23_MA_MASK (0x3 << 28)
+#define PINCTRL_DRIVE14_BANK3_PIN23_MA_OFFSET 28
+#define PINCTRL_DRIVE14_BANK3_PIN22_V (1 << 26)
+#define PINCTRL_DRIVE14_BANK3_PIN22_MA_MASK (0x3 << 24)
+#define PINCTRL_DRIVE14_BANK3_PIN22_MA_OFFSET 24
+#define PINCTRL_DRIVE14_BANK3_PIN21_V (1 << 22)
+#define PINCTRL_DRIVE14_BANK3_PIN21_MA_MASK (0x3 << 20)
+#define PINCTRL_DRIVE14_BANK3_PIN21_MA_OFFSET 20
+#define PINCTRL_DRIVE14_BANK3_PIN20_V (1 << 18)
+#define PINCTRL_DRIVE14_BANK3_PIN20_MA_MASK (0x3 << 16)
+#define PINCTRL_DRIVE14_BANK3_PIN20_MA_OFFSET 16
+#define PINCTRL_DRIVE14_BANK3_PIN18_V (1 << 10)
+#define PINCTRL_DRIVE14_BANK3_PIN18_MA_MASK (0x3 << 8)
+#define PINCTRL_DRIVE14_BANK3_PIN18_MA_OFFSET 8
+#define PINCTRL_DRIVE14_BANK3_PIN17_V (1 << 6)
+#define PINCTRL_DRIVE14_BANK3_PIN17_MA_MASK (0x3 << 4)
+#define PINCTRL_DRIVE14_BANK3_PIN17_MA_OFFSET 4
+#define PINCTRL_DRIVE14_BANK3_PIN16_V (1 << 2)
+#define PINCTRL_DRIVE14_BANK3_PIN16_MA_MASK (0x3 << 0)
+#define PINCTRL_DRIVE14_BANK3_PIN16_MA_OFFSET 0
+
+#define PINCTRL_DRIVE15_BANK3_PIN30_V (1 << 26)
+#define PINCTRL_DRIVE15_BANK3_PIN30_MA_MASK (0x3 << 24)
+#define PINCTRL_DRIVE15_BANK3_PIN30_MA_OFFSET 24
+#define PINCTRL_DRIVE15_BANK3_PIN29_V (1 << 22)
+#define PINCTRL_DRIVE15_BANK3_PIN29_MA_MASK (0x3 << 20)
+#define PINCTRL_DRIVE15_BANK3_PIN29_MA_OFFSET 20
+#define PINCTRL_DRIVE15_BANK3_PIN28_V (1 << 18)
+#define PINCTRL_DRIVE15_BANK3_PIN28_MA_MASK (0x3 << 16)
+#define PINCTRL_DRIVE15_BANK3_PIN28_MA_OFFSET 16
+#define PINCTRL_DRIVE15_BANK3_PIN27_V (1 << 14)
+#define PINCTRL_DRIVE15_BANK3_PIN27_MA_MASK (0x3 << 12)
+#define PINCTRL_DRIVE15_BANK3_PIN27_MA_OFFSET 12
+#define PINCTRL_DRIVE15_BANK3_PIN26_V (1 << 10)
+#define PINCTRL_DRIVE15_BANK3_PIN26_MA_MASK (0x3 << 8)
+#define PINCTRL_DRIVE15_BANK3_PIN26_MA_OFFSET 8
+#define PINCTRL_DRIVE15_BANK3_PIN25_V (1 << 6)
+#define PINCTRL_DRIVE15_BANK3_PIN25_MA_MASK (0x3 << 4)
+#define PINCTRL_DRIVE15_BANK3_PIN25_MA_OFFSET 4
+#define PINCTRL_DRIVE15_BANK3_PIN24_V (1 << 2)
+#define PINCTRL_DRIVE15_BANK3_PIN24_MA_MASK (0x3 << 0)
+#define PINCTRL_DRIVE15_BANK3_PIN24_MA_OFFSET 0
+
+#define PINCTRL_DRIVE16_BANK4_PIN07_V (1 << 30)
+#define PINCTRL_DRIVE16_BANK4_PIN07_MA_MASK (0x3 << 28)
+#define PINCTRL_DRIVE16_BANK4_PIN07_MA_OFFSET 28
+#define PINCTRL_DRIVE16_BANK4_PIN06_V (1 << 26)
+#define PINCTRL_DRIVE16_BANK4_PIN06_MA_MASK (0x3 << 24)
+#define PINCTRL_DRIVE16_BANK4_PIN06_MA_OFFSET 24
+#define PINCTRL_DRIVE16_BANK4_PIN05_V (1 << 22)
+#define PINCTRL_DRIVE16_BANK4_PIN05_MA_MASK (0x3 << 20)
+#define PINCTRL_DRIVE16_BANK4_PIN05_MA_OFFSET 20
+#define PINCTRL_DRIVE16_BANK4_PIN04_V (1 << 18)
+#define PINCTRL_DRIVE16_BANK4_PIN04_MA_MASK (0x3 << 16)
+#define PINCTRL_DRIVE16_BANK4_PIN04_MA_OFFSET 16
+#define PINCTRL_DRIVE16_BANK4_PIN03_V (1 << 14)
+#define PINCTRL_DRIVE16_BANK4_PIN03_MA_MASK (0x3 << 12)
+#define PINCTRL_DRIVE16_BANK4_PIN03_MA_OFFSET 12
+#define PINCTRL_DRIVE16_BANK4_PIN02_V (1 << 10)
+#define PINCTRL_DRIVE16_BANK4_PIN02_MA_MASK (0x3 << 8)
+#define PINCTRL_DRIVE16_BANK4_PIN02_MA_OFFSET 8
+#define PINCTRL_DRIVE16_BANK4_PIN01_V (1 << 6)
+#define PINCTRL_DRIVE16_BANK4_PIN01_MA_MASK (0x3 << 4)
+#define PINCTRL_DRIVE16_BANK4_PIN01_MA_OFFSET 4
+#define PINCTRL_DRIVE16_BANK4_PIN00_V (1 << 2)
+#define PINCTRL_DRIVE16_BANK4_PIN00_MA_MASK (0x3 << 0)
+#define PINCTRL_DRIVE16_BANK4_PIN00_MA_OFFSET 0
+
+#define PINCTRL_DRIVE17_BANK4_PIN15_V (1 << 30)
+#define PINCTRL_DRIVE17_BANK4_PIN15_MA_MASK (0x3 << 28)
+#define PINCTRL_DRIVE17_BANK4_PIN15_MA_OFFSET 28
+#define PINCTRL_DRIVE17_BANK4_PIN14_V (1 << 26)
+#define PINCTRL_DRIVE17_BANK4_PIN14_MA_MASK (0x3 << 24)
+#define PINCTRL_DRIVE17_BANK4_PIN14_MA_OFFSET 24
+#define PINCTRL_DRIVE17_BANK4_PIN13_V (1 << 22)
+#define PINCTRL_DRIVE17_BANK4_PIN13_MA_MASK (0x3 << 20)
+#define PINCTRL_DRIVE17_BANK4_PIN13_MA_OFFSET 20
+#define PINCTRL_DRIVE17_BANK4_PIN12_V (1 << 18)
+#define PINCTRL_DRIVE17_BANK4_PIN12_MA_MASK (0x3 << 16)
+#define PINCTRL_DRIVE17_BANK4_PIN12_MA_OFFSET 16
+#define PINCTRL_DRIVE17_BANK4_PIN11_V (1 << 14)
+#define PINCTRL_DRIVE17_BANK4_PIN11_MA_MASK (0x3 << 12)
+#define PINCTRL_DRIVE17_BANK4_PIN11_MA_OFFSET 12
+#define PINCTRL_DRIVE17_BANK4_PIN10_V (1 << 10)
+#define PINCTRL_DRIVE17_BANK4_PIN10_MA_MASK (0x3 << 8)
+#define PINCTRL_DRIVE17_BANK4_PIN10_MA_OFFSET 8
+#define PINCTRL_DRIVE17_BANK4_PIN09_V (1 << 6)
+#define PINCTRL_DRIVE17_BANK4_PIN09_MA_MASK (0x3 << 4)
+#define PINCTRL_DRIVE17_BANK4_PIN09_MA_OFFSET 4
+#define PINCTRL_DRIVE17_BANK4_PIN08_V (1 << 2)
+#define PINCTRL_DRIVE17_BANK4_PIN08_MA_MASK (0x3 << 0)
+#define PINCTRL_DRIVE17_BANK4_PIN08_MA_OFFSET 0
+
+#define PINCTRL_DRIVE18_BANK4_PIN20_V (1 << 18)
+#define PINCTRL_DRIVE18_BANK4_PIN20_MA_MASK (0x3 << 16)
+#define PINCTRL_DRIVE18_BANK4_PIN20_MA_OFFSET 16
+#define PINCTRL_DRIVE18_BANK4_PIN16_V (1 << 2)
+#define PINCTRL_DRIVE18_BANK4_PIN16_MA_MASK (0x3 << 0)
+#define PINCTRL_DRIVE18_BANK4_PIN16_MA_OFFSET 0
+
+#define PINCTRL_PULL0_BANK0_PIN28 (1 << 28)
+#define PINCTRL_PULL0_BANK0_PIN27 (1 << 27)
+#define PINCTRL_PULL0_BANK0_PIN26 (1 << 26)
+#define PINCTRL_PULL0_BANK0_PIN25 (1 << 25)
+#define PINCTRL_PULL0_BANK0_PIN24 (1 << 24)
+#define PINCTRL_PULL0_BANK0_PIN23 (1 << 23)
+#define PINCTRL_PULL0_BANK0_PIN22 (1 << 22)
+#define PINCTRL_PULL0_BANK0_PIN21 (1 << 21)
+#define PINCTRL_PULL0_BANK0_PIN20 (1 << 20)
+#define PINCTRL_PULL0_BANK0_PIN19 (1 << 19)
+#define PINCTRL_PULL0_BANK0_PIN18 (1 << 18)
+#define PINCTRL_PULL0_BANK0_PIN17 (1 << 17)
+#define PINCTRL_PULL0_BANK0_PIN16 (1 << 16)
+#define PINCTRL_PULL0_BANK0_PIN07 (1 << 7)
+#define PINCTRL_PULL0_BANK0_PIN06 (1 << 6)
+#define PINCTRL_PULL0_BANK0_PIN05 (1 << 5)
+#define PINCTRL_PULL0_BANK0_PIN04 (1 << 4)
+#define PINCTRL_PULL0_BANK0_PIN03 (1 << 3)
+#define PINCTRL_PULL0_BANK0_PIN02 (1 << 2)
+#define PINCTRL_PULL0_BANK0_PIN01 (1 << 1)
+#define PINCTRL_PULL0_BANK0_PIN00 (1 << 0)
+
+#define PINCTRL_PULL1_BANK1_PIN31 (1 << 31)
+#define PINCTRL_PULL1_BANK1_PIN30 (1 << 30)
+#define PINCTRL_PULL1_BANK1_PIN29 (1 << 29)
+#define PINCTRL_PULL1_BANK1_PIN28 (1 << 28)
+#define PINCTRL_PULL1_BANK1_PIN27 (1 << 27)
+#define PINCTRL_PULL1_BANK1_PIN26 (1 << 26)
+#define PINCTRL_PULL1_BANK1_PIN25 (1 << 25)
+#define PINCTRL_PULL1_BANK1_PIN24 (1 << 24)
+#define PINCTRL_PULL1_BANK1_PIN23 (1 << 23)
+#define PINCTRL_PULL1_BANK1_PIN22 (1 << 22)
+#define PINCTRL_PULL1_BANK1_PIN21 (1 << 21)
+#define PINCTRL_PULL1_BANK1_PIN20 (1 << 20)
+#define PINCTRL_PULL1_BANK1_PIN19 (1 << 19)
+#define PINCTRL_PULL1_BANK1_PIN18 (1 << 18)
+#define PINCTRL_PULL1_BANK1_PIN17 (1 << 17)
+#define PINCTRL_PULL1_BANK1_PIN16 (1 << 16)
+#define PINCTRL_PULL1_BANK1_PIN15 (1 << 15)
+#define PINCTRL_PULL1_BANK1_PIN14 (1 << 14)
+#define PINCTRL_PULL1_BANK1_PIN13 (1 << 13)
+#define PINCTRL_PULL1_BANK1_PIN12 (1 << 12)
+#define PINCTRL_PULL1_BANK1_PIN11 (1 << 11)
+#define PINCTRL_PULL1_BANK1_PIN10 (1 << 10)
+#define PINCTRL_PULL1_BANK1_PIN09 (1 << 9)
+#define PINCTRL_PULL1_BANK1_PIN08 (1 << 8)
+#define PINCTRL_PULL1_BANK1_PIN07 (1 << 7)
+#define PINCTRL_PULL1_BANK1_PIN06 (1 << 6)
+#define PINCTRL_PULL1_BANK1_PIN05 (1 << 5)
+#define PINCTRL_PULL1_BANK1_PIN04 (1 << 4)
+#define PINCTRL_PULL1_BANK1_PIN03 (1 << 3)
+#define PINCTRL_PULL1_BANK1_PIN02 (1 << 2)
+#define PINCTRL_PULL1_BANK1_PIN01 (1 << 1)
+#define PINCTRL_PULL1_BANK1_PIN00 (1 << 0)
+
+#define PINCTRL_PULL2_BANK2_PIN27 (1 << 27)
+#define PINCTRL_PULL2_BANK2_PIN26 (1 << 26)
+#define PINCTRL_PULL2_BANK2_PIN25 (1 << 25)
+#define PINCTRL_PULL2_BANK2_PIN24 (1 << 24)
+#define PINCTRL_PULL2_BANK2_PIN21 (1 << 21)
+#define PINCTRL_PULL2_BANK2_PIN20 (1 << 20)
+#define PINCTRL_PULL2_BANK2_PIN19 (1 << 19)
+#define PINCTRL_PULL2_BANK2_PIN18 (1 << 18)
+#define PINCTRL_PULL2_BANK2_PIN17 (1 << 17)
+#define PINCTRL_PULL2_BANK2_PIN16 (1 << 16)
+#define PINCTRL_PULL2_BANK2_PIN15 (1 << 15)
+#define PINCTRL_PULL2_BANK2_PIN14 (1 << 14)
+#define PINCTRL_PULL2_BANK2_PIN13 (1 << 13)
+#define PINCTRL_PULL2_BANK2_PIN12 (1 << 12)
+#define PINCTRL_PULL2_BANK2_PIN10 (1 << 10)
+#define PINCTRL_PULL2_BANK2_PIN09 (1 << 9)
+#define PINCTRL_PULL2_BANK2_PIN08 (1 << 8)
+#define PINCTRL_PULL2_BANK2_PIN07 (1 << 7)
+#define PINCTRL_PULL2_BANK2_PIN06 (1 << 6)
+#define PINCTRL_PULL2_BANK2_PIN05 (1 << 5)
+#define PINCTRL_PULL2_BANK2_PIN04 (1 << 4)
+#define PINCTRL_PULL2_BANK2_PIN03 (1 << 3)
+#define PINCTRL_PULL2_BANK2_PIN02 (1 << 2)
+#define PINCTRL_PULL2_BANK2_PIN01 (1 << 1)
+#define PINCTRL_PULL2_BANK2_PIN00 (1 << 0)
+
+#define PINCTRL_PULL3_BANK3_PIN30 (1 << 30)
+#define PINCTRL_PULL3_BANK3_PIN29 (1 << 29)
+#define PINCTRL_PULL3_BANK3_PIN28 (1 << 28)
+#define PINCTRL_PULL3_BANK3_PIN27 (1 << 27)
+#define PINCTRL_PULL3_BANK3_PIN26 (1 << 26)
+#define PINCTRL_PULL3_BANK3_PIN25 (1 << 25)
+#define PINCTRL_PULL3_BANK3_PIN24 (1 << 24)
+#define PINCTRL_PULL3_BANK3_PIN23 (1 << 23)
+#define PINCTRL_PULL3_BANK3_PIN22 (1 << 22)
+#define PINCTRL_PULL3_BANK3_PIN21 (1 << 21)
+#define PINCTRL_PULL3_BANK3_PIN20 (1 << 20)
+#define PINCTRL_PULL3_BANK3_PIN18 (1 << 18)
+#define PINCTRL_PULL3_BANK3_PIN17 (1 << 17)
+#define PINCTRL_PULL3_BANK3_PIN16 (1 << 16)
+#define PINCTRL_PULL3_BANK3_PIN15 (1 << 15)
+#define PINCTRL_PULL3_BANK3_PIN14 (1 << 14)
+#define PINCTRL_PULL3_BANK3_PIN13 (1 << 13)
+#define PINCTRL_PULL3_BANK3_PIN12 (1 << 12)
+#define PINCTRL_PULL3_BANK3_PIN11 (1 << 11)
+#define PINCTRL_PULL3_BANK3_PIN10 (1 << 10)
+#define PINCTRL_PULL3_BANK3_PIN09 (1 << 9)
+#define PINCTRL_PULL3_BANK3_PIN08 (1 << 8)
+#define PINCTRL_PULL3_BANK3_PIN07 (1 << 7)
+#define PINCTRL_PULL3_BANK3_PIN06 (1 << 6)
+#define PINCTRL_PULL3_BANK3_PIN05 (1 << 5)
+#define PINCTRL_PULL3_BANK3_PIN04 (1 << 4)
+#define PINCTRL_PULL3_BANK3_PIN03 (1 << 3)
+#define PINCTRL_PULL3_BANK3_PIN02 (1 << 2)
+#define PINCTRL_PULL3_BANK3_PIN01 (1 << 1)
+#define PINCTRL_PULL3_BANK3_PIN00 (1 << 0)
+
+#define PINCTRL_PULL4_BANK4_PIN20 (1 << 20)
+#define PINCTRL_PULL4_BANK4_PIN16 (1 << 16)
+#define PINCTRL_PULL4_BANK4_PIN15 (1 << 15)
+#define PINCTRL_PULL4_BANK4_PIN14 (1 << 14)
+#define PINCTRL_PULL4_BANK4_PIN13 (1 << 13)
+#define PINCTRL_PULL4_BANK4_PIN12 (1 << 12)
+#define PINCTRL_PULL4_BANK4_PIN11 (1 << 11)
+#define PINCTRL_PULL4_BANK4_PIN10 (1 << 10)
+#define PINCTRL_PULL4_BANK4_PIN09 (1 << 9)
+#define PINCTRL_PULL4_BANK4_PIN08 (1 << 8)
+#define PINCTRL_PULL4_BANK4_PIN07 (1 << 7)
+#define PINCTRL_PULL4_BANK4_PIN06 (1 << 6)
+#define PINCTRL_PULL4_BANK4_PIN05 (1 << 5)
+#define PINCTRL_PULL4_BANK4_PIN04 (1 << 4)
+#define PINCTRL_PULL4_BANK4_PIN03 (1 << 3)
+#define PINCTRL_PULL4_BANK4_PIN02 (1 << 2)
+#define PINCTRL_PULL4_BANK4_PIN01 (1 << 1)
+#define PINCTRL_PULL4_BANK4_PIN00 (1 << 0)
+
+#define PINCTRL_PULL5_BANK5_PIN26 (1 << 26)
+#define PINCTRL_PULL5_BANK5_PIN23 (1 << 23)
+#define PINCTRL_PULL5_BANK5_PIN22 (1 << 22)
+#define PINCTRL_PULL5_BANK5_PIN21 (1 << 21)
+#define PINCTRL_PULL5_BANK5_PIN20 (1 << 20)
+#define PINCTRL_PULL5_BANK5_PIN19 (1 << 19)
+#define PINCTRL_PULL5_BANK5_PIN18 (1 << 18)
+#define PINCTRL_PULL5_BANK5_PIN17 (1 << 17)
+#define PINCTRL_PULL5_BANK5_PIN16 (1 << 16)
+#define PINCTRL_PULL5_BANK5_PIN15 (1 << 15)
+#define PINCTRL_PULL5_BANK5_PIN14 (1 << 14)
+#define PINCTRL_PULL5_BANK5_PIN13 (1 << 13)
+#define PINCTRL_PULL5_BANK5_PIN12 (1 << 12)
+#define PINCTRL_PULL5_BANK5_PIN11 (1 << 11)
+#define PINCTRL_PULL5_BANK5_PIN10 (1 << 10)
+#define PINCTRL_PULL5_BANK5_PIN09 (1 << 9)
+#define PINCTRL_PULL5_BANK5_PIN08 (1 << 8)
+#define PINCTRL_PULL5_BANK5_PIN07 (1 << 7)
+#define PINCTRL_PULL5_BANK5_PIN06 (1 << 6)
+#define PINCTRL_PULL5_BANK5_PIN05 (1 << 5)
+#define PINCTRL_PULL5_BANK5_PIN04 (1 << 4)
+#define PINCTRL_PULL5_BANK5_PIN03 (1 << 3)
+#define PINCTRL_PULL5_BANK5_PIN02 (1 << 2)
+#define PINCTRL_PULL5_BANK5_PIN01 (1 << 1)
+#define PINCTRL_PULL5_BANK5_PIN00 (1 << 0)
+
+#define PINCTRL_PULL6_BANK6_PIN24 (1 << 24)
+#define PINCTRL_PULL6_BANK6_PIN23 (1 << 23)
+#define PINCTRL_PULL6_BANK6_PIN22 (1 << 22)
+#define PINCTRL_PULL6_BANK6_PIN21 (1 << 21)
+#define PINCTRL_PULL6_BANK6_PIN20 (1 << 20)
+#define PINCTRL_PULL6_BANK6_PIN19 (1 << 19)
+#define PINCTRL_PULL6_BANK6_PIN18 (1 << 18)
+#define PINCTRL_PULL6_BANK6_PIN17 (1 << 17)
+#define PINCTRL_PULL6_BANK6_PIN16 (1 << 16)
+#define PINCTRL_PULL6_BANK6_PIN14 (1 << 14)
+#define PINCTRL_PULL6_BANK6_PIN13 (1 << 13)
+#define PINCTRL_PULL6_BANK6_PIN12 (1 << 12)
+#define PINCTRL_PULL6_BANK6_PIN11 (1 << 11)
+#define PINCTRL_PULL6_BANK6_PIN10 (1 << 10)
+#define PINCTRL_PULL6_BANK6_PIN09 (1 << 9)
+#define PINCTRL_PULL6_BANK6_PIN08 (1 << 8)
+#define PINCTRL_PULL6_BANK6_PIN07 (1 << 7)
+#define PINCTRL_PULL6_BANK6_PIN06 (1 << 6)
+#define PINCTRL_PULL6_BANK6_PIN05 (1 << 5)
+#define PINCTRL_PULL6_BANK6_PIN04 (1 << 4)
+#define PINCTRL_PULL6_BANK6_PIN03 (1 << 3)
+#define PINCTRL_PULL6_BANK6_PIN02 (1 << 2)
+#define PINCTRL_PULL6_BANK6_PIN01 (1 << 1)
+#define PINCTRL_PULL6_BANK6_PIN00 (1 << 0)
+
+#define PINCTRL_DOUT0_DOUT_MASK 0x1fffffff
+#define PINCTRL_DOUT0_DOUT_OFFSET 0
+
+#define PINCTRL_DOUT1_DOUT_MASK 0xffffffff
+#define PINCTRL_DOUT1_DOUT_OFFSET 0
+
+#define PINCTRL_DOUT2_DOUT_MASK 0xfffffff
+#define PINCTRL_DOUT2_DOUT_OFFSET 0
+
+#define PINCTRL_DOUT3_DOUT_MASK 0x7fffffff
+#define PINCTRL_DOUT3_DOUT_OFFSET 0
+
+#define PINCTRL_DOUT4_DOUT_MASK 0x1fffff
+#define PINCTRL_DOUT4_DOUT_OFFSET 0
+
+#define PINCTRL_DIN0_DIN_MASK 0x1fffffff
+#define PINCTRL_DIN0_DIN_OFFSET 0
+
+#define PINCTRL_DIN1_DIN_MASK 0xffffffff
+#define PINCTRL_DIN1_DIN_OFFSET 0
+
+#define PINCTRL_DIN2_DIN_MASK 0xfffffff
+#define PINCTRL_DIN2_DIN_OFFSET 0
+
+#define PINCTRL_DIN3_DIN_MASK 0x7fffffff
+#define PINCTRL_DIN3_DIN_OFFSET 0
+
+#define PINCTRL_DIN4_DIN_MASK 0x1fffff
+#define PINCTRL_DIN4_DIN_OFFSET 0
+
+#define PINCTRL_DOE0_DOE_MASK 0x1fffffff
+#define PINCTRL_DOE0_DOE_OFFSET 0
+
+#define PINCTRL_DOE1_DOE_MASK 0xffffffff
+#define PINCTRL_DOE1_DOE_OFFSET 0
+
+#define PINCTRL_DOE2_DOE_MASK 0xfffffff
+#define PINCTRL_DOE2_DOE_OFFSET 0
+
+#define PINCTRL_DOE3_DOE_MASK 0x7fffffff
+#define PINCTRL_DOE3_DOE_OFFSET 0
+
+#define PINCTRL_DOE4_DOE_MASK 0x1fffff
+#define PINCTRL_DOE4_DOE_OFFSET 0
+
+#define PINCTRL_PIN2IRQ0_PIN2IRQ_MASK 0x1fffffff
+#define PINCTRL_PIN2IRQ0_PIN2IRQ_OFFSET 0
+
+#define PINCTRL_PIN2IRQ1_PIN2IRQ_MASK 0xffffffff
+#define PINCTRL_PIN2IRQ1_PIN2IRQ_OFFSET 0
+
+#define PINCTRL_PIN2IRQ2_PIN2IRQ_MASK 0xfffffff
+#define PINCTRL_PIN2IRQ2_PIN2IRQ_OFFSET 0
+
+#define PINCTRL_PIN2IRQ3_PIN2IRQ_MASK 0x7fffffff
+#define PINCTRL_PIN2IRQ3_PIN2IRQ_OFFSET 0
+
+#define PINCTRL_PIN2IRQ4_PIN2IRQ_MASK 0x1fffff
+#define PINCTRL_PIN2IRQ4_PIN2IRQ_OFFSET 0
+
+#define PINCTRL_IRQEN0_IRQEN_MASK 0x1fffffff
+#define PINCTRL_IRQEN0_IRQEN_OFFSET 0
+
+#define PINCTRL_IRQEN1_IRQEN_MASK 0xffffffff
+#define PINCTRL_IRQEN1_IRQEN_OFFSET 0
+
+#define PINCTRL_IRQEN2_IRQEN_MASK 0xfffffff
+#define PINCTRL_IRQEN2_IRQEN_OFFSET 0
+
+#define PINCTRL_IRQEN3_IRQEN_MASK 0x7fffffff
+#define PINCTRL_IRQEN3_IRQEN_OFFSET 0
+
+#define PINCTRL_IRQEN4_IRQEN_MASK 0x1fffff
+#define PINCTRL_IRQEN4_IRQEN_OFFSET 0
+
+#define PINCTRL_IRQLEVEL0_IRQLEVEL_MASK 0x1fffffff
+#define PINCTRL_IRQLEVEL0_IRQLEVEL_OFFSET 0
+
+#define PINCTRL_IRQLEVEL1_IRQLEVEL_MASK 0xffffffff
+#define PINCTRL_IRQLEVEL1_IRQLEVEL_OFFSET 0
+
+#define PINCTRL_IRQLEVEL2_IRQLEVEL_MASK 0xfffffff
+#define PINCTRL_IRQLEVEL2_IRQLEVEL_OFFSET 0
+
+#define PINCTRL_IRQLEVEL3_IRQLEVEL_MASK 0x7fffffff
+#define PINCTRL_IRQLEVEL3_IRQLEVEL_OFFSET 0
+
+#define PINCTRL_IRQLEVEL4_IRQLEVEL_MASK 0x1fffff
+#define PINCTRL_IRQLEVEL4_IRQLEVEL_OFFSET 0
+
+#define PINCTRL_IRQPOL0_IRQPOL_MASK 0x1fffffff
+#define PINCTRL_IRQPOL0_IRQPOL_OFFSET 0
+
+#define PINCTRL_IRQPOL1_IRQPOL_MASK 0xffffffff
+#define PINCTRL_IRQPOL1_IRQPOL_OFFSET 0
+
+#define PINCTRL_IRQPOL2_IRQPOL_MASK 0xfffffff
+#define PINCTRL_IRQPOL2_IRQPOL_OFFSET 0
+
+#define PINCTRL_IRQPOL3_IRQPOL_MASK 0x7fffffff
+#define PINCTRL_IRQPOL3_IRQPOL_OFFSET 0
+
+#define PINCTRL_IRQPOL4_IRQPOL_MASK 0x1fffff
+#define PINCTRL_IRQPOL4_IRQPOL_OFFSET 0
+
+#define PINCTRL_IRQSTAT0_IRQSTAT_MASK 0x1fffffff
+#define PINCTRL_IRQSTAT0_IRQSTAT_OFFSET 0
+
+#define PINCTRL_IRQSTAT1_IRQSTAT_MASK 0xffffffff
+#define PINCTRL_IRQSTAT1_IRQSTAT_OFFSET 0
+
+#define PINCTRL_IRQSTAT2_IRQSTAT_MASK 0xfffffff
+#define PINCTRL_IRQSTAT2_IRQSTAT_OFFSET 0
+
+#define PINCTRL_IRQSTAT3_IRQSTAT_MASK 0x7fffffff
+#define PINCTRL_IRQSTAT3_IRQSTAT_OFFSET 0
+
+#define PINCTRL_IRQSTAT4_IRQSTAT_MASK 0x1fffff
+#define PINCTRL_IRQSTAT4_IRQSTAT_OFFSET 0
+
+#define PINCTRL_EMI_ODT_CTRL_ADDRESS_CALIB_MASK (0x3 << 26)
+#define PINCTRL_EMI_ODT_CTRL_ADDRESS_CALIB_OFFSET 26
+#define PINCTRL_EMI_ODT_CTRL_ADDRESS_TLOAD_MASK (0x3 << 24)
+#define PINCTRL_EMI_ODT_CTRL_ADDRESS_TLOAD_OFFSET 24
+#define PINCTRL_EMI_ODT_CTRL_CONTROL_CALIB_MASK (0x3 << 22)
+#define PINCTRL_EMI_ODT_CTRL_CONTROL_CALIB_OFFSET 22
+#define PINCTRL_EMI_ODT_CTRL_CONTROL_TLOAD_MASK (0x3 << 20)
+#define PINCTRL_EMI_ODT_CTRL_CONTROL_TLOAD_OFFSET 20
+#define PINCTRL_EMI_ODT_CTRL_DUALPAD_CALIB_MASK (0x3 << 18)
+#define PINCTRL_EMI_ODT_CTRL_DUALPAD_CALIB_OFFSET 18
+#define PINCTRL_EMI_ODT_CTRL_DUALPAD_TLOAD_MASK (0x3 << 16)
+#define PINCTRL_EMI_ODT_CTRL_DUALPAD_TLOAD_OFFSET 16
+#define PINCTRL_EMI_ODT_CTRL_SLICE3_CALIB_MASK (0x3 << 14)
+#define PINCTRL_EMI_ODT_CTRL_SLICE3_CALIB_OFFSET 14
+#define PINCTRL_EMI_ODT_CTRL_SLICE3_TLOAD_MASK (0x3 << 12)
+#define PINCTRL_EMI_ODT_CTRL_SLICE3_TLOAD_OFFSET 12
+#define PINCTRL_EMI_ODT_CTRL_SLICE2_CALIB_MASK (0x3 << 10)
+#define PINCTRL_EMI_ODT_CTRL_SLICE2_CALIB_OFFSET 10
+#define PINCTRL_EMI_ODT_CTRL_SLICE2_TLOAD_MASK (0x3 << 8)
+#define PINCTRL_EMI_ODT_CTRL_SLICE2_TLOAD_OFFSET 8
+#define PINCTRL_EMI_ODT_CTRL_SLICE1_CALIB_MASK (0x3 << 6)
+#define PINCTRL_EMI_ODT_CTRL_SLICE1_CALIB_OFFSET 6
+#define PINCTRL_EMI_ODT_CTRL_SLICE1_TLOAD_MASK (0x3 << 4)
+#define PINCTRL_EMI_ODT_CTRL_SLICE1_TLOAD_OFFSET 4
+#define PINCTRL_EMI_ODT_CTRL_SLICE0_CALIB_MASK (0x3 << 2)
+#define PINCTRL_EMI_ODT_CTRL_SLICE0_CALIB_OFFSET 2
+#define PINCTRL_EMI_ODT_CTRL_SLICE0_TLOAD_MASK (0x3 << 0)
+#define PINCTRL_EMI_ODT_CTRL_SLICE0_TLOAD_OFFSET 0
+
+#define PINCTRL_EMI_DS_CTRL_DDR_MODE_MASK (0x3 << 16)
+#define PINCTRL_EMI_DS_CTRL_DDR_MODE_OFFSET 16
+#define PINCTRL_EMI_DS_CTRL_DDR_MODE_mDDR (0x0 << 16)
+#define PINCTRL_EMI_DS_CTRL_DDR_MODE_GPIO (0x1 << 16)
+#define PINCTRL_EMI_DS_CTRL_DDR_MODE_LVDDR2 (0x2 << 16)
+#define PINCTRL_EMI_DS_CTRL_DDR_MODE_DDR2 (0x3 << 16)
+#define PINCTRL_EMI_DS_CTRL_ADDRESS_MA_MASK (0x3 << 12)
+#define PINCTRL_EMI_DS_CTRL_ADDRESS_MA_OFFSET 12
+#define PINCTRL_EMI_DS_CTRL_CONTROL_MA_MASK (0x3 << 10)
+#define PINCTRL_EMI_DS_CTRL_CONTROL_MA_OFFSET 10
+#define PINCTRL_EMI_DS_CTRL_DUALPAD_MA_MASK (0x3 << 8)
+#define PINCTRL_EMI_DS_CTRL_DUALPAD_MA_OFFSET 8
+#define PINCTRL_EMI_DS_CTRL_SLICE3_MA_MASK (0x3 << 6)
+#define PINCTRL_EMI_DS_CTRL_SLICE3_MA_OFFSET 6
+#define PINCTRL_EMI_DS_CTRL_SLICE2_MA_MASK (0x3 << 4)
+#define PINCTRL_EMI_DS_CTRL_SLICE2_MA_OFFSET 4
+#define PINCTRL_EMI_DS_CTRL_SLICE1_MA_MASK (0x3 << 2)
+#define PINCTRL_EMI_DS_CTRL_SLICE1_MA_OFFSET 2
+#define PINCTRL_EMI_DS_CTRL_SLICE0_MA_MASK (0x3 << 0)
+#define PINCTRL_EMI_DS_CTRL_SLICE0_MA_OFFSET 0
+
+#endif /* __MX28_REGS_PINCTRL_H__ */
diff --git a/arch/arm/include/asm/arch-mx28/regs-power.h b/arch/arm/include/asm/arch-mx28/regs-power.h
new file mode 100644
index 0000000..9da63ad
--- /dev/null
+++ b/arch/arm/include/asm/arch-mx28/regs-power.h
@@ -0,0 +1,413 @@
+/*
+ * Freescale i.MX28 Power Controller Register Definitions
+ *
+ * Copyright (C) 2011 Marek Vasut <marek.vasut@gmail.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
+ *
+ */
+
+#ifndef __MX28_REGS_POWER_H__
+#define __MX28_REGS_POWER_H__
+
+#include <asm/arch/regs-common.h>
+
+#ifndef __ASSEMBLY__
+struct mx28_power_regs {
+ mx28_reg(hw_power_ctrl)
+ mx28_reg(hw_power_5vctrl)
+ mx28_reg(hw_power_minpwr)
+ mx28_reg(hw_power_charge)
+ uint32_t hw_power_vdddctrl;
+ uint32_t reserved_vddd[3];
+ uint32_t hw_power_vddactrl;
+ uint32_t reserved_vdda[3];
+ uint32_t hw_power_vddioctrl;
+ uint32_t reserved_vddio[3];
+ uint32_t hw_power_vddmemctrl;
+ uint32_t reserved_vddmem[3];
+ uint32_t hw_power_dcdc4p2;
+ uint32_t reserved_dcdc4p2[3];
+ uint32_t hw_power_misc;
+ uint32_t reserved_misc[3];
+ uint32_t hw_power_dclimits;
+ uint32_t reserved_dclimits[3];
+ mx28_reg(hw_power_loopctrl)
+ uint32_t hw_power_sts;
+ uint32_t reserved_sts[3];
+ mx28_reg(hw_power_speed)
+ uint32_t hw_power_battmonitor;
+ uint32_t reserved_battmonitor[3];
+
+ uint32_t reserved[4];
+
+ mx28_reg(hw_power_reset)
+ mx28_reg(hw_power_debug)
+ mx28_reg(hw_power_thermal)
+ mx28_reg(hw_power_usb1ctrl)
+ mx28_reg(hw_power_special)
+ mx28_reg(hw_power_version)
+ mx28_reg(hw_power_anaclkctrl)
+ mx28_reg(hw_power_refctrl)
+};
+#endif
+
+#define POWER_CTRL_PSWITCH_MID_TRAN (1 << 27)
+#define POWER_CTRL_DCDC4P2_BO_IRQ (1 << 24)
+#define POWER_CTRL_ENIRQ_DCDC4P2_BO (1 << 23)
+#define POWER_CTRL_VDD5V_DROOP_IRQ (1 << 22)
+#define POWER_CTRL_ENIRQ_VDD5V_DROOP (1 << 21)
+#define POWER_CTRL_PSWITCH_IRQ (1 << 20)
+#define POWER_CTRL_PSWITCH_IRQ_SRC (1 << 19)
+#define POWER_CTRL_POLARITY_PSWITCH (1 << 18)
+#define POWER_CTRL_ENIRQ_PSWITCH (1 << 17)
+#define POWER_CTRL_POLARITY_DC_OK (1 << 16)
+#define POWER_CTRL_DC_OK_IRQ (1 << 15)
+#define POWER_CTRL_ENIRQ_DC_OK (1 << 14)
+#define POWER_CTRL_BATT_BO_IRQ (1 << 13)
+#define POWER_CTRL_ENIRQ_BATT_BO (1 << 12)
+#define POWER_CTRL_VDDIO_BO_IRQ (1 << 11)
+#define POWER_CTRL_ENIRQ_VDDIO_BO (1 << 10)
+#define POWER_CTRL_VDDA_BO_IRQ (1 << 9)
+#define POWER_CTRL_ENIRQ_VDDA_BO (1 << 8)
+#define POWER_CTRL_VDDD_BO_IRQ (1 << 7)
+#define POWER_CTRL_ENIRQ_VDDD_BO (1 << 6)
+#define POWER_CTRL_POLARITY_VBUSVALID (1 << 5)
+#define POWER_CTRL_VBUS_VALID_IRQ (1 << 4)
+#define POWER_CTRL_ENIRQ_VBUS_VALID (1 << 3)
+#define POWER_CTRL_POLARITY_VDD5V_GT_VDDIO (1 << 2)
+#define POWER_CTRL_VDD5V_GT_VDDIO_IRQ (1 << 1)
+#define POWER_CTRL_ENIRQ_VDD5V_GT_VDDIO (1 << 0)
+
+#define POWER_5VCTRL_VBUSDROOP_TRSH_MASK (0x3 << 30)
+#define POWER_5VCTRL_VBUSDROOP_TRSH_OFFSET 30
+#define POWER_5VCTRL_VBUSDROOP_TRSH_4V3 (0x0 << 30)
+#define POWER_5VCTRL_VBUSDROOP_TRSH_4V4 (0x1 << 30)
+#define POWER_5VCTRL_VBUSDROOP_TRSH_4V5 (0x2 << 30)
+#define POWER_5VCTRL_VBUSDROOP_TRSH_4V7 (0x3 << 30)
+#define POWER_5VCTRL_HEADROOM_ADJ_MASK (0x7 << 24)
+#define POWER_5VCTRL_HEADROOM_ADJ_OFFSET 24
+#define POWER_5VCTRL_PWD_CHARGE_4P2_MASK (0x3 << 20)
+#define POWER_5VCTRL_PWD_CHARGE_4P2_OFFSET 20
+#define POWER_5VCTRL_CHARGE_4P2_ILIMIT_MASK (0x3f << 12)
+#define POWER_5VCTRL_CHARGE_4P2_ILIMIT_OFFSET 12
+#define POWER_5VCTRL_VBUSVALID_TRSH_MASK (0x7 << 8)
+#define POWER_5VCTRL_VBUSVALID_TRSH_OFFSET 8
+#define POWER_5VCTRL_VBUSVALID_TRSH_2V9 (0x0 << 8)
+#define POWER_5VCTRL_VBUSVALID_TRSH_4V0 (0x1 << 8)
+#define POWER_5VCTRL_VBUSVALID_TRSH_4V1 (0x2 << 8)
+#define POWER_5VCTRL_VBUSVALID_TRSH_4V2 (0x3 << 8)
+#define POWER_5VCTRL_VBUSVALID_TRSH_4V3 (0x4 << 8)
+#define POWER_5VCTRL_VBUSVALID_TRSH_4V4 (0x5 << 8)
+#define POWER_5VCTRL_VBUSVALID_TRSH_4V5 (0x6 << 8)
+#define POWER_5VCTRL_VBUSVALID_TRSH_4V6 (0x7 << 8)
+#define POWER_5VCTRL_PWDN_5VBRNOUT (1 << 7)
+#define POWER_5VCTRL_ENABLE_LINREG_ILIMIT (1 << 6)
+#define POWER_5VCTRL_DCDC_XFER (1 << 5)
+#define POWER_5VCTRL_VBUSVALID_5VDETECT (1 << 4)
+#define POWER_5VCTRL_VBUSVALID_TO_B (1 << 3)
+#define POWER_5VCTRL_ILIMIT_EQ_ZERO (1 << 2)
+#define POWER_5VCTRL_PWRUP_VBUS_CMPS (1 << 1)
+#define POWER_5VCTRL_ENABLE_DCDC (1 << 0)
+
+#define POWER_MINPWR_LOWPWR_4P2 (1 << 14)
+#define POWER_MINPWR_PWD_BO (1 << 12)
+#define POWER_MINPWR_USE_VDDXTAL_VBG (1 << 11)
+#define POWER_MINPWR_PWD_ANA_CMPS (1 << 10)
+#define POWER_MINPWR_ENABLE_OSC (1 << 9)
+#define POWER_MINPWR_SELECT_OSC (1 << 8)
+#define POWER_MINPWR_FBG_OFF (1 << 7)
+#define POWER_MINPWR_DOUBLE_FETS (1 << 6)
+#define POWER_MINPWR_HALFFETS (1 << 5)
+#define POWER_MINPWR_LESSANA_I (1 << 4)
+#define POWER_MINPWR_PWD_XTAL24 (1 << 3)
+#define POWER_MINPWR_DC_STOPCLK (1 << 2)
+#define POWER_MINPWR_EN_DC_PFM (1 << 1)
+#define POWER_MINPWR_DC_HALFCLK (1 << 0)
+
+#define POWER_CHARGE_ADJ_VOLT_MASK (0x7 << 24)
+#define POWER_CHARGE_ADJ_VOLT_OFFSET 24
+#define POWER_CHARGE_ADJ_VOLT_M025P (0x1 << 24)
+#define POWER_CHARGE_ADJ_VOLT_P050P (0x2 << 24)
+#define POWER_CHARGE_ADJ_VOLT_M075P (0x3 << 24)
+#define POWER_CHARGE_ADJ_VOLT_P025P (0x4 << 24)
+#define POWER_CHARGE_ADJ_VOLT_M050P (0x5 << 24)
+#define POWER_CHARGE_ADJ_VOLT_P075P (0x6 << 24)
+#define POWER_CHARGE_ADJ_VOLT_M100P (0x7 << 24)
+#define POWER_CHARGE_ENABLE_LOAD (1 << 22)
+#define POWER_CHARGE_ENABLE_FAULT_DETECT (1 << 20)
+#define POWER_CHARGE_CHRG_STS_OFF (1 << 19)
+#define POWER_CHARGE_LIION_4P1 (1 << 18)
+#define POWER_CHARGE_PWD_BATTCHRG (1 << 16)
+#define POWER_CHARGE_ENABLE_CHARGER_USB1 (1 << 13)
+#define POWER_CHARGE_ENABLE_CHARGER_USB0 (1 << 12)
+#define POWER_CHARGE_STOP_ILIMIT_MASK (0xf << 8)
+#define POWER_CHARGE_STOP_ILIMIT_OFFSET 8
+#define POWER_CHARGE_STOP_ILIMIT_10MA (0x1 << 8)
+#define POWER_CHARGE_STOP_ILIMIT_20MA (0x2 << 8)
+#define POWER_CHARGE_STOP_ILIMIT_50MA (0x4 << 8)
+#define POWER_CHARGE_STOP_ILIMIT_100MA (0x8 << 8)
+#define POWER_CHARGE_BATTCHRG_I_MASK 0x3f
+#define POWER_CHARGE_BATTCHRG_I_OFFSET 0
+#define POWER_CHARGE_BATTCHRG_I_10MA 0x01
+#define POWER_CHARGE_BATTCHRG_I_20MA 0x02
+#define POWER_CHARGE_BATTCHRG_I_50MA 0x04
+#define POWER_CHARGE_BATTCHRG_I_100MA 0x08
+#define POWER_CHARGE_BATTCHRG_I_200MA 0x10
+#define POWER_CHARGE_BATTCHRG_I_400MA 0x20
+
+#define POWER_VDDDCTRL_ADJTN_MASK (0xf << 28)
+#define POWER_VDDDCTRL_ADJTN_OFFSET 28
+#define POWER_VDDDCTRL_PWDN_BRNOUT (1 << 23)
+#define POWER_VDDDCTRL_DISABLE_STEPPING (1 << 22)
+#define POWER_VDDDCTRL_ENABLE_LINREG (1 << 21)
+#define POWER_VDDDCTRL_DISABLE_FET (1 << 20)
+#define POWER_VDDDCTRL_LINREG_OFFSET_MASK (0x3 << 16)
+#define POWER_VDDDCTRL_LINREG_OFFSET_OFFSET 16
+#define POWER_VDDDCTRL_LINREG_OFFSET_0STEPS (0x0 << 16)
+#define POWER_VDDDCTRL_LINREG_OFFSET_1STEPS_ABOVE (0x1 << 16)
+#define POWER_VDDDCTRL_LINREG_OFFSET_1STEPS_BELOW (0x2 << 16)
+#define POWER_VDDDCTRL_LINREG_OFFSET_2STEPS_BELOW (0x3 << 16)
+#define POWER_VDDDCTRL_BO_OFFSET_MASK (0x7 << 8)
+#define POWER_VDDDCTRL_BO_OFFSET_OFFSET 8
+#define POWER_VDDDCTRL_TRG_MASK 0x1f
+#define POWER_VDDDCTRL_TRG_OFFSET 0
+
+#define POWER_VDDACTRL_PWDN_BRNOUT (1 << 19)
+#define POWER_VDDACTRL_DISABLE_STEPPING (1 << 18)
+#define POWER_VDDACTRL_ENABLE_LINREG (1 << 17)
+#define POWER_VDDACTRL_DISABLE_FET (1 << 16)
+#define POWER_VDDACTRL_LINREG_OFFSET_MASK (0x3 << 12)
+#define POWER_VDDACTRL_LINREG_OFFSET_OFFSET 12
+#define POWER_VDDACTRL_LINREG_OFFSET_0STEPS (0x0 << 12)
+#define POWER_VDDACTRL_LINREG_OFFSET_1STEPS_ABOVE (0x1 << 12)
+#define POWER_VDDACTRL_LINREG_OFFSET_1STEPS_BELOW (0x2 << 12)
+#define POWER_VDDACTRL_LINREG_OFFSET_2STEPS_BELOW (0x3 << 12)
+#define POWER_VDDACTRL_BO_OFFSET_MASK (0x7 << 8)
+#define POWER_VDDACTRL_BO_OFFSET_OFFSET 8
+#define POWER_VDDACTRL_TRG_MASK 0x1f
+#define POWER_VDDACTRL_TRG_OFFSET 0
+
+#define POWER_VDDIOCTRL_ADJTN_MASK (0xf << 20)
+#define POWER_VDDIOCTRL_ADJTN_OFFSET 20
+#define POWER_VDDIOCTRL_PWDN_BRNOUT (1 << 18)
+#define POWER_VDDIOCTRL_DISABLE_STEPPING (1 << 17)
+#define POWER_VDDIOCTRL_DISABLE_FET (1 << 16)
+#define POWER_VDDIOCTRL_LINREG_OFFSET_MASK (0x3 << 12)
+#define POWER_VDDIOCTRL_LINREG_OFFSET_OFFSET 12
+#define POWER_VDDIOCTRL_LINREG_OFFSET_0STEPS (0x0 << 12)
+#define POWER_VDDIOCTRL_LINREG_OFFSET_1STEPS_ABOVE (0x1 << 12)
+#define POWER_VDDIOCTRL_LINREG_OFFSET_1STEPS_BELOW (0x2 << 12)
+#define POWER_VDDIOCTRL_LINREG_OFFSET_2STEPS_BELOW (0x3 << 12)
+#define POWER_VDDIOCTRL_BO_OFFSET_MASK (0x7 << 8)
+#define POWER_VDDIOCTRL_BO_OFFSET_OFFSET 8
+#define POWER_VDDIOCTRL_TRG_MASK 0x1f
+#define POWER_VDDIOCTRL_TRG_OFFSET 0
+
+#define POWER_VDDMEMCTRL_PULLDOWN_ACTIVE (1 << 10)
+#define POWER_VDDMEMCTRL_ENABLE_ILIMIT (1 << 9)
+#define POWER_VDDMEMCTRL_ENABLE_LINREG (1 << 8)
+#define POWER_VDDMEMCTRL_BO_OFFSET_MASK (0x7 << 5)
+#define POWER_VDDMEMCTRL_BO_OFFSET_OFFSET 5
+#define POWER_VDDMEMCTRL_TRG_MASK 0x1f
+#define POWER_VDDMEMCTRL_TRG_OFFSET 0
+
+#define POWER_DCDC4P2_DROPOUT_CTRL_MASK (0xf << 28)
+#define POWER_DCDC4P2_DROPOUT_CTRL_OFFSET 28
+#define POWER_DCDC4P2_DROPOUT_CTRL_200MV (0x3 << 30)
+#define POWER_DCDC4P2_DROPOUT_CTRL_100MV (0x2 << 30)
+#define POWER_DCDC4P2_DROPOUT_CTRL_50MV (0x1 << 30)
+#define POWER_DCDC4P2_DROPOUT_CTRL_25MV (0x0 << 30)
+#define POWER_DCDC4P2_DROPOUT_CTRL_SRC_4P2 (0x0 << 28)
+#define POWER_DCDC4P2_DROPOUT_CTRL_SRC_4P2_LT_BATT (0x1 << 28)
+#define POWER_DCDC4P2_DROPOUT_CTRL_SRC_SEL (0x2 << 28)
+#define POWER_DCDC4P2_ISTEAL_THRESH_MASK (0x3 << 24)
+#define POWER_DCDC4P2_ISTEAL_THRESH_OFFSET 24
+#define POWER_DCDC4P2_ENABLE_4P2 (1 << 23)
+#define POWER_DCDC4P2_ENABLE_DCDC (1 << 22)
+#define POWER_DCDC4P2_HYST_DIR (1 << 21)
+#define POWER_DCDC4P2_HYST_THRESH (1 << 20)
+#define POWER_DCDC4P2_TRG_MASK (0x7 << 16)
+#define POWER_DCDC4P2_TRG_OFFSET 16
+#define POWER_DCDC4P2_TRG_4V2 (0x0 << 16)
+#define POWER_DCDC4P2_TRG_4V1 (0x1 << 16)
+#define POWER_DCDC4P2_TRG_4V0 (0x2 << 16)
+#define POWER_DCDC4P2_TRG_3V9 (0x3 << 16)
+#define POWER_DCDC4P2_TRG_BATT (0x4 << 16)
+#define POWER_DCDC4P2_BO_MASK (0x1f << 8)
+#define POWER_DCDC4P2_BO_OFFSET 8
+#define POWER_DCDC4P2_CMPTRIP_MASK 0x1f
+#define POWER_DCDC4P2_CMPTRIP_OFFSET 0
+
+#define POWER_MISC_FREQSEL_MASK (0x7 << 4)
+#define POWER_MISC_FREQSEL_OFFSET 4
+#define POWER_MISC_FREQSEL_20MHZ (0x1 << 4)
+#define POWER_MISC_FREQSEL_24MHZ (0x2 << 4)
+#define POWER_MISC_FREQSEL_19MHZ (0x3 << 4)
+#define POWER_MISC_FREQSEL_14MHZ (0x4 << 4)
+#define POWER_MISC_FREQSEL_18MHZ (0x5 << 4)
+#define POWER_MISC_FREQSEL_21MHZ (0x6 << 4)
+#define POWER_MISC_FREQSEL_17MHZ (0x7 << 4)
+#define POWER_MISC_DISABLE_FET_BO_LOGIC (1 << 3)
+#define POWER_MISC_DELAY_TIMING (1 << 2)
+#define POWER_MISC_TEST (1 << 1)
+#define POWER_MISC_SEL_PLLCLK (1 << 0)
+
+#define POWER_DCLIMITS_POSLIMIT_BUCK_MASK (0x7f << 8)
+#define POWER_DCLIMITS_POSLIMIT_BUCK_OFFSET 8
+#define POWER_DCLIMITS_NEGLIMIT_MASK 0x7f
+#define POWER_DCLIMITS_NETLIMIT_OFFSET 0
+
+#define POWER_LOOPCTRL_TOGGLE_DIF (1 << 20)
+#define POWER_LOOPCTRL_HYST_SIGN (1 << 19)
+#define POWER_LOOPCTRL_EN_CM_HYST (1 << 18)
+#define POWER_LOOPCTRL_EN_DF_HYST (1 << 17)
+#define POWER_LOOPCTRL_CM_HYST_THRESH (1 << 16)
+#define POWER_LOOPCTRL_DF_HYST_THRESH (1 << 15)
+#define POWER_LOOPCTRL_RCSCALE_THRESH (1 << 14)
+#define POWER_LOOPCTRL_EN_RCSCALE_MASK (0x3 << 12)
+#define POWER_LOOPCTRL_EN_RCSCALE_OFFSET 12
+#define POWER_LOOPCTRL_EN_RCSCALE_DIS (0x0 << 12)
+#define POWER_LOOPCTRL_EN_RCSCALE_2X (0x1 << 12)
+#define POWER_LOOPCTRL_EN_RCSCALE_4X (0x2 << 12)
+#define POWER_LOOPCTRL_EN_RCSCALE_8X (0x3 << 12)
+#define POWER_LOOPCTRL_DC_FF_MASK (0x7 << 8)
+#define POWER_LOOPCTRL_DC_FF_OFFSET 8
+#define POWER_LOOPCTRL_DC_R_MASK (0xf << 4)
+#define POWER_LOOPCTRL_DC_R_OFFSET 4
+#define POWER_LOOPCTRL_DC_C_MASK 0x3
+#define POWER_LOOPCTRL_DC_C_OFFSET 0
+#define POWER_LOOPCTRL_DC_C_MAX 0x0
+#define POWER_LOOPCTRL_DC_C_2X 0x1
+#define POWER_LOOPCTRL_DC_C_4X 0x2
+#define POWER_LOOPCTRL_DC_C_MIN 0x3
+
+#define POWER_STS_PWRUP_SOURCE_MASK (0x3f << 24)
+#define POWER_STS_PWRUP_SOURCE_OFFSET 24
+#define POWER_STS_PWRUP_SOURCE_5V (0x20 << 24)
+#define POWER_STS_PWRUP_SOURCE_RTC (0x10 << 24)
+#define POWER_STS_PWRUP_SOURCE_PSWITCH_HIGH (0x02 << 24)
+#define POWER_STS_PWRUP_SOURCE_PSWITCH_MID (0x01 << 24)
+#define POWER_STS_PSWITCH_MASK (0x3 << 20)
+#define POWER_STS_PSWITCH_OFFSET 20
+#define POWER_STS_THERMAL_WARNING (1 << 19)
+#define POWER_STS_VDDMEM_BO (1 << 18)
+#define POWER_STS_AVALID0_STATUS (1 << 17)
+#define POWER_STS_BVALID0_STATUS (1 << 16)
+#define POWER_STS_VBUSVALID0_STATUS (1 << 15)
+#define POWER_STS_SESSEND0_STATUS (1 << 14)
+#define POWER_STS_BATT_BO (1 << 13)
+#define POWER_STS_VDD5V_FAULT (1 << 12)
+#define POWER_STS_CHRGSTS (1 << 11)
+#define POWER_STS_DCDC_4P2_BO (1 << 10)
+#define POWER_STS_DC_OK (1 << 9)
+#define POWER_STS_VDDIO_BO (1 << 8)
+#define POWER_STS_VDDA_BO (1 << 7)
+#define POWER_STS_VDDD_BO (1 << 6)
+#define POWER_STS_VDD5V_GT_VDDIO (1 << 5)
+#define POWER_STS_VDD5V_DROOP (1 << 4)
+#define POWER_STS_AVALID0 (1 << 3)
+#define POWER_STS_BVALID0 (1 << 2)
+#define POWER_STS_VBUSVALID0 (1 << 1)
+#define POWER_STS_SESSEND0 (1 << 0)
+
+#define POWER_SPEED_STATUS_MASK (0xffff << 8)
+#define POWER_SPEED_STATUS_OFFSET 8
+#define POWER_SPEED_STATUS_SEL_MASK (0x3 << 6)
+#define POWER_SPEED_STATUS_SEL_OFFSET 6
+#define POWER_SPEED_STATUS_SEL_DCDC_STAT (0x0 << 6)
+#define POWER_SPEED_STATUS_SEL_CORE_STAT (0x1 << 6)
+#define POWER_SPEED_STATUS_SEL_ARM_STAT (0x2 << 6)
+#define POWER_SPEED_CTRL_MASK 0x3
+#define POWER_SPEED_CTRL_OFFSET 0
+#define POWER_SPEED_CTRL_SS_OFF 0x0
+#define POWER_SPEED_CTRL_SS_ON 0x1
+#define POWER_SPEED_CTRL_SS_ENABLE 0x3
+
+#define POWER_BATTMONITOR_BATT_VAL_MASK (0x3ff << 16)
+#define POWER_BATTMONITOR_BATT_VAL_OFFSET 16
+#define POWER_BATTMONITOR_PWDN_BATTBRNOUT_5VDETECT_EN (1 << 11)
+#define POWER_BATTMONITOR_EN_BATADJ (1 << 10)
+#define POWER_BATTMONITOR_PWDN_BATTBRNOUT (1 << 9)
+#define POWER_BATTMONITOR_BRWNOUT_PWD (1 << 8)
+#define POWER_BATTMONITOR_BRWNOUT_LVL_MASK 0x1f
+#define POWER_BATTMONITOR_BRWNOUT_LVL_OFFSET 0
+
+#define POWER_RESET_UNLOCK_MASK (0xffff << 16)
+#define POWER_RESET_UNLOCK_OFFSET 16
+#define POWER_RESET_UNLOCK_KEY (0x3e77 << 16)
+#define POWER_RESET_FASTFALL_PSWITCH_OFF (1 << 2)
+#define POWER_RESET_PWD_OFF (1 << 1)
+#define POWER_RESET_PWD (1 << 0)
+
+#define POWER_DEBUG_VBUSVALIDPIOLOCK (1 << 3)
+#define POWER_DEBUG_AVALIDPIOLOCK (1 << 2)
+#define POWER_DEBUG_BVALIDPIOLOCK (1 << 1)
+#define POWER_DEBUG_SESSENDPIOLOCK (1 << 0)
+
+#define POWER_THERMAL_TEST (1 << 8)
+#define POWER_THERMAL_PWD (1 << 7)
+#define POWER_THERMAL_LOW_POWER (1 << 6)
+#define POWER_THERMAL_OFFSET_ADJ_MASK (0x3 << 4)
+#define POWER_THERMAL_OFFSET_ADJ_OFFSET 4
+#define POWER_THERMAL_OFFSET_ADJ_ENABLE (1 << 3)
+#define POWER_THERMAL_TEMP_THRESHOLD_MASK 0x7
+#define POWER_THERMAL_TEMP_THRESHOLD_OFFSET 0
+
+#define POWER_USB1CTRL_AVALID1 (1 << 3)
+#define POWER_USB1CTRL_BVALID1 (1 << 2)
+#define POWER_USB1CTRL_VBUSVALID1 (1 << 1)
+#define POWER_USB1CTRL_SESSEND1 (1 << 0)
+
+#define POWER_SPECIAL_TEST_MASK 0xffffffff
+#define POWER_SPECIAL_TEST_OFFSET 0
+
+#define POWER_VERSION_MAJOR_MASK (0xff << 24)
+#define POWER_VERSION_MAJOR_OFFSET 24
+#define POWER_VERSION_MINOR_MASK (0xff << 16)
+#define POWER_VERSION_MINOR_OFFSET 16
+#define POWER_VERSION_STEP_MASK 0xffff
+#define POWER_VERSION_STEP_OFFSET 0
+
+#define POWER_ANACLKCTRL_CLKGATE_0 (1 << 31)
+#define POWER_ANACLKCTRL_OUTDIV_MASK (0x7 << 28)
+#define POWER_ANACLKCTRL_OUTDIV_OFFSET 28
+#define POWER_ANACLKCTRL_INVERT_OUTCLK (1 << 27)
+#define POWER_ANACLKCTRL_CLKGATE_I (1 << 26)
+#define POWER_ANACLKCTRL_DITHER_OFF (1 << 10)
+#define POWER_ANACLKCTRL_SLOW_DITHER (1 << 9)
+#define POWER_ANACLKCTRL_INVERT_INCLK (1 << 8)
+#define POWER_ANACLKCTRL_INCLK_SHIFT_MASK (0x3 << 4)
+#define POWER_ANACLKCTRL_INCLK_SHIFT_OFFSET 4
+#define POWER_ANACLKCTRL_INDIV_MASK 0x7
+#define POWER_ANACLKCTRL_INDIV_OFFSET 0
+
+#define POWER_REFCTRL_FASTSETTLING (1 << 26)
+#define POWER_REFCTRL_RAISE_REF (1 << 25)
+#define POWER_REFCTRL_XTAL_BGR_BIAS (1 << 24)
+#define POWER_REFCTRL_VBG_ADJ_MASK (0x7 << 20)
+#define POWER_REFCTRL_VBG_ADJ_OFFSET 20
+#define POWER_REFCTRL_LOW_PWR (1 << 19)
+#define POWER_REFCTRL_BIAS_CTRL_MASK (0x3 << 16)
+#define POWER_REFCTRL_BIAS_CTRL_OFFSET 16
+#define POWER_REFCTRL_VDDXTAL_TO_VDDD (1 << 14)
+#define POWER_REFCTRL_ADJ_ANA (1 << 13)
+#define POWER_REFCTRL_ADJ_VAG (1 << 12)
+#define POWER_REFCTRL_ANA_REFVAL_MASK (0xf << 8)
+#define POWER_REFCTRL_ANA_REFVAL_OFFSET 8
+#define POWER_REFCTRL_VAG_VAL_MASK (0xf << 4)
+#define POWER_REFCTRL_VAG_VAL_OFFSET 4
+
+#endif /* __MX28_REGS_POWER_H__ */
diff --git a/arch/arm/include/asm/arch-mx28/regs-rtc.h b/arch/arm/include/asm/arch-mx28/regs-rtc.h
new file mode 100644
index 0000000..fe2fda9
--- /dev/null
+++ b/arch/arm/include/asm/arch-mx28/regs-rtc.h
@@ -0,0 +1,147 @@
+/*
+ * Freescale i.MX28 RTC Register Definitions
+ *
+ * Copyright (C) 2011 Marek Vasut <marek.vasut@gmail.com>
+ * on behalf of DENX Software Engineering GmbH
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
+ *
+ */
+
+#ifndef __MX28_REGS_RTC_H__
+#define __MX28_REGS_RTC_H__
+
+#include <asm/arch/regs-common.h>
+
+#ifndef __ASSEMBLY__
+struct mx28_rtc_regs {
+ mx28_reg(hw_rtc_ctrl)
+ mx28_reg(hw_rtc_stat)
+ mx28_reg(hw_rtc_milliseconds)
+ mx28_reg(hw_rtc_seconds)
+ mx28_reg(hw_rtc_rtc_alarm)
+ mx28_reg(hw_rtc_watchdog)
+ mx28_reg(hw_rtc_persistent0)
+ mx28_reg(hw_rtc_persistent1)
+ mx28_reg(hw_rtc_persistent2)
+ mx28_reg(hw_rtc_persistent3)
+ mx28_reg(hw_rtc_persistent4)
+ mx28_reg(hw_rtc_persistent5)
+ mx28_reg(hw_rtc_debug)
+ mx28_reg(hw_rtc_version)
+};
+#endif
+
+#define RTC_CTRL_SFTRST (1 << 31)
+#define RTC_CTRL_CLKGATE (1 << 30)
+#define RTC_CTRL_SUPPRESS_COPY2ANALOG (1 << 6)
+#define RTC_CTRL_FORCE_UPDATE (1 << 5)
+#define RTC_CTRL_WATCHDOGEN (1 << 4)
+#define RTC_CTRL_ONEMSEC_IRQ (1 << 3)
+#define RTC_CTRL_ALARM_IRQ (1 << 2)
+#define RTC_CTRL_ONEMSEC_IRQ_EN (1 << 1)
+#define RTC_CTRL_ALARM_IRQ_EN (1 << 0)
+
+#define RTC_STAT_RTC_PRESENT (1 << 31)
+#define RTC_STAT_ALARM_PRESENT (1 << 30)
+#define RTC_STAT_WATCHDOG_PRESENT (1 << 29)
+#define RTC_STAT_XTAL32000_PRESENT (1 << 28)
+#define RTC_STAT_XTAL32768_PRESENT (1 << 27)
+#define RTC_STAT_STALE_REGS_MASK (0xff << 16)
+#define RTC_STAT_STALE_REGS_OFFSET 16
+#define RTC_STAT_NEW_REGS_MASK (0xff << 8)
+#define RTC_STAT_NEW_REGS_OFFSET 8
+
+#define RTC_MILLISECONDS_COUNT_MASK 0xffffffff
+#define RTC_MILLISECONDS_COUNT_OFFSET 0
+
+#define RTC_SECONDS_COUNT_MASK 0xffffffff
+#define RTC_SECONDS_COUNT_OFFSET 0
+
+#define RTC_ALARM_VALUE_MASK 0xffffffff
+#define RTC_ALARM_VALUE_OFFSET 0
+
+#define RTC_WATCHDOG_COUNT_MASK 0xffffffff
+#define RTC_WATCHDOG_COUNT_OFFSET 0
+
+#define RTC_PERSISTENT0_ADJ_POSLIMITBUCK_MASK (0xf << 28)
+#define RTC_PERSISTENT0_ADJ_POSLIMITBUCK_OFFSET 28
+#define RTC_PERSISTENT0_ADJ_POSLIMITBUCK_2V83 (0x0 << 28)
+#define RTC_PERSISTENT0_ADJ_POSLIMITBUCK_2V78 (0x1 << 28)
+#define RTC_PERSISTENT0_ADJ_POSLIMITBUCK_2V73 (0x2 << 28)
+#define RTC_PERSISTENT0_ADJ_POSLIMITBUCK_2V68 (0x3 << 28)
+#define RTC_PERSISTENT0_ADJ_POSLIMITBUCK_2V62 (0x4 << 28)
+#define RTC_PERSISTENT0_ADJ_POSLIMITBUCK_2V57 (0x5 << 28)
+#define RTC_PERSISTENT0_ADJ_POSLIMITBUCK_2V52 (0x6 << 28)
+#define RTC_PERSISTENT0_ADJ_POSLIMITBUCK_2V48 (0x7 << 28)
+#define RTC_PERSISTENT0_EXTERNAL_RESET (1 << 21)
+#define RTC_PERSISTENT0_THERMAL_RESET (1 << 20)
+#define RTC_PERSISTENT0_ENABLE_LRADC_PWRUP (1 << 18)
+#define RTC_PERSISTENT0_AUTO_RESTART (1 << 17)
+#define RTC_PERSISTENT0_DISABLE_PSWITCH (1 << 16)
+#define RTC_PERSISTENT0_LOWERBIAS_MASK (0xf << 14)
+#define RTC_PERSISTENT0_LOWERBIAS_OFFSET 14
+#define RTC_PERSISTENT0_LOWERBIAS_NOMINAL (0x0 << 14)
+#define RTC_PERSISTENT0_LOWERBIAS_M25P (0x1 << 14)
+#define RTC_PERSISTENT0_LOWERBIAS_M50P (0x3 << 14)
+#define RTC_PERSISTENT0_DISABLE_XTALOK (1 << 13)
+#define RTC_PERSISTENT0_MSEC_RES_MASK (0x1f << 8)
+#define RTC_PERSISTENT0_MSEC_RES_OFFSET 8
+#define RTC_PERSISTENT0_MSEC_RES_1MS (0x01 << 8)
+#define RTC_PERSISTENT0_MSEC_RES_2MS (0x02 << 8)
+#define RTC_PERSISTENT0_MSEC_RES_4MS (0x04 << 8)
+#define RTC_PERSISTENT0_MSEC_RES_8MS (0x08 << 8)
+#define RTC_PERSISTENT0_MSEC_RES_16MS (0x10 << 8)
+#define RTC_PERSISTENT0_ALARM_WAKE (1 << 7)
+#define RTC_PERSISTENT0_XTAL32_FREQ (1 << 6)
+#define RTC_PERSISTENT0_XTAL32KHZ_PWRUP (1 << 5)
+#define RTC_PERSISTENT0_XTAL24KHZ_PWRUP (1 << 4)
+#define RTC_PERSISTENT0_LCK_SECS (1 << 3)
+#define RTC_PERSISTENT0_ALARM_EN (1 << 2)
+#define RTC_PERSISTENT0_ALARM_WAKE_EN (1 << 1)
+#define RTC_PERSISTENT0_CLOCKSOURCE (1 << 0)
+
+#define RTC_PERSISTENT1_GENERAL_MASK 0xffffffff
+#define RTC_PERSISTENT1_GENERAL_OFFSET 0
+#define RTC_PERSISTENT1_GENERAL_OTG_ALT_ROLE 0x0080
+#define RTC_PERSISTENT1_GENERAL_OTG_HNP 0x0100
+#define RTC_PERSISTENT1_GENERAL_USB_LPM 0x0200
+#define RTC_PERSISTENT1_GENERAL_SKIP_CHECKDISK 0x0400
+#define RTC_PERSISTENT1_GENERAL_USB_BOOT_PLAYER 0x0800
+#define RTC_PERSISTENT1_GENERAL_ENUM_500MA_2X 0x1000
+
+#define RTC_PERSISTENT2_GENERAL_MASK 0xffffffff
+#define RTC_PERSISTENT2_GENERAL_OFFSET 0
+
+#define RTC_PERSISTENT3_GENERAL_MASK 0xffffffff
+#define RTC_PERSISTENT3_GENERAL_OFFSET 0
+
+#define RTC_PERSISTENT4_GENERAL_MASK 0xffffffff
+#define RTC_PERSISTENT4_GENERAL_OFFSET 0
+
+#define RTC_PERSISTENT5_GENERAL_MASK 0xffffffff
+#define RTC_PERSISTENT5_GENERAL_OFFSET 0
+
+#define RTC_DEBUG_WATCHDOG_RESET_MASK (1 << 1)
+#define RTC_DEBUG_WATCHDOG_RESET (1 << 0)
+
+#define RTC_VERSION_MAJOR_MASK (0xff << 24)
+#define RTC_VERSION_MAJOR_OFFSET 24
+#define RTC_VERSION_MINOR_MASK (0xff << 16)
+#define RTC_VERSION_MINOR_OFFSET 16
+#define RTC_VERSION_STEP_MASK 0xffff
+#define RTC_VERSION_STEP_OFFSET 0
+
+#endif /* __MX28_REGS_RTC_H__ */
diff --git a/arch/arm/include/asm/arch-mx28/regs-ssp.h b/arch/arm/include/asm/arch-mx28/regs-ssp.h
new file mode 100644
index 0000000..ab3870c
--- /dev/null
+++ b/arch/arm/include/asm/arch-mx28/regs-ssp.h
@@ -0,0 +1,349 @@
+/*
+ * Freescale i.MX28 SSP Register Definitions
+ *
+ * Copyright (C) 2011 Marek Vasut <marek.vasut@gmail.com>
+ *
+ * Based on code from LTIB:
+ * Copyright 2008-2010 Freescale Semiconductor, Inc. All Rights Reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
+ *
+ */
+
+#ifndef __MX28_REGS_SSP_H__
+#define __MX28_REGS_SSP_H__
+
+#include <asm/arch/regs-common.h>
+
+#ifndef __ASSEMBLY__
+struct mx28_ssp_regs {
+ mx28_reg(hw_ssp_ctrl0)
+ mx28_reg(hw_ssp_cmd0)
+ mx28_reg(hw_ssp_cmd1)
+ mx28_reg(hw_ssp_xfer_size)
+ mx28_reg(hw_ssp_block_size)
+ mx28_reg(hw_ssp_compref)
+ mx28_reg(hw_ssp_compmask)
+ mx28_reg(hw_ssp_timing)
+ mx28_reg(hw_ssp_ctrl1)
+ mx28_reg(hw_ssp_data)
+ mx28_reg(hw_ssp_sdresp0)
+ mx28_reg(hw_ssp_sdresp1)
+ mx28_reg(hw_ssp_sdresp2)
+ mx28_reg(hw_ssp_sdresp3)
+ mx28_reg(hw_ssp_ddr_ctrl)
+ mx28_reg(hw_ssp_dll_ctrl)
+ mx28_reg(hw_ssp_status)
+ mx28_reg(hw_ssp_dll_sts)
+ mx28_reg(hw_ssp_debug)
+ mx28_reg(hw_ssp_version)
+};
+#endif
+
+#define SSP_CTRL0_SFTRST (1 << 31)
+#define SSP_CTRL0_CLKGATE (1 << 30)
+#define SSP_CTRL0_RUN (1 << 29)
+#define SSP_CTRL0_SDIO_IRQ_CHECK (1 << 28)
+#define SSP_CTRL0_LOCK_CS (1 << 27)
+#define SSP_CTRL0_IGNORE_CRC (1 << 26)
+#define SSP_CTRL0_READ (1 << 25)
+#define SSP_CTRL0_DATA_XFER (1 << 24)
+#define SSP_CTRL0_BUS_WIDTH_MASK (0x3 << 22)
+#define SSP_CTRL0_BUS_WIDTH_OFFSET 22
+#define SSP_CTRL0_BUS_WIDTH_ONE_BIT (0x0 << 22)
+#define SSP_CTRL0_BUS_WIDTH_FOUR_BIT (0x1 << 22)
+#define SSP_CTRL0_BUS_WIDTH_EIGHT_BIT (0x2 << 22)
+#define SSP_CTRL0_WAIT_FOR_IRQ (1 << 21)
+#define SSP_CTRL0_WAIT_FOR_CMD (1 << 20)
+#define SSP_CTRL0_LONG_RESP (1 << 19)
+#define SSP_CTRL0_CHECK_RESP (1 << 18)
+#define SSP_CTRL0_GET_RESP (1 << 17)
+#define SSP_CTRL0_ENABLE (1 << 16)
+
+#define SSP_CMD0_SOFT_TERMINATE (1 << 26)
+#define SSP_CMD0_DBL_DATA_RATE_EN (1 << 25)
+#define SSP_CMD0_PRIM_BOOT_OP_EN (1 << 24)
+#define SSP_CMD0_BOOT_ACK_EN (1 << 23)
+#define SSP_CMD0_SLOW_CLKING_EN (1 << 22)
+#define SSP_CMD0_CONT_CLKING_EN (1 << 21)
+#define SSP_CMD0_APPEND_8CYC (1 << 20)
+#define SSP_CMD0_CMD_MASK 0xff
+#define SSP_CMD0_CMD_OFFSET 0
+#define SSP_CMD0_CMD_MMC_GO_IDLE_STATE 0x00
+#define SSP_CMD0_CMD_MMC_SEND_OP_COND 0x01
+#define SSP_CMD0_CMD_MMC_ALL_SEND_CID 0x02
+#define SSP_CMD0_CMD_MMC_SET_RELATIVE_ADDR 0x03
+#define SSP_CMD0_CMD_MMC_SET_DSR 0x04
+#define SSP_CMD0_CMD_MMC_RESERVED_5 0x05
+#define SSP_CMD0_CMD_MMC_SWITCH 0x06
+#define SSP_CMD0_CMD_MMC_SELECT_DESELECT_CARD 0x07
+#define SSP_CMD0_CMD_MMC_SEND_EXT_CSD 0x08
+#define SSP_CMD0_CMD_MMC_SEND_CSD 0x09
+#define SSP_CMD0_CMD_MMC_SEND_CID 0x0a
+#define SSP_CMD0_CMD_MMC_READ_DAT_UNTIL_STOP 0x0b
+#define SSP_CMD0_CMD_MMC_STOP_TRANSMISSION 0x0c
+#define SSP_CMD0_CMD_MMC_SEND_STATUS 0x0d
+#define SSP_CMD0_CMD_MMC_BUSTEST_R 0x0e
+#define SSP_CMD0_CMD_MMC_GO_INACTIVE_STATE 0x0f
+#define SSP_CMD0_CMD_MMC_SET_BLOCKLEN 0x10
+#define SSP_CMD0_CMD_MMC_READ_SINGLE_BLOCK 0x11
+#define SSP_CMD0_CMD_MMC_READ_MULTIPLE_BLOCK 0x12
+#define SSP_CMD0_CMD_MMC_BUSTEST_W 0x13
+#define SSP_CMD0_CMD_MMC_WRITE_DAT_UNTIL_STOP 0x14
+#define SSP_CMD0_CMD_MMC_SET_BLOCK_COUNT 0x17
+#define SSP_CMD0_CMD_MMC_WRITE_BLOCK 0x18
+#define SSP_CMD0_CMD_MMC_WRITE_MULTIPLE_BLOCK 0x19
+#define SSP_CMD0_CMD_MMC_PROGRAM_CID 0x1a
+#define SSP_CMD0_CMD_MMC_PROGRAM_CSD 0x1b
+#define SSP_CMD0_CMD_MMC_SET_WRITE_PROT 0x1c
+#define SSP_CMD0_CMD_MMC_CLR_WRITE_PROT 0x1d
+#define SSP_CMD0_CMD_MMC_SEND_WRITE_PROT 0x1e
+#define SSP_CMD0_CMD_MMC_ERASE_GROUP_START 0x23
+#define SSP_CMD0_CMD_MMC_ERASE_GROUP_END 0x24
+#define SSP_CMD0_CMD_MMC_ERASE 0x26
+#define SSP_CMD0_CMD_MMC_FAST_IO 0x27
+#define SSP_CMD0_CMD_MMC_GO_IRQ_STATE 0x28
+#define SSP_CMD0_CMD_MMC_LOCK_UNLOCK 0x2a
+#define SSP_CMD0_CMD_MMC_APP_CMD 0x37
+#define SSP_CMD0_CMD_MMC_GEN_CMD 0x38
+#define SSP_CMD0_CMD_SD_GO_IDLE_STATE 0x00
+#define SSP_CMD0_CMD_SD_ALL_SEND_CID 0x02
+#define SSP_CMD0_CMD_SD_SEND_RELATIVE_ADDR 0x03
+#define SSP_CMD0_CMD_SD_SET_DSR 0x04
+#define SSP_CMD0_CMD_SD_IO_SEND_OP_COND 0x05
+#define SSP_CMD0_CMD_SD_SELECT_DESELECT_CARD 0x07
+#define SSP_CMD0_CMD_SD_SEND_CSD 0x09
+#define SSP_CMD0_CMD_SD_SEND_CID 0x0a
+#define SSP_CMD0_CMD_SD_STOP_TRANSMISSION 0x0c
+#define SSP_CMD0_CMD_SD_SEND_STATUS 0x0d
+#define SSP_CMD0_CMD_SD_GO_INACTIVE_STATE 0x0f
+#define SSP_CMD0_CMD_SD_SET_BLOCKLEN 0x10
+#define SSP_CMD0_CMD_SD_READ_SINGLE_BLOCK 0x11
+#define SSP_CMD0_CMD_SD_READ_MULTIPLE_BLOCK 0x12
+#define SSP_CMD0_CMD_SD_WRITE_BLOCK 0x18
+#define SSP_CMD0_CMD_SD_WRITE_MULTIPLE_BLOCK 0x19
+#define SSP_CMD0_CMD_SD_PROGRAM_CSD 0x1b
+#define SSP_CMD0_CMD_SD_SET_WRITE_PROT 0x1c
+#define SSP_CMD0_CMD_SD_CLR_WRITE_PROT 0x1d
+#define SSP_CMD0_CMD_SD_SEND_WRITE_PROT 0x1e
+#define SSP_CMD0_CMD_SD_ERASE_WR_BLK_START 0x20
+#define SSP_CMD0_CMD_SD_ERASE_WR_BLK_END 0x21
+#define SSP_CMD0_CMD_SD_ERASE_GROUP_START 0x23
+#define SSP_CMD0_CMD_SD_ERASE_GROUP_END 0x24
+#define SSP_CMD0_CMD_SD_ERASE 0x26
+#define SSP_CMD0_CMD_SD_LOCK_UNLOCK 0x2a
+#define SSP_CMD0_CMD_SD_IO_RW_DIRECT 0x34
+#define SSP_CMD0_CMD_SD_IO_RW_EXTENDED 0x35
+#define SSP_CMD0_CMD_SD_APP_CMD 0x37
+#define SSP_CMD0_CMD_SD_GEN_CMD 0x38
+
+#define SSP_CMD1_CMD_ARG_MASK 0xffffffff
+#define SSP_CMD1_CMD_ARG_OFFSET 0
+
+#define SSP_XFER_SIZE_XFER_COUNT_MASK 0xffffffff
+#define SSP_XFER_SIZE_XFER_COUNT_OFFSET 0
+
+#define SSP_BLOCK_SIZE_BLOCK_COUNT_MASK (0xffffff << 4)
+#define SSP_BLOCK_SIZE_BLOCK_COUNT_OFFSET 4
+#define SSP_BLOCK_SIZE_BLOCK_SIZE_MASK 0xf
+#define SSP_BLOCK_SIZE_BLOCK_SIZE_OFFSET 0
+
+#define SSP_COMPREF_REFERENCE_MASK 0xffffffff
+#define SSP_COMPREF_REFERENCE_OFFSET 0
+
+#define SSP_COMPMASK_MASK_MASK 0xffffffff
+#define SSP_COMPMASK_MASK_OFFSET 0
+
+#define SSP_TIMING_TIMEOUT_MASK (0xffff << 16)
+#define SSP_TIMING_TIMEOUT_OFFSET 16
+#define SSP_TIMING_CLOCK_DIVIDE_MASK (0xff << 8)
+#define SSP_TIMING_CLOCK_DIVIDE_OFFSET 8
+#define SSP_TIMING_CLOCK_RATE_MASK 0xff
+#define SSP_TIMING_CLOCK_RATE_OFFSET 0
+
+#define SSP_CTRL1_SDIO_IRQ (1 << 31)
+#define SSP_CTRL1_SDIO_IRQ_EN (1 << 30)
+#define SSP_CTRL1_RESP_ERR_IRQ (1 << 29)
+#define SSP_CTRL1_RESP_ERR_IRQ_EN (1 << 28)
+#define SSP_CTRL1_RESP_TIMEOUT_IRQ (1 << 27)
+#define SSP_CTRL1_RESP_TIMEOUT_IRQ_EN (1 << 26)
+#define SSP_CTRL1_DATA_TIMEOUT_IRQ (1 << 25)
+#define SSP_CTRL1_DATA_TIMEOUT_IRQ_EN (1 << 24)
+#define SSP_CTRL1_DATA_CRC_IRQ (1 << 23)
+#define SSP_CTRL1_DATA_CRC_IRQ_EN (1 << 22)
+#define SSP_CTRL1_FIFO_UNDERRUN_IRQ (1 << 21)
+#define SSP_CTRL1_FIFO_UNDERRUN_EN (1 << 20)
+#define SSP_CTRL1_CEATA_CCS_ERR_IRQ (1 << 19)
+#define SSP_CTRL1_CEATA_CCS_ERR_IRQ_EN (1 << 18)
+#define SSP_CTRL1_RECV_TIMEOUT_IRQ (1 << 17)
+#define SSP_CTRL1_RECV_TIMEOUT_IRQ_EN (1 << 16)
+#define SSP_CTRL1_FIFO_OVERRUN_IRQ (1 << 15)
+#define SSP_CTRL1_FIFO_OVERRUN_IRQ_EN (1 << 14)
+#define SSP_CTRL1_DMA_ENABLE (1 << 13)
+#define SSP_CTRL1_CEATA_CCS_ERR_EN (1 << 12)
+#define SSP_CTRL1_SLAVE_OUT_DISABLE (1 << 11)
+#define SSP_CTRL1_PHASE (1 << 10)
+#define SSP_CTRL1_POLARITY (1 << 9)
+#define SSP_CTRL1_SLAVE_MODE (1 << 8)
+#define SSP_CTRL1_WORD_LENGTH_MASK (0xf << 4)
+#define SSP_CTRL1_WORD_LENGTH_OFFSET 4
+#define SSP_CTRL1_WORD_LENGTH_RESERVED0 (0x0 << 4)
+#define SSP_CTRL1_WORD_LENGTH_RESERVED1 (0x1 << 4)
+#define SSP_CTRL1_WORD_LENGTH_RESERVED2 (0x2 << 4)
+#define SSP_CTRL1_WORD_LENGTH_FOUR_BITS (0x3 << 4)
+#define SSP_CTRL1_WORD_LENGTH_EIGHT_BITS (0x7 << 4)
+#define SSP_CTRL1_WORD_LENGTH_SIXTEEN_BITS (0xf << 4)
+#define SSP_CTRL1_SSP_MODE_MASK 0xf
+#define SSP_CTRL1_SSP_MODE_OFFSET 0
+#define SSP_CTRL1_SSP_MODE_SPI 0x0
+#define SSP_CTRL1_SSP_MODE_SSI 0x1
+#define SSP_CTRL1_SSP_MODE_SD_MMC 0x3
+#define SSP_CTRL1_SSP_MODE_MS 0x4
+
+#define SSP_DATA_DATA_MASK 0xffffffff
+#define SSP_DATA_DATA_OFFSET 0
+
+#define SSP_SDRESP0_RESP0_MASK 0xffffffff
+#define SSP_SDRESP0_RESP0_OFFSET 0
+
+#define SSP_SDRESP1_RESP1_MASK 0xffffffff
+#define SSP_SDRESP1_RESP1_OFFSET 0
+
+#define SSP_SDRESP2_RESP2_MASK 0xffffffff
+#define SSP_SDRESP2_RESP2_OFFSET 0
+
+#define SSP_SDRESP3_RESP3_MASK 0xffffffff
+#define SSP_SDRESP3_RESP3_OFFSET 0
+
+#define SSP_DDR_CTRL_DMA_BURST_TYPE_MASK (0x3 << 30)
+#define SSP_DDR_CTRL_DMA_BURST_TYPE_OFFSET 30
+#define SSP_DDR_CTRL_NIBBLE_POS (1 << 1)
+#define SSP_DDR_CTRL_TXCLK_DELAY_TYPE (1 << 0)
+
+#define SSP_DLL_CTRL_REF_UPDATE_INT_MASK (0xf << 28)
+#define SSP_DLL_CTRL_REF_UPDATE_INT_OFFSET 28
+#define SSP_DLL_CTRL_SLV_UPDATE_INT_MASK (0xff << 20)
+#define SSP_DLL_CTRL_SLV_UPDATE_INT_OFFSET 20
+#define SSP_DLL_CTRL_SLV_OVERRIDE_VAL_MASK (0x3f << 10)
+#define SSP_DLL_CTRL_SLV_OVERRIDE_VAL_OFFSET 10
+#define SSP_DLL_CTRL_SLV_OVERRIDE (1 << 9)
+#define SSP_DLL_CTRL_GATE_UPDATE (1 << 7)
+#define SSP_DLL_CTRL_SLV_DLY_TARGET_MASK (0xf << 3)
+#define SSP_DLL_CTRL_SLV_DLY_TARGET_OFFSET 3
+#define SSP_DLL_CTRL_SLV_FORCE_UPD (1 << 2)
+#define SSP_DLL_CTRL_RESET (1 << 1)
+#define SSP_DLL_CTRL_ENABLE (1 << 0)
+
+#define SSP_STATUS_PRESENT (1 << 31)
+#define SSP_STATUS_MS_PRESENT (1 << 30)
+#define SSP_STATUS_SD_PRESENT (1 << 29)
+#define SSP_STATUS_CARD_DETECT (1 << 28)
+#define SSP_STATUS_DMABURST (1 << 22)
+#define SSP_STATUS_DMASENSE (1 << 21)
+#define SSP_STATUS_DMATERM (1 << 20)
+#define SSP_STATUS_DMAREQ (1 << 19)
+#define SSP_STATUS_DMAEND (1 << 18)
+#define SSP_STATUS_SDIO_IRQ (1 << 17)
+#define SSP_STATUS_RESP_CRC_ERR (1 << 16)
+#define SSP_STATUS_RESP_ERR (1 << 15)
+#define SSP_STATUS_RESP_TIMEOUT (1 << 14)
+#define SSP_STATUS_DATA_CRC_ERR (1 << 13)
+#define SSP_STATUS_TIMEOUT (1 << 12)
+#define SSP_STATUS_RECV_TIMEOUT_STAT (1 << 11)
+#define SSP_STATUS_CEATA_CCS_ERR (1 << 10)
+#define SSP_STATUS_FIFO_OVRFLW (1 << 9)
+#define SSP_STATUS_FIFO_FULL (1 << 8)
+#define SSP_STATUS_FIFO_EMPTY (1 << 5)
+#define SSP_STATUS_FIFO_UNDRFLW (1 << 4)
+#define SSP_STATUS_CMD_BUSY (1 << 3)
+#define SSP_STATUS_DATA_BUSY (1 << 2)
+#define SSP_STATUS_BUSY (1 << 0)
+
+#define SSP_DLL_STS_REF_SEL_MASK (0x3f << 8)
+#define SSP_DLL_STS_REF_SEL_OFFSET 8
+#define SSP_DLL_STS_SLV_SEL_MASK (0x3f << 2)
+#define SSP_DLL_STS_SLV_SEL_OFFSET 2
+#define SSP_DLL_STS_REF_LOCK (1 << 1)
+#define SSP_DLL_STS_SLV_LOCK (1 << 0)
+
+#define SSP_DEBUG_DATACRC_ERR_MASK (0xf << 28)
+#define SSP_DEBUG_DATACRC_ERR_OFFSET 28
+#define SSP_DEBUG_DATA_STALL (1 << 27)
+#define SSP_DEBUG_DAT_SM_MASK (0x7 << 24)
+#define SSP_DEBUG_DAT_SM_OFFSET 24
+#define SSP_DEBUG_DAT_SM_DSM_IDLE (0x0 << 24)
+#define SSP_DEBUG_DAT_SM_DSM_WORD (0x2 << 24)
+#define SSP_DEBUG_DAT_SM_DSM_CRC1 (0x3 << 24)
+#define SSP_DEBUG_DAT_SM_DSM_CRC2 (0x4 << 24)
+#define SSP_DEBUG_DAT_SM_DSM_END (0x5 << 24)
+#define SSP_DEBUG_MSTK_SM_MASK (0xf << 20)
+#define SSP_DEBUG_MSTK_SM_OFFSET 20
+#define SSP_DEBUG_MSTK_SM_MSTK_IDLE (0x0 << 20)
+#define SSP_DEBUG_MSTK_SM_MSTK_CKON (0x1 << 20)
+#define SSP_DEBUG_MSTK_SM_MSTK_BS1 (0x2 << 20)
+#define SSP_DEBUG_MSTK_SM_MSTK_TPC (0x3 << 20)
+#define SSP_DEBUG_MSTK_SM_MSTK_BS2 (0x4 << 20)
+#define SSP_DEBUG_MSTK_SM_MSTK_HDSHK (0x5 << 20)
+#define SSP_DEBUG_MSTK_SM_MSTK_BS3 (0x6 << 20)
+#define SSP_DEBUG_MSTK_SM_MSTK_RW (0x7 << 20)
+#define SSP_DEBUG_MSTK_SM_MSTK_CRC1 (0x8 << 20)
+#define SSP_DEBUG_MSTK_SM_MSTK_CRC2 (0x9 << 20)
+#define SSP_DEBUG_MSTK_SM_MSTK_BS0 (0xa << 20)
+#define SSP_DEBUG_MSTK_SM_MSTK_END1 (0xb << 20)
+#define SSP_DEBUG_MSTK_SM_MSTK_END2W (0xc << 20)
+#define SSP_DEBUG_MSTK_SM_MSTK_END2R (0xd << 20)
+#define SSP_DEBUG_MSTK_SM_MSTK_DONE (0xe << 20)
+#define SSP_DEBUG_CMD_OE (1 << 19)
+#define SSP_DEBUG_DMA_SM_MASK (0x7 << 16)
+#define SSP_DEBUG_DMA_SM_OFFSET 16
+#define SSP_DEBUG_DMA_SM_DMA_IDLE (0x0 << 16)
+#define SSP_DEBUG_DMA_SM_DMA_DMAREQ (0x1 << 16)
+#define SSP_DEBUG_DMA_SM_DMA_DMAACK (0x2 << 16)
+#define SSP_DEBUG_DMA_SM_DMA_STALL (0x3 << 16)
+#define SSP_DEBUG_DMA_SM_DMA_BUSY (0x4 << 16)
+#define SSP_DEBUG_DMA_SM_DMA_DONE (0x5 << 16)
+#define SSP_DEBUG_DMA_SM_DMA_COUNT (0x6 << 16)
+#define SSP_DEBUG_MMC_SM_MASK (0xf << 12)
+#define SSP_DEBUG_MMC_SM_OFFSET 12
+#define SSP_DEBUG_MMC_SM_MMC_IDLE (0x0 << 12)
+#define SSP_DEBUG_MMC_SM_MMC_CMD (0x1 << 12)
+#define SSP_DEBUG_MMC_SM_MMC_TRC (0x2 << 12)
+#define SSP_DEBUG_MMC_SM_MMC_RESP (0x3 << 12)
+#define SSP_DEBUG_MMC_SM_MMC_RPRX (0x4 << 12)
+#define SSP_DEBUG_MMC_SM_MMC_TX (0x5 << 12)
+#define SSP_DEBUG_MMC_SM_MMC_CTOK (0x6 << 12)
+#define SSP_DEBUG_MMC_SM_MMC_RX (0x7 << 12)
+#define SSP_DEBUG_MMC_SM_MMC_CCS (0x8 << 12)
+#define SSP_DEBUG_MMC_SM_MMC_PUP (0x9 << 12)
+#define SSP_DEBUG_MMC_SM_MMC_WAIT (0xa << 12)
+#define SSP_DEBUG_CMD_SM_MASK (0x3 << 10)
+#define SSP_DEBUG_CMD_SM_OFFSET 10
+#define SSP_DEBUG_CMD_SM_CSM_IDLE (0x0 << 10)
+#define SSP_DEBUG_CMD_SM_CSM_INDEX (0x1 << 10)
+#define SSP_DEBUG_CMD_SM_CSM_ARG (0x2 << 10)
+#define SSP_DEBUG_CMD_SM_CSM_CRC (0x3 << 10)
+#define SSP_DEBUG_SSP_CMD (1 << 9)
+#define SSP_DEBUG_SSP_RESP (1 << 8)
+#define SSP_DEBUG_SSP_RXD_MASK 0xff
+#define SSP_DEBUG_SSP_RXD_OFFSET 0
+
+#define SSP_VERSION_MAJOR_MASK (0xff << 24)
+#define SSP_VERSION_MAJOR_OFFSET 24
+#define SSP_VERSION_MINOR_MASK (0xff << 16)
+#define SSP_VERSION_MINOR_OFFSET 16
+#define SSP_VERSION_STEP_MASK 0xffff
+#define SSP_VERSION_STEP_OFFSET 0
+
+#endif /* __MX28_REGS_SSP_H__ */
diff --git a/arch/arm/include/asm/arch-mx28/regs-timrot.h b/arch/arm/include/asm/arch-mx28/regs-timrot.h
new file mode 100644
index 0000000..1b941cf
--- /dev/null
+++ b/arch/arm/include/asm/arch-mx28/regs-timrot.h
@@ -0,0 +1,171 @@
+/*
+ * Freescale i.MX28 TIMROT Register Definitions
+ *
+ * Copyright (C) 2011 Marek Vasut <marek.vasut@gmail.com>
+ *
+ * Based on code from LTIB:
+ * Copyright 2008-2010 Freescale Semiconductor, Inc. All Rights Reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
+ *
+ */
+
+#ifndef __MX28_REGS_TIMROT_H__
+#define __MX28_REGS_TIMROT_H__
+
+#include <asm/arch/regs-common.h>
+
+#ifndef __ASSEMBLY__
+struct mx28_timrot_regs {
+ mx28_reg(hw_timrot_rotctrl)
+ mx28_reg(hw_timrot_rotcount)
+ mx28_reg(hw_timrot_timctrl0)
+ mx28_reg(hw_timrot_running_count0)
+ mx28_reg(hw_timrot_fixed_count0)
+ mx28_reg(hw_timrot_match_count0)
+ mx28_reg(hw_timrot_timctrl1)
+ mx28_reg(hw_timrot_running_count1)
+ mx28_reg(hw_timrot_fixed_count1)
+ mx28_reg(hw_timrot_match_count1)
+ mx28_reg(hw_timrot_timctrl2)
+ mx28_reg(hw_timrot_running_count2)
+ mx28_reg(hw_timrot_fixed_count2)
+ mx28_reg(hw_timrot_match_count2)
+ mx28_reg(hw_timrot_timctrl3)
+ mx28_reg(hw_timrot_running_count3)
+ mx28_reg(hw_timrot_fixed_count3)
+ mx28_reg(hw_timrot_match_count3)
+ mx28_reg(hw_timrot_version)
+};
+#endif
+
+#define TIMROT_ROTCTRL_SFTRST (1 << 31)
+#define TIMROT_ROTCTRL_CLKGATE (1 << 30)
+#define TIMROT_ROTCTRL_ROTARY_PRESENT (1 << 29)
+#define TIMROT_ROTCTRL_TIM3_PRESENT (1 << 28)
+#define TIMROT_ROTCTRL_TIM2_PRESENT (1 << 27)
+#define TIMROT_ROTCTRL_TIM1_PRESENT (1 << 26)
+#define TIMROT_ROTCTRL_TIM0_PRESENT (1 << 25)
+#define TIMROT_ROTCTRL_STATE_MASK (0x7 << 22)
+#define TIMROT_ROTCTRL_STATE_OFFSET 22
+#define TIMROT_ROTCTRL_DIVIDER_MASK (0x3f << 16)
+#define TIMROT_ROTCTRL_DIVIDER_OFFSET 16
+#define TIMROT_ROTCTRL_RELATIVE (1 << 12)
+#define TIMROT_ROTCTRL_OVERSAMPLE_MASK (0x3 << 10)
+#define TIMROT_ROTCTRL_OVERSAMPLE_OFFSET 10
+#define TIMROT_ROTCTRL_OVERSAMPLE_8X (0x0 << 10)
+#define TIMROT_ROTCTRL_OVERSAMPLE_4X (0x1 << 10)
+#define TIMROT_ROTCTRL_OVERSAMPLE_2X (0x2 << 10)
+#define TIMROT_ROTCTRL_OVERSAMPLE_1X (0x3 << 10)
+#define TIMROT_ROTCTRL_POLARITY_B (1 << 9)
+#define TIMROT_ROTCTRL_POLARITY_A (1 << 8)
+#define TIMROT_ROTCTRL_SELECT_B_MASK (0xf << 4)
+#define TIMROT_ROTCTRL_SELECT_B_OFFSET 4
+#define TIMROT_ROTCTRL_SELECT_B_NEVER_TICK (0x0 << 4)
+#define TIMROT_ROTCTRL_SELECT_B_PWM0 (0x1 << 4)
+#define TIMROT_ROTCTRL_SELECT_B_PWM1 (0x2 << 4)
+#define TIMROT_ROTCTRL_SELECT_B_PWM2 (0x3 << 4)
+#define TIMROT_ROTCTRL_SELECT_B_PWM3 (0x4 << 4)
+#define TIMROT_ROTCTRL_SELECT_B_PWM4 (0x5 << 4)
+#define TIMROT_ROTCTRL_SELECT_B_PWM5 (0x6 << 4)
+#define TIMROT_ROTCTRL_SELECT_B_PWM6 (0x7 << 4)
+#define TIMROT_ROTCTRL_SELECT_B_PWM7 (0x8 << 4)
+#define TIMROT_ROTCTRL_SELECT_B_ROTARYA (0x9 << 4)
+#define TIMROT_ROTCTRL_SELECT_B_ROTARYB (0xa << 4)
+#define TIMROT_ROTCTRL_SELECT_A_MASK 0xf
+#define TIMROT_ROTCTRL_SELECT_A_OFFSET 0
+#define TIMROT_ROTCTRL_SELECT_A_NEVER_TICK 0x0
+#define TIMROT_ROTCTRL_SELECT_A_PWM0 0x1
+#define TIMROT_ROTCTRL_SELECT_A_PWM1 0x2
+#define TIMROT_ROTCTRL_SELECT_A_PWM2 0x3
+#define TIMROT_ROTCTRL_SELECT_A_PWM3 0x4
+#define TIMROT_ROTCTRL_SELECT_A_PWM4 0x5
+#define TIMROT_ROTCTRL_SELECT_A_PWM5 0x6
+#define TIMROT_ROTCTRL_SELECT_A_PWM6 0x7
+#define TIMROT_ROTCTRL_SELECT_A_PWM7 0x8
+#define TIMROT_ROTCTRL_SELECT_A_ROTARYA 0x9
+#define TIMROT_ROTCTRL_SELECT_A_ROTARYB 0xa
+
+#define TIMROT_ROTCOUNT_UPDOWN_MASK 0xffff
+#define TIMROT_ROTCOUNT_UPDOWN_OFFSET 0
+
+#define TIMROT_TIMCTRLn_IRQ (1 << 15)
+#define TIMROT_TIMCTRLn_IRQ_EN (1 << 14)
+#define TIMROT_TIMCTRLn_MATCH_MODE (1 << 11)
+#define TIMROT_TIMCTRLn_POLARITY (1 << 8)
+#define TIMROT_TIMCTRLn_UPDATE (1 << 7)
+#define TIMROT_TIMCTRLn_RELOAD (1 << 6)
+#define TIMROT_TIMCTRLn_PRESCALE_MASK (0x3 << 4)
+#define TIMROT_TIMCTRLn_PRESCALE_OFFSET 4
+#define TIMROT_TIMCTRLn_PRESCALE_DIV_BY_1 (0x0 << 4)
+#define TIMROT_TIMCTRLn_PRESCALE_DIV_BY_2 (0x1 << 4)
+#define TIMROT_TIMCTRLn_PRESCALE_DIV_BY_4 (0x2 << 4)
+#define TIMROT_TIMCTRLn_PRESCALE_DIV_BY_8 (0x3 << 4)
+#define TIMROT_TIMCTRLn_SELECT_MASK 0xf
+#define TIMROT_TIMCTRLn_SELECT_OFFSET 0
+#define TIMROT_TIMCTRLn_SELECT_NEVER_TICK 0x0
+#define TIMROT_TIMCTRLn_SELECT_PWM0 0x1
+#define TIMROT_TIMCTRLn_SELECT_PWM1 0x2
+#define TIMROT_TIMCTRLn_SELECT_PWM2 0x3
+#define TIMROT_TIMCTRLn_SELECT_PWM3 0x4
+#define TIMROT_TIMCTRLn_SELECT_PWM4 0x5
+#define TIMROT_TIMCTRLn_SELECT_PWM5 0x6
+#define TIMROT_TIMCTRLn_SELECT_PWM6 0x7
+#define TIMROT_TIMCTRLn_SELECT_PWM7 0x8
+#define TIMROT_TIMCTRLn_SELECT_ROTARYA 0x9
+#define TIMROT_TIMCTRLn_SELECT_ROTARYB 0xa
+#define TIMROT_TIMCTRLn_SELECT_32KHZ_XTAL 0xb
+#define TIMROT_TIMCTRLn_SELECT_8KHZ_XTAL 0xc
+#define TIMROT_TIMCTRLn_SELECT_4KHZ_XTAL 0xd
+#define TIMROT_TIMCTRLn_SELECT_1KHZ_XTAL 0xe
+#define TIMROT_TIMCTRLn_SELECT_TICK_ALWAYS 0xf
+
+#define TIMROT_RUNNING_COUNTn_RUNNING_COUNT_MASK 0xffffffff
+#define TIMROT_RUNNING_COUNTn_RUNNING_COUNT_OFFSET 0
+
+#define TIMROT_FIXED_COUNTn_FIXED_COUNT_MASK 0xffffffff
+#define TIMROT_FIXED_COUNTn_FIXED_COUNT_OFFSET 0
+
+#define TIMROT_MATCH_COUNTn_MATCH_COUNT_MASK 0xffffffff
+#define TIMROT_MATCH_COUNTn_MATCH_COUNT_OFFSET 0
+
+#define TIMROT_TIMCTRL3_TEST_SIGNAL_MASK (0xf << 16)
+#define TIMROT_TIMCTRL3_TEST_SIGNAL_OFFSET 16
+#define TIMROT_TIMCTRL3_TEST_SIGNAL_NEVER_TICK (0x0 << 16)
+#define TIMROT_TIMCTRL3_TEST_SIGNAL_PWM0 (0x1 << 16)
+#define TIMROT_TIMCTRL3_TEST_SIGNAL_PWM1 (0x2 << 16)
+#define TIMROT_TIMCTRL3_TEST_SIGNAL_PWM2 (0x3 << 16)
+#define TIMROT_TIMCTRL3_TEST_SIGNAL_PWM3 (0x4 << 16)
+#define TIMROT_TIMCTRL3_TEST_SIGNAL_PWM4 (0x5 << 16)
+#define TIMROT_TIMCTRL3_TEST_SIGNAL_PWM5 (0x6 << 16)
+#define TIMROT_TIMCTRL3_TEST_SIGNAL_PWM6 (0x7 << 16)
+#define TIMROT_TIMCTRL3_TEST_SIGNAL_PWM7 (0x8 << 16)
+#define TIMROT_TIMCTRL3_TEST_SIGNAL_ROTARYA (0x9 << 16)
+#define TIMROT_TIMCTRL3_TEST_SIGNAL_ROTARYB (0xa << 16)
+#define TIMROT_TIMCTRL3_TEST_SIGNAL_32KHZ_XTAL (0xb << 16)
+#define TIMROT_TIMCTRL3_TEST_SIGNAL_8KHZ_XTAL (0xc << 16)
+#define TIMROT_TIMCTRL3_TEST_SIGNAL_4KHZ_XTAL (0xd << 16)
+#define TIMROT_TIMCTRL3_TEST_SIGNAL_1KHZ_XTAL (0xe << 16)
+#define TIMROT_TIMCTRL3_TEST_SIGNAL_TICK_ALWAYS (0xf << 16)
+#define TIMROT_TIMCTRL3_DUTY_CYCLE (1 << 9)
+
+#define TIMROT_VERSION_MAJOR_MASK (0xff << 24)
+#define TIMROT_VERSION_MAJOR_OFFSET 24
+#define TIMROT_VERSION_MINOR_MASK (0xff << 16)
+#define TIMROT_VERSION_MINOR_OFFSET 16
+#define TIMROT_VERSION_STEP_MASK 0xffff
+#define TIMROT_VERSION_STEP_OFFSET 0
+
+#endif /* __MX28_REGS_TIMROT_H__ */
diff --git a/arch/arm/include/asm/arch-mx28/regs-usb.h b/arch/arm/include/asm/arch-mx28/regs-usb.h
new file mode 100644
index 0000000..ea61de8
--- /dev/null
+++ b/arch/arm/include/asm/arch-mx28/regs-usb.h
@@ -0,0 +1,178 @@
+/*
+ * Freescale i.MX28 USB OTG Register Definitions
+ *
+ * Copyright (C) 2011 Marek Vasut <marek.vasut@gmail.com>
+ * on behalf of DENX Software Engineering GmbH
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
+ *
+ */
+
+#ifndef __REGS_USB_H__
+#define __REGS_USB_H__
+
+struct mx28_usb_regs {
+ uint32_t hw_usbctrl_id; /* 0x000 */
+ uint32_t hw_usbctrl_hwgeneral; /* 0x004 */
+ uint32_t hw_usbctrl_hwhost; /* 0x008 */
+ uint32_t hw_usbctrl_hwdevice; /* 0x00c */
+ uint32_t hw_usbctrl_hwtxbuf; /* 0x010 */
+ uint32_t hw_usbctrl_hwrxbuf; /* 0x014 */
+
+ uint32_t reserved1[26];
+
+ uint32_t hw_usbctrl_gptimer0ld; /* 0x080 */
+ uint32_t hw_usbctrl_gptimer0ctrl; /* 0x084 */
+ uint32_t hw_usbctrl_gptimer1ld; /* 0x088 */
+ uint32_t hw_usbctrl_gptimer1ctrl; /* 0x08c */
+ uint32_t hw_usbctrl_sbuscfg; /* 0x090 */
+
+ uint32_t reserved2[27];
+
+ uint32_t hw_usbctrl_caplength; /* 0x100 */
+ uint32_t hw_usbctrl_hcsparams; /* 0x104 */
+ uint32_t hw_usbctrl_hccparams; /* 0x108 */
+
+ uint32_t reserved3[5];
+
+ uint32_t hw_usbctrl_dciversion; /* 0x120 */
+ uint32_t hw_usbctrl_dccparams; /* 0x124 */
+
+ uint32_t reserved4[6];
+
+ uint32_t hw_usbctrl_usbcmd; /* 0x140 */
+ uint32_t hw_usbctrl_usbsts; /* 0x144 */
+ uint32_t hw_usbctrl_usbintr; /* 0x148 */
+ uint32_t hw_usbctrl_frindex; /* 0x14c */
+
+ uint32_t reserved5;
+
+ union {
+ uint32_t hw_usbctrl_periodiclistbase; /* 0x154 */
+ uint32_t hw_usbctrl_deviceaddr; /* 0x154 */
+ };
+ union {
+ uint32_t hw_usbctrl_asynclistaddr; /* 0x158 */
+ uint32_t hw_usbctrl_endpointlistaddr; /* 0x158 */
+ };
+
+ uint32_t hw_usbctrl_ttctrl; /* 0x15c */
+ uint32_t hw_usbctrl_burstsize; /* 0x160 */
+ uint32_t hw_usbctrl_txfilltuning; /* 0x164 */
+
+ uint32_t reserved6;
+
+ uint32_t hw_usbctrl_ic_usb; /* 0x16c */
+ uint32_t hw_usbctrl_ulpi; /* 0x170 */
+
+ uint32_t reserved7;
+
+ uint32_t hw_usbctrl_endptnak; /* 0x178 */
+ uint32_t hw_usbctrl_endptnaken; /* 0x17c */
+
+ uint32_t reserved8;
+
+ uint32_t hw_usbctrl_portsc1; /* 0x184 */
+
+ uint32_t reserved9[7];
+
+ uint32_t hw_usbctrl_otgsc; /* 0x1a4 */
+ uint32_t hw_usbctrl_usbmode; /* 0x1a8 */
+ uint32_t hw_usbctrl_endptsetupstat; /* 0x1ac */
+ uint32_t hw_usbctrl_endptprime; /* 0x1b0 */
+ uint32_t hw_usbctrl_endptflush; /* 0x1b4 */
+ uint32_t hw_usbctrl_endptstat; /* 0x1b8 */
+ uint32_t hw_usbctrl_endptcomplete; /* 0x1bc */
+ uint32_t hw_usbctrl_endptctrl0; /* 0x1c0 */
+ uint32_t hw_usbctrl_endptctrl1; /* 0x1c4 */
+ uint32_t hw_usbctrl_endptctrl2; /* 0x1c8 */
+ uint32_t hw_usbctrl_endptctrl3; /* 0x1cc */
+ uint32_t hw_usbctrl_endptctrl4; /* 0x1d0 */
+ uint32_t hw_usbctrl_endptctrl5; /* 0x1d4 */
+ uint32_t hw_usbctrl_endptctrl6; /* 0x1d8 */
+ uint32_t hw_usbctrl_endptctrl7; /* 0x1dc */
+};
+
+#define CLKCTRL_PLL0CTRL0_LFR_SEL_MASK (0x3 << 28)
+
+#define HW_USBCTRL_ID_CIVERSION_OFFSET 29
+#define HW_USBCTRL_ID_CIVERSION_MASK (0x7 << 29)
+#define HW_USBCTRL_ID_VERSION_OFFSET 25
+#define HW_USBCTRL_ID_VERSION_MASK (0xf << 25)
+#define HW_USBCTRL_ID_REVISION_OFFSET 21
+#define HW_USBCTRL_ID_REVISION_MASK (0xf << 21)
+#define HW_USBCTRL_ID_TAG_OFFSET 16
+#define HW_USBCTRL_ID_TAG_MASK (0x1f << 16)
+#define HW_USBCTRL_ID_NID_OFFSET 8
+#define HW_USBCTRL_ID_NID_MASK (0x3f << 8)
+#define HW_USBCTRL_ID_ID_OFFSET 0
+#define HW_USBCTRL_ID_ID_MASK (0x3f << 0)
+
+#define HW_USBCTRL_HWGENERAL_SM_OFFSET 9
+#define HW_USBCTRL_HWGENERAL_SM_MASK (0x3 << 9)
+#define HW_USBCTRL_HWGENERAL_PHYM_OFFSET 6
+#define HW_USBCTRL_HWGENERAL_PHYM_MASK (0x7 << 6)
+#define HW_USBCTRL_HWGENERAL_PHYW_OFFSET 4
+#define HW_USBCTRL_HWGENERAL_PHYW_MASK (0x3 << 4)
+#define HW_USBCTRL_HWGENERAL_BWT (1 << 3)
+#define HW_USBCTRL_HWGENERAL_CLKC_OFFSET 1
+#define HW_USBCTRL_HWGENERAL_CLKC_MASK (0x3 << 1)
+#define HW_USBCTRL_HWGENERAL_RT (1 << 0)
+
+#define HW_USBCTRL_HWHOST_TTPER_OFFSET 24
+#define HW_USBCTRL_HWHOST_TTPER_MASK (0xff << 24)
+#define HW_USBCTRL_HWHOST_TTASY_OFFSET 16
+#define HW_USBCTRL_HWHOST_TTASY_MASK (0xff << 19)
+#define HW_USBCTRL_HWHOST_NPORT_OFFSET 1
+#define HW_USBCTRL_HWHOST_NPORT_MASK (0x7 << 1)
+#define HW_USBCTRL_HWHOST_HC (1 << 0)
+
+#define HW_USBCTRL_HWDEVICE_DEVEP_OFFSET 1
+#define HW_USBCTRL_HWDEVICE_DEVEP_MASK (0x1f << 1)
+#define HW_USBCTRL_HWDEVICE_DC (1 << 0)
+
+#define HW_USBCTRL_HWTXBUF_TXLCR (1 << 31)
+#define HW_USBCTRL_HWTXBUF_TXCHANADD_OFFSET 16
+#define HW_USBCTRL_HWTXBUF_TXCHANADD_MASK (0xff << 16)
+#define HW_USBCTRL_HWTXBUF_TXADD_OFFSET 8
+#define HW_USBCTRL_HWTXBUF_TXADD_MASK (0xff << 8)
+#define HW_USBCTRL_HWTXBUF_TXBURST_OFFSET 0
+#define HW_USBCTRL_HWTXBUF_TXBURST_MASK 0xff
+
+#define HW_USBCTRL_HWRXBUF_RXADD_OFFSET 8
+#define HW_USBCTRL_HWRXBUF_RXADD_MASK (0xff << 8)
+#define HW_USBCTRL_HWRXBUF_RXBURST_OFFSET 0
+#define HW_USBCTRL_HWRXBUF_RXBURST_MASK 0xff
+
+#define HW_USBCTRL_GPTIMERLD_GPTLD_OFFSET 0
+#define HW_USBCTRL_GPTIMERLD_GPTLD_MASK 0xffffff
+
+#define HW_USBCTRL_GPTIMERCTRL_GPTRUN (1 << 31)
+#define HW_USBCTRL_GPTIMERCTRL_GPTRST (1 << 30)
+#define HW_USBCTRL_GPTIMERCTRL_GPTMODE (1 << 24)
+#define HW_USBCTRL_GPTIMERCTRL_GPTCNT_OFFSET 0
+#define HW_USBCTRL_GPTIMERCTRL_GPTCNT_MASK 0xffffff
+
+#define HW_USBCTRL_SBUSCFG_AHBBURST_OFFSET 0
+#define HW_USBCTRL_SBUSCFG_AHBBURST_MASK 0x7
+#define HW_USBCTRL_SBUSCFG_AHBBURST_U_INCR 0x0
+#define HW_USBCTRL_SBUSCFG_AHBBURST_S_INCR4 0x1
+#define HW_USBCTRL_SBUSCFG_AHBBURST_S_INCR8 0x2
+#define HW_USBCTRL_SBUSCFG_AHBBURST_S_INCR16 0x3
+#define HW_USBCTRL_SBUSCFG_AHBBURST_U_INCR4 0x5
+#define HW_USBCTRL_SBUSCFG_AHBBURST_U_INCR8 0x6
+#define HW_USBCTRL_SBUSCFG_AHBBURST_U_INCR16 0x7
+
+#endif /* __REGS_USB_H__ */
diff --git a/arch/arm/include/asm/arch-mx28/regs-usbphy.h b/arch/arm/include/asm/arch-mx28/regs-usbphy.h
new file mode 100644
index 0000000..e823e19
--- /dev/null
+++ b/arch/arm/include/asm/arch-mx28/regs-usbphy.h
@@ -0,0 +1,151 @@
+/*
+ * Freescale i.MX28 USB PHY Register Definitions
+ *
+ * Copyright (C) 2011 Marek Vasut <marek.vasut@gmail.com>
+ * on behalf of DENX Software Engineering GmbH
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
+ *
+ */
+
+#ifndef __REGS_USBPHY_H__
+#define __REGS_USBPHY_H__
+
+struct mx28_usbphy_regs {
+ mx28_reg(hw_usbphy_pwd)
+ mx28_reg(hw_usbphy_tx)
+ mx28_reg(hw_usbphy_rx)
+ mx28_reg(hw_usbphy_ctrl)
+ mx28_reg(hw_usbphy_status)
+ mx28_reg(hw_usbphy_debug)
+ mx28_reg(hw_usbphy_debug0_status)
+ mx28_reg(hw_usbphy_debug1)
+ mx28_reg(hw_usbphy_version)
+ mx28_reg(hw_usbphy_ip)
+};
+
+#define USBPHY_PWD_RXPWDRX (1 << 20)
+#define USBPHY_PWD_RXPWDDIFF (1 << 19)
+#define USBPHY_PWD_RXPWD1PT1 (1 << 18)
+#define USBPHY_PWD_RXPWDENV (1 << 17)
+#define USBPHY_PWD_TXPWDV2I (1 << 12)
+#define USBPHY_PWD_TXPWDIBIAS (1 << 11)
+#define USBPHY_PWD_TXPWDFS (1 << 10)
+
+#define USBPHY_TX_USBPHY_TX_EDGECTRL_OFFSET 26
+#define USBPHY_TX_USBPHY_TX_EDGECTRL_MASK (0x7 << 26)
+#define USBPHY_TX_USBPHY_TX_SYNC_INVERT (1 << 25)
+#define USBPHY_TX_USBPHY_TX_SYNC_MUX (1 << 24)
+#define USBPHY_TX_TXENCAL45DP (1 << 21)
+#define USBPHY_TX_TXCAL45DP_OFFSET 16
+#define USBPHY_TX_TXCAL45DP_MASK (0xf << 16)
+#define USBPHY_TX_TXENCAL45DM (1 << 13)
+#define USBPHY_TX_TXCAL45DM_OFFSET 8
+#define USBPHY_TX_TXCAL45DM_MASK (0xf << 8)
+#define USBPHY_TX_D_CAL_OFFSET 0
+#define USBPHY_TX_D_CAL_MASK 0xf
+
+#define USBPHY_RX_RXDBYPASS (1 << 22)
+#define USBPHY_RX_DISCONADJ_OFFSET 4
+#define USBPHY_RX_DISCONADJ_MASK (0x7 << 4)
+#define USBPHY_RX_ENVADJ_OFFSET 0
+#define USBPHY_RX_ENVADJ_MASK 0x7
+
+#define USBPHY_CTRL_SFTRST (1 << 31)
+#define USBPHY_CTRL_CLKGATE (1 << 30)
+#define USBPHY_CTRL_UTMI_SUSPENDM (1 << 29)
+#define USBPHY_CTRL_HOST_FORCE_LS_SE0 (1 << 28)
+#define USBPHY_CTRL_ENAUTOSET_USBCLKS (1 << 26)
+#define USBPHY_CTRL_ENAUTOCLR_USBCLKGATE (1 << 25)
+#define USBPHY_CTRL_FSDLL_RST_EN (1 << 24)
+#define USBPHY_CTRL_ENVBUSCHG_WKUP (1 << 23)
+#define USBPHY_CTRL_ENIDCHG_WKUP (1 << 22)
+#define USBPHY_CTRL_ENDPDMCHG_WKUP (1 << 21)
+#define USBPHY_CTRL_ENAUTOCLR_PHY_PWD (1 << 20)
+#define USBPHY_CTRL_ENAUTOCLR_CLKGATE (1 << 19)
+#define USBPHY_CTRL_ENAUTO_PWRON_PLL (1 << 18)
+#define USBPHY_CTRL_WAKEUP_IRQ (1 << 17)
+#define USBPHY_CTRL_ENIRQWAKEUP (1 << 16)
+#define USBPHY_CTRL_ENUTMILEVEL3 (1 << 15)
+#define USBPHY_CTRL_ENUTMILEVEL2 (1 << 14)
+#define USBPHY_CTRL_DATA_ON_LRADC (1 << 13)
+#define USBPHY_CTRL_DEVPLUGIN_IRQ (1 << 12)
+#define USBPHY_CTRL_ENIRQDEVPLUGIN (1 << 11)
+#define USBPHY_CTRL_RESUME_IRQ (1 << 10)
+#define USBPHY_CTRL_ENIRQRESUMEDETECT (1 << 9)
+#define USBPHY_CTRL_RESUMEIRQSTICKY (1 << 8)
+#define USBPHY_CTRL_ENOTGIDDETECT (1 << 7)
+#define USBPHY_CTRL_DEVPLUGIN_POLARITY (1 << 5)
+#define USBPHY_CTRL_ENDEVPLUGINDETECT (1 << 4)
+#define USBPHY_CTRL_HOSTDISCONDETECT_IRQ (1 << 3)
+#define USBPHY_CTRL_ENIRQHOSTDISCON (1 << 2)
+#define USBPHY_CTRL_ENHOSTDISCONDETECT (1 << 1)
+
+#define USBPHY_STATUS_RESUME_STATUS (1 << 10)
+#define USBPHY_STATUS_OTGID_STATUS (1 << 8)
+#define USBPHY_STATUS_DEVPLUGIN_STATUS (1 << 6)
+#define USBPHY_STATUS_HOSTDISCONDETECT_STATUS (1 << 3)
+
+#define USBPHY_DEBUG_CLKGATE (1 << 30)
+#define USBPHY_DEBUG_HOST_RESUME_DEBUG (1 << 29)
+#define USBPHY_DEBUG_SQUELCHRESETLENGTH_OFFSET 25
+#define USBPHY_DEBUG_SQUELCHRESETLENGTH_MASK (0xf << 25)
+#define USBPHY_DEBUG_ENSQUELCHRESET (1 << 24)
+#define USBPHY_DEBUG_SQUELCHRESETCOUNT_OFFSET 16
+#define USBPHY_DEBUG_SQUELCHRESETCOUNT_MASK (0x1f << 16)
+#define USBPHY_DEBUG_ENTX2RXCOUNT (1 << 12)
+#define USBPHY_DEBUG_TX2RXCOUNT_OFFSET 8
+#define USBPHY_DEBUG_TX2RXCOUNT_MASK (0xf << 8)
+#define USBPHY_DEBUG_ENHSTPULLDOWN_OFFSET 4
+#define USBPHY_DEBUG_ENHSTPULLDOWN_MASK (0x3 << 4)
+#define USBPHY_DEBUG_HSTPULLDOWN_OFFSET 2
+#define USBPHY_DEBUG_HSTPULLDOWN_MASK (0x3 << 2)
+#define USBPHY_DEBUG_DEBUG_INTERFACE_HOLD (1 << 1)
+#define USBPHY_DEBUG_OTGIDPIDLOCK (1 << 0)
+
+#define USBPHY_DEBUG0_STATUS_SQUELCH_COUNT_OFFSET 26
+#define USBPHY_DEBUG0_STATUS_SQUELCH_COUNT_MASK (0x3f << 26)
+#define USBPHY_DEBUG0_STATUS_UTMI_RXERROR_OFFSET 16
+#define USBPHY_DEBUG0_STATUS_UTMI_RXERROR_MASK (0x3ff << 16)
+#define USBPHY_DEBUG0_STATUS_LOOP_BACK_OFFSET 0
+#define USBPHY_DEBUG0_STATUS_LOOP_BACK_MASK 0xffff
+
+#define USBPHY_DEBUG1_ENTAILADJVD_OFFSET 13
+#define USBPHY_DEBUG1_ENTAILADJVD_MASK (0x3 << 13)
+#define USBPHY_DEBUG1_ENTX2TX (1 << 12)
+#define USBPHY_DEBUG1_DBG_ADDRESS_OFFSET 0
+#define USBPHY_DEBUG1_DBG_ADDRESS_MASK 0xf
+
+#define USBPHY_VERSION_MAJOR_MASK (0xff << 24)
+#define USBPHY_VERSION_MAJOR_OFFSET 24
+#define USBPHY_VERSION_MINOR_MASK (0xff << 16)
+#define USBPHY_VERSION_MINOR_OFFSET 16
+#define USBPHY_VERSION_STEP_MASK 0xffff
+#define USBPHY_VERSION_STEP_OFFSET 0
+
+#define USBPHY_IP_DIV_SEL_OFFSET 23
+#define USBPHY_IP_DIV_SEL_MASK (0x3 << 23)
+#define USBPHY_IP_LFR_SEL_OFFSET 21
+#define USBPHY_IP_LFR_SEL_MASK (0x3 << 21)
+#define USBPHY_IP_CP_SEL_OFFSET 19
+#define USBPHY_IP_CP_SEL_MASK (0x3 << 19)
+#define USBPHY_IP_TSTI_TX_DP (1 << 18)
+#define USBPHY_IP_TSTI_TX_DM (1 << 17)
+#define USBPHY_IP_ANALOG_TESTMODE (1 << 16)
+#define USBPHY_IP_EN_USB_CLKS (1 << 2)
+#define USBPHY_IP_PLL_LOCKED (1 << 1)
+#define USBPHY_IP_PLL_POWER (1 << 0)
+
+#endif /* __REGS_USBPHY_H__ */
diff --git a/arch/arm/include/asm/arch-mx28/sys_proto.h b/arch/arm/include/asm/arch-mx28/sys_proto.h
new file mode 100644
index 0000000..a226ea4
--- /dev/null
+++ b/arch/arm/include/asm/arch-mx28/sys_proto.h
@@ -0,0 +1,32 @@
+/*
+ * Freescale i.MX28 MX28 specific functions
+ *
+ * Copyright (C) 2011 Marek Vasut <marek.vasut@gmail.com>
+ * on behalf of DENX Software Engineering GmbH
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
+ *
+ */
+
+#ifndef __MX28_H__
+#define __MX28_H__
+
+int mx28_reset_block(struct mx28_register *reg);
+int mx28_wait_mask_set(struct mx28_register *reg, uint32_t mask, int timeout);
+int mx28_wait_mask_clr(struct mx28_register *reg, uint32_t mask, int timeout);
+
+int mxsmmc_initialize(bd_t *bis, int id, int (*wp)(int));
+
+#endif /* __MX28_H__ */
diff --git a/arch/arm/include/asm/arch-mx31/imx-regs.h b/arch/arm/include/asm/arch-mx31/imx-regs.h
index afdaa1c..0147920 100644
--- a/arch/arm/include/asm/arch-mx31/imx-regs.h
+++ b/arch/arm/include/asm/arch-mx31/imx-regs.h
@@ -98,6 +98,12 @@
u32 iim_scs3;
};
+struct iomuxc_regs {
+ u32 unused1;
+ u32 unused2;
+ u32 gpr;
+};
+
struct mx3_cpu_type {
u8 srev;
u32 v;
@@ -636,7 +642,6 @@
#define WEIM_BASE 0xb8002000
#define IOMUXC_BASE 0x43FAC000
-#define IOMUXC_GPR (IOMUXC_BASE + 0x8)
#define IOMUXC_SW_MUX_CTL(x) (IOMUXC_BASE + 0xc + (x) * 4)
#define IOMUXC_SW_PAD_CTL(x) (IOMUXC_BASE + 0x154 + (x) * 4)
diff --git a/arch/arm/include/asm/arch-omap3/mmc_host_def.h b/arch/arm/include/asm/arch-omap3/mmc_host_def.h
index ba1c2ff..2963679 100644
--- a/arch/arm/include/asm/arch-omap3/mmc_host_def.h
+++ b/arch/arm/include/asm/arch-omap3/mmc_host_def.h
@@ -55,7 +55,7 @@
#define OMAP_HSMMC2_BASE 0x480B4000
#define OMAP_HSMMC3_BASE 0x480AD000
-typedef struct hsmmc {
+struct hsmmc {
unsigned char res1[0x10];
unsigned int sysconfig; /* 0x10 */
unsigned int sysstatus; /* 0x14 */
@@ -77,7 +77,7 @@
unsigned int ie; /* 0x134 */
unsigned char res4[0x8];
unsigned int capa; /* 0x140 */
-} hsmmc_t;
+};
/*
* OMAP HS MMC Bit definitions
@@ -182,13 +182,6 @@
#define CLK_400KHZ 1
#define CLK_MISC 2
-typedef struct {
- unsigned int card_type;
- unsigned int version;
- unsigned int mode;
- unsigned int size;
- unsigned int RCA;
-} mmc_card_data;
#define RSP_TYPE_NONE (RSP_TYPE_NORSP | CCCE_NOCHECK | CICE_NOCHECK)
#define MMC_CMD0 (INDEX(0) | RSP_TYPE_NONE | DP_NO_DATA | DDIR_WRITE)
diff --git a/arch/arm/include/asm/arch-omap4/clocks.h b/arch/arm/include/asm/arch-omap4/clocks.h
index 45c947d..c2a9b46 100644
--- a/arch/arm/include/asm/arch-omap4/clocks.h
+++ b/arch/arm/include/asm/arch-omap4/clocks.h
@@ -687,4 +687,27 @@
s8 m7;
};
+extern struct omap4_prcm_regs *const prcm;
+extern const u32 sys_clk_array[8];
+
+void scale_vcores(void);
+void do_scale_tps62361(u32 reg, u32 volt_mv);
+u32 omap_ddr_clk(void);
+void do_scale_vcore(u32 vcore_reg, u32 volt_mv);
+void setup_sri2c(void);
+void setup_post_dividers(u32 *const base, const struct dpll_params *params);
+u32 get_sys_clk_index(void);
+void enable_basic_clocks(void);
+void enable_basic_uboot_clocks(void);
+void enable_non_essential_clocks(void);
+void do_enable_clocks(u32 *const *clk_domains,
+ u32 *const *clk_modules_hw_auto,
+ u32 *const *clk_modules_explicit_en,
+ u8 wait_for_enable);
+const struct dpll_params *get_mpu_dpll_params(void);
+const struct dpll_params *get_core_dpll_params(void);
+const struct dpll_params *get_per_dpll_params(void);
+const struct dpll_params *get_iva_dpll_params(void);
+const struct dpll_params *get_usb_dpll_params(void);
+const struct dpll_params *get_abe_dpll_params(void);
#endif /* _CLOCKS_OMAP4_H_ */
diff --git a/arch/arm/include/asm/arch-omap4/emif.h b/arch/arm/include/asm/arch-omap4/emif.h
deleted file mode 100644
index 3a549ba..0000000
--- a/arch/arm/include/asm/arch-omap4/emif.h
+++ /dev/null
@@ -1,1021 +0,0 @@
-/*
- * OMAP44xx EMIF header
- *
- * Copyright (C) 2009-2010 Texas Instruments, Inc.
- *
- * Aneesh V <aneesh@ti.com>
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
- */
-
-#ifndef _EMIF_H_
-#define _EMIF_H_
-#include <asm/types.h>
-#include <common.h>
-
-/* Base address */
-#define OMAP44XX_EMIF1 0x4c000000
-#define OMAP44XX_EMIF2 0x4d000000
-
-/* Registers shifts and masks */
-
-/* EMIF_MOD_ID_REV */
-#define OMAP44XX_REG_SCHEME_SHIFT 30
-#define OMAP44XX_REG_SCHEME_MASK (0x3 << 30)
-#define OMAP44XX_REG_MODULE_ID_SHIFT 16
-#define OMAP44XX_REG_MODULE_ID_MASK (0xfff << 16)
-#define OMAP44XX_REG_RTL_VERSION_SHIFT 11
-#define OMAP44XX_REG_RTL_VERSION_MASK (0x1f << 11)
-#define OMAP44XX_REG_MAJOR_REVISION_SHIFT 8
-#define OMAP44XX_REG_MAJOR_REVISION_MASK (0x7 << 8)
-#define OMAP44XX_REG_MINOR_REVISION_SHIFT 0
-#define OMAP44XX_REG_MINOR_REVISION_MASK (0x3f << 0)
-
-/* STATUS */
-#define OMAP44XX_REG_BE_SHIFT 31
-#define OMAP44XX_REG_BE_MASK (1 << 31)
-#define OMAP44XX_REG_DUAL_CLK_MODE_SHIFT 30
-#define OMAP44XX_REG_DUAL_CLK_MODE_MASK (1 << 30)
-#define OMAP44XX_REG_FAST_INIT_SHIFT 29
-#define OMAP44XX_REG_FAST_INIT_MASK (1 << 29)
-#define OMAP44XX_REG_PHY_DLL_READY_SHIFT 2
-#define OMAP44XX_REG_PHY_DLL_READY_MASK (1 << 2)
-
-/* SDRAM_CONFIG */
-#define OMAP44XX_REG_SDRAM_TYPE_SHIFT 29
-#define OMAP44XX_REG_SDRAM_TYPE_MASK (0x7 << 29)
-#define OMAP44XX_REG_IBANK_POS_SHIFT 27
-#define OMAP44XX_REG_IBANK_POS_MASK (0x3 << 27)
-#define OMAP44XX_REG_DDR_TERM_SHIFT 24
-#define OMAP44XX_REG_DDR_TERM_MASK (0x7 << 24)
-#define OMAP44XX_REG_DDR2_DDQS_SHIFT 23
-#define OMAP44XX_REG_DDR2_DDQS_MASK (1 << 23)
-#define OMAP44XX_REG_DYN_ODT_SHIFT 21
-#define OMAP44XX_REG_DYN_ODT_MASK (0x3 << 21)
-#define OMAP44XX_REG_DDR_DISABLE_DLL_SHIFT 20
-#define OMAP44XX_REG_DDR_DISABLE_DLL_MASK (1 << 20)
-#define OMAP44XX_REG_SDRAM_DRIVE_SHIFT 18
-#define OMAP44XX_REG_SDRAM_DRIVE_MASK (0x3 << 18)
-#define OMAP44XX_REG_CWL_SHIFT 16
-#define OMAP44XX_REG_CWL_MASK (0x3 << 16)
-#define OMAP44XX_REG_NARROW_MODE_SHIFT 14
-#define OMAP44XX_REG_NARROW_MODE_MASK (0x3 << 14)
-#define OMAP44XX_REG_CL_SHIFT 10
-#define OMAP44XX_REG_CL_MASK (0xf << 10)
-#define OMAP44XX_REG_ROWSIZE_SHIFT 7
-#define OMAP44XX_REG_ROWSIZE_MASK (0x7 << 7)
-#define OMAP44XX_REG_IBANK_SHIFT 4
-#define OMAP44XX_REG_IBANK_MASK (0x7 << 4)
-#define OMAP44XX_REG_EBANK_SHIFT 3
-#define OMAP44XX_REG_EBANK_MASK (1 << 3)
-#define OMAP44XX_REG_PAGESIZE_SHIFT 0
-#define OMAP44XX_REG_PAGESIZE_MASK (0x7 << 0)
-
-/* SDRAM_CONFIG_2 */
-#define OMAP44XX_REG_CS1NVMEN_SHIFT 30
-#define OMAP44XX_REG_CS1NVMEN_MASK (1 << 30)
-#define OMAP44XX_REG_EBANK_POS_SHIFT 27
-#define OMAP44XX_REG_EBANK_POS_MASK (1 << 27)
-#define OMAP44XX_REG_RDBNUM_SHIFT 4
-#define OMAP44XX_REG_RDBNUM_MASK (0x3 << 4)
-#define OMAP44XX_REG_RDBSIZE_SHIFT 0
-#define OMAP44XX_REG_RDBSIZE_MASK (0x7 << 0)
-
-/* SDRAM_REF_CTRL */
-#define OMAP44XX_REG_INITREF_DIS_SHIFT 31
-#define OMAP44XX_REG_INITREF_DIS_MASK (1 << 31)
-#define OMAP44XX_REG_SRT_SHIFT 29
-#define OMAP44XX_REG_SRT_MASK (1 << 29)
-#define OMAP44XX_REG_ASR_SHIFT 28
-#define OMAP44XX_REG_ASR_MASK (1 << 28)
-#define OMAP44XX_REG_PASR_SHIFT 24
-#define OMAP44XX_REG_PASR_MASK (0x7 << 24)
-#define OMAP44XX_REG_REFRESH_RATE_SHIFT 0
-#define OMAP44XX_REG_REFRESH_RATE_MASK (0xffff << 0)
-
-/* SDRAM_REF_CTRL_SHDW */
-#define OMAP44XX_REG_REFRESH_RATE_SHDW_SHIFT 0
-#define OMAP44XX_REG_REFRESH_RATE_SHDW_MASK (0xffff << 0)
-
-/* SDRAM_TIM_1 */
-#define OMAP44XX_REG_T_RP_SHIFT 25
-#define OMAP44XX_REG_T_RP_MASK (0xf << 25)
-#define OMAP44XX_REG_T_RCD_SHIFT 21
-#define OMAP44XX_REG_T_RCD_MASK (0xf << 21)
-#define OMAP44XX_REG_T_WR_SHIFT 17
-#define OMAP44XX_REG_T_WR_MASK (0xf << 17)
-#define OMAP44XX_REG_T_RAS_SHIFT 12
-#define OMAP44XX_REG_T_RAS_MASK (0x1f << 12)
-#define OMAP44XX_REG_T_RC_SHIFT 6
-#define OMAP44XX_REG_T_RC_MASK (0x3f << 6)
-#define OMAP44XX_REG_T_RRD_SHIFT 3
-#define OMAP44XX_REG_T_RRD_MASK (0x7 << 3)
-#define OMAP44XX_REG_T_WTR_SHIFT 0
-#define OMAP44XX_REG_T_WTR_MASK (0x7 << 0)
-
-/* SDRAM_TIM_1_SHDW */
-#define OMAP44XX_REG_T_RP_SHDW_SHIFT 25
-#define OMAP44XX_REG_T_RP_SHDW_MASK (0xf << 25)
-#define OMAP44XX_REG_T_RCD_SHDW_SHIFT 21
-#define OMAP44XX_REG_T_RCD_SHDW_MASK (0xf << 21)
-#define OMAP44XX_REG_T_WR_SHDW_SHIFT 17
-#define OMAP44XX_REG_T_WR_SHDW_MASK (0xf << 17)
-#define OMAP44XX_REG_T_RAS_SHDW_SHIFT 12
-#define OMAP44XX_REG_T_RAS_SHDW_MASK (0x1f << 12)
-#define OMAP44XX_REG_T_RC_SHDW_SHIFT 6
-#define OMAP44XX_REG_T_RC_SHDW_MASK (0x3f << 6)
-#define OMAP44XX_REG_T_RRD_SHDW_SHIFT 3
-#define OMAP44XX_REG_T_RRD_SHDW_MASK (0x7 << 3)
-#define OMAP44XX_REG_T_WTR_SHDW_SHIFT 0
-#define OMAP44XX_REG_T_WTR_SHDW_MASK (0x7 << 0)
-
-/* SDRAM_TIM_2 */
-#define OMAP44XX_REG_T_XP_SHIFT 28
-#define OMAP44XX_REG_T_XP_MASK (0x7 << 28)
-#define OMAP44XX_REG_T_ODT_SHIFT 25
-#define OMAP44XX_REG_T_ODT_MASK (0x7 << 25)
-#define OMAP44XX_REG_T_XSNR_SHIFT 16
-#define OMAP44XX_REG_T_XSNR_MASK (0x1ff << 16)
-#define OMAP44XX_REG_T_XSRD_SHIFT 6
-#define OMAP44XX_REG_T_XSRD_MASK (0x3ff << 6)
-#define OMAP44XX_REG_T_RTP_SHIFT 3
-#define OMAP44XX_REG_T_RTP_MASK (0x7 << 3)
-#define OMAP44XX_REG_T_CKE_SHIFT 0
-#define OMAP44XX_REG_T_CKE_MASK (0x7 << 0)
-
-/* SDRAM_TIM_2_SHDW */
-#define OMAP44XX_REG_T_XP_SHDW_SHIFT 28
-#define OMAP44XX_REG_T_XP_SHDW_MASK (0x7 << 28)
-#define OMAP44XX_REG_T_ODT_SHDW_SHIFT 25
-#define OMAP44XX_REG_T_ODT_SHDW_MASK (0x7 << 25)
-#define OMAP44XX_REG_T_XSNR_SHDW_SHIFT 16
-#define OMAP44XX_REG_T_XSNR_SHDW_MASK (0x1ff << 16)
-#define OMAP44XX_REG_T_XSRD_SHDW_SHIFT 6
-#define OMAP44XX_REG_T_XSRD_SHDW_MASK (0x3ff << 6)
-#define OMAP44XX_REG_T_RTP_SHDW_SHIFT 3
-#define OMAP44XX_REG_T_RTP_SHDW_MASK (0x7 << 3)
-#define OMAP44XX_REG_T_CKE_SHDW_SHIFT 0
-#define OMAP44XX_REG_T_CKE_SHDW_MASK (0x7 << 0)
-
-/* SDRAM_TIM_3 */
-#define OMAP44XX_REG_T_CKESR_SHIFT 21
-#define OMAP44XX_REG_T_CKESR_MASK (0x7 << 21)
-#define OMAP44XX_REG_ZQ_ZQCS_SHIFT 15
-#define OMAP44XX_REG_ZQ_ZQCS_MASK (0x3f << 15)
-#define OMAP44XX_REG_T_TDQSCKMAX_SHIFT 13
-#define OMAP44XX_REG_T_TDQSCKMAX_MASK (0x3 << 13)
-#define OMAP44XX_REG_T_RFC_SHIFT 4
-#define OMAP44XX_REG_T_RFC_MASK (0x1ff << 4)
-#define OMAP44XX_REG_T_RAS_MAX_SHIFT 0
-#define OMAP44XX_REG_T_RAS_MAX_MASK (0xf << 0)
-
-/* SDRAM_TIM_3_SHDW */
-#define OMAP44XX_REG_T_CKESR_SHDW_SHIFT 21
-#define OMAP44XX_REG_T_CKESR_SHDW_MASK (0x7 << 21)
-#define OMAP44XX_REG_ZQ_ZQCS_SHDW_SHIFT 15
-#define OMAP44XX_REG_ZQ_ZQCS_SHDW_MASK (0x3f << 15)
-#define OMAP44XX_REG_T_TDQSCKMAX_SHDW_SHIFT 13
-#define OMAP44XX_REG_T_TDQSCKMAX_SHDW_MASK (0x3 << 13)
-#define OMAP44XX_REG_T_RFC_SHDW_SHIFT 4
-#define OMAP44XX_REG_T_RFC_SHDW_MASK (0x1ff << 4)
-#define OMAP44XX_REG_T_RAS_MAX_SHDW_SHIFT 0
-#define OMAP44XX_REG_T_RAS_MAX_SHDW_MASK (0xf << 0)
-
-/* LPDDR2_NVM_TIM */
-#define OMAP44XX_REG_NVM_T_XP_SHIFT 28
-#define OMAP44XX_REG_NVM_T_XP_MASK (0x7 << 28)
-#define OMAP44XX_REG_NVM_T_WTR_SHIFT 24
-#define OMAP44XX_REG_NVM_T_WTR_MASK (0x7 << 24)
-#define OMAP44XX_REG_NVM_T_RP_SHIFT 20
-#define OMAP44XX_REG_NVM_T_RP_MASK (0xf << 20)
-#define OMAP44XX_REG_NVM_T_WRA_SHIFT 16
-#define OMAP44XX_REG_NVM_T_WRA_MASK (0xf << 16)
-#define OMAP44XX_REG_NVM_T_RRD_SHIFT 8
-#define OMAP44XX_REG_NVM_T_RRD_MASK (0xff << 8)
-#define OMAP44XX_REG_NVM_T_RCDMIN_SHIFT 0
-#define OMAP44XX_REG_NVM_T_RCDMIN_MASK (0xff << 0)
-
-/* LPDDR2_NVM_TIM_SHDW */
-#define OMAP44XX_REG_NVM_T_XP_SHDW_SHIFT 28
-#define OMAP44XX_REG_NVM_T_XP_SHDW_MASK (0x7 << 28)
-#define OMAP44XX_REG_NVM_T_WTR_SHDW_SHIFT 24
-#define OMAP44XX_REG_NVM_T_WTR_SHDW_MASK (0x7 << 24)
-#define OMAP44XX_REG_NVM_T_RP_SHDW_SHIFT 20
-#define OMAP44XX_REG_NVM_T_RP_SHDW_MASK (0xf << 20)
-#define OMAP44XX_REG_NVM_T_WRA_SHDW_SHIFT 16
-#define OMAP44XX_REG_NVM_T_WRA_SHDW_MASK (0xf << 16)
-#define OMAP44XX_REG_NVM_T_RRD_SHDW_SHIFT 8
-#define OMAP44XX_REG_NVM_T_RRD_SHDW_MASK (0xff << 8)
-#define OMAP44XX_REG_NVM_T_RCDMIN_SHDW_SHIFT 0
-#define OMAP44XX_REG_NVM_T_RCDMIN_SHDW_MASK (0xff << 0)
-
-/* PWR_MGMT_CTRL */
-#define OMAP44XX_REG_IDLEMODE_SHIFT 30
-#define OMAP44XX_REG_IDLEMODE_MASK (0x3 << 30)
-#define OMAP44XX_REG_PD_TIM_SHIFT 12
-#define OMAP44XX_REG_PD_TIM_MASK (0xf << 12)
-#define OMAP44XX_REG_DPD_EN_SHIFT 11
-#define OMAP44XX_REG_DPD_EN_MASK (1 << 11)
-#define OMAP44XX_REG_LP_MODE_SHIFT 8
-#define OMAP44XX_REG_LP_MODE_MASK (0x7 << 8)
-#define OMAP44XX_REG_SR_TIM_SHIFT 4
-#define OMAP44XX_REG_SR_TIM_MASK (0xf << 4)
-#define OMAP44XX_REG_CS_TIM_SHIFT 0
-#define OMAP44XX_REG_CS_TIM_MASK (0xf << 0)
-
-/* PWR_MGMT_CTRL_SHDW */
-#define OMAP44XX_REG_PD_TIM_SHDW_SHIFT 8
-#define OMAP44XX_REG_PD_TIM_SHDW_MASK (0xf << 8)
-#define OMAP44XX_REG_SR_TIM_SHDW_SHIFT 4
-#define OMAP44XX_REG_SR_TIM_SHDW_MASK (0xf << 4)
-#define OMAP44XX_REG_CS_TIM_SHDW_SHIFT 0
-#define OMAP44XX_REG_CS_TIM_SHDW_MASK (0xf << 0)
-
-/* LPDDR2_MODE_REG_DATA */
-#define OMAP44XX_REG_VALUE_0_SHIFT 0
-#define OMAP44XX_REG_VALUE_0_MASK (0x7f << 0)
-
-/* LPDDR2_MODE_REG_CFG */
-#define OMAP44XX_REG_CS_SHIFT 31
-#define OMAP44XX_REG_CS_MASK (1 << 31)
-#define OMAP44XX_REG_REFRESH_EN_SHIFT 30
-#define OMAP44XX_REG_REFRESH_EN_MASK (1 << 30)
-#define OMAP44XX_REG_ADDRESS_SHIFT 0
-#define OMAP44XX_REG_ADDRESS_MASK (0xff << 0)
-
-/* OCP_CONFIG */
-#define OMAP44XX_REG_SYS_THRESH_MAX_SHIFT 24
-#define OMAP44XX_REG_SYS_THRESH_MAX_MASK (0xf << 24)
-#define OMAP44XX_REG_MPU_THRESH_MAX_SHIFT 20
-#define OMAP44XX_REG_MPU_THRESH_MAX_MASK (0xf << 20)
-#define OMAP44XX_REG_LL_THRESH_MAX_SHIFT 16
-#define OMAP44XX_REG_LL_THRESH_MAX_MASK (0xf << 16)
-#define OMAP44XX_REG_PR_OLD_COUNT_SHIFT 0
-#define OMAP44XX_REG_PR_OLD_COUNT_MASK (0xff << 0)
-
-/* OCP_CFG_VAL_1 */
-#define OMAP44XX_REG_SYS_BUS_WIDTH_SHIFT 30
-#define OMAP44XX_REG_SYS_BUS_WIDTH_MASK (0x3 << 30)
-#define OMAP44XX_REG_LL_BUS_WIDTH_SHIFT 28
-#define OMAP44XX_REG_LL_BUS_WIDTH_MASK (0x3 << 28)
-#define OMAP44XX_REG_WR_FIFO_DEPTH_SHIFT 8
-#define OMAP44XX_REG_WR_FIFO_DEPTH_MASK (0xff << 8)
-#define OMAP44XX_REG_CMD_FIFO_DEPTH_SHIFT 0
-#define OMAP44XX_REG_CMD_FIFO_DEPTH_MASK (0xff << 0)
-
-/* OCP_CFG_VAL_2 */
-#define OMAP44XX_REG_RREG_FIFO_DEPTH_SHIFT 16
-#define OMAP44XX_REG_RREG_FIFO_DEPTH_MASK (0xff << 16)
-#define OMAP44XX_REG_RSD_FIFO_DEPTH_SHIFT 8
-#define OMAP44XX_REG_RSD_FIFO_DEPTH_MASK (0xff << 8)
-#define OMAP44XX_REG_RCMD_FIFO_DEPTH_SHIFT 0
-#define OMAP44XX_REG_RCMD_FIFO_DEPTH_MASK (0xff << 0)
-
-/* IODFT_TLGC */
-#define OMAP44XX_REG_TLEC_SHIFT 16
-#define OMAP44XX_REG_TLEC_MASK (0xffff << 16)
-#define OMAP44XX_REG_MT_SHIFT 14
-#define OMAP44XX_REG_MT_MASK (1 << 14)
-#define OMAP44XX_REG_ACT_CAP_EN_SHIFT 13
-#define OMAP44XX_REG_ACT_CAP_EN_MASK (1 << 13)
-#define OMAP44XX_REG_OPG_LD_SHIFT 12
-#define OMAP44XX_REG_OPG_LD_MASK (1 << 12)
-#define OMAP44XX_REG_RESET_PHY_SHIFT 10
-#define OMAP44XX_REG_RESET_PHY_MASK (1 << 10)
-#define OMAP44XX_REG_MMS_SHIFT 8
-#define OMAP44XX_REG_MMS_MASK (1 << 8)
-#define OMAP44XX_REG_MC_SHIFT 4
-#define OMAP44XX_REG_MC_MASK (0x3 << 4)
-#define OMAP44XX_REG_PC_SHIFT 1
-#define OMAP44XX_REG_PC_MASK (0x7 << 1)
-#define OMAP44XX_REG_TM_SHIFT 0
-#define OMAP44XX_REG_TM_MASK (1 << 0)
-
-/* IODFT_CTRL_MISR_RSLT */
-#define OMAP44XX_REG_DQM_TLMR_SHIFT 16
-#define OMAP44XX_REG_DQM_TLMR_MASK (0x3ff << 16)
-#define OMAP44XX_REG_CTL_TLMR_SHIFT 0
-#define OMAP44XX_REG_CTL_TLMR_MASK (0x7ff << 0)
-
-/* IODFT_ADDR_MISR_RSLT */
-#define OMAP44XX_REG_ADDR_TLMR_SHIFT 0
-#define OMAP44XX_REG_ADDR_TLMR_MASK (0x1fffff << 0)
-
-/* IODFT_DATA_MISR_RSLT_1 */
-#define OMAP44XX_REG_DATA_TLMR_31_0_SHIFT 0
-#define OMAP44XX_REG_DATA_TLMR_31_0_MASK (0xffffffff << 0)
-
-/* IODFT_DATA_MISR_RSLT_2 */
-#define OMAP44XX_REG_DATA_TLMR_63_32_SHIFT 0
-#define OMAP44XX_REG_DATA_TLMR_63_32_MASK (0xffffffff << 0)
-
-/* IODFT_DATA_MISR_RSLT_3 */
-#define OMAP44XX_REG_DATA_TLMR_66_64_SHIFT 0
-#define OMAP44XX_REG_DATA_TLMR_66_64_MASK (0x7 << 0)
-
-/* PERF_CNT_1 */
-#define OMAP44XX_REG_COUNTER1_SHIFT 0
-#define OMAP44XX_REG_COUNTER1_MASK (0xffffffff << 0)
-
-/* PERF_CNT_2 */
-#define OMAP44XX_REG_COUNTER2_SHIFT 0
-#define OMAP44XX_REG_COUNTER2_MASK (0xffffffff << 0)
-
-/* PERF_CNT_CFG */
-#define OMAP44XX_REG_CNTR2_MCONNID_EN_SHIFT 31
-#define OMAP44XX_REG_CNTR2_MCONNID_EN_MASK (1 << 31)
-#define OMAP44XX_REG_CNTR2_REGION_EN_SHIFT 30
-#define OMAP44XX_REG_CNTR2_REGION_EN_MASK (1 << 30)
-#define OMAP44XX_REG_CNTR2_CFG_SHIFT 16
-#define OMAP44XX_REG_CNTR2_CFG_MASK (0xf << 16)
-#define OMAP44XX_REG_CNTR1_MCONNID_EN_SHIFT 15
-#define OMAP44XX_REG_CNTR1_MCONNID_EN_MASK (1 << 15)
-#define OMAP44XX_REG_CNTR1_REGION_EN_SHIFT 14
-#define OMAP44XX_REG_CNTR1_REGION_EN_MASK (1 << 14)
-#define OMAP44XX_REG_CNTR1_CFG_SHIFT 0
-#define OMAP44XX_REG_CNTR1_CFG_MASK (0xf << 0)
-
-/* PERF_CNT_SEL */
-#define OMAP44XX_REG_MCONNID2_SHIFT 24
-#define OMAP44XX_REG_MCONNID2_MASK (0xff << 24)
-#define OMAP44XX_REG_REGION_SEL2_SHIFT 16
-#define OMAP44XX_REG_REGION_SEL2_MASK (0x3 << 16)
-#define OMAP44XX_REG_MCONNID1_SHIFT 8
-#define OMAP44XX_REG_MCONNID1_MASK (0xff << 8)
-#define OMAP44XX_REG_REGION_SEL1_SHIFT 0
-#define OMAP44XX_REG_REGION_SEL1_MASK (0x3 << 0)
-
-/* PERF_CNT_TIM */
-#define OMAP44XX_REG_TOTAL_TIME_SHIFT 0
-#define OMAP44XX_REG_TOTAL_TIME_MASK (0xffffffff << 0)
-
-/* READ_IDLE_CTRL */
-#define OMAP44XX_REG_READ_IDLE_LEN_SHIFT 16
-#define OMAP44XX_REG_READ_IDLE_LEN_MASK (0xf << 16)
-#define OMAP44XX_REG_READ_IDLE_INTERVAL_SHIFT 0
-#define OMAP44XX_REG_READ_IDLE_INTERVAL_MASK (0x1ff << 0)
-
-/* READ_IDLE_CTRL_SHDW */
-#define OMAP44XX_REG_READ_IDLE_LEN_SHDW_SHIFT 16
-#define OMAP44XX_REG_READ_IDLE_LEN_SHDW_MASK (0xf << 16)
-#define OMAP44XX_REG_READ_IDLE_INTERVAL_SHDW_SHIFT 0
-#define OMAP44XX_REG_READ_IDLE_INTERVAL_SHDW_MASK (0x1ff << 0)
-
-/* IRQ_EOI */
-#define OMAP44XX_REG_EOI_SHIFT 0
-#define OMAP44XX_REG_EOI_MASK (1 << 0)
-
-/* IRQSTATUS_RAW_SYS */
-#define OMAP44XX_REG_DNV_SYS_SHIFT 2
-#define OMAP44XX_REG_DNV_SYS_MASK (1 << 2)
-#define OMAP44XX_REG_TA_SYS_SHIFT 1
-#define OMAP44XX_REG_TA_SYS_MASK (1 << 1)
-#define OMAP44XX_REG_ERR_SYS_SHIFT 0
-#define OMAP44XX_REG_ERR_SYS_MASK (1 << 0)
-
-/* IRQSTATUS_RAW_LL */
-#define OMAP44XX_REG_DNV_LL_SHIFT 2
-#define OMAP44XX_REG_DNV_LL_MASK (1 << 2)
-#define OMAP44XX_REG_TA_LL_SHIFT 1
-#define OMAP44XX_REG_TA_LL_MASK (1 << 1)
-#define OMAP44XX_REG_ERR_LL_SHIFT 0
-#define OMAP44XX_REG_ERR_LL_MASK (1 << 0)
-
-/* IRQSTATUS_SYS */
-
-/* IRQSTATUS_LL */
-
-/* IRQENABLE_SET_SYS */
-#define OMAP44XX_REG_EN_DNV_SYS_SHIFT 2
-#define OMAP44XX_REG_EN_DNV_SYS_MASK (1 << 2)
-#define OMAP44XX_REG_EN_TA_SYS_SHIFT 1
-#define OMAP44XX_REG_EN_TA_SYS_MASK (1 << 1)
-#define OMAP44XX_REG_EN_ERR_SYS_SHIFT 0
-#define OMAP44XX_REG_EN_ERR_SYS_MASK (1 << 0)
-
-/* IRQENABLE_SET_LL */
-#define OMAP44XX_REG_EN_DNV_LL_SHIFT 2
-#define OMAP44XX_REG_EN_DNV_LL_MASK (1 << 2)
-#define OMAP44XX_REG_EN_TA_LL_SHIFT 1
-#define OMAP44XX_REG_EN_TA_LL_MASK (1 << 1)
-#define OMAP44XX_REG_EN_ERR_LL_SHIFT 0
-#define OMAP44XX_REG_EN_ERR_LL_MASK (1 << 0)
-
-/* IRQENABLE_CLR_SYS */
-
-/* IRQENABLE_CLR_LL */
-
-/* ZQ_CONFIG */
-#define OMAP44XX_REG_ZQ_CS1EN_SHIFT 31
-#define OMAP44XX_REG_ZQ_CS1EN_MASK (1 << 31)
-#define OMAP44XX_REG_ZQ_CS0EN_SHIFT 30
-#define OMAP44XX_REG_ZQ_CS0EN_MASK (1 << 30)
-#define OMAP44XX_REG_ZQ_DUALCALEN_SHIFT 29
-#define OMAP44XX_REG_ZQ_DUALCALEN_MASK (1 << 29)
-#define OMAP44XX_REG_ZQ_SFEXITEN_SHIFT 28
-#define OMAP44XX_REG_ZQ_SFEXITEN_MASK (1 << 28)
-#define OMAP44XX_REG_ZQ_ZQINIT_MULT_SHIFT 18
-#define OMAP44XX_REG_ZQ_ZQINIT_MULT_MASK (0x3 << 18)
-#define OMAP44XX_REG_ZQ_ZQCL_MULT_SHIFT 16
-#define OMAP44XX_REG_ZQ_ZQCL_MULT_MASK (0x3 << 16)
-#define OMAP44XX_REG_ZQ_REFINTERVAL_SHIFT 0
-#define OMAP44XX_REG_ZQ_REFINTERVAL_MASK (0xffff << 0)
-
-/* TEMP_ALERT_CONFIG */
-#define OMAP44XX_REG_TA_CS1EN_SHIFT 31
-#define OMAP44XX_REG_TA_CS1EN_MASK (1 << 31)
-#define OMAP44XX_REG_TA_CS0EN_SHIFT 30
-#define OMAP44XX_REG_TA_CS0EN_MASK (1 << 30)
-#define OMAP44XX_REG_TA_SFEXITEN_SHIFT 28
-#define OMAP44XX_REG_TA_SFEXITEN_MASK (1 << 28)
-#define OMAP44XX_REG_TA_DEVWDT_SHIFT 26
-#define OMAP44XX_REG_TA_DEVWDT_MASK (0x3 << 26)
-#define OMAP44XX_REG_TA_DEVCNT_SHIFT 24
-#define OMAP44XX_REG_TA_DEVCNT_MASK (0x3 << 24)
-#define OMAP44XX_REG_TA_REFINTERVAL_SHIFT 0
-#define OMAP44XX_REG_TA_REFINTERVAL_MASK (0x3fffff << 0)
-
-/* OCP_ERR_LOG */
-#define OMAP44XX_REG_MADDRSPACE_SHIFT 14
-#define OMAP44XX_REG_MADDRSPACE_MASK (0x3 << 14)
-#define OMAP44XX_REG_MBURSTSEQ_SHIFT 11
-#define OMAP44XX_REG_MBURSTSEQ_MASK (0x7 << 11)
-#define OMAP44XX_REG_MCMD_SHIFT 8
-#define OMAP44XX_REG_MCMD_MASK (0x7 << 8)
-#define OMAP44XX_REG_MCONNID_SHIFT 0
-#define OMAP44XX_REG_MCONNID_MASK (0xff << 0)
-
-/* DDR_PHY_CTRL_1 */
-#define OMAP44XX_REG_DDR_PHY_CTRL_1_SHIFT 4
-#define OMAP44XX_REG_DDR_PHY_CTRL_1_MASK (0xfffffff << 4)
-#define OMAP44XX_REG_READ_LATENCY_SHIFT 0
-#define OMAP44XX_REG_READ_LATENCY_MASK (0xf << 0)
-#define OMAP44XX_REG_DLL_SLAVE_DLY_CTRL_SHIFT 4
-#define OMAP44XX_REG_DLL_SLAVE_DLY_CTRL_MASK (0xFF << 4)
-#define OMAP44XX_EMIF_DDR_PHY_CTRL_1_BASE_VAL_SHIFT 12
-#define OMAP44XX_EMIF_DDR_PHY_CTRL_1_BASE_VAL_MASK (0xFFFFF << 12)
-
-/* DDR_PHY_CTRL_1_SHDW */
-#define OMAP44XX_REG_DDR_PHY_CTRL_1_SHDW_SHIFT 4
-#define OMAP44XX_REG_DDR_PHY_CTRL_1_SHDW_MASK (0xfffffff << 4)
-#define OMAP44XX_REG_READ_LATENCY_SHDW_SHIFT 0
-#define OMAP44XX_REG_READ_LATENCY_SHDW_MASK (0xf << 0)
-#define OMAP44XX_REG_DLL_SLAVE_DLY_CTRL_SHDW_SHIFT 4
-#define OMAP44XX_REG_DLL_SLAVE_DLY_CTRL_SHDW_MASK (0xFF << 4)
-#define OMAP44XX_EMIF_DDR_PHY_CTRL_1_BASE_VAL_SHDW_SHIFT 12
-#define OMAP44XX_EMIF_DDR_PHY_CTRL_1_BASE_VAL_SHDW_MASK (0xFFFFF << 12)
-
-/* DDR_PHY_CTRL_2 */
-#define OMAP44XX_REG_DDR_PHY_CTRL_2_SHIFT 0
-#define OMAP44XX_REG_DDR_PHY_CTRL_2_MASK (0xffffffff << 0)
-
-/* DMM */
-#define OMAP44XX_DMM_LISA_MAP_BASE 0x4E000040
-
-/* Memory Adapter (4460 onwards) */
-#define OMAP44XX_MA_LISA_MAP_BASE 0x482AF040
-
-/* DMM_LISA_MAP */
-#define OMAP44XX_SYS_ADDR_SHIFT 24
-#define OMAP44XX_SYS_ADDR_MASK (0xff << 24)
-#define OMAP44XX_SYS_SIZE_SHIFT 20
-#define OMAP44XX_SYS_SIZE_MASK (0x7 << 20)
-#define OMAP44XX_SDRC_INTL_SHIFT 18
-#define OMAP44XX_SDRC_INTL_MASK (0x3 << 18)
-#define OMAP44XX_SDRC_ADDRSPC_SHIFT 16
-#define OMAP44XX_SDRC_ADDRSPC_MASK (0x3 << 16)
-#define OMAP44XX_SDRC_MAP_SHIFT 8
-#define OMAP44XX_SDRC_MAP_MASK (0x3 << 8)
-#define OMAP44XX_SDRC_ADDR_SHIFT 0
-#define OMAP44XX_SDRC_ADDR_MASK (0xff << 0)
-
-/* DMM_LISA_MAP fields */
-#define DMM_SDRC_MAP_UNMAPPED 0
-#define DMM_SDRC_MAP_EMIF1_ONLY 1
-#define DMM_SDRC_MAP_EMIF2_ONLY 2
-#define DMM_SDRC_MAP_EMIF1_AND_EMIF2 3
-
-#define DMM_SDRC_INTL_NONE 0
-#define DMM_SDRC_INTL_128B 1
-#define DMM_SDRC_INTL_256B 2
-#define DMM_SDRC_INTL_512 3
-
-#define DMM_SDRC_ADDR_SPC_SDRAM 0
-#define DMM_SDRC_ADDR_SPC_NVM 1
-#define DMM_SDRC_ADDR_SPC_INVALID 2
-
-#define DMM_LISA_MAP_INTERLEAVED_BASE_VAL (\
- (DMM_SDRC_MAP_EMIF1_AND_EMIF2 << OMAP44XX_SDRC_MAP_SHIFT) |\
- (DMM_SDRC_ADDR_SPC_SDRAM << OMAP44XX_SDRC_ADDRSPC_SHIFT) |\
- (DMM_SDRC_INTL_128B << OMAP44XX_SDRC_INTL_SHIFT) |\
- (CONFIG_SYS_SDRAM_BASE << OMAP44XX_SYS_ADDR_SHIFT))
-
-#define DMM_LISA_MAP_EMIF1_ONLY_BASE_VAL (\
- (DMM_SDRC_MAP_EMIF1_ONLY << OMAP44XX_SDRC_MAP_SHIFT)|\
- (DMM_SDRC_ADDR_SPC_SDRAM << OMAP44XX_SDRC_ADDRSPC_SHIFT)|\
- (DMM_SDRC_INTL_NONE << OMAP44XX_SDRC_INTL_SHIFT))
-
-#define DMM_LISA_MAP_EMIF2_ONLY_BASE_VAL (\
- (DMM_SDRC_MAP_EMIF2_ONLY << OMAP44XX_SDRC_MAP_SHIFT)|\
- (DMM_SDRC_ADDR_SPC_SDRAM << OMAP44XX_SDRC_ADDRSPC_SHIFT)|\
- (DMM_SDRC_INTL_NONE << OMAP44XX_SDRC_INTL_SHIFT))
-
-/* Trap for invalid TILER PAT entries */
-#define DMM_LISA_MAP_0_INVAL_ADDR_TRAP (\
- (0 << OMAP44XX_SDRC_ADDR_SHIFT) |\
- (DMM_SDRC_MAP_EMIF1_ONLY << OMAP44XX_SDRC_MAP_SHIFT)|\
- (DMM_SDRC_ADDR_SPC_INVALID << OMAP44XX_SDRC_ADDRSPC_SHIFT)|\
- (DMM_SDRC_INTL_NONE << OMAP44XX_SDRC_INTL_SHIFT)|\
- (0xFF << OMAP44XX_SYS_ADDR_SHIFT))
-
-
-/* Reg mapping structure */
-struct emif_reg_struct {
- u32 emif_mod_id_rev;
- u32 emif_status;
- u32 emif_sdram_config;
- u32 emif_lpddr2_nvm_config;
- u32 emif_sdram_ref_ctrl;
- u32 emif_sdram_ref_ctrl_shdw;
- u32 emif_sdram_tim_1;
- u32 emif_sdram_tim_1_shdw;
- u32 emif_sdram_tim_2;
- u32 emif_sdram_tim_2_shdw;
- u32 emif_sdram_tim_3;
- u32 emif_sdram_tim_3_shdw;
- u32 emif_lpddr2_nvm_tim;
- u32 emif_lpddr2_nvm_tim_shdw;
- u32 emif_pwr_mgmt_ctrl;
- u32 emif_pwr_mgmt_ctrl_shdw;
- u32 emif_lpddr2_mode_reg_data;
- u32 padding1[1];
- u32 emif_lpddr2_mode_reg_data_es2;
- u32 padding11[1];
- u32 emif_lpddr2_mode_reg_cfg;
- u32 emif_l3_config;
- u32 emif_l3_cfg_val_1;
- u32 emif_l3_cfg_val_2;
- u32 emif_iodft_tlgc;
- u32 padding2[7];
- u32 emif_perf_cnt_1;
- u32 emif_perf_cnt_2;
- u32 emif_perf_cnt_cfg;
- u32 emif_perf_cnt_sel;
- u32 emif_perf_cnt_tim;
- u32 padding3;
- u32 emif_read_idlectrl;
- u32 emif_read_idlectrl_shdw;
- u32 padding4;
- u32 emif_irqstatus_raw_sys;
- u32 emif_irqstatus_raw_ll;
- u32 emif_irqstatus_sys;
- u32 emif_irqstatus_ll;
- u32 emif_irqenable_set_sys;
- u32 emif_irqenable_set_ll;
- u32 emif_irqenable_clr_sys;
- u32 emif_irqenable_clr_ll;
- u32 padding5;
- u32 emif_zq_config;
- u32 emif_temp_alert_config;
- u32 emif_l3_err_log;
- u32 padding6[4];
- u32 emif_ddr_phy_ctrl_1;
- u32 emif_ddr_phy_ctrl_1_shdw;
- u32 emif_ddr_phy_ctrl_2;
-};
-
-struct dmm_lisa_map_regs {
- u32 dmm_lisa_map_0;
- u32 dmm_lisa_map_1;
- u32 dmm_lisa_map_2;
- u32 dmm_lisa_map_3;
-};
-
-#define CS0 0
-#define CS1 1
-/* The maximum frequency at which the LPDDR2 interface can operate in Hz*/
-#define MAX_LPDDR2_FREQ 400000000 /* 400 MHz */
-
-/*
- * The period of DDR clk is represented as numerator and denominator for
- * better accuracy in integer based calculations. However, if the numerator
- * and denominator are very huge there may be chances of overflow in
- * calculations. So, as a trade-off keep denominator(and consequently
- * numerator) within a limit sacrificing some accuracy - but not much
- * If denominator and numerator are already small (such as at 400 MHz)
- * no adjustment is needed
- */
-#define EMIF_PERIOD_DEN_LIMIT 1000
-/*
- * Maximum number of different frequencies supported by EMIF driver
- * Determines the number of entries in the pointer array for register
- * cache
- */
-#define EMIF_MAX_NUM_FREQUENCIES 6
-/*
- * Indices into the Addressing Table array.
- * One entry each for all the different types of devices with different
- * addressing schemes
- */
-#define ADDR_TABLE_INDEX64M 0
-#define ADDR_TABLE_INDEX128M 1
-#define ADDR_TABLE_INDEX256M 2
-#define ADDR_TABLE_INDEX512M 3
-#define ADDR_TABLE_INDEX1GS4 4
-#define ADDR_TABLE_INDEX2GS4 5
-#define ADDR_TABLE_INDEX4G 6
-#define ADDR_TABLE_INDEX8G 7
-#define ADDR_TABLE_INDEX1GS2 8
-#define ADDR_TABLE_INDEX2GS2 9
-#define ADDR_TABLE_INDEXMAX 10
-
-/* Number of Row bits */
-#define ROW_9 0
-#define ROW_10 1
-#define ROW_11 2
-#define ROW_12 3
-#define ROW_13 4
-#define ROW_14 5
-#define ROW_15 6
-#define ROW_16 7
-
-/* Number of Column bits */
-#define COL_8 0
-#define COL_9 1
-#define COL_10 2
-#define COL_11 3
-#define COL_7 4 /*Not supported by OMAP included for completeness */
-
-/* Number of Banks*/
-#define BANKS1 0
-#define BANKS2 1
-#define BANKS4 2
-#define BANKS8 3
-
-/* Refresh rate in micro seconds x 10 */
-#define T_REFI_15_6 156
-#define T_REFI_7_8 78
-#define T_REFI_3_9 39
-
-#define EBANK_CS1_DIS 0
-#define EBANK_CS1_EN 1
-
-/* Read Latency used by the device at reset */
-#define RL_BOOT 3
-/* Read Latency for the highest frequency you want to use */
-#define RL_FINAL 6
-
-/* Interleaving policies at EMIF level- between banks and Chip Selects */
-#define EMIF_INTERLEAVING_POLICY_MAX_INTERLEAVING 0
-#define EMIF_INTERLEAVING_POLICY_NO_BANK_INTERLEAVING 3
-
-/*
- * Interleaving policy to be used
- * Currently set to MAX interleaving for better performance
- */
-#define EMIF_INTERLEAVING_POLICY EMIF_INTERLEAVING_POLICY_MAX_INTERLEAVING
-
-/* State of the core voltage:
- * This is important for some parameters such as read idle control and
- * ZQ calibration timings. Timings are much stricter when voltage ramp
- * is happening compared to when the voltage is stable.
- * We need to calculate two sets of values for these parameters and use
- * them accordingly
- */
-#define LPDDR2_VOLTAGE_STABLE 0
-#define LPDDR2_VOLTAGE_RAMPING 1
-
-/* Length of the forced read idle period in terms of cycles */
-#define EMIF_REG_READ_IDLE_LEN_VAL 5
-
-/* Interval between forced 'read idles' */
-/* To be used when voltage is changed for DPS/DVFS - 1us */
-#define READ_IDLE_INTERVAL_DVFS (1*1000)
-/*
- * To be used when voltage is not scaled except by Smart Reflex
- * 50us - or maximum value will do
- */
-#define READ_IDLE_INTERVAL_NORMAL (50*1000)
-
-
-/*
- * Unless voltage is changing due to DVFS one ZQCS command every 50ms should
- * be enough. This shoule be enough also in the case when voltage is changing
- * due to smart-reflex.
- */
-#define EMIF_ZQCS_INTERVAL_NORMAL_IN_US (50*1000)
-/*
- * If voltage is changing due to DVFS ZQCS should be performed more
- * often(every 50us)
- */
-#define EMIF_ZQCS_INTERVAL_DVFS_IN_US 50
-
-/* The interval between ZQCL commands as a multiple of ZQCS interval */
-#define REG_ZQ_ZQCL_MULT 4
-/* The interval between ZQINIT commands as a multiple of ZQCL interval */
-#define REG_ZQ_ZQINIT_MULT 3
-/* Enable ZQ Calibration on exiting Self-refresh */
-#define REG_ZQ_SFEXITEN_ENABLE 1
-/*
- * ZQ Calibration simultaneously on both chip-selects:
- * Needs one calibration resistor per CS
- * None of the boards that we know of have this capability
- * So disabled by default
- */
-#define REG_ZQ_DUALCALEN_DISABLE 0
-/*
- * Enable ZQ Calibration by default on CS0. If we are asked to program
- * the EMIF there will be something connected to CS0 for sure
- */
-#define REG_ZQ_CS0EN_ENABLE 1
-
-/* EMIF_PWR_MGMT_CTRL register */
-/* Low power modes */
-#define LP_MODE_DISABLE 0
-#define LP_MODE_CLOCK_STOP 1
-#define LP_MODE_SELF_REFRESH 2
-#define LP_MODE_PWR_DN 3
-
-/* REG_DPD_EN */
-#define DPD_DISABLE 0
-#define DPD_ENABLE 1
-
-/* Maximum delay before Low Power Modes */
-#define REG_CS_TIM 0xF
-#define REG_SR_TIM 0xF
-#define REG_PD_TIM 0xF
-
-/* EMIF_PWR_MGMT_CTRL register */
-#define EMIF_PWR_MGMT_CTRL (\
- ((REG_CS_TIM << OMAP44XX_REG_CS_TIM_SHIFT) & OMAP44XX_REG_CS_TIM_MASK)|\
- ((REG_SR_TIM << OMAP44XX_REG_SR_TIM_SHIFT) & OMAP44XX_REG_SR_TIM_MASK)|\
- ((REG_PD_TIM << OMAP44XX_REG_PD_TIM_SHIFT) & OMAP44XX_REG_PD_TIM_MASK)|\
- ((REG_PD_TIM << OMAP44XX_REG_PD_TIM_SHIFT) & OMAP44XX_REG_PD_TIM_MASK)|\
- ((LP_MODE_DISABLE << OMAP44XX_REG_LP_MODE_SHIFT)\
- & OMAP44XX_REG_LP_MODE_MASK) |\
- ((DPD_DISABLE << OMAP44XX_REG_DPD_EN_SHIFT)\
- & OMAP44XX_REG_DPD_EN_MASK))\
-
-#define EMIF_PWR_MGMT_CTRL_SHDW (\
- ((REG_CS_TIM << OMAP44XX_REG_CS_TIM_SHDW_SHIFT)\
- & OMAP44XX_REG_CS_TIM_SHDW_MASK) |\
- ((REG_SR_TIM << OMAP44XX_REG_SR_TIM_SHDW_SHIFT)\
- & OMAP44XX_REG_SR_TIM_SHDW_MASK) |\
- ((REG_PD_TIM << OMAP44XX_REG_PD_TIM_SHDW_SHIFT)\
- & OMAP44XX_REG_PD_TIM_SHDW_MASK) |\
- ((REG_PD_TIM << OMAP44XX_REG_PD_TIM_SHDW_SHIFT)\
- & OMAP44XX_REG_PD_TIM_SHDW_MASK))
-
-/* EMIF_L3_CONFIG register value */
-#define EMIF_L3_CONFIG_VAL_SYS_10_LL_0 0x0A0000FF
-#define EMIF_L3_CONFIG_VAL_SYS_10_MPU_3_LL_0 0x0A300000
-/*
- * Value of bits 12:31 of DDR_PHY_CTRL_1 register:
- * All these fields have magic values dependent on frequency and
- * determined by PHY and DLL integration with EMIF. Setting the magic
- * values suggested by hw team.
- */
-#define EMIF_DDR_PHY_CTRL_1_BASE_VAL 0x049FF
-#define EMIF_DLL_SLAVE_DLY_CTRL_400_MHZ 0x41
-#define EMIF_DLL_SLAVE_DLY_CTRL_200_MHZ 0x80
-#define EMIF_DLL_SLAVE_DLY_CTRL_100_MHZ_AND_LESS 0xFF
-
-/*
-* MR1 value:
-* Burst length : 8
-* Burst type : sequential
-* Wrap : enabled
-* nWR : 3(default). EMIF does not do pre-charge.
-* : So nWR is don't care
-*/
-#define MR1_BL_8_BT_SEQ_WRAP_EN_NWR_3 0x23
-
-/* MR2 */
-#define MR2_RL3_WL1 1
-#define MR2_RL4_WL2 2
-#define MR2_RL5_WL2 3
-#define MR2_RL6_WL3 4
-
-/* MR10: ZQ calibration codes */
-#define MR10_ZQ_ZQCS 0x56
-#define MR10_ZQ_ZQCL 0xAB
-#define MR10_ZQ_ZQINIT 0xFF
-#define MR10_ZQ_ZQRESET 0xC3
-
-/* TEMP_ALERT_CONFIG */
-#define TEMP_ALERT_POLL_INTERVAL_MS 360 /* for temp gradient - 5 C/s */
-#define TEMP_ALERT_CONFIG_DEVCT_1 0
-#define TEMP_ALERT_CONFIG_DEVWDT_32 2
-
-/* MR16 value: refresh full array(no partial array self refresh) */
-#define MR16_REF_FULL_ARRAY 0
-
-/*
- * Maximum number of entries we keep in our array of timing tables
- * We need not keep all the speed bins supported by the device
- * We need to keep timing tables for only the speed bins that we
- * are interested in
- */
-#define MAX_NUM_SPEEDBINS 4
-
-/* LPDDR2 Densities */
-#define LPDDR2_DENSITY_64Mb 0
-#define LPDDR2_DENSITY_128Mb 1
-#define LPDDR2_DENSITY_256Mb 2
-#define LPDDR2_DENSITY_512Mb 3
-#define LPDDR2_DENSITY_1Gb 4
-#define LPDDR2_DENSITY_2Gb 5
-#define LPDDR2_DENSITY_4Gb 6
-#define LPDDR2_DENSITY_8Gb 7
-#define LPDDR2_DENSITY_16Gb 8
-#define LPDDR2_DENSITY_32Gb 9
-
-/* LPDDR2 type */
-#define LPDDR2_TYPE_S4 0
-#define LPDDR2_TYPE_S2 1
-#define LPDDR2_TYPE_NVM 2
-
-/* LPDDR2 IO width */
-#define LPDDR2_IO_WIDTH_32 0
-#define LPDDR2_IO_WIDTH_16 1
-#define LPDDR2_IO_WIDTH_8 2
-
-/* Mode register numbers */
-#define LPDDR2_MR0 0
-#define LPDDR2_MR1 1
-#define LPDDR2_MR2 2
-#define LPDDR2_MR3 3
-#define LPDDR2_MR4 4
-#define LPDDR2_MR5 5
-#define LPDDR2_MR6 6
-#define LPDDR2_MR7 7
-#define LPDDR2_MR8 8
-#define LPDDR2_MR9 9
-#define LPDDR2_MR10 10
-#define LPDDR2_MR11 11
-#define LPDDR2_MR16 16
-#define LPDDR2_MR17 17
-#define LPDDR2_MR18 18
-
-/* MR0 */
-#define LPDDR2_MR0_DAI_SHIFT 0
-#define LPDDR2_MR0_DAI_MASK 1
-#define LPDDR2_MR0_DI_SHIFT 1
-#define LPDDR2_MR0_DI_MASK (1 << 1)
-#define LPDDR2_MR0_DNVI_SHIFT 2
-#define LPDDR2_MR0_DNVI_MASK (1 << 2)
-
-/* MR4 */
-#define MR4_SDRAM_REF_RATE_SHIFT 0
-#define MR4_SDRAM_REF_RATE_MASK 7
-#define MR4_TUF_SHIFT 7
-#define MR4_TUF_MASK (1 << 7)
-
-/* MR4 SDRAM Refresh Rate field values */
-#define SDRAM_TEMP_LESS_LOW_SHUTDOWN 0x0
-#define SDRAM_TEMP_LESS_4X_REFRESH_AND_TIMINGS 0x1
-#define SDRAM_TEMP_LESS_2X_REFRESH_AND_TIMINGS 0x2
-#define SDRAM_TEMP_NOMINAL 0x3
-#define SDRAM_TEMP_RESERVED_4 0x4
-#define SDRAM_TEMP_HIGH_DERATE_REFRESH 0x5
-#define SDRAM_TEMP_HIGH_DERATE_REFRESH_AND_TIMINGS 0x6
-#define SDRAM_TEMP_VERY_HIGH_SHUTDOWN 0x7
-
-#define LPDDR2_MANUFACTURER_SAMSUNG 1
-#define LPDDR2_MANUFACTURER_QIMONDA 2
-#define LPDDR2_MANUFACTURER_ELPIDA 3
-#define LPDDR2_MANUFACTURER_ETRON 4
-#define LPDDR2_MANUFACTURER_NANYA 5
-#define LPDDR2_MANUFACTURER_HYNIX 6
-#define LPDDR2_MANUFACTURER_MOSEL 7
-#define LPDDR2_MANUFACTURER_WINBOND 8
-#define LPDDR2_MANUFACTURER_ESMT 9
-#define LPDDR2_MANUFACTURER_SPANSION 11
-#define LPDDR2_MANUFACTURER_SST 12
-#define LPDDR2_MANUFACTURER_ZMOS 13
-#define LPDDR2_MANUFACTURER_INTEL 14
-#define LPDDR2_MANUFACTURER_NUMONYX 254
-#define LPDDR2_MANUFACTURER_MICRON 255
-
-/* MR8 register fields */
-#define MR8_TYPE_SHIFT 0x0
-#define MR8_TYPE_MASK 0x3
-#define MR8_DENSITY_SHIFT 0x2
-#define MR8_DENSITY_MASK (0xF << 0x2)
-#define MR8_IO_WIDTH_SHIFT 0x6
-#define MR8_IO_WIDTH_MASK (0x3 << 0x6)
-
-struct lpddr2_addressing {
- u8 num_banks;
- u8 t_REFI_us_x10;
- u8 row_sz[2]; /* One entry each for x32 and x16 */
- u8 col_sz[2]; /* One entry each for x32 and x16 */
-};
-
-/* Structure for timings from the DDR datasheet */
-struct lpddr2_ac_timings {
- u32 max_freq;
- u8 RL;
- u8 tRPab;
- u8 tRCD;
- u8 tWR;
- u8 tRASmin;
- u8 tRRD;
- u8 tWTRx2;
- u8 tXSR;
- u8 tXPx2;
- u8 tRFCab;
- u8 tRTPx2;
- u8 tCKE;
- u8 tCKESR;
- u8 tZQCS;
- u32 tZQCL;
- u32 tZQINIT;
- u8 tDQSCKMAXx2;
- u8 tRASmax;
- u8 tFAW;
-
-};
-
-/*
- * Min tCK values for some of the parameters:
- * If the calculated clock cycles for the respective parameter is
- * less than the corresponding min tCK value, we need to set the min
- * tCK value. This may happen at lower frequencies.
- */
-struct lpddr2_min_tck {
- u32 tRL;
- u32 tRP_AB;
- u32 tRCD;
- u32 tWR;
- u32 tRAS_MIN;
- u32 tRRD;
- u32 tWTR;
- u32 tXP;
- u32 tRTP;
- u8 tCKE;
- u32 tCKESR;
- u32 tFAW;
-};
-
-struct lpddr2_device_details {
- u8 type;
- u8 density;
- u8 io_width;
- u8 manufacturer;
-};
-
-struct lpddr2_device_timings {
- const struct lpddr2_ac_timings **ac_timings;
- const struct lpddr2_min_tck *min_tck;
-};
-
-/* Details of the devices connected to each chip-select of an EMIF instance */
-struct emif_device_details {
- const struct lpddr2_device_details *cs0_device_details;
- const struct lpddr2_device_details *cs1_device_details;
- const struct lpddr2_device_timings *cs0_device_timings;
- const struct lpddr2_device_timings *cs1_device_timings;
-};
-
-/*
- * Structure containing shadow of important registers in EMIF
- * The calculation function fills in this structure to be later used for
- * initialization and DVFS
- */
-struct emif_regs {
- u32 freq;
- u32 sdram_config_init;
- u32 sdram_config;
- u32 ref_ctrl;
- u32 sdram_tim1;
- u32 sdram_tim2;
- u32 sdram_tim3;
- u32 read_idle_ctrl;
- u32 zq_config;
- u32 temp_alert_config;
- u32 emif_ddr_phy_ctlr_1_init;
- u32 emif_ddr_phy_ctlr_1;
-};
-
-/* assert macros */
-#if defined(DEBUG)
-#define emif_assert(c) ({ if (!(c)) for (;;); })
-#else
-#define emif_assert(c) ({ if (0) hang(); })
-#endif
-
-#ifdef CONFIG_SYS_EMIF_PRECALCULATED_TIMING_REGS
-void emif_get_reg_dump(u32 emif_nr, const struct emif_regs **regs);
-void emif_get_dmm_regs(const struct dmm_lisa_map_regs **dmm_lisa_regs);
-#else
-struct lpddr2_device_details *emif_get_device_details(u32 emif_nr, u8 cs,
- struct lpddr2_device_details *lpddr2_dev_details);
-void emif_get_device_timings(u32 emif_nr,
- const struct lpddr2_device_timings **cs0_device_timings,
- const struct lpddr2_device_timings **cs1_device_timings);
-#endif
-
-#endif
diff --git a/arch/arm/include/asm/arch-omap4/mmc_host_def.h b/arch/arm/include/asm/arch-omap4/mmc_host_def.h
index 733d8ed..74439c9 100644
--- a/arch/arm/include/asm/arch-omap4/mmc_host_def.h
+++ b/arch/arm/include/asm/arch-omap4/mmc_host_def.h
@@ -33,7 +33,7 @@
#define OMAP_HSMMC2_BASE 0x480B4100
#define OMAP_HSMMC3_BASE 0x480AD100
-typedef struct hsmmc {
+struct hsmmc {
unsigned char res1[0x10];
unsigned int sysconfig; /* 0x10 */
unsigned int sysstatus; /* 0x14 */
@@ -55,7 +55,7 @@
unsigned int ie; /* 0x134 */
unsigned char res4[0x8];
unsigned int capa; /* 0x140 */
-} hsmmc_t;
+};
/*
* OMAP HS MMC Bit definitions
@@ -160,13 +160,6 @@
#define CLK_400KHZ 1
#define CLK_MISC 2
-typedef struct {
- unsigned int card_type;
- unsigned int version;
- unsigned int mode;
- unsigned int size;
- unsigned int RCA;
-} mmc_card_data;
#define RSP_TYPE_NONE (RSP_TYPE_NORSP | CCCE_NOCHECK | CICE_NOCHECK)
#define MMC_CMD0 (INDEX(0) | RSP_TYPE_NONE | DP_NO_DATA | DDIR_WRITE)
diff --git a/arch/arm/include/asm/arch-omap4/omap4.h b/arch/arm/include/asm/arch-omap4/omap.h
similarity index 86%
rename from arch/arm/include/asm/arch-omap4/omap4.h
rename to arch/arm/include/asm/arch-omap4/omap.h
index 61ebb3d..e994257 100644
--- a/arch/arm/include/asm/arch-omap4/omap4.h
+++ b/arch/arm/include/asm/arch-omap4/omap.h
@@ -44,7 +44,8 @@
#define OMAP44XX_DRAM_ADDR_SPACE_START 0x80000000
#define OMAP44XX_DRAM_ADDR_SPACE_END 0xD0000000
-
+#define DRAM_ADDR_SPACE_START OMAP44XX_DRAM_ADDR_SPACE_START
+#define DRAM_ADDR_SPACE_END OMAP44XX_DRAM_ADDR_SPACE_END
/* CONTROL */
#define CTRL_BASE (OMAP44XX_L4_CORE_BASE + 0x2000)
@@ -57,16 +58,11 @@
/* CONTROL_ID_CODE */
#define CONTROL_ID_CODE 0x4A002204
-/* 4430 */
-#define OMAP4430_CONTROL_ID_CODE_ES1_0 0x0B85202F
-#define OMAP4430_CONTROL_ID_CODE_ES2_0 0x1B85202F
-#define OMAP4430_CONTROL_ID_CODE_ES2_1 0x3B95C02F
-#define OMAP4430_CONTROL_ID_CODE_ES2_2 0x4B95C02F
-#define OMAP4430_CONTROL_ID_CODE_ES2_3 0x6B95C02F
-
-/* 4460 */
-#define OMAP4460_CONTROL_ID_CODE_ES1_0 0x0B94E02F
-#define OMAP4460_CONTROL_ID_CODE_ES1_1 0x2B94E02F
+#define OMAP4_CONTROL_ID_CODE_ES1_0 0x0B85202F
+#define OMAP4_CONTROL_ID_CODE_ES2_0 0x1B85202F
+#define OMAP4_CONTROL_ID_CODE_ES2_1 0x3B95C02F
+#define OMAP4_CONTROL_ID_CODE_ES2_2 0x4B95C02F
+#define OMAP4_CONTROL_ID_CODE_ES2_3 0x6B95C02F
/* UART */
#define UART1_BASE (OMAP44XX_L4_PER_BASE + 0x6a000)
@@ -151,7 +147,7 @@
unsigned int control_ldosram_mpu_voltage_ctrl; /* 0x4A002324 */
unsigned int control_ldosram_core_voltage_ctrl; /* 0x4A002328 */
unsigned int pad3[260277];
- unsigned int control_pbiaslite; /* 0x4A100600 */
+ unsigned int control_pbiaslite; /* 0x4A100600 */
unsigned int pad4[63];
unsigned int control_efuse_1; /* 0x4A100700 */
unsigned int control_efuse_2; /* 0x4A100704 */
@@ -188,16 +184,6 @@
#define OMAP4_SRAM_SCRATCH_EMIF_T_DEN (SRAM_SCRATCH_SPACE_ADDR + 0x10)
#define OMAP4_SRAM_SCRATCH_SPACE_END (SRAM_SCRATCH_SPACE_ADDR + 0x14)
-/* Silicon revisions */
-#define OMAP4430_SILICON_ID_INVALID 0xFFFFFFFF
-#define OMAP4430_ES1_0 0x44300100
-#define OMAP4430_ES2_0 0x44300200
-#define OMAP4430_ES2_1 0x44300210
-#define OMAP4430_ES2_2 0x44300220
-#define OMAP4430_ES2_3 0x44300230
-#define OMAP4460_ES1_0 0x44600100
-#define OMAP4460_ES1_1 0x44600110
-
/* ROM code defines */
/* Boot device */
#define BOOT_DEVICE_MASK 0xFF
@@ -205,5 +191,21 @@
#define DEV_DESC_PTR_OFFSET 0x4
#define DEV_DATA_PTR_OFFSET 0x18
#define BOOT_MODE_OFFSET 0x8
+#define RESET_REASON_OFFSET 0x9
+#define CH_FLAGS_OFFSET 0xA
+#define CH_FLAGS_CHSETTINGS (0x1 << 0)
+#define CH_FLAGS_CHRAM (0x1 << 1)
+#define CH_FLAGS_CHFLASH (0x1 << 2)
+#define CH_FLAGS_CHMMCSD (0x1 << 3)
+
+#ifndef __ASSEMBLY__
+struct omap_boot_parameters {
+ char *boot_message;
+ unsigned int mem_boot_descriptor;
+ unsigned char omap_bootdevice;
+ unsigned char reset_reason;
+ unsigned char ch_flags;
+};
+#endif
#endif
diff --git a/arch/arm/include/asm/arch-omap4/sys_proto.h b/arch/arm/include/asm/arch-omap4/sys_proto.h
index 1aacbb1..4146e21 100644
--- a/arch/arm/include/asm/arch-omap4/sys_proto.h
+++ b/arch/arm/include/asm/arch-omap4/sys_proto.h
@@ -21,7 +21,7 @@
#ifndef _SYS_PROTO_H_
#define _SYS_PROTO_H_
-#include <asm/arch/omap4.h>
+#include <asm/arch/omap.h>
#include <asm/arch/clocks.h>
#include <asm/io.h>
#include <asm/omap_common.h>
@@ -32,17 +32,17 @@
};
extern const struct omap_sysinfo sysinfo;
-extern struct omap4_prcm_regs *const prcm;
-
void gpmc_init(void);
void watchdog_init(void);
u32 get_device_type(void);
void do_set_mux(u32 base, struct pad_conf_entry const *array, int size);
+void set_muxconf_regs_essential(void);
void set_muxconf_regs_non_essential(void);
void sr32(void *, u32, u32, u32);
u32 wait_on_value(u32, u32, void *, u32);
void sdelay(unsigned long);
void set_pl310_ctrl_reg(u32 val);
+void omap_rev_string(char *omap_rev_string);
void setup_clocks_for_console(void);
void prcm_init(void);
void bypass_dpll(u32 *const base);
@@ -51,7 +51,17 @@
u32 omap4_ddr_clk(void);
void cancel_out(u32 *num, u32 *den, u32 den_limit);
void sdram_init(void);
-u32 omap4_sdram_size(void);
+u32 omap_sdram_size(void);
+u32 cortex_rev(void);
+void init_omap_revision(void);
+void do_io_settings(void);
+/*
+ * This is used to verify if the configuration header
+ * was executed by Romcode prior to control of transfer
+ * to the bootloader. SPL is responsible for saving and
+ * passing this to the u-boot.
+ */
+extern struct omap_boot_parameters boot_params;
static inline u32 running_from_sdram(void)
{
@@ -64,15 +74,17 @@
static inline u8 uboot_loaded_by_spl(void)
{
/*
- * Configuration Header is not supported yet, so u-boot init running
- * from SDRAM implies that it was loaded by SPL. When this situation
- * changes one of these approaches could be taken:
- * i. Pass a magic from SPL to U-Boot and U-Boot save it at a known
- * location.
- * ii. Check the OPP. CH can support only 50% OPP while SPL initializes
- * the DPLLs at 100% OPP.
+ * u-boot can be running from sdram either because of configuration
+ * Header or by SPL. If because of CH, then the romcode sets the
+ * CHSETTINGS executed bit to true in the boot parameter structure that
+ * it passes to the bootloader.This parameter is stored in the ch_flags
+ * variable by both SPL and u-boot.Check out for CHSETTINGS, which is a
+ * mandatory section if CH is present.
*/
- return running_from_sdram();
+ if ((boot_params.ch_flags) & (CH_FLAGS_CHSETTINGS))
+ return 0;
+ else
+ return running_from_sdram();
}
/*
* The basic hardware init of OMAP(s_init()) can happen in 4
@@ -86,7 +98,7 @@
* This function finds this context.
* Defining as inline may help in compiling out unused functions in SPL
*/
-static inline u32 omap4_hw_init_context(void)
+static inline u32 omap_hw_init_context(void)
{
#ifdef CONFIG_SPL_BUILD
return OMAP_INIT_CONTEXT_SPL;
diff --git a/arch/arm/include/asm/arch-omap5/clocks.h b/arch/arm/include/asm/arch-omap5/clocks.h
new file mode 100644
index 0000000..fa99f65
--- /dev/null
+++ b/arch/arm/include/asm/arch-omap5/clocks.h
@@ -0,0 +1,722 @@
+/*
+ * (C) Copyright 2010
+ * Texas Instruments, <www.ti.com>
+ *
+ * Aneesh V <aneesh@ti.com>
+ * Sricharan R <r.sricharan@ti.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+#ifndef _CLOCKS_OMAP5_H_
+#define _CLOCKS_OMAP5_H_
+#include <common.h>
+
+/*
+ * Assuming a maximum of 1.5 GHz ARM speed and a minimum of 2 cycles per
+ * loop, allow for a minimum of 2 ms wait (in reality the wait will be
+ * much more than that)
+ */
+#define LDELAY 1000000
+
+#define CM_CLKMODE_DPLL_CORE (OMAP54XX_L4_CORE_BASE + 0x4120)
+#define CM_CLKMODE_DPLL_PER (OMAP54XX_L4_CORE_BASE + 0x8140)
+#define CM_CLKMODE_DPLL_MPU (OMAP54XX_L4_CORE_BASE + 0x4160)
+#define CM_CLKSEL_CORE (OMAP54XX_L4_CORE_BASE + 0x4100)
+
+struct omap5_prcm_regs {
+ /* cm1.ckgen */
+ u32 cm_clksel_core; /* 4a004100 */
+ u32 pad001[1]; /* 4a004104 */
+ u32 cm_clksel_abe; /* 4a004108 */
+ u32 pad002[1]; /* 4a00410c */
+ u32 cm_dll_ctrl; /* 4a004110 */
+ u32 pad003[3]; /* 4a004114 */
+ u32 cm_clkmode_dpll_core; /* 4a004120 */
+ u32 cm_idlest_dpll_core; /* 4a004124 */
+ u32 cm_autoidle_dpll_core; /* 4a004128 */
+ u32 cm_clksel_dpll_core; /* 4a00412c */
+ u32 cm_div_m2_dpll_core; /* 4a004130 */
+ u32 cm_div_m3_dpll_core; /* 4a004134 */
+ u32 cm_div_h11_dpll_core; /* 4a004138 */
+ u32 cm_div_h12_dpll_core; /* 4a00413c */
+ u32 cm_div_h13_dpll_core; /* 4a004140 */
+ u32 cm_div_h14_dpll_core; /* 4a004144 */
+ u32 cm_ssc_deltamstep_dpll_core; /* 4a004148 */
+ u32 cm_ssc_modfreqdiv_dpll_core; /* 4a00414c */
+ u32 cm_emu_override_dpll_core; /* 4a004150 */
+
+ u32 cm_div_h22_dpllcore; /* 4a004154 */
+ u32 cm_div_h23_dpll_core; /* 4a004158 */
+ u32 pad0041[1]; /* 4a00415c */
+ u32 cm_clkmode_dpll_mpu; /* 4a004160 */
+ u32 cm_idlest_dpll_mpu; /* 4a004164 */
+ u32 cm_autoidle_dpll_mpu; /* 4a004168 */
+ u32 cm_clksel_dpll_mpu; /* 4a00416c */
+ u32 cm_div_m2_dpll_mpu; /* 4a004170 */
+ u32 pad005[5]; /* 4a004174 */
+ u32 cm_ssc_deltamstep_dpll_mpu; /* 4a004188 */
+ u32 cm_ssc_modfreqdiv_dpll_mpu; /* 4a00418c */
+ u32 pad006[3]; /* 4a004190 */
+ u32 cm_bypclk_dpll_mpu; /* 4a00419c */
+ u32 cm_clkmode_dpll_iva; /* 4a0041a0 */
+ u32 cm_idlest_dpll_iva; /* 4a0041a4 */
+ u32 cm_autoidle_dpll_iva; /* 4a0041a8 */
+ u32 cm_clksel_dpll_iva; /* 4a0041ac */
+ u32 pad007[2]; /* 4a0041b0 */
+ u32 cm_div_h11_dpll_iva; /* 4a0041b8 */
+ u32 cm_div_h12_dpll_iva; /* 4a0041bc */
+ u32 pad008[2]; /* 4a0041c0 */
+ u32 cm_ssc_deltamstep_dpll_iva; /* 4a0041c8 */
+ u32 cm_ssc_modfreqdiv_dpll_iva; /* 4a0041cc */
+ u32 pad009[3]; /* 4a0041d0 */
+ u32 cm_bypclk_dpll_iva; /* 4a0041dc */
+ u32 cm_clkmode_dpll_abe; /* 4a0041e0 */
+ u32 cm_idlest_dpll_abe; /* 4a0041e4 */
+ u32 cm_autoidle_dpll_abe; /* 4a0041e8 */
+ u32 cm_clksel_dpll_abe; /* 4a0041ec */
+ u32 cm_div_m2_dpll_abe; /* 4a0041f0 */
+ u32 cm_div_m3_dpll_abe; /* 4a0041f4 */
+ u32 pad010[4]; /* 4a0041f8 */
+ u32 cm_ssc_deltamstep_dpll_abe; /* 4a004208 */
+ u32 cm_ssc_modfreqdiv_dpll_abe; /* 4a00420c */
+ u32 pad011[4]; /* 4a004210 */
+ u32 cm_clkmode_dpll_ddrphy; /* 4a004220 */
+ u32 cm_idlest_dpll_ddrphy; /* 4a004224 */
+ u32 cm_autoidle_dpll_ddrphy; /* 4a004228 */
+ u32 cm_clksel_dpll_ddrphy; /* 4a00422c */
+ u32 cm_div_m2_dpll_ddrphy; /* 4a004230 */
+ u32 pad012[1]; /* 4a004234 */
+ u32 cm_div_h11_dpll_ddrphy; /* 4a004238 */
+ u32 cm_div_h12_dpll_ddrphy; /* 4a00423c */
+ u32 cm_div_h13_dpll_ddrphy; /* 4a004240 */
+ u32 pad013[1]; /* 4a004244 */
+ u32 cm_ssc_deltamstep_dpll_ddrphy; /* 4a004248 */
+ u32 pad014[5]; /* 4a00424c */
+ u32 cm_shadow_freq_config1; /* 4a004260 */
+ u32 pad0141[47]; /* 4a004264 */
+ u32 cm_mpu_mpu_clkctrl; /* 4a004320 */
+
+
+ /* cm1.dsp */
+ u32 pad015[55]; /* 4a004324 */
+ u32 cm_dsp_clkstctrl; /* 4a004400 */
+ u32 pad016[7]; /* 4a004404 */
+ u32 cm_dsp_dsp_clkctrl; /* 4a004420 */
+
+ /* cm1.abe */
+ u32 pad017[55]; /* 4a004424 */
+ u32 cm1_abe_clkstctrl; /* 4a004500 */
+ u32 pad018[7]; /* 4a004504 */
+ u32 cm1_abe_l4abe_clkctrl; /* 4a004520 */
+ u32 pad019[1]; /* 4a004524 */
+ u32 cm1_abe_aess_clkctrl; /* 4a004528 */
+ u32 pad020[1]; /* 4a00452c */
+ u32 cm1_abe_pdm_clkctrl; /* 4a004530 */
+ u32 pad021[1]; /* 4a004534 */
+ u32 cm1_abe_dmic_clkctrl; /* 4a004538 */
+ u32 pad022[1]; /* 4a00453c */
+ u32 cm1_abe_mcasp_clkctrl; /* 4a004540 */
+ u32 pad023[1]; /* 4a004544 */
+ u32 cm1_abe_mcbsp1_clkctrl; /* 4a004548 */
+ u32 pad024[1]; /* 4a00454c */
+ u32 cm1_abe_mcbsp2_clkctrl; /* 4a004550 */
+ u32 pad025[1]; /* 4a004554 */
+ u32 cm1_abe_mcbsp3_clkctrl; /* 4a004558 */
+ u32 pad026[1]; /* 4a00455c */
+ u32 cm1_abe_slimbus_clkctrl; /* 4a004560 */
+ u32 pad027[1]; /* 4a004564 */
+ u32 cm1_abe_timer5_clkctrl; /* 4a004568 */
+ u32 pad028[1]; /* 4a00456c */
+ u32 cm1_abe_timer6_clkctrl; /* 4a004570 */
+ u32 pad029[1]; /* 4a004574 */
+ u32 cm1_abe_timer7_clkctrl; /* 4a004578 */
+ u32 pad030[1]; /* 4a00457c */
+ u32 cm1_abe_timer8_clkctrl; /* 4a004580 */
+ u32 pad031[1]; /* 4a004584 */
+ u32 cm1_abe_wdt3_clkctrl; /* 4a004588 */
+
+ /* cm2.ckgen */
+ u32 pad032[3805]; /* 4a00458c */
+ u32 cm_clksel_mpu_m3_iss_root; /* 4a008100 */
+ u32 cm_clksel_usb_60mhz; /* 4a008104 */
+ u32 cm_scale_fclk; /* 4a008108 */
+ u32 pad033[1]; /* 4a00810c */
+ u32 cm_core_dvfs_perf1; /* 4a008110 */
+ u32 cm_core_dvfs_perf2; /* 4a008114 */
+ u32 cm_core_dvfs_perf3; /* 4a008118 */
+ u32 cm_core_dvfs_perf4; /* 4a00811c */
+ u32 pad034[1]; /* 4a008120 */
+ u32 cm_core_dvfs_current; /* 4a008124 */
+ u32 cm_iva_dvfs_perf_tesla; /* 4a008128 */
+ u32 cm_iva_dvfs_perf_ivahd; /* 4a00812c */
+ u32 cm_iva_dvfs_perf_abe; /* 4a008130 */
+ u32 pad035[1]; /* 4a008134 */
+ u32 cm_iva_dvfs_current; /* 4a008138 */
+ u32 pad036[1]; /* 4a00813c */
+ u32 cm_clkmode_dpll_per; /* 4a008140 */
+ u32 cm_idlest_dpll_per; /* 4a008144 */
+ u32 cm_autoidle_dpll_per; /* 4a008148 */
+ u32 cm_clksel_dpll_per; /* 4a00814c */
+ u32 cm_div_m2_dpll_per; /* 4a008150 */
+ u32 cm_div_m3_dpll_per; /* 4a008154 */
+ u32 cm_div_h11_dpll_per; /* 4a008158 */
+ u32 cm_div_h12_dpll_per; /* 4a00815c */
+ u32 pad0361[1]; /* 4a008160 */
+ u32 cm_div_h14_dpll_per; /* 4a008164 */
+ u32 cm_ssc_deltamstep_dpll_per; /* 4a008168 */
+ u32 cm_ssc_modfreqdiv_dpll_per; /* 4a00816c */
+ u32 cm_emu_override_dpll_per; /* 4a008170 */
+ u32 pad037[3]; /* 4a008174 */
+ u32 cm_clkmode_dpll_usb; /* 4a008180 */
+ u32 cm_idlest_dpll_usb; /* 4a008184 */
+ u32 cm_autoidle_dpll_usb; /* 4a008188 */
+ u32 cm_clksel_dpll_usb; /* 4a00818c */
+ u32 cm_div_m2_dpll_usb; /* 4a008190 */
+ u32 pad038[5]; /* 4a008194 */
+ u32 cm_ssc_deltamstep_dpll_usb; /* 4a0081a8 */
+ u32 cm_ssc_modfreqdiv_dpll_usb; /* 4a0081ac */
+ u32 pad039[1]; /* 4a0081b0 */
+ u32 cm_clkdcoldo_dpll_usb; /* 4a0081b4 */
+ u32 pad040[2]; /* 4a0081b8 */
+ u32 cm_clkmode_dpll_unipro; /* 4a0081c0 */
+ u32 cm_idlest_dpll_unipro; /* 4a0081c4 */
+ u32 cm_autoidle_dpll_unipro; /* 4a0081c8 */
+ u32 cm_clksel_dpll_unipro; /* 4a0081cc */
+ u32 cm_div_m2_dpll_unipro; /* 4a0081d0 */
+ u32 pad041[5]; /* 4a0081d4 */
+ u32 cm_ssc_deltamstep_dpll_unipro; /* 4a0081e8 */
+ u32 cm_ssc_modfreqdiv_dpll_unipro; /* 4a0081ec */
+
+ /* cm2.core */
+ u32 pad0411[324]; /* 4a0081f0 */
+ u32 cm_l3_1_clkstctrl; /* 4a008700 */
+ u32 pad042[1]; /* 4a008704 */
+ u32 cm_l3_1_dynamicdep; /* 4a008708 */
+ u32 pad043[5]; /* 4a00870c */
+ u32 cm_l3_1_l3_1_clkctrl; /* 4a008720 */
+ u32 pad044[55]; /* 4a008724 */
+ u32 cm_l3_2_clkstctrl; /* 4a008800 */
+ u32 pad045[1]; /* 4a008804 */
+ u32 cm_l3_2_dynamicdep; /* 4a008808 */
+ u32 pad046[5]; /* 4a00880c */
+ u32 cm_l3_2_l3_2_clkctrl; /* 4a008820 */
+ u32 pad047[1]; /* 4a008824 */
+ u32 cm_l3_2_gpmc_clkctrl; /* 4a008828 */
+ u32 pad048[1]; /* 4a00882c */
+ u32 cm_l3_2_ocmc_ram_clkctrl; /* 4a008830 */
+ u32 pad049[51]; /* 4a008834 */
+ u32 cm_mpu_m3_clkstctrl; /* 4a008900 */
+ u32 cm_mpu_m3_staticdep; /* 4a008904 */
+ u32 cm_mpu_m3_dynamicdep; /* 4a008908 */
+ u32 pad050[5]; /* 4a00890c */
+ u32 cm_mpu_m3_mpu_m3_clkctrl; /* 4a008920 */
+ u32 pad051[55]; /* 4a008924 */
+ u32 cm_sdma_clkstctrl; /* 4a008a00 */
+ u32 cm_sdma_staticdep; /* 4a008a04 */
+ u32 cm_sdma_dynamicdep; /* 4a008a08 */
+ u32 pad052[5]; /* 4a008a0c */
+ u32 cm_sdma_sdma_clkctrl; /* 4a008a20 */
+ u32 pad053[55]; /* 4a008a24 */
+ u32 cm_memif_clkstctrl; /* 4a008b00 */
+ u32 pad054[7]; /* 4a008b04 */
+ u32 cm_memif_dmm_clkctrl; /* 4a008b20 */
+ u32 pad055[1]; /* 4a008b24 */
+ u32 cm_memif_emif_fw_clkctrl; /* 4a008b28 */
+ u32 pad056[1]; /* 4a008b2c */
+ u32 cm_memif_emif_1_clkctrl; /* 4a008b30 */
+ u32 pad057[1]; /* 4a008b34 */
+ u32 cm_memif_emif_2_clkctrl; /* 4a008b38 */
+ u32 pad058[1]; /* 4a008b3c */
+ u32 cm_memif_dll_clkctrl; /* 4a008b40 */
+ u32 pad059[3]; /* 4a008b44 */
+ u32 cm_memif_emif_h1_clkctrl; /* 4a008b50 */
+ u32 pad060[1]; /* 4a008b54 */
+ u32 cm_memif_emif_h2_clkctrl; /* 4a008b58 */
+ u32 pad061[1]; /* 4a008b5c */
+ u32 cm_memif_dll_h_clkctrl; /* 4a008b60 */
+ u32 pad062[39]; /* 4a008b64 */
+ u32 cm_c2c_clkstctrl; /* 4a008c00 */
+ u32 cm_c2c_staticdep; /* 4a008c04 */
+ u32 cm_c2c_dynamicdep; /* 4a008c08 */
+ u32 pad063[5]; /* 4a008c0c */
+ u32 cm_c2c_sad2d_clkctrl; /* 4a008c20 */
+ u32 pad064[1]; /* 4a008c24 */
+ u32 cm_c2c_modem_icr_clkctrl; /* 4a008c28 */
+ u32 pad065[1]; /* 4a008c2c */
+ u32 cm_c2c_sad2d_fw_clkctrl; /* 4a008c30 */
+ u32 pad066[51]; /* 4a008c34 */
+ u32 cm_l4cfg_clkstctrl; /* 4a008d00 */
+ u32 pad067[1]; /* 4a008d04 */
+ u32 cm_l4cfg_dynamicdep; /* 4a008d08 */
+ u32 pad068[5]; /* 4a008d0c */
+ u32 cm_l4cfg_l4_cfg_clkctrl; /* 4a008d20 */
+ u32 pad069[1]; /* 4a008d24 */
+ u32 cm_l4cfg_hw_sem_clkctrl; /* 4a008d28 */
+ u32 pad070[1]; /* 4a008d2c */
+ u32 cm_l4cfg_mailbox_clkctrl; /* 4a008d30 */
+ u32 pad071[1]; /* 4a008d34 */
+ u32 cm_l4cfg_sar_rom_clkctrl; /* 4a008d38 */
+ u32 pad072[49]; /* 4a008d3c */
+ u32 cm_l3instr_clkstctrl; /* 4a008e00 */
+ u32 pad073[7]; /* 4a008e04 */
+ u32 cm_l3instr_l3_3_clkctrl; /* 4a008e20 */
+ u32 pad074[1]; /* 4a008e24 */
+ u32 cm_l3instr_l3_instr_clkctrl; /* 4a008e28 */
+ u32 pad075[5]; /* 4a008e2c */
+ u32 cm_l3instr_intrconn_wp1_clkctrl; /* 4a008e40 */
+
+
+ /* cm2.ivahd */
+ u32 pad076[47]; /* 4a008e44 */
+ u32 cm_ivahd_clkstctrl; /* 4a008f00 */
+ u32 pad077[7]; /* 4a008f04 */
+ u32 cm_ivahd_ivahd_clkctrl; /* 4a008f20 */
+ u32 pad078[1]; /* 4a008f24 */
+ u32 cm_ivahd_sl2_clkctrl; /* 4a008f28 */
+
+ /* cm2.cam */
+ u32 pad079[53]; /* 4a008f2c */
+ u32 cm_cam_clkstctrl; /* 4a009000 */
+ u32 pad080[7]; /* 4a009004 */
+ u32 cm_cam_iss_clkctrl; /* 4a009020 */
+ u32 pad081[1]; /* 4a009024 */
+ u32 cm_cam_fdif_clkctrl; /* 4a009028 */
+
+ /* cm2.dss */
+ u32 pad082[53]; /* 4a00902c */
+ u32 cm_dss_clkstctrl; /* 4a009100 */
+ u32 pad083[7]; /* 4a009104 */
+ u32 cm_dss_dss_clkctrl; /* 4a009120 */
+
+ /* cm2.sgx */
+ u32 pad084[55]; /* 4a009124 */
+ u32 cm_sgx_clkstctrl; /* 4a009200 */
+ u32 pad085[7]; /* 4a009204 */
+ u32 cm_sgx_sgx_clkctrl; /* 4a009220 */
+
+ /* cm2.l3init */
+ u32 pad086[55]; /* 4a009224 */
+ u32 cm_l3init_clkstctrl; /* 4a009300 */
+
+ /* cm2.l3init */
+ u32 pad087[9]; /* 4a009304 */
+ u32 cm_l3init_hsmmc1_clkctrl; /* 4a009328 */
+ u32 pad088[1]; /* 4a00932c */
+ u32 cm_l3init_hsmmc2_clkctrl; /* 4a009330 */
+ u32 pad089[1]; /* 4a009334 */
+ u32 cm_l3init_hsi_clkctrl; /* 4a009338 */
+ u32 pad090[7]; /* 4a00933c */
+ u32 cm_l3init_hsusbhost_clkctrl; /* 4a009358 */
+ u32 pad091[1]; /* 4a00935c */
+ u32 cm_l3init_hsusbotg_clkctrl; /* 4a009360 */
+ u32 pad092[1]; /* 4a009364 */
+ u32 cm_l3init_hsusbtll_clkctrl; /* 4a009368 */
+ u32 pad093[3]; /* 4a00936c */
+ u32 cm_l3init_p1500_clkctrl; /* 4a009378 */
+ u32 pad094[21]; /* 4a00937c */
+ u32 cm_l3init_fsusb_clkctrl; /* 4a0093d0 */
+ u32 pad095[3]; /* 4a0093d4 */
+ u32 cm_l3init_ocp2scp1_clkctrl;
+
+ /* cm2.l4per */
+ u32 pad096[7]; /* 4a0093e4 */
+ u32 cm_l4per_clkstctrl; /* 4a009400 */
+ u32 pad097[1]; /* 4a009404 */
+ u32 cm_l4per_dynamicdep; /* 4a009408 */
+ u32 pad098[5]; /* 4a00940c */
+ u32 cm_l4per_adc_clkctrl; /* 4a009420 */
+ u32 pad100[1]; /* 4a009424 */
+ u32 cm_l4per_gptimer10_clkctrl; /* 4a009428 */
+ u32 pad101[1]; /* 4a00942c */
+ u32 cm_l4per_gptimer11_clkctrl; /* 4a009430 */
+ u32 pad102[1]; /* 4a009434 */
+ u32 cm_l4per_gptimer2_clkctrl; /* 4a009438 */
+ u32 pad103[1]; /* 4a00943c */
+ u32 cm_l4per_gptimer3_clkctrl; /* 4a009440 */
+ u32 pad104[1]; /* 4a009444 */
+ u32 cm_l4per_gptimer4_clkctrl; /* 4a009448 */
+ u32 pad105[1]; /* 4a00944c */
+ u32 cm_l4per_gptimer9_clkctrl; /* 4a009450 */
+ u32 pad106[1]; /* 4a009454 */
+ u32 cm_l4per_elm_clkctrl; /* 4a009458 */
+ u32 pad107[1]; /* 4a00945c */
+ u32 cm_l4per_gpio2_clkctrl; /* 4a009460 */
+ u32 pad108[1]; /* 4a009464 */
+ u32 cm_l4per_gpio3_clkctrl; /* 4a009468 */
+ u32 pad109[1]; /* 4a00946c */
+ u32 cm_l4per_gpio4_clkctrl; /* 4a009470 */
+ u32 pad110[1]; /* 4a009474 */
+ u32 cm_l4per_gpio5_clkctrl; /* 4a009478 */
+ u32 pad111[1]; /* 4a00947c */
+ u32 cm_l4per_gpio6_clkctrl; /* 4a009480 */
+ u32 pad112[1]; /* 4a009484 */
+ u32 cm_l4per_hdq1w_clkctrl; /* 4a009488 */
+ u32 pad113[1]; /* 4a00948c */
+ u32 cm_l4per_hecc1_clkctrl; /* 4a009490 */
+ u32 pad114[1]; /* 4a009494 */
+ u32 cm_l4per_hecc2_clkctrl; /* 4a009498 */
+ u32 pad115[1]; /* 4a00949c */
+ u32 cm_l4per_i2c1_clkctrl; /* 4a0094a0 */
+ u32 pad116[1]; /* 4a0094a4 */
+ u32 cm_l4per_i2c2_clkctrl; /* 4a0094a8 */
+ u32 pad117[1]; /* 4a0094ac */
+ u32 cm_l4per_i2c3_clkctrl; /* 4a0094b0 */
+ u32 pad118[1]; /* 4a0094b4 */
+ u32 cm_l4per_i2c4_clkctrl; /* 4a0094b8 */
+ u32 pad119[1]; /* 4a0094bc */
+ u32 cm_l4per_l4per_clkctrl; /* 4a0094c0 */
+ u32 pad1191[3]; /* 4a0094c4 */
+ u32 cm_l4per_mcasp2_clkctrl; /* 4a0094d0 */
+ u32 pad120[1]; /* 4a0094d4 */
+ u32 cm_l4per_mcasp3_clkctrl; /* 4a0094d8 */
+ u32 pad121[3]; /* 4a0094dc */
+ u32 cm_l4per_mgate_clkctrl; /* 4a0094e8 */
+ u32 pad123[1]; /* 4a0094ec */
+ u32 cm_l4per_mcspi1_clkctrl; /* 4a0094f0 */
+ u32 pad124[1]; /* 4a0094f4 */
+ u32 cm_l4per_mcspi2_clkctrl; /* 4a0094f8 */
+ u32 pad125[1]; /* 4a0094fc */
+ u32 cm_l4per_mcspi3_clkctrl; /* 4a009500 */
+ u32 pad126[1]; /* 4a009504 */
+ u32 cm_l4per_mcspi4_clkctrl; /* 4a009508 */
+ u32 pad127[1]; /* 4a00950c */
+ u32 cm_l4per_gpio7_clkctrl; /* 4a009510 */
+ u32 pad1271[1]; /* 4a009514 */
+ u32 cm_l4per_gpio8_clkctrl; /* 4a009518 */
+ u32 pad1272[1]; /* 4a00951c */
+ u32 cm_l4per_mmcsd3_clkctrl; /* 4a009520 */
+ u32 pad128[1]; /* 4a009524 */
+ u32 cm_l4per_mmcsd4_clkctrl; /* 4a009528 */
+ u32 pad129[1]; /* 4a00952c */
+ u32 cm_l4per_msprohg_clkctrl; /* 4a009530 */
+ u32 pad130[1]; /* 4a009534 */
+ u32 cm_l4per_slimbus2_clkctrl; /* 4a009538 */
+ u32 pad131[1]; /* 4a00953c */
+ u32 cm_l4per_uart1_clkctrl; /* 4a009540 */
+ u32 pad132[1]; /* 4a009544 */
+ u32 cm_l4per_uart2_clkctrl; /* 4a009548 */
+ u32 pad133[1]; /* 4a00954c */
+ u32 cm_l4per_uart3_clkctrl; /* 4a009550 */
+ u32 pad134[1]; /* 4a009554 */
+ u32 cm_l4per_uart4_clkctrl; /* 4a009558 */
+ u32 pad135[1]; /* 4a00955c */
+ u32 cm_l4per_mmcsd5_clkctrl; /* 4a009560 */
+ u32 pad136[1]; /* 4a009564 */
+ u32 cm_l4per_i2c5_clkctrl; /* 4a009568 */
+ u32 pad1371[1]; /* 4a00956c */
+ u32 cm_l4per_uart5_clkctrl; /* 4a009570 */
+ u32 pad1372[1]; /* 4a009574 */
+ u32 cm_l4per_uart6_clkctrl; /* 4a009578 */
+ u32 pad1374[1]; /* 4a00957c */
+ u32 cm_l4sec_clkstctrl; /* 4a009580 */
+ u32 cm_l4sec_staticdep; /* 4a009584 */
+ u32 cm_l4sec_dynamicdep; /* 4a009588 */
+ u32 pad138[5]; /* 4a00958c */
+ u32 cm_l4sec_aes1_clkctrl; /* 4a0095a0 */
+ u32 pad139[1]; /* 4a0095a4 */
+ u32 cm_l4sec_aes2_clkctrl; /* 4a0095a8 */
+ u32 pad140[1]; /* 4a0095ac */
+ u32 cm_l4sec_des3des_clkctrl; /* 4a0095b0 */
+ u32 pad141[1]; /* 4a0095b4 */
+ u32 cm_l4sec_pkaeip29_clkctrl; /* 4a0095b8 */
+ u32 pad142[1]; /* 4a0095bc */
+ u32 cm_l4sec_rng_clkctrl; /* 4a0095c0 */
+ u32 pad143[1]; /* 4a0095c4 */
+ u32 cm_l4sec_sha2md51_clkctrl; /* 4a0095c8 */
+ u32 pad144[3]; /* 4a0095cc */
+ u32 cm_l4sec_cryptodma_clkctrl; /* 4a0095d8 */
+ u32 pad145[3660425]; /* 4a0095dc */
+
+ /* l4 wkup regs */
+ u32 pad201[6211]; /* 4ae00000 */
+ u32 cm_abe_pll_ref_clksel; /* 4ae0610c */
+ u32 cm_sys_clksel; /* 4ae06110 */
+ u32 pad202[1467]; /* 4ae06114 */
+ u32 cm_wkup_clkstctrl; /* 4ae07800 */
+ u32 pad203[7]; /* 4ae07804 */
+ u32 cm_wkup_l4wkup_clkctrl; /* 4ae07820 */
+ u32 pad204; /* 4ae07824 */
+ u32 cm_wkup_wdtimer1_clkctrl; /* 4ae07828 */
+ u32 pad205; /* 4ae0782c */
+ u32 cm_wkup_wdtimer2_clkctrl; /* 4ae07830 */
+ u32 pad206; /* 4ae07834 */
+ u32 cm_wkup_gpio1_clkctrl; /* 4ae07838 */
+ u32 pad207; /* 4ae0783c */
+ u32 cm_wkup_gptimer1_clkctrl; /* 4ae07840 */
+ u32 pad208; /* 4ae07844 */
+ u32 cm_wkup_gptimer12_clkctrl; /* 4ae07848 */
+ u32 pad209; /* 4ae0784c */
+ u32 cm_wkup_synctimer_clkctrl; /* 4ae07850 */
+ u32 pad210; /* 4ae07854 */
+ u32 cm_wkup_usim_clkctrl; /* 4ae07858 */
+ u32 pad211; /* 4ae0785c */
+ u32 cm_wkup_sarram_clkctrl; /* 4ae07860 */
+ u32 pad212[5]; /* 4ae07864 */
+ u32 cm_wkup_keyboard_clkctrl; /* 4ae07878 */
+ u32 pad213; /* 4ae0787c */
+ u32 cm_wkup_rtc_clkctrl; /* 4ae07880 */
+ u32 pad214; /* 4ae07884 */
+ u32 cm_wkup_bandgap_clkctrl; /* 4ae07888 */
+ u32 pad215[197]; /* 4ae0788c */
+ u32 prm_vc_val_bypass; /* 4ae07ba0 */
+ u32 pad216[4];
+ u32 prm_vc_cfg_i2c_mode; /* 4ae07bb4 */
+ u32 prm_vc_cfg_i2c_clk; /* 4ae07bb8 */
+};
+
+/* DPLL register offsets */
+#define CM_CLKMODE_DPLL 0
+#define CM_IDLEST_DPLL 0x4
+#define CM_AUTOIDLE_DPLL 0x8
+#define CM_CLKSEL_DPLL 0xC
+
+#define DPLL_CLKOUT_DIV_MASK 0x1F /* post-divider mask */
+
+/* CM_CLKMODE_DPLL */
+#define CM_CLKMODE_DPLL_REGM4XEN_SHIFT 11
+#define CM_CLKMODE_DPLL_REGM4XEN_MASK (1 << 11)
+#define CM_CLKMODE_DPLL_LPMODE_EN_SHIFT 10
+#define CM_CLKMODE_DPLL_LPMODE_EN_MASK (1 << 10)
+#define CM_CLKMODE_DPLL_RELOCK_RAMP_EN_SHIFT 9
+#define CM_CLKMODE_DPLL_RELOCK_RAMP_EN_MASK (1 << 9)
+#define CM_CLKMODE_DPLL_DRIFTGUARD_EN_SHIFT 8
+#define CM_CLKMODE_DPLL_DRIFTGUARD_EN_MASK (1 << 8)
+#define CM_CLKMODE_DPLL_RAMP_RATE_SHIFT 5
+#define CM_CLKMODE_DPLL_RAMP_RATE_MASK (0x7 << 5)
+#define CM_CLKMODE_DPLL_EN_SHIFT 0
+#define CM_CLKMODE_DPLL_EN_MASK (0x7 << 0)
+
+#define CM_CLKMODE_DPLL_DPLL_EN_SHIFT 0
+#define CM_CLKMODE_DPLL_DPLL_EN_MASK 7
+
+#define DPLL_EN_STOP 1
+#define DPLL_EN_MN_BYPASS 4
+#define DPLL_EN_LOW_POWER_BYPASS 5
+#define DPLL_EN_FAST_RELOCK_BYPASS 6
+#define DPLL_EN_LOCK 7
+
+/* CM_IDLEST_DPLL fields */
+#define ST_DPLL_CLK_MASK 1
+
+/* CM_CLKSEL_DPLL */
+#define CM_CLKSEL_DPLL_DPLL_SD_DIV_SHIFT 24
+#define CM_CLKSEL_DPLL_DPLL_SD_DIV_MASK (0xFF << 24)
+#define CM_CLKSEL_DPLL_M_SHIFT 8
+#define CM_CLKSEL_DPLL_M_MASK (0x7FF << 8)
+#define CM_CLKSEL_DPLL_N_SHIFT 0
+#define CM_CLKSEL_DPLL_N_MASK 0x7F
+#define CM_CLKSEL_DCC_EN_SHIFT 22
+#define CM_CLKSEL_DCC_EN_MASK (1 << 22)
+
+#define OMAP4_DPLL_MAX_N 127
+
+/* CM_SYS_CLKSEL */
+#define CM_SYS_CLKSEL_SYS_CLKSEL_MASK 7
+
+/* CM_CLKSEL_CORE */
+#define CLKSEL_CORE_SHIFT 0
+#define CLKSEL_L3_SHIFT 4
+#define CLKSEL_L4_SHIFT 8
+
+#define CLKSEL_CORE_X2_DIV_1 0
+#define CLKSEL_L3_CORE_DIV_2 1
+#define CLKSEL_L4_L3_DIV_2 1
+
+/* CM_ABE_PLL_REF_CLKSEL */
+#define CM_ABE_PLL_REF_CLKSEL_CLKSEL_SHIFT 0
+#define CM_ABE_PLL_REF_CLKSEL_CLKSEL_MASK 1
+#define CM_ABE_PLL_REF_CLKSEL_CLKSEL_SYSCLK 0
+#define CM_ABE_PLL_REF_CLKSEL_CLKSEL_32KCLK 1
+
+/* CM_BYPCLK_DPLL_IVA */
+#define CM_BYPCLK_DPLL_IVA_CLKSEL_SHIFT 0
+#define CM_BYPCLK_DPLL_IVA_CLKSEL_MASK 3
+
+#define DPLL_IVA_CLKSEL_CORE_X2_DIV_2 1
+
+/* CM_SHADOW_FREQ_CONFIG1 */
+#define SHADOW_FREQ_CONFIG1_FREQ_UPDATE_MASK 1
+#define SHADOW_FREQ_CONFIG1_DLL_OVERRIDE_MASK 4
+#define SHADOW_FREQ_CONFIG1_DLL_RESET_MASK 8
+
+#define SHADOW_FREQ_CONFIG1_DPLL_EN_SHIFT 8
+#define SHADOW_FREQ_CONFIG1_DPLL_EN_MASK (7 << 8)
+
+#define SHADOW_FREQ_CONFIG1_M2_DIV_SHIFT 11
+#define SHADOW_FREQ_CONFIG1_M2_DIV_MASK (0x1F << 11)
+
+/*CM_<clock_domain>__CLKCTRL */
+#define CD_CLKCTRL_CLKTRCTRL_SHIFT 0
+#define CD_CLKCTRL_CLKTRCTRL_MASK 3
+
+#define CD_CLKCTRL_CLKTRCTRL_NO_SLEEP 0
+#define CD_CLKCTRL_CLKTRCTRL_SW_SLEEP 1
+#define CD_CLKCTRL_CLKTRCTRL_SW_WKUP 2
+#define CD_CLKCTRL_CLKTRCTRL_HW_AUTO 3
+
+
+/* CM_<clock_domain>_<module>_CLKCTRL */
+#define MODULE_CLKCTRL_MODULEMODE_SHIFT 0
+#define MODULE_CLKCTRL_MODULEMODE_MASK 3
+#define MODULE_CLKCTRL_IDLEST_SHIFT 16
+#define MODULE_CLKCTRL_IDLEST_MASK (3 << 16)
+
+#define MODULE_CLKCTRL_MODULEMODE_SW_DISABLE 0
+#define MODULE_CLKCTRL_MODULEMODE_HW_AUTO 1
+#define MODULE_CLKCTRL_MODULEMODE_SW_EXPLICIT_EN 2
+
+#define MODULE_CLKCTRL_IDLEST_FULLY_FUNCTIONAL 0
+#define MODULE_CLKCTRL_IDLEST_TRANSITIONING 1
+#define MODULE_CLKCTRL_IDLEST_IDLE 2
+#define MODULE_CLKCTRL_IDLEST_DISABLED 3
+
+/* CM_L4PER_GPIO4_CLKCTRL */
+#define GPIO4_CLKCTRL_OPTFCLKEN_MASK (1 << 8)
+
+/* CM_L3INIT_HSMMCn_CLKCTRL */
+#define HSMMC_CLKCTRL_CLKSEL_MASK (1 << 24)
+
+/* CM_WKUP_GPTIMER1_CLKCTRL */
+#define GPTIMER1_CLKCTRL_CLKSEL_MASK (1 << 24)
+
+/* CM_CAM_ISS_CLKCTRL */
+#define ISS_CLKCTRL_OPTFCLKEN_MASK (1 << 8)
+
+/* CM_DSS_DSS_CLKCTRL */
+#define DSS_CLKCTRL_OPTFCLKEN_MASK 0xF00
+
+/* CM_L3INIT_USBPHY_CLKCTRL */
+#define USBPHY_CLKCTRL_OPTFCLKEN_PHY_48M_MASK 8
+
+/* CM_MPU_MPU_CLKCTRL */
+#define MPU_CLKCTRL_CLKSEL_EMIF_DIV_MODE_SHIFT 24
+#define MPU_CLKCTRL_CLKSEL_EMIF_DIV_MODE_MASK (1 << 24)
+#define MPU_CLKCTRL_CLKSEL_ABE_DIV_MODE_SHIFT 25
+#define MPU_CLKCTRL_CLKSEL_ABE_DIV_MODE_MASK (1 << 25)
+
+/* Clock frequencies */
+#define OMAP_SYS_CLK_FREQ_38_4_MHZ 38400000
+#define OMAP_SYS_CLK_IND_38_4_MHZ 6
+#define OMAP_32K_CLK_FREQ 32768
+
+/* PRM_VC_CFG_I2C_CLK */
+#define PRM_VC_CFG_I2C_CLK_SCLH_SHIFT 0
+#define PRM_VC_CFG_I2C_CLK_SCLH_MASK 0xFF
+#define PRM_VC_CFG_I2C_CLK_SCLL_SHIFT 8
+#define PRM_VC_CFG_I2C_CLK_SCLL_MASK (0xFF << 8)
+
+/* PRM_VC_VAL_BYPASS */
+#define PRM_VC_I2C_CHANNEL_FREQ_KHZ 400
+
+#define PRM_VC_VAL_BYPASS_VALID_BIT 0x1000000
+#define PRM_VC_VAL_BYPASS_SLAVEADDR_SHIFT 0
+#define PRM_VC_VAL_BYPASS_SLAVEADDR_MASK 0x7F
+#define PRM_VC_VAL_BYPASS_REGADDR_SHIFT 8
+#define PRM_VC_VAL_BYPASS_REGADDR_MASK 0xFF
+#define PRM_VC_VAL_BYPASS_DATA_SHIFT 16
+#define PRM_VC_VAL_BYPASS_DATA_MASK 0xFF
+
+/* SMPS */
+#define SMPS_I2C_SLAVE_ADDR 0x12
+#define SMPS_REG_ADDR_VCORE1 0x55
+#define SMPS_REG_ADDR_VCORE2 0x5B
+#define SMPS_REG_ADDR_VCORE3 0x61
+
+#define PHOENIX_SMPS_BASE_VOLT_STD_MODE_UV 607700
+#define PHOENIX_SMPS_BASE_VOLT_STD_MODE_WITH_OFFSET_UV 709000
+
+/* TPS */
+#define TPS62361_I2C_SLAVE_ADDR 0x60
+#define TPS62361_REG_ADDR_SET0 0x0
+#define TPS62361_REG_ADDR_SET1 0x1
+#define TPS62361_REG_ADDR_SET2 0x2
+#define TPS62361_REG_ADDR_SET3 0x3
+#define TPS62361_REG_ADDR_CTRL 0x4
+#define TPS62361_REG_ADDR_TEMP 0x5
+#define TPS62361_REG_ADDR_RMP_CTRL 0x6
+#define TPS62361_REG_ADDR_CHIP_ID 0x8
+#define TPS62361_REG_ADDR_CHIP_ID_2 0x9
+
+#define TPS62361_BASE_VOLT_MV 500
+#define TPS62361_VSEL0_GPIO 7
+
+/* Defines for DPLL setup */
+#define DPLL_LOCKED_FREQ_TOLERANCE_0 0
+#define DPLL_LOCKED_FREQ_TOLERANCE_500_KHZ 500
+#define DPLL_LOCKED_FREQ_TOLERANCE_1_MHZ 1000
+
+#define DPLL_NO_LOCK 0
+#define DPLL_LOCK 1
+
+#define NUM_SYS_CLKS 7
+
+struct dpll_regs {
+ u32 cm_clkmode_dpll;
+ u32 cm_idlest_dpll;
+ u32 cm_autoidle_dpll;
+ u32 cm_clksel_dpll;
+ u32 cm_div_m2_dpll;
+ u32 cm_div_m3_dpll;
+ u32 cm_div_h11_dpll;
+ u32 cm_div_h12_dpll;
+ u32 cm_div_h13_dpll;
+ u32 cm_div_h14_dpll;
+ u32 reserved[2];
+ u32 cm_div_h22_dpll;
+ u32 cm_div_h23_dpll;
+};
+
+/* DPLL parameter table */
+struct dpll_params {
+ u32 m;
+ u32 n;
+ u8 m2;
+ u8 m3;
+ u8 h11;
+ u8 h12;
+ u8 h13;
+ u8 h14;
+ u8 h22;
+ u8 h23;
+};
+
+extern struct omap5_prcm_regs *const prcm;
+extern const u32 sys_clk_array[8];
+
+void scale_vcores(void);
+void do_scale_tps62361(u32 reg, u32 volt_mv);
+u32 omap_ddr_clk(void);
+void do_scale_vcore(u32 vcore_reg, u32 volt_mv);
+void setup_sri2c(void);
+void setup_post_dividers(u32 *const base, const struct dpll_params *params);
+u32 get_sys_clk_index(void);
+void enable_basic_clocks(void);
+void enable_non_essential_clocks(void);
+void enable_basic_uboot_clocks(void);
+void do_enable_clocks(u32 *const *clk_domains,
+ u32 *const *clk_modules_hw_auto,
+ u32 *const *clk_modules_explicit_en,
+ u8 wait_for_enable);
+const struct dpll_params *get_mpu_dpll_params(void);
+const struct dpll_params *get_core_dpll_params(void);
+const struct dpll_params *get_per_dpll_params(void);
+const struct dpll_params *get_iva_dpll_params(void);
+const struct dpll_params *get_usb_dpll_params(void);
+const struct dpll_params *get_abe_dpll_params(void);
+#endif /* _CLOCKS_OMAP5_H_ */
diff --git a/arch/arm/include/asm/arch-omap5/cpu.h b/arch/arm/include/asm/arch-omap5/cpu.h
new file mode 100644
index 0000000..0697a73
--- /dev/null
+++ b/arch/arm/include/asm/arch-omap5/cpu.h
@@ -0,0 +1,175 @@
+/*
+ * (C) Copyright 2006-2010
+ * Texas Instruments, <www.ti.com>
+ *
+ * Aneesh V <aneesh@ti.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ *
+ */
+
+#ifndef _CPU_H
+#define _CPU_H
+
+#if !(defined(__KERNEL_STRICT_NAMES) || defined(__ASSEMBLY__))
+#include <asm/types.h>
+#endif /* !(__KERNEL_STRICT_NAMES || __ASSEMBLY__) */
+
+#ifndef __KERNEL_STRICT_NAMES
+#ifndef __ASSEMBLY__
+struct gpmc_cs {
+ u32 config1; /* 0x00 */
+ u32 config2; /* 0x04 */
+ u32 config3; /* 0x08 */
+ u32 config4; /* 0x0C */
+ u32 config5; /* 0x10 */
+ u32 config6; /* 0x14 */
+ u32 config7; /* 0x18 */
+ u32 nand_cmd; /* 0x1C */
+ u32 nand_adr; /* 0x20 */
+ u32 nand_dat; /* 0x24 */
+ u8 res[8]; /* blow up to 0x30 byte */
+};
+
+struct gpmc {
+ u8 res1[0x10];
+ u32 sysconfig; /* 0x10 */
+ u8 res2[0x4];
+ u32 irqstatus; /* 0x18 */
+ u32 irqenable; /* 0x1C */
+ u8 res3[0x20];
+ u32 timeout_control; /* 0x40 */
+ u8 res4[0xC];
+ u32 config; /* 0x50 */
+ u32 status; /* 0x54 */
+ u8 res5[0x8]; /* 0x58 */
+ struct gpmc_cs cs[8]; /* 0x60, 0x90, .. */
+ u8 res6[0x14]; /* 0x1E0 */
+ u32 ecc_config; /* 0x1F4 */
+ u32 ecc_control; /* 0x1F8 */
+ u32 ecc_size_config; /* 0x1FC */
+ u32 ecc1_result; /* 0x200 */
+ u32 ecc2_result; /* 0x204 */
+ u32 ecc3_result; /* 0x208 */
+ u32 ecc4_result; /* 0x20C */
+ u32 ecc5_result; /* 0x210 */
+ u32 ecc6_result; /* 0x214 */
+ u32 ecc7_result; /* 0x218 */
+ u32 ecc8_result; /* 0x21C */
+ u32 ecc9_result; /* 0x220 */
+};
+
+/* Used for board specific gpmc initialization */
+extern struct gpmc *gpmc_cfg;
+
+struct gptimer {
+ u32 tidr; /* 0x00 r */
+ u8 res1[0xc];
+ u32 tiocp_cfg; /* 0x10 rw */
+ u8 res2[0x10];
+ u32 tisr_raw; /* 0x24 r */
+ u32 tisr; /* 0x28 rw */
+ u32 tier; /* 0x2c rw */
+ u32 ticr; /* 0x30 rw */
+ u32 twer; /* 0x34 rw */
+ u32 tclr; /* 0x38 rw */
+ u32 tcrr; /* 0x3c rw */
+ u32 tldr; /* 0x40 rw */
+ u32 ttgr; /* 0x44 rw */
+ u32 twpc; /* 0x48 r */
+ u32 tmar; /* 0x4c rw */
+ u32 tcar1; /* 0x50 r */
+ u32 tcicr; /* 0x54 rw */
+ u32 tcar2; /* 0x58 r */
+};
+#endif /* __ASSEMBLY__ */
+#endif /* __KERNEL_STRICT_NAMES */
+
+/* enable sys_clk NO-prescale /1 */
+#define GPT_EN ((0x0 << 2) | (0x1 << 1) | (0x1 << 0))
+
+/* Watchdog */
+#ifndef __KERNEL_STRICT_NAMES
+#ifndef __ASSEMBLY__
+struct watchdog {
+ u8 res1[0x34];
+ u32 wwps; /* 0x34 r */
+ u8 res2[0x10];
+ u32 wspr; /* 0x48 rw */
+};
+#endif /* __ASSEMBLY__ */
+#endif /* __KERNEL_STRICT_NAMES */
+
+#define WD_UNLOCK1 0xAAAA
+#define WD_UNLOCK2 0x5555
+
+#define SYSCLKDIV_1 (0x1 << 6)
+#define SYSCLKDIV_2 (0x1 << 7)
+
+#define CLKSEL_GPT1 (0x1 << 0)
+
+#define EN_GPT1 (0x1 << 0)
+#define EN_32KSYNC (0x1 << 2)
+
+#define ST_WDT2 (0x1 << 5)
+
+#define RESETDONE (0x1 << 0)
+
+#define TCLR_ST (0x1 << 0)
+#define TCLR_AR (0x1 << 1)
+#define TCLR_PRE (0x1 << 5)
+
+/* GPMC BASE */
+#define GPMC_BASE (OMAP54XX_GPMC_BASE)
+
+/* I2C base */
+#define I2C_BASE1 (OMAP54XX_L4_PER_BASE + 0x70000)
+#define I2C_BASE2 (OMAP54XX_L4_PER_BASE + 0x72000)
+#define I2C_BASE3 (OMAP54XX_L4_PER_BASE + 0x60000)
+
+/* MUSB base */
+#define MUSB_BASE (OMAP54XX_L4_CORE_BASE + 0xAB000)
+
+/* OMAP4 GPIO registers */
+#define OMAP_GPIO_REVISION 0x0000
+#define OMAP_GPIO_SYSCONFIG 0x0010
+#define OMAP_GPIO_SYSSTATUS 0x0114
+#define OMAP_GPIO_IRQSTATUS1 0x0118
+#define OMAP_GPIO_IRQSTATUS2 0x0128
+#define OMAP_GPIO_IRQENABLE2 0x012c
+#define OMAP_GPIO_IRQENABLE1 0x011c
+#define OMAP_GPIO_WAKE_EN 0x0120
+#define OMAP_GPIO_CTRL 0x0130
+#define OMAP_GPIO_OE 0x0134
+#define OMAP_GPIO_DATAIN 0x0138
+#define OMAP_GPIO_DATAOUT 0x013c
+#define OMAP_GPIO_LEVELDETECT0 0x0140
+#define OMAP_GPIO_LEVELDETECT1 0x0144
+#define OMAP_GPIO_RISINGDETECT 0x0148
+#define OMAP_GPIO_FALLINGDETECT 0x014c
+#define OMAP_GPIO_DEBOUNCE_EN 0x0150
+#define OMAP_GPIO_DEBOUNCE_VAL 0x0154
+#define OMAP_GPIO_CLEARIRQENABLE1 0x0160
+#define OMAP_GPIO_SETIRQENABLE1 0x0164
+#define OMAP_GPIO_CLEARWKUENA 0x0180
+#define OMAP_GPIO_SETWKUENA 0x0184
+#define OMAP_GPIO_CLEARDATAOUT 0x0190
+#define OMAP_GPIO_SETDATAOUT 0x0194
+
+#endif /* _CPU_H */
diff --git a/arch/arm/include/asm/arch-omap5/gpio.h b/arch/arm/include/asm/arch-omap5/gpio.h
new file mode 100644
index 0000000..c14dff0
--- /dev/null
+++ b/arch/arm/include/asm/arch-omap5/gpio.h
@@ -0,0 +1,50 @@
+/*
+ * Copyright (c) 2009 Wind River Systems, Inc.
+ * Tom Rix <Tom.Rix@windriver.com>
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ *
+ * This work is derived from the linux 2.6.27 kernel source
+ * To fetch, use the kernel repository
+ * git://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux-2.6.git
+ * Use the v2.6.27 tag.
+ *
+ * Below is the original's header including its copyright
+ *
+ * linux/arch/arm/plat-omap/gpio.c
+ *
+ * Support functions for OMAP GPIO
+ *
+ * Copyright (C) 2003-2005 Nokia Corporation
+ * Written by Juha Yrjölä <juha.yrjola@nokia.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+#ifndef _GPIO_OMAP5_H
+#define _GPIO_OMAP5_H
+
+#include <asm/omap_gpio.h>
+
+#define OMAP54XX_GPIO1_BASE 0x4Ae10000
+#define OMAP54XX_GPIO2_BASE 0x48055000
+#define OMAP54XX_GPIO3_BASE 0x48057000
+#define OMAP54XX_GPIO4_BASE 0x48059000
+#define OMAP54XX_GPIO5_BASE 0x4805B000
+#define OMAP54XX_GPIO6_BASE 0x4805D000
+
+#endif /* _GPIO_OMAP5_H */
diff --git a/arch/arm/include/asm/arch-omap5/i2c.h b/arch/arm/include/asm/arch-omap5/i2c.h
new file mode 100644
index 0000000..68be03b
--- /dev/null
+++ b/arch/arm/include/asm/arch-omap5/i2c.h
@@ -0,0 +1,74 @@
+/*
+ * (C) Copyright 2004-2010
+ * Texas Instruments, <www.ti.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+#ifndef _OMAP5_I2C_H_
+#define _OMAP5_I2C_H_
+
+#define I2C_BUS_MAX 3
+#define I2C_DEFAULT_BASE I2C_BASE1
+
+struct i2c {
+ unsigned short revnb_lo; /* 0x00 */
+ unsigned short res1;
+ unsigned short revnb_hi; /* 0x04 */
+ unsigned short res2[13];
+ unsigned short sysc; /* 0x20 */
+ unsigned short res3;
+ unsigned short irqstatus_raw; /* 0x24 */
+ unsigned short res4;
+ unsigned short stat; /* 0x28 */
+ unsigned short res5;
+ unsigned short ie; /* 0x2C */
+ unsigned short res6;
+ unsigned short irqenable_clr; /* 0x30 */
+ unsigned short res7;
+ unsigned short iv; /* 0x34 */
+ unsigned short res8[45];
+ unsigned short syss; /* 0x90 */
+ unsigned short res9;
+ unsigned short buf; /* 0x94 */
+ unsigned short res10;
+ unsigned short cnt; /* 0x98 */
+ unsigned short res11;
+ unsigned short data; /* 0x9C */
+ unsigned short res13;
+ unsigned short res14; /* 0xA0 */
+ unsigned short res15;
+ unsigned short con; /* 0xA4 */
+ unsigned short res16;
+ unsigned short oa; /* 0xA8 */
+ unsigned short res17;
+ unsigned short sa; /* 0xAC */
+ unsigned short res18;
+ unsigned short psc; /* 0xB0 */
+ unsigned short res19;
+ unsigned short scll; /* 0xB4 */
+ unsigned short res20;
+ unsigned short sclh; /* 0xB8 */
+ unsigned short res21;
+ unsigned short systest; /* 0xBC */
+ unsigned short res22;
+ unsigned short bufstat; /* 0xC0 */
+ unsigned short res23;
+};
+
+#endif /* _OMAP5_I2C_H_ */
diff --git a/arch/arm/include/asm/arch-omap5/mmc_host_def.h b/arch/arm/include/asm/arch-omap5/mmc_host_def.h
new file mode 100644
index 0000000..74439c9
--- /dev/null
+++ b/arch/arm/include/asm/arch-omap5/mmc_host_def.h
@@ -0,0 +1,174 @@
+/*
+ * (C) Copyright 2010
+ * Texas Instruments, <www.ti.com>
+ * Syed Mohammed Khasim <khasim@ti.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation's version 2 of
+ * the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#ifndef MMC_HOST_DEF_H
+#define MMC_HOST_DEF_H
+
+/*
+ * OMAP HSMMC register definitions
+ */
+
+#define OMAP_HSMMC1_BASE 0x4809C100
+#define OMAP_HSMMC2_BASE 0x480B4100
+#define OMAP_HSMMC3_BASE 0x480AD100
+
+struct hsmmc {
+ unsigned char res1[0x10];
+ unsigned int sysconfig; /* 0x10 */
+ unsigned int sysstatus; /* 0x14 */
+ unsigned char res2[0x14];
+ unsigned int con; /* 0x2C */
+ unsigned char res3[0xD4];
+ unsigned int blk; /* 0x104 */
+ unsigned int arg; /* 0x108 */
+ unsigned int cmd; /* 0x10C */
+ unsigned int rsp10; /* 0x110 */
+ unsigned int rsp32; /* 0x114 */
+ unsigned int rsp54; /* 0x118 */
+ unsigned int rsp76; /* 0x11C */
+ unsigned int data; /* 0x120 */
+ unsigned int pstate; /* 0x124 */
+ unsigned int hctl; /* 0x128 */
+ unsigned int sysctl; /* 0x12C */
+ unsigned int stat; /* 0x130 */
+ unsigned int ie; /* 0x134 */
+ unsigned char res4[0x8];
+ unsigned int capa; /* 0x140 */
+};
+
+/*
+ * OMAP HS MMC Bit definitions
+ */
+#define MMC_SOFTRESET (0x1 << 1)
+#define RESETDONE (0x1 << 0)
+#define NOOPENDRAIN (0x0 << 0)
+#define OPENDRAIN (0x1 << 0)
+#define OD (0x1 << 0)
+#define INIT_NOINIT (0x0 << 1)
+#define INIT_INITSTREAM (0x1 << 1)
+#define HR_NOHOSTRESP (0x0 << 2)
+#define STR_BLOCK (0x0 << 3)
+#define MODE_FUNC (0x0 << 4)
+#define DW8_1_4BITMODE (0x0 << 5)
+#define MIT_CTO (0x0 << 6)
+#define CDP_ACTIVEHIGH (0x0 << 7)
+#define WPP_ACTIVEHIGH (0x0 << 8)
+#define RESERVED_MASK (0x3 << 9)
+#define CTPL_MMC_SD (0x0 << 11)
+#define BLEN_512BYTESLEN (0x200 << 0)
+#define NBLK_STPCNT (0x0 << 16)
+#define DE_DISABLE (0x0 << 0)
+#define BCE_DISABLE (0x0 << 1)
+#define BCE_ENABLE (0x1 << 1)
+#define ACEN_DISABLE (0x0 << 2)
+#define DDIR_OFFSET (4)
+#define DDIR_MASK (0x1 << 4)
+#define DDIR_WRITE (0x0 << 4)
+#define DDIR_READ (0x1 << 4)
+#define MSBS_SGLEBLK (0x0 << 5)
+#define MSBS_MULTIBLK (0x1 << 5)
+#define RSP_TYPE_OFFSET (16)
+#define RSP_TYPE_MASK (0x3 << 16)
+#define RSP_TYPE_NORSP (0x0 << 16)
+#define RSP_TYPE_LGHT136 (0x1 << 16)
+#define RSP_TYPE_LGHT48 (0x2 << 16)
+#define RSP_TYPE_LGHT48B (0x3 << 16)
+#define CCCE_NOCHECK (0x0 << 19)
+#define CCCE_CHECK (0x1 << 19)
+#define CICE_NOCHECK (0x0 << 20)
+#define CICE_CHECK (0x1 << 20)
+#define DP_OFFSET (21)
+#define DP_MASK (0x1 << 21)
+#define DP_NO_DATA (0x0 << 21)
+#define DP_DATA (0x1 << 21)
+#define CMD_TYPE_NORMAL (0x0 << 22)
+#define INDEX_OFFSET (24)
+#define INDEX_MASK (0x3f << 24)
+#define INDEX(i) (i << 24)
+#define DATI_MASK (0x1 << 1)
+#define DATI_CMDDIS (0x1 << 1)
+#define DTW_1_BITMODE (0x0 << 1)
+#define DTW_4_BITMODE (0x1 << 1)
+#define DTW_8_BITMODE (0x1 << 5) /* CON[DW8]*/
+#define SDBP_PWROFF (0x0 << 8)
+#define SDBP_PWRON (0x1 << 8)
+#define SDVS_1V8 (0x5 << 9)
+#define SDVS_3V0 (0x6 << 9)
+#define ICE_MASK (0x1 << 0)
+#define ICE_STOP (0x0 << 0)
+#define ICS_MASK (0x1 << 1)
+#define ICS_NOTREADY (0x0 << 1)
+#define ICE_OSCILLATE (0x1 << 0)
+#define CEN_MASK (0x1 << 2)
+#define CEN_DISABLE (0x0 << 2)
+#define CEN_ENABLE (0x1 << 2)
+#define CLKD_OFFSET (6)
+#define CLKD_MASK (0x3FF << 6)
+#define DTO_MASK (0xF << 16)
+#define DTO_15THDTO (0xE << 16)
+#define SOFTRESETALL (0x1 << 24)
+#define CC_MASK (0x1 << 0)
+#define TC_MASK (0x1 << 1)
+#define BWR_MASK (0x1 << 4)
+#define BRR_MASK (0x1 << 5)
+#define ERRI_MASK (0x1 << 15)
+#define IE_CC (0x01 << 0)
+#define IE_TC (0x01 << 1)
+#define IE_BWR (0x01 << 4)
+#define IE_BRR (0x01 << 5)
+#define IE_CTO (0x01 << 16)
+#define IE_CCRC (0x01 << 17)
+#define IE_CEB (0x01 << 18)
+#define IE_CIE (0x01 << 19)
+#define IE_DTO (0x01 << 20)
+#define IE_DCRC (0x01 << 21)
+#define IE_DEB (0x01 << 22)
+#define IE_CERR (0x01 << 28)
+#define IE_BADA (0x01 << 29)
+
+#define VS30_3V0SUP (1 << 25)
+#define VS18_1V8SUP (1 << 26)
+
+/* Driver definitions */
+#define MMCSD_SECTOR_SIZE 512
+#define MMC_CARD 0
+#define SD_CARD 1
+#define BYTE_MODE 0
+#define SECTOR_MODE 1
+#define CLK_INITSEQ 0
+#define CLK_400KHZ 1
+#define CLK_MISC 2
+
+#define RSP_TYPE_NONE (RSP_TYPE_NORSP | CCCE_NOCHECK | CICE_NOCHECK)
+#define MMC_CMD0 (INDEX(0) | RSP_TYPE_NONE | DP_NO_DATA | DDIR_WRITE)
+
+/* Clock Configurations and Macros */
+#define MMC_CLOCK_REFERENCE 96 /* MHz */
+
+#define mmc_reg_out(addr, mask, val)\
+ writel((readl(addr) & (~(mask))) | ((val) & (mask)), (addr))
+
+int omap_mmc_init(int dev_index);
+
+#endif /* MMC_HOST_DEF_H */
diff --git a/arch/arm/include/asm/arch-omap5/mux_omap5.h b/arch/arm/include/asm/arch-omap5/mux_omap5.h
new file mode 100644
index 0000000..b8c2185
--- /dev/null
+++ b/arch/arm/include/asm/arch-omap5/mux_omap5.h
@@ -0,0 +1,344 @@
+/*
+ * (C) Copyright 2004-2009
+ * Texas Instruments Incorporated
+ * Richard Woodruff <r-woodruff2@ti.com>
+ * Aneesh V <aneesh@ti.com>
+ * Balaji Krishnamoorthy <balajitk@ti.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+#ifndef _MUX_OMAP5_H_
+#define _MUX_OMAP5_H_
+
+#include <asm/types.h>
+
+struct pad_conf_entry {
+
+ u16 offset;
+
+ u16 val;
+
+} __attribute__ ((__packed__));
+
+#ifdef CONFIG_OFF_PADCONF
+#define OFF_PD (1 << 12)
+#define OFF_PU (3 << 12)
+#define OFF_OUT_PTD (0 << 10)
+#define OFF_OUT_PTU (2 << 10)
+#define OFF_IN (1 << 10)
+#define OFF_OUT (0 << 10)
+#define OFF_EN (1 << 9)
+#else
+#define OFF_PD (0 << 12)
+#define OFF_PU (0 << 12)
+#define OFF_OUT_PTD (0 << 10)
+#define OFF_OUT_PTU (0 << 10)
+#define OFF_IN (0 << 10)
+#define OFF_OUT (0 << 10)
+#define OFF_EN (0 << 9)
+#endif
+
+#define IEN (1 << 8)
+#define IDIS (0 << 8)
+#define PTU (3 << 3)
+#define PTD (1 << 3)
+#define EN (1 << 3)
+#define DIS (0 << 3)
+
+#define M0 0
+#define M1 1
+#define M2 2
+#define M3 3
+#define M4 4
+#define M5 5
+#define M6 6
+#define M7 7
+
+#define SAFE_MODE M7
+
+#ifdef CONFIG_OFF_PADCONF
+#define OFF_IN_PD (OFF_PD | OFF_IN | OFF_EN)
+#define OFF_IN_PU (OFF_PU | OFF_IN | OFF_EN)
+#define OFF_OUT_PD (OFF_OUT_PTD | OFF_OUT | OFF_EN)
+#define OFF_OUT_PU (OFF_OUT_PTU | OFF_OUT | OFF_EN)
+#else
+#define OFF_IN_PD 0
+#define OFF_IN_PU 0
+#define OFF_OUT_PD 0
+#define OFF_OUT_PU 0
+#endif
+
+#define CORE_REVISION 0x0000
+#define CORE_HWINFO 0x0004
+#define CORE_SYSCONFIG 0x0010
+#define GPMC_AD0 0x0040
+#define GPMC_AD1 0x0042
+#define GPMC_AD2 0x0044
+#define GPMC_AD3 0x0046
+#define GPMC_AD4 0x0048
+#define GPMC_AD5 0x004A
+#define GPMC_AD6 0x004C
+#define GPMC_AD7 0x004E
+#define GPMC_AD8 0x0050
+#define GPMC_AD9 0x0052
+#define GPMC_AD10 0x0054
+#define GPMC_AD11 0x0056
+#define GPMC_AD12 0x0058
+#define GPMC_AD13 0x005A
+#define GPMC_AD14 0x005C
+#define GPMC_AD15 0x005E
+#define GPMC_A16 0x0060
+#define GPMC_A17 0x0062
+#define GPMC_A18 0x0064
+#define GPMC_A19 0x0066
+#define GPMC_A20 0x0068
+#define GPMC_A21 0x006A
+#define GPMC_A22 0x006C
+#define GPMC_A23 0x006E
+#define GPMC_A24 0x0070
+#define GPMC_A25 0x0072
+#define GPMC_NCS0 0x0074
+#define GPMC_NCS1 0x0076
+#define GPMC_NCS2 0x0078
+#define GPMC_NCS3 0x007A
+#define GPMC_NWP 0x007C
+#define GPMC_CLK 0x007E
+#define GPMC_NADV_ALE 0x0080
+#define GPMC_NOE 0x0082
+#define GPMC_NWE 0x0084
+#define GPMC_NBE0_CLE 0x0086
+#define GPMC_NBE1 0x0088
+#define GPMC_WAIT0 0x008A
+#define GPMC_WAIT1 0x008C
+#define C2C_DATA11 0x008E
+#define C2C_DATA12 0x0090
+#define C2C_DATA13 0x0092
+#define C2C_DATA14 0x0094
+#define C2C_DATA15 0x0096
+#define HDMI_HPD 0x0098
+#define HDMI_CEC 0x009A
+#define HDMI_DDC_SCL 0x009C
+#define HDMI_DDC_SDA 0x009E
+#define CSI21_DX0 0x00A0
+#define CSI21_DY0 0x00A2
+#define CSI21_DX1 0x00A4
+#define CSI21_DY1 0x00A6
+#define CSI21_DX2 0x00A8
+#define CSI21_DY2 0x00AA
+#define CSI21_DX3 0x00AC
+#define CSI21_DY3 0x00AE
+#define CSI21_DX4 0x00B0
+#define CSI21_DY4 0x00B2
+#define CSI22_DX0 0x00B4
+#define CSI22_DY0 0x00B6
+#define CSI22_DX1 0x00B8
+#define CSI22_DY1 0x00BA
+#define CAM_SHUTTER 0x00BC
+#define CAM_STROBE 0x00BE
+#define CAM_GLOBALRESET 0x00C0
+#define USBB1_ULPITLL_CLK 0x00C2
+#define USBB1_ULPITLL_STP 0x00C4
+#define USBB1_ULPITLL_DIR 0x00C6
+#define USBB1_ULPITLL_NXT 0x00C8
+#define USBB1_ULPITLL_DAT0 0x00CA
+#define USBB1_ULPITLL_DAT1 0x00CC
+#define USBB1_ULPITLL_DAT2 0x00CE
+#define USBB1_ULPITLL_DAT3 0x00D0
+#define USBB1_ULPITLL_DAT4 0x00D2
+#define USBB1_ULPITLL_DAT5 0x00D4
+#define USBB1_ULPITLL_DAT6 0x00D6
+#define USBB1_ULPITLL_DAT7 0x00D8
+#define USBB1_HSIC_DATA 0x00DA
+#define USBB1_HSIC_STROBE 0x00DC
+#define USBC1_ICUSB_DP 0x00DE
+#define USBC1_ICUSB_DM 0x00E0
+#define SDMMC1_CLK 0x00E2
+#define SDMMC1_CMD 0x00E4
+#define SDMMC1_DAT0 0x00E6
+#define SDMMC1_DAT1 0x00E8
+#define SDMMC1_DAT2 0x00EA
+#define SDMMC1_DAT3 0x00EC
+#define SDMMC1_DAT4 0x00EE
+#define SDMMC1_DAT5 0x00F0
+#define SDMMC1_DAT6 0x00F2
+#define SDMMC1_DAT7 0x00F4
+#define ABE_MCBSP2_CLKX 0x00F6
+#define ABE_MCBSP2_DR 0x00F8
+#define ABE_MCBSP2_DX 0x00FA
+#define ABE_MCBSP2_FSX 0x00FC
+#define ABE_MCBSP1_CLKX 0x00FE
+#define ABE_MCBSP1_DR 0x0100
+#define ABE_MCBSP1_DX 0x0102
+#define ABE_MCBSP1_FSX 0x0104
+#define ABE_PDM_UL_DATA 0x0106
+#define ABE_PDM_DL_DATA 0x0108
+#define ABE_PDM_FRAME 0x010A
+#define ABE_PDM_LB_CLK 0x010C
+#define ABE_CLKS 0x010E
+#define ABE_DMIC_CLK1 0x0110
+#define ABE_DMIC_DIN1 0x0112
+#define ABE_DMIC_DIN2 0x0114
+#define ABE_DMIC_DIN3 0x0116
+#define UART2_CTS 0x0118
+#define UART2_RTS 0x011A
+#define UART2_RX 0x011C
+#define UART2_TX 0x011E
+#define HDQ_SIO 0x0120
+#define I2C1_SCL 0x0122
+#define I2C1_SDA 0x0124
+#define I2C2_SCL 0x0126
+#define I2C2_SDA 0x0128
+#define I2C3_SCL 0x012A
+#define I2C3_SDA 0x012C
+#define I2C4_SCL 0x012E
+#define I2C4_SDA 0x0130
+#define MCSPI1_CLK 0x0132
+#define MCSPI1_SOMI 0x0134
+#define MCSPI1_SIMO 0x0136
+#define MCSPI1_CS0 0x0138
+#define MCSPI1_CS1 0x013A
+#define MCSPI1_CS2 0x013C
+#define MCSPI1_CS3 0x013E
+#define UART3_CTS_RCTX 0x0140
+#define UART3_RTS_SD 0x0142
+#define UART3_RX_IRRX 0x0144
+#define UART3_TX_IRTX 0x0146
+#define SDMMC5_CLK 0x0148
+#define SDMMC5_CMD 0x014A
+#define SDMMC5_DAT0 0x014C
+#define SDMMC5_DAT1 0x014E
+#define SDMMC5_DAT2 0x0150
+#define SDMMC5_DAT3 0x0152
+#define MCSPI4_CLK 0x0154
+#define MCSPI4_SIMO 0x0156
+#define MCSPI4_SOMI 0x0158
+#define MCSPI4_CS0 0x015A
+#define UART4_RX 0x015C
+#define UART4_TX 0x015E
+#define USBB2_ULPITLL_CLK 0x0160
+#define USBB2_ULPITLL_STP 0x0162
+#define USBB2_ULPITLL_DIR 0x0164
+#define USBB2_ULPITLL_NXT 0x0166
+#define USBB2_ULPITLL_DAT0 0x0168
+#define USBB2_ULPITLL_DAT1 0x016A
+#define USBB2_ULPITLL_DAT2 0x016C
+#define USBB2_ULPITLL_DAT3 0x016E
+#define USBB2_ULPITLL_DAT4 0x0170
+#define USBB2_ULPITLL_DAT5 0x0172
+#define USBB2_ULPITLL_DAT6 0x0174
+#define USBB2_ULPITLL_DAT7 0x0176
+#define USBB2_HSIC_DATA 0x0178
+#define USBB2_HSIC_STROBE 0x017A
+#define UNIPRO_TX0 0x017C
+#define UNIPRO_TY0 0x017E
+#define UNIPRO_TX1 0x0180
+#define UNIPRO_TY1 0x0182
+#define UNIPRO_TX2 0x0184
+#define UNIPRO_TY2 0x0186
+#define UNIPRO_RX0 0x0188
+#define UNIPRO_RY0 0x018A
+#define UNIPRO_RX1 0x018C
+#define UNIPRO_RY1 0x018E
+#define UNIPRO_RX2 0x0190
+#define UNIPRO_RY2 0x0192
+#define USBA0_OTG_CE 0x0194
+#define USBA0_OTG_DP 0x0196
+#define USBA0_OTG_DM 0x0198
+#define FREF_CLK1_OUT 0x019A
+#define FREF_CLK2_OUT 0x019C
+#define SYS_NIRQ1 0x019E
+#define SYS_NIRQ2 0x01A0
+#define SYS_BOOT0 0x01A2
+#define SYS_BOOT1 0x01A4
+#define SYS_BOOT2 0x01A6
+#define SYS_BOOT3 0x01A8
+#define SYS_BOOT4 0x01AA
+#define SYS_BOOT5 0x01AC
+#define DPM_EMU0 0x01AE
+#define DPM_EMU1 0x01B0
+#define DPM_EMU2 0x01B2
+#define DPM_EMU3 0x01B4
+#define DPM_EMU4 0x01B6
+#define DPM_EMU5 0x01B8
+#define DPM_EMU6 0x01BA
+#define DPM_EMU7 0x01BC
+#define DPM_EMU8 0x01BE
+#define DPM_EMU9 0x01C0
+#define DPM_EMU10 0x01C2
+#define DPM_EMU11 0x01C4
+#define DPM_EMU12 0x01C6
+#define DPM_EMU13 0x01C8
+#define DPM_EMU14 0x01CA
+#define DPM_EMU15 0x01CC
+#define DPM_EMU16 0x01CE
+#define DPM_EMU17 0x01D0
+#define DPM_EMU18 0x01D2
+#define DPM_EMU19 0x01D4
+#define WAKEUPEVENT_0 0x01D8
+#define WAKEUPEVENT_1 0x01DC
+#define WAKEUPEVENT_2 0x01E0
+#define WAKEUPEVENT_3 0x01E4
+#define WAKEUPEVENT_4 0x01E8
+#define WAKEUPEVENT_5 0x01EC
+#define WAKEUPEVENT_6 0x01F0
+
+#define WKUP_REVISION 0x0000
+#define WKUP_HWINFO 0x0004
+#define WKUP_SYSCONFIG 0x0010
+#define PAD0_SIM_IO 0x0040
+#define PAD1_SIM_CLK 0x0042
+#define PAD0_SIM_RESET 0x0044
+#define PAD1_SIM_CD 0x0046
+#define PAD0_SIM_PWRCTRL 0x0048
+#define PAD1_SR_SCL 0x004A
+#define PAD0_SR_SDA 0x004C
+#define PAD1_FREF_XTAL_IN 0x004E
+#define PAD0_FREF_SLICER_IN 0x0050
+#define PAD1_FREF_CLK_IOREQ 0x0052
+#define PAD0_FREF_CLK0_OUT 0x0054
+#define PAD1_FREF_CLK3_REQ 0x0056
+#define PAD0_FREF_CLK3_OUT 0x0058
+#define PAD1_FREF_CLK4_REQ 0x005A
+#define PAD0_FREF_CLK4_OUT 0x005C
+#define PAD1_SYS_32K 0x005E
+#define PAD0_SYS_NRESPWRON 0x0060
+#define PAD1_SYS_NRESWARM 0x0062
+#define PAD0_SYS_PWR_REQ 0x0064
+#define PAD1_SYS_PWRON_RESET 0x0066
+#define PAD0_SYS_BOOT6 0x0068
+#define PAD1_SYS_BOOT7 0x006A
+#define PAD0_JTAG_NTRST 0x006C
+#define PAD1_JTAG_TCK 0x006D
+#define PAD0_JTAG_RTCK 0x0070
+#define PAD1_JTAG_TMS_TMSC 0x0072
+#define PAD0_JTAG_TDI 0x0074
+#define PAD1_JTAG_TDO 0x0076
+#define PADCONF_WAKEUPEVENT_0 0x007C
+#define CONTROL_SMART1NOPMIO_PADCONF_0 0x05A0
+#define CONTROL_SMART1NOPMIO_PADCONF_1 0x05A4
+#define PADCONF_MODE 0x05A8
+#define CONTROL_XTAL_OSCILLATOR 0x05AC
+#define CONTROL_CONTROL_I2C_2 0x0604
+#define CONTROL_CONTROL_JTAG 0x0608
+#define CONTROL_CONTROL_SYS 0x060C
+#define CONTROL_SPARE_RW 0x0614
+#define CONTROL_SPARE_R 0x0618
+#define CONTROL_SPARE_R_C0 0x061C
+
+#endif /* _MUX_OMAP5_H_ */
diff --git a/arch/arm/include/asm/arch-omap4/omap4.h b/arch/arm/include/asm/arch-omap5/omap.h
similarity index 65%
copy from arch/arm/include/asm/arch-omap4/omap4.h
copy to arch/arm/include/asm/arch-omap5/omap.h
index 61ebb3d..d811d6e 100644
--- a/arch/arm/include/asm/arch-omap4/omap4.h
+++ b/arch/arm/include/asm/arch-omap5/omap.h
@@ -4,10 +4,7 @@
*
* Authors:
* Aneesh V <aneesh@ti.com>
- *
- * Derived from OMAP3 work by
- * Richard Woodruff <r-woodruff2@ti.com>
- * Syed Mohammed Khasim <x0khasim@ti.com>
+ * Sricharan R <r.sricharan@ti.com>
*
* See file CREDITS for list of people who contributed to this
* project.
@@ -28,8 +25,8 @@
* MA 02111-1307 USA
*/
-#ifndef _OMAP4_H_
-#define _OMAP4_H_
+#ifndef _OMAP5_H_
+#define _OMAP5_H_
#if !(defined(__KERNEL_STRICT_NAMES) || defined(__ASSEMBLY__))
#include <asm/types.h>
@@ -38,54 +35,52 @@
/*
* L4 Peripherals - L4 Wakeup and L4 Core now
*/
-#define OMAP44XX_L4_CORE_BASE 0x4A000000
-#define OMAP44XX_L4_WKUP_BASE 0x4A300000
-#define OMAP44XX_L4_PER_BASE 0x48000000
+#define OMAP54XX_L4_CORE_BASE 0x4A000000
+#define OMAP54XX_L4_WKUP_BASE 0x4Ae00000
+#define OMAP54XX_L4_PER_BASE 0x48000000
-#define OMAP44XX_DRAM_ADDR_SPACE_START 0x80000000
-#define OMAP44XX_DRAM_ADDR_SPACE_END 0xD0000000
-
+#define OMAP54XX_DRAM_ADDR_SPACE_START 0x80000000
+#define OMAP54XX_DRAM_ADDR_SPACE_END 0xD0000000
+#define DRAM_ADDR_SPACE_START OMAP54XX_DRAM_ADDR_SPACE_START
+#define DRAM_ADDR_SPACE_END OMAP54XX_DRAM_ADDR_SPACE_END
/* CONTROL */
-#define CTRL_BASE (OMAP44XX_L4_CORE_BASE + 0x2000)
-#define CONTROL_PADCONF_CORE (OMAP44XX_L4_CORE_BASE + 0x100000)
-#define CONTROL_PADCONF_WKUP (OMAP44XX_L4_CORE_BASE + 0x31E000)
+#define CTRL_BASE (OMAP54XX_L4_CORE_BASE + 0x2000)
+#define CONTROL_PADCONF_CORE (CTRL_BASE + 0x0800)
+#define CONTROL_PADCONF_WKUP (OMAP54XX_L4_WKUP_BASE + 0xc800)
-/* LPDDR2 IO regs */
+/* LPDDR2 IO regs. To be verified */
#define LPDDR2_IO_REGS_BASE 0x4A100638
/* CONTROL_ID_CODE */
-#define CONTROL_ID_CODE 0x4A002204
+#define CONTROL_ID_CODE (CTRL_BASE + 0x204)
-/* 4430 */
-#define OMAP4430_CONTROL_ID_CODE_ES1_0 0x0B85202F
-#define OMAP4430_CONTROL_ID_CODE_ES2_0 0x1B85202F
-#define OMAP4430_CONTROL_ID_CODE_ES2_1 0x3B95C02F
-#define OMAP4430_CONTROL_ID_CODE_ES2_2 0x4B95C02F
-#define OMAP4430_CONTROL_ID_CODE_ES2_3 0x6B95C02F
+/* To be verified */
+#define OMAP5_CONTROL_ID_CODE_ES1_0 0x0B85202F
-/* 4460 */
-#define OMAP4460_CONTROL_ID_CODE_ES1_0 0x0B94E02F
-#define OMAP4460_CONTROL_ID_CODE_ES1_1 0x2B94E02F
+/* STD_FUSE_PROD_ID_1 */
+#define STD_FUSE_PROD_ID_1 (CTRL_BASE + 0x218)
+#define PROD_ID_1_SILICON_TYPE_SHIFT 16
+#define PROD_ID_1_SILICON_TYPE_MASK (3 << 16)
/* UART */
-#define UART1_BASE (OMAP44XX_L4_PER_BASE + 0x6a000)
-#define UART2_BASE (OMAP44XX_L4_PER_BASE + 0x6c000)
-#define UART3_BASE (OMAP44XX_L4_PER_BASE + 0x20000)
+#define UART1_BASE (OMAP54XX_L4_PER_BASE + 0x6a000)
+#define UART2_BASE (OMAP54XX_L4_PER_BASE + 0x6c000)
+#define UART3_BASE (OMAP54XX_L4_PER_BASE + 0x20000)
/* General Purpose Timers */
-#define GPT1_BASE (OMAP44XX_L4_WKUP_BASE + 0x18000)
-#define GPT2_BASE (OMAP44XX_L4_PER_BASE + 0x32000)
-#define GPT3_BASE (OMAP44XX_L4_PER_BASE + 0x34000)
+#define GPT1_BASE (OMAP54XX_L4_WKUP_BASE + 0x18000)
+#define GPT2_BASE (OMAP54XX_L4_PER_BASE + 0x32000)
+#define GPT3_BASE (OMAP54XX_L4_PER_BASE + 0x34000)
/* Watchdog Timer2 - MPU watchdog */
-#define WDT2_BASE (OMAP44XX_L4_WKUP_BASE + 0x14000)
+#define WDT2_BASE (OMAP54XX_L4_WKUP_BASE + 0x14000)
/* 32KTIMER */
-#define SYNC_32KTIMER_BASE (OMAP44XX_L4_WKUP_BASE + 0x4000)
+#define SYNC_32KTIMER_BASE (OMAP54XX_L4_WKUP_BASE + 0x4000)
/* GPMC */
-#define OMAP44XX_GPMC_BASE 0x50000000
+#define OMAP54XX_GPMC_BASE 0x50000000
/* SYSTEM CONTROL MODULE */
#define SYSCTRL_GENERAL_CORE_BASE 0x4A002000
@@ -108,7 +103,7 @@
*/
/* PRM */
-#define PRM_BASE 0x4A306000
+#define PRM_BASE 0x4AE06000
#define PRM_DEVICE_BASE (PRM_BASE + 0x1B00)
#define PRM_RSTCTRL PRM_DEVICE_BASE
@@ -175,18 +170,21 @@
* at 0x40304000(EMU base) so that our code works for both EMU and GP
*/
#define NON_SECURE_SRAM_START 0x40304000
-#define NON_SECURE_SRAM_END 0x4030E000 /* Not inclusive */
+#define NON_SECURE_SRAM_END 0x40320000 /* Not inclusive */
/* base address for indirect vectors (internal boot mode) */
-#define SRAM_ROM_VECT_BASE 0x4030D000
+#define SRAM_ROM_VECT_BASE 0x4031F000
/* Temporary SRAM stack used while low level init is done */
-#define LOW_LEVEL_SRAM_STACK NON_SECURE_SRAM_END
+#define LOW_LEVEL_SRAM_STACK NON_SECURE_SRAM_END
+
#define SRAM_SCRATCH_SPACE_ADDR NON_SECURE_SRAM_START
-/* SRAM scratch space entries */
-#define OMAP4_SRAM_SCRATCH_OMAP4_REV SRAM_SCRATCH_SPACE_ADDR
-#define OMAP4_SRAM_SCRATCH_EMIF_SIZE (SRAM_SCRATCH_SPACE_ADDR + 0x4)
-#define OMAP4_SRAM_SCRATCH_EMIF_T_NUM (SRAM_SCRATCH_SPACE_ADDR + 0xC)
-#define OMAP4_SRAM_SCRATCH_EMIF_T_DEN (SRAM_SCRATCH_SPACE_ADDR + 0x10)
-#define OMAP4_SRAM_SCRATCH_SPACE_END (SRAM_SCRATCH_SPACE_ADDR + 0x14)
+/*
+ * SRAM scratch space entries
+ */
+#define OMAP5_SRAM_SCRATCH_OMAP5_REV SRAM_SCRATCH_SPACE_ADDR
+#define OMAP5_SRAM_SCRATCH_EMIF_SIZE (SRAM_SCRATCH_SPACE_ADDR + 0x4)
+#define OMAP5_SRAM_SCRATCH_EMIF_T_NUM (SRAM_SCRATCH_SPACE_ADDR + 0xC)
+#define OMAP5_SRAM_SCRATCH_EMIF_T_DEN (SRAM_SCRATCH_SPACE_ADDR + 0x10)
+#define OMAP5_SRAM_SCRATCH_SPACE_END (SRAM_SCRATCH_SPACE_ADDR + 0x14)
/* Silicon revisions */
#define OMAP4430_SILICON_ID_INVALID 0xFFFFFFFF
@@ -205,5 +203,21 @@
#define DEV_DESC_PTR_OFFSET 0x4
#define DEV_DATA_PTR_OFFSET 0x18
#define BOOT_MODE_OFFSET 0x8
+#define RESET_REASON_OFFSET 0x9
+#define CH_FLAGS_OFFSET 0xA
+#define CH_FLAGS_CHSETTINGS (0x1 << 0)
+#define CH_FLAGS_CHRAM (0x1 << 1)
+#define CH_FLAGS_CHFLASH (0x1 << 2)
+#define CH_FLAGS_CHMMCSD (0x1 << 3)
+
+#ifndef __ASSEMBLY__
+struct omap_boot_parameters {
+ char *boot_message;
+ unsigned int mem_boot_descriptor;
+ unsigned char omap_bootdevice;
+ unsigned char reset_reason;
+ unsigned char ch_flags;
+};
+#endif /* __ASSEMBLY__ */
#endif
diff --git a/arch/arm/include/asm/arch-omap5/sys_proto.h b/arch/arm/include/asm/arch-omap5/sys_proto.h
new file mode 100644
index 0000000..c31e18c
--- /dev/null
+++ b/arch/arm/include/asm/arch-omap5/sys_proto.h
@@ -0,0 +1,122 @@
+/*
+ * (C) Copyright 2010
+ * Texas Instruments, <www.ti.com>
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#ifndef _SYS_PROTO_H_
+#define _SYS_PROTO_H_
+
+#include <asm/arch/omap.h>
+#include <asm/io.h>
+#include <asm/arch/clocks.h>
+#include <asm/omap_common.h>
+#include <asm/arch/mux_omap5.h>
+#include <asm/arch/clocks.h>
+
+struct omap_sysinfo {
+ char *board_string;
+};
+extern const struct omap_sysinfo sysinfo;
+
+void gpmc_init(void);
+void watchdog_init(void);
+u32 get_device_type(void);
+void do_set_mux(u32 base, struct pad_conf_entry const *array, int size);
+void set_muxconf_regs_essential(void);
+void set_muxconf_regs_non_essential(void);
+void sr32(void *, u32, u32, u32);
+u32 wait_on_value(u32, u32, void *, u32);
+void sdelay(unsigned long);
+void omap_rev_string(char *omap_rev_string);
+void setup_clocks_for_console(void);
+void prcm_init(void);
+void bypass_dpll(u32 *const base);
+void freq_update_core(void);
+u32 get_sys_clk_freq(void);
+u32 omap5_ddr_clk(void);
+void cancel_out(u32 *num, u32 *den, u32 den_limit);
+void sdram_init(void);
+u32 omap_sdram_size(void);
+u32 cortex_rev(void);
+void init_omap_revision(void);
+void do_io_settings(void);
+
+/*
+ * This is used to verify if the configuration header
+ * was executed by Romcode prior to control of transfer
+ * to the bootloader. SPL is responsible for saving and
+ * passing this to the u-boot.
+ */
+extern struct omap_boot_parameters boot_params;
+
+static inline u32 running_from_sdram(void)
+{
+ u32 pc;
+ asm volatile ("mov %0, pc" : "=r" (pc));
+ return ((pc >= OMAP54XX_DRAM_ADDR_SPACE_START) &&
+ (pc < OMAP54XX_DRAM_ADDR_SPACE_END));
+}
+
+static inline u8 uboot_loaded_by_spl(void)
+{
+ /*
+ * u-boot can be running from sdram either because of configuration
+ * Header or by SPL. If because of CH, then the romcode sets the
+ * CHSETTINGS executed bit to true in the boot parameter structure that
+ * it passes to the bootloader.This parameter is stored in the ch_flags
+ * variable by both SPL and u-boot.Check out for CHSETTINGS, which is a
+ * mandatory section if CH is present.
+ */
+ if ((boot_params.ch_flags) & (CH_FLAGS_CHSETTINGS))
+ return 0;
+ else
+ return running_from_sdram();
+}
+/*
+ * The basic hardware init of OMAP(s_init()) can happen in 4
+ * different contexts:
+ * 1. SPL running from SRAM
+ * 2. U-Boot running from FLASH
+ * 3. Non-XIP U-Boot loaded to SDRAM by SPL
+ * 4. Non-XIP U-Boot loaded to SDRAM by ROM code using the
+ * Configuration Header feature
+ *
+ * This function finds this context.
+ * Defining as inline may help in compiling out unused functions in SPL
+ */
+static inline u32 omap_hw_init_context(void)
+{
+#ifdef CONFIG_SPL_BUILD
+ return OMAP_INIT_CONTEXT_SPL;
+#else
+ if (uboot_loaded_by_spl())
+ return OMAP_INIT_CONTEXT_UBOOT_AFTER_SPL;
+ else if (running_from_sdram())
+ return OMAP_INIT_CONTEXT_UBOOT_AFTER_CH;
+ else
+ return OMAP_INIT_CONTEXT_UBOOT_FROM_NOR;
+#endif
+}
+
+static inline u32 omap_revision(void)
+{
+ extern u32 *const omap5_revision;
+ return *omap5_revision;
+}
+
+#endif
diff --git a/arch/arm/include/asm/arch-pxa/pxa-regs.h b/arch/arm/include/asm/arch-pxa/pxa-regs.h
index 109fdc0..52c79a9 100644
--- a/arch/arm/include/asm/arch-pxa/pxa-regs.h
+++ b/arch/arm/include/asm/arch-pxa/pxa-regs.h
@@ -315,117 +315,6 @@
/******************************************************************************/
/*
- * UARTs
- */
-/* Full Function UART (FFUART) */
-#define FFUART FFRBR
-#define FFRBR 0x40100000 /* Receive Buffer Register (read only) */
-#define FFTHR 0x40100000 /* Transmit Holding Register (write only) */
-#define FFIER 0x40100004 /* Interrupt Enable Register (read/write) */
-#define FFIIR 0x40100008 /* Interrupt ID Register (read only) */
-#define FFFCR 0x40100008 /* FIFO Control Register (write only) */
-#define FFLCR 0x4010000C /* Line Control Register (read/write) */
-#define FFMCR 0x40100010 /* Modem Control Register (read/write) */
-#define FFLSR 0x40100014 /* Line Status Register (read only) */
-#define FFMSR 0x40100018 /* Modem Status Register (read only) */
-#define FFSPR 0x4010001C /* Scratch Pad Register (read/write) */
-#define FFISR 0x40100020 /* Infrared Selection Register (read/write) */
-#define FFDLL 0x40100000 /* Divisor Latch Low Register (DLAB = 1) (read/write) */
-#define FFDLH 0x40100004 /* Divisor Latch High Register (DLAB = 1) (read/write) */
-
-/* Bluetooth UART (BTUART) */
-#define BTUART BTRBR
-#define BTRBR 0x40200000 /* Receive Buffer Register (read only) */
-#define BTTHR 0x40200000 /* Transmit Holding Register (write only) */
-#define BTIER 0x40200004 /* Interrupt Enable Register (read/write) */
-#define BTIIR 0x40200008 /* Interrupt ID Register (read only) */
-#define BTFCR 0x40200008 /* FIFO Control Register (write only) */
-#define BTLCR 0x4020000C /* Line Control Register (read/write) */
-#define BTMCR 0x40200010 /* Modem Control Register (read/write) */
-#define BTLSR 0x40200014 /* Line Status Register (read only) */
-#define BTMSR 0x40200018 /* Modem Status Register (read only) */
-#define BTSPR 0x4020001C /* Scratch Pad Register (read/write) */
-#define BTISR 0x40200020 /* Infrared Selection Register (read/write) */
-#define BTDLL 0x40200000 /* Divisor Latch Low Register (DLAB = 1) (read/write) */
-#define BTDLH 0x40200004 /* Divisor Latch High Register (DLAB = 1) (read/write) */
-
-/* Standard UART (STUART) */
-#define STUART STRBR
-#define STRBR 0x40700000 /* Receive Buffer Register (read only) */
-#define STTHR 0x40700000 /* Transmit Holding Register (write only) */
-#define STIER 0x40700004 /* Interrupt Enable Register (read/write) */
-#define STIIR 0x40700008 /* Interrupt ID Register (read only) */
-#define STFCR 0x40700008 /* FIFO Control Register (write only) */
-#define STLCR 0x4070000C /* Line Control Register (read/write) */
-#define STMCR 0x40700010 /* Modem Control Register (read/write) */
-#define STLSR 0x40700014 /* Line Status Register (read only) */
-#define STMSR 0x40700018 /* Reserved */
-#define STSPR 0x4070001C /* Scratch Pad Register (read/write) */
-#define STISR 0x40700020 /* Infrared Selection Register (read/write) */
-#define STDLL 0x40700000 /* Divisor Latch Low Register (DLAB = 1) (read/write) */
-#define STDLH 0x40700004 /* Divisor Latch High Register (DLAB = 1) (read/write) */
-
-#define IER_DMAE (1 << 7) /* DMA Requests Enable */
-#define IER_UUE (1 << 6) /* UART Unit Enable */
-#define IER_NRZE (1 << 5) /* NRZ coding Enable */
-#define IER_RTIOE (1 << 4) /* Receiver Time Out Interrupt Enable */
-#define IER_MIE (1 << 3) /* Modem Interrupt Enable */
-#define IER_RLSE (1 << 2) /* Receiver Line Status Interrupt Enable */
-#define IER_TIE (1 << 1) /* Transmit Data request Interrupt Enable */
-#define IER_RAVIE (1 << 0) /* Receiver Data Available Interrupt Enable */
-
-#define IIR_FIFOES1 (1 << 7) /* FIFO Mode Enable Status */
-#define IIR_FIFOES0 (1 << 6) /* FIFO Mode Enable Status */
-#define IIR_TOD (1 << 3) /* Time Out Detected */
-#define IIR_IID2 (1 << 2) /* Interrupt Source Encoded */
-#define IIR_IID1 (1 << 1) /* Interrupt Source Encoded */
-#define IIR_IP (1 << 0) /* Interrupt Pending (active low) */
-
-#define FCR_ITL2 (1 << 7) /* Interrupt Trigger Level */
-#define FCR_ITL1 (1 << 6) /* Interrupt Trigger Level */
-#define FCR_RESETTF (1 << 2) /* Reset Transmitter FIFO */
-#define FCR_RESETRF (1 << 1) /* Reset Receiver FIFO */
-#define FCR_TRFIFOE (1 << 0) /* Transmit and Receive FIFO Enable */
-#define FCR_ITL_1 (0)
-#define FCR_ITL_8 (FCR_ITL1)
-#define FCR_ITL_16 (FCR_ITL2)
-#define FCR_ITL_32 (FCR_ITL2|FCR_ITL1)
-
-#define LCR_DLAB (1 << 7) /* Divisor Latch Access Bit */
-#define LCR_SB (1 << 6) /* Set Break */
-#define LCR_STKYP (1 << 5) /* Sticky Parity */
-#define LCR_EPS (1 << 4) /* Even Parity Select */
-#define LCR_PEN (1 << 3) /* Parity Enable */
-#define LCR_STB (1 << 2) /* Stop Bit */
-#define LCR_WLS1 (1 << 1) /* Word Length Select */
-#define LCR_WLS0 (1 << 0) /* Word Length Select */
-
-#define LSR_FIFOE (1 << 7) /* FIFO Error Status */
-#define LSR_TEMT (1 << 6) /* Transmitter Empty */
-#define LSR_TDRQ (1 << 5) /* Transmit Data Request */
-#define LSR_BI (1 << 4) /* Break Interrupt */
-#define LSR_FE (1 << 3) /* Framing Error */
-#define LSR_PE (1 << 2) /* Parity Error */
-#define LSR_OE (1 << 1) /* Overrun Error */
-#define LSR_DR (1 << 0) /* Data Ready */
-
-#define MCR_LOOP (1 << 4) /* */
-#define MCR_OUT2 (1 << 3) /* force MSR_DCD in loopback mode */
-#define MCR_OUT1 (1 << 2) /* force MSR_RI in loopback mode */
-#define MCR_RTS (1 << 1) /* Request to Send */
-#define MCR_DTR (1 << 0) /* Data Terminal Ready */
-
-#define MSR_DCD (1 << 7) /* Data Carrier Detect */
-#define MSR_RI (1 << 6) /* Ring Indicator */
-#define MSR_DSR (1 << 5) /* Data Set Ready */
-#define MSR_CTS (1 << 4) /* Clear To Send */
-#define MSR_DDCD (1 << 3) /* Delta Data Carrier Detect */
-#define MSR_TERI (1 << 2) /* Trailing Edge Ring Indicator */
-#define MSR_DDSR (1 << 1) /* Delta Data Set Ready */
-#define MSR_DCTS (1 << 0) /* Delta Clear To Send */
-
-/******************************************************************************/
-/*
* IrSR (Infrared Selection Register)
*/
#define IrSR_OFFSET 0x20
diff --git a/arch/arm/include/asm/arch-pxa/regs-uart.h b/arch/arm/include/asm/arch-pxa/regs-uart.h
new file mode 100644
index 0000000..355e892
--- /dev/null
+++ b/arch/arm/include/asm/arch-pxa/regs-uart.h
@@ -0,0 +1,109 @@
+/*
+ * Copyright (C) 2011 Marek Vasut <marek.vasut@gmail.com>
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#ifndef __REGS_UART_H__
+#define __REGS_UART_H__
+
+#define FFUART_BASE 0x40100000
+#define BTUART_BASE 0x40200000
+#define STUART_BASE 0x40700000
+#define HWUART_BASE 0x41600000
+
+struct pxa_uart_regs {
+ union {
+ uint32_t thr;
+ uint32_t rbr;
+ uint32_t dll;
+ };
+ union {
+ uint32_t ier;
+ uint32_t dlh;
+ };
+ union {
+ uint32_t fcr;
+ uint32_t iir;
+ };
+ uint32_t lcr;
+ uint32_t mcr;
+ uint32_t lsr;
+ uint32_t msr;
+ uint32_t spr;
+ uint32_t isr;
+};
+
+#define IER_DMAE (1 << 7)
+#define IER_UUE (1 << 6)
+#define IER_NRZE (1 << 5)
+#define IER_RTIOE (1 << 4)
+#define IER_MIE (1 << 3)
+#define IER_RLSE (1 << 2)
+#define IER_TIE (1 << 1)
+#define IER_RAVIE (1 << 0)
+
+#define IIR_FIFOES1 (1 << 7)
+#define IIR_FIFOES0 (1 << 6)
+#define IIR_TOD (1 << 3)
+#define IIR_IID2 (1 << 2)
+#define IIR_IID1 (1 << 1)
+#define IIR_IP (1 << 0)
+
+#define FCR_ITL2 (1 << 7)
+#define FCR_ITL1 (1 << 6)
+#define FCR_RESETTF (1 << 2)
+#define FCR_RESETRF (1 << 1)
+#define FCR_TRFIFOE (1 << 0)
+#define FCR_ITL_1 0
+#define FCR_ITL_8 (FCR_ITL1)
+#define FCR_ITL_16 (FCR_ITL2)
+#define FCR_ITL_32 (FCR_ITL2|FCR_ITL1)
+
+#define LCR_DLAB (1 << 7)
+#define LCR_SB (1 << 6)
+#define LCR_STKYP (1 << 5)
+#define LCR_EPS (1 << 4)
+#define LCR_PEN (1 << 3)
+#define LCR_STB (1 << 2)
+#define LCR_WLS1 (1 << 1)
+#define LCR_WLS0 (1 << 0)
+
+#define LSR_FIFOE (1 << 7)
+#define LSR_TEMT (1 << 6)
+#define LSR_TDRQ (1 << 5)
+#define LSR_BI (1 << 4)
+#define LSR_FE (1 << 3)
+#define LSR_PE (1 << 2)
+#define LSR_OE (1 << 1)
+#define LSR_DR (1 << 0)
+
+#define MCR_LOOP (1 << 4)
+#define MCR_OUT2 (1 << 3)
+#define MCR_OUT1 (1 << 2)
+#define MCR_RTS (1 << 1)
+#define MCR_DTR (1 << 0)
+
+#define MSR_DCD (1 << 7)
+#define MSR_RI (1 << 6)
+#define MSR_DSR (1 << 5)
+#define MSR_CTS (1 << 4)
+#define MSR_DDCD (1 << 3)
+#define MSR_TERI (1 << 2)
+#define MSR_DDSR (1 << 1)
+#define MSR_DCTS (1 << 0)
+
+#endif /* __REGS_UART_H__ */
diff --git a/arch/arm/include/asm/armv7.h b/arch/arm/include/asm/armv7.h
index 9adc563..ad9a875 100644
--- a/arch/arm/include/asm/armv7.h
+++ b/arch/arm/include/asm/armv7.h
@@ -31,6 +31,9 @@
#define MIDR_CORTEX_A9_R1P3 0x411FC093
#define MIDR_CORTEX_A9_R2P10 0x412FC09A
+/* Cortex-A15 revisions */
+#define MIDR_CORTEX_A15_R0P0 0x410FC0F0
+
/* CCSIDR */
#define CCSIDR_LINE_SIZE_OFFSET 0
#define CCSIDR_LINE_SIZE_MASK 0x7
diff --git a/arch/arm/include/asm/emif.h b/arch/arm/include/asm/emif.h
new file mode 100644
index 0000000..e5c7d2c
--- /dev/null
+++ b/arch/arm/include/asm/emif.h
@@ -0,0 +1,1035 @@
+/*
+ * OMAP44xx EMIF header
+ *
+ * Copyright (C) 2009-2010 Texas Instruments, Inc.
+ *
+ * Aneesh V <aneesh@ti.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#ifndef _EMIF_H_
+#define _EMIF_H_
+#include <asm/types.h>
+#include <common.h>
+
+/* Base address */
+#define EMIF1_BASE 0x4c000000
+#define EMIF2_BASE 0x4d000000
+
+/* Registers shifts and masks */
+
+/* EMIF_MOD_ID_REV */
+#define EMIF_REG_SCHEME_SHIFT 30
+#define EMIF_REG_SCHEME_MASK (0x3 << 30)
+#define EMIF_REG_MODULE_ID_SHIFT 16
+#define EMIF_REG_MODULE_ID_MASK (0xfff << 16)
+#define EMIF_REG_RTL_VERSION_SHIFT 11
+#define EMIF_REG_RTL_VERSION_MASK (0x1f << 11)
+#define EMIF_REG_MAJOR_REVISION_SHIFT 8
+#define EMIF_REG_MAJOR_REVISION_MASK (0x7 << 8)
+#define EMIF_REG_MINOR_REVISION_SHIFT 0
+#define EMIF_REG_MINOR_REVISION_MASK (0x3f << 0)
+
+/* STATUS */
+#define EMIF_REG_BE_SHIFT 31
+#define EMIF_REG_BE_MASK (1 << 31)
+#define EMIF_REG_DUAL_CLK_MODE_SHIFT 30
+#define EMIF_REG_DUAL_CLK_MODE_MASK (1 << 30)
+#define EMIF_REG_FAST_INIT_SHIFT 29
+#define EMIF_REG_FAST_INIT_MASK (1 << 29)
+#define EMIF_REG_PHY_DLL_READY_SHIFT 2
+#define EMIF_REG_PHY_DLL_READY_MASK (1 << 2)
+
+/* SDRAM_CONFIG */
+#define EMIF_REG_SDRAM_TYPE_SHIFT 29
+#define EMIF_REG_SDRAM_TYPE_MASK (0x7 << 29)
+#define EMIF_REG_IBANK_POS_SHIFT 27
+#define EMIF_REG_IBANK_POS_MASK (0x3 << 27)
+#define EMIF_REG_DDR_TERM_SHIFT 24
+#define EMIF_REG_DDR_TERM_MASK (0x7 << 24)
+#define EMIF_REG_DDR2_DDQS_SHIFT 23
+#define EMIF_REG_DDR2_DDQS_MASK (1 << 23)
+#define EMIF_REG_DYN_ODT_SHIFT 21
+#define EMIF_REG_DYN_ODT_MASK (0x3 << 21)
+#define EMIF_REG_DDR_DISABLE_DLL_SHIFT 20
+#define EMIF_REG_DDR_DISABLE_DLL_MASK (1 << 20)
+#define EMIF_REG_SDRAM_DRIVE_SHIFT 18
+#define EMIF_REG_SDRAM_DRIVE_MASK (0x3 << 18)
+#define EMIF_REG_CWL_SHIFT 16
+#define EMIF_REG_CWL_MASK (0x3 << 16)
+#define EMIF_REG_NARROW_MODE_SHIFT 14
+#define EMIF_REG_NARROW_MODE_MASK (0x3 << 14)
+#define EMIF_REG_CL_SHIFT 10
+#define EMIF_REG_CL_MASK (0xf << 10)
+#define EMIF_REG_ROWSIZE_SHIFT 7
+#define EMIF_REG_ROWSIZE_MASK (0x7 << 7)
+#define EMIF_REG_IBANK_SHIFT 4
+#define EMIF_REG_IBANK_MASK (0x7 << 4)
+#define EMIF_REG_EBANK_SHIFT 3
+#define EMIF_REG_EBANK_MASK (1 << 3)
+#define EMIF_REG_PAGESIZE_SHIFT 0
+#define EMIF_REG_PAGESIZE_MASK (0x7 << 0)
+
+/* SDRAM_CONFIG_2 */
+#define EMIF_REG_CS1NVMEN_SHIFT 30
+#define EMIF_REG_CS1NVMEN_MASK (1 << 30)
+#define EMIF_REG_EBANK_POS_SHIFT 27
+#define EMIF_REG_EBANK_POS_MASK (1 << 27)
+#define EMIF_REG_RDBNUM_SHIFT 4
+#define EMIF_REG_RDBNUM_MASK (0x3 << 4)
+#define EMIF_REG_RDBSIZE_SHIFT 0
+#define EMIF_REG_RDBSIZE_MASK (0x7 << 0)
+
+/* SDRAM_REF_CTRL */
+#define EMIF_REG_INITREF_DIS_SHIFT 31
+#define EMIF_REG_INITREF_DIS_MASK (1 << 31)
+#define EMIF_REG_SRT_SHIFT 29
+#define EMIF_REG_SRT_MASK (1 << 29)
+#define EMIF_REG_ASR_SHIFT 28
+#define EMIF_REG_ASR_MASK (1 << 28)
+#define EMIF_REG_PASR_SHIFT 24
+#define EMIF_REG_PASR_MASK (0x7 << 24)
+#define EMIF_REG_REFRESH_RATE_SHIFT 0
+#define EMIF_REG_REFRESH_RATE_MASK (0xffff << 0)
+
+/* SDRAM_REF_CTRL_SHDW */
+#define EMIF_REG_REFRESH_RATE_SHDW_SHIFT 0
+#define EMIF_REG_REFRESH_RATE_SHDW_MASK (0xffff << 0)
+
+/* SDRAM_TIM_1 */
+#define EMIF_REG_T_RP_SHIFT 25
+#define EMIF_REG_T_RP_MASK (0xf << 25)
+#define EMIF_REG_T_RCD_SHIFT 21
+#define EMIF_REG_T_RCD_MASK (0xf << 21)
+#define EMIF_REG_T_WR_SHIFT 17
+#define EMIF_REG_T_WR_MASK (0xf << 17)
+#define EMIF_REG_T_RAS_SHIFT 12
+#define EMIF_REG_T_RAS_MASK (0x1f << 12)
+#define EMIF_REG_T_RC_SHIFT 6
+#define EMIF_REG_T_RC_MASK (0x3f << 6)
+#define EMIF_REG_T_RRD_SHIFT 3
+#define EMIF_REG_T_RRD_MASK (0x7 << 3)
+#define EMIF_REG_T_WTR_SHIFT 0
+#define EMIF_REG_T_WTR_MASK (0x7 << 0)
+
+/* SDRAM_TIM_1_SHDW */
+#define EMIF_REG_T_RP_SHDW_SHIFT 25
+#define EMIF_REG_T_RP_SHDW_MASK (0xf << 25)
+#define EMIF_REG_T_RCD_SHDW_SHIFT 21
+#define EMIF_REG_T_RCD_SHDW_MASK (0xf << 21)
+#define EMIF_REG_T_WR_SHDW_SHIFT 17
+#define EMIF_REG_T_WR_SHDW_MASK (0xf << 17)
+#define EMIF_REG_T_RAS_SHDW_SHIFT 12
+#define EMIF_REG_T_RAS_SHDW_MASK (0x1f << 12)
+#define EMIF_REG_T_RC_SHDW_SHIFT 6
+#define EMIF_REG_T_RC_SHDW_MASK (0x3f << 6)
+#define EMIF_REG_T_RRD_SHDW_SHIFT 3
+#define EMIF_REG_T_RRD_SHDW_MASK (0x7 << 3)
+#define EMIF_REG_T_WTR_SHDW_SHIFT 0
+#define EMIF_REG_T_WTR_SHDW_MASK (0x7 << 0)
+
+/* SDRAM_TIM_2 */
+#define EMIF_REG_T_XP_SHIFT 28
+#define EMIF_REG_T_XP_MASK (0x7 << 28)
+#define EMIF_REG_T_ODT_SHIFT 25
+#define EMIF_REG_T_ODT_MASK (0x7 << 25)
+#define EMIF_REG_T_XSNR_SHIFT 16
+#define EMIF_REG_T_XSNR_MASK (0x1ff << 16)
+#define EMIF_REG_T_XSRD_SHIFT 6
+#define EMIF_REG_T_XSRD_MASK (0x3ff << 6)
+#define EMIF_REG_T_RTP_SHIFT 3
+#define EMIF_REG_T_RTP_MASK (0x7 << 3)
+#define EMIF_REG_T_CKE_SHIFT 0
+#define EMIF_REG_T_CKE_MASK (0x7 << 0)
+
+/* SDRAM_TIM_2_SHDW */
+#define EMIF_REG_T_XP_SHDW_SHIFT 28
+#define EMIF_REG_T_XP_SHDW_MASK (0x7 << 28)
+#define EMIF_REG_T_ODT_SHDW_SHIFT 25
+#define EMIF_REG_T_ODT_SHDW_MASK (0x7 << 25)
+#define EMIF_REG_T_XSNR_SHDW_SHIFT 16
+#define EMIF_REG_T_XSNR_SHDW_MASK (0x1ff << 16)
+#define EMIF_REG_T_XSRD_SHDW_SHIFT 6
+#define EMIF_REG_T_XSRD_SHDW_MASK (0x3ff << 6)
+#define EMIF_REG_T_RTP_SHDW_SHIFT 3
+#define EMIF_REG_T_RTP_SHDW_MASK (0x7 << 3)
+#define EMIF_REG_T_CKE_SHDW_SHIFT 0
+#define EMIF_REG_T_CKE_SHDW_MASK (0x7 << 0)
+
+/* SDRAM_TIM_3 */
+#define EMIF_REG_T_CKESR_SHIFT 21
+#define EMIF_REG_T_CKESR_MASK (0x7 << 21)
+#define EMIF_REG_ZQ_ZQCS_SHIFT 15
+#define EMIF_REG_ZQ_ZQCS_MASK (0x3f << 15)
+#define EMIF_REG_T_TDQSCKMAX_SHIFT 13
+#define EMIF_REG_T_TDQSCKMAX_MASK (0x3 << 13)
+#define EMIF_REG_T_RFC_SHIFT 4
+#define EMIF_REG_T_RFC_MASK (0x1ff << 4)
+#define EMIF_REG_T_RAS_MAX_SHIFT 0
+#define EMIF_REG_T_RAS_MAX_MASK (0xf << 0)
+
+/* SDRAM_TIM_3_SHDW */
+#define EMIF_REG_T_CKESR_SHDW_SHIFT 21
+#define EMIF_REG_T_CKESR_SHDW_MASK (0x7 << 21)
+#define EMIF_REG_ZQ_ZQCS_SHDW_SHIFT 15
+#define EMIF_REG_ZQ_ZQCS_SHDW_MASK (0x3f << 15)
+#define EMIF_REG_T_TDQSCKMAX_SHDW_SHIFT 13
+#define EMIF_REG_T_TDQSCKMAX_SHDW_MASK (0x3 << 13)
+#define EMIF_REG_T_RFC_SHDW_SHIFT 4
+#define EMIF_REG_T_RFC_SHDW_MASK (0x1ff << 4)
+#define EMIF_REG_T_RAS_MAX_SHDW_SHIFT 0
+#define EMIF_REG_T_RAS_MAX_SHDW_MASK (0xf << 0)
+
+/* LPDDR2_NVM_TIM */
+#define EMIF_REG_NVM_T_XP_SHIFT 28
+#define EMIF_REG_NVM_T_XP_MASK (0x7 << 28)
+#define EMIF_REG_NVM_T_WTR_SHIFT 24
+#define EMIF_REG_NVM_T_WTR_MASK (0x7 << 24)
+#define EMIF_REG_NVM_T_RP_SHIFT 20
+#define EMIF_REG_NVM_T_RP_MASK (0xf << 20)
+#define EMIF_REG_NVM_T_WRA_SHIFT 16
+#define EMIF_REG_NVM_T_WRA_MASK (0xf << 16)
+#define EMIF_REG_NVM_T_RRD_SHIFT 8
+#define EMIF_REG_NVM_T_RRD_MASK (0xff << 8)
+#define EMIF_REG_NVM_T_RCDMIN_SHIFT 0
+#define EMIF_REG_NVM_T_RCDMIN_MASK (0xff << 0)
+
+/* LPDDR2_NVM_TIM_SHDW */
+#define EMIF_REG_NVM_T_XP_SHDW_SHIFT 28
+#define EMIF_REG_NVM_T_XP_SHDW_MASK (0x7 << 28)
+#define EMIF_REG_NVM_T_WTR_SHDW_SHIFT 24
+#define EMIF_REG_NVM_T_WTR_SHDW_MASK (0x7 << 24)
+#define EMIF_REG_NVM_T_RP_SHDW_SHIFT 20
+#define EMIF_REG_NVM_T_RP_SHDW_MASK (0xf << 20)
+#define EMIF_REG_NVM_T_WRA_SHDW_SHIFT 16
+#define EMIF_REG_NVM_T_WRA_SHDW_MASK (0xf << 16)
+#define EMIF_REG_NVM_T_RRD_SHDW_SHIFT 8
+#define EMIF_REG_NVM_T_RRD_SHDW_MASK (0xff << 8)
+#define EMIF_REG_NVM_T_RCDMIN_SHDW_SHIFT 0
+#define EMIF_REG_NVM_T_RCDMIN_SHDW_MASK (0xff << 0)
+
+/* PWR_MGMT_CTRL */
+#define EMIF_REG_IDLEMODE_SHIFT 30
+#define EMIF_REG_IDLEMODE_MASK (0x3 << 30)
+#define EMIF_REG_PD_TIM_SHIFT 12
+#define EMIF_REG_PD_TIM_MASK (0xf << 12)
+#define EMIF_REG_DPD_EN_SHIFT 11
+#define EMIF_REG_DPD_EN_MASK (1 << 11)
+#define EMIF_REG_LP_MODE_SHIFT 8
+#define EMIF_REG_LP_MODE_MASK (0x7 << 8)
+#define EMIF_REG_SR_TIM_SHIFT 4
+#define EMIF_REG_SR_TIM_MASK (0xf << 4)
+#define EMIF_REG_CS_TIM_SHIFT 0
+#define EMIF_REG_CS_TIM_MASK (0xf << 0)
+
+/* PWR_MGMT_CTRL_SHDW */
+#define EMIF_REG_PD_TIM_SHDW_SHIFT 8
+#define EMIF_REG_PD_TIM_SHDW_MASK (0xf << 8)
+#define EMIF_REG_SR_TIM_SHDW_SHIFT 4
+#define EMIF_REG_SR_TIM_SHDW_MASK (0xf << 4)
+#define EMIF_REG_CS_TIM_SHDW_SHIFT 0
+#define EMIF_REG_CS_TIM_SHDW_MASK (0xf << 0)
+
+/* LPDDR2_MODE_REG_DATA */
+#define EMIF_REG_VALUE_0_SHIFT 0
+#define EMIF_REG_VALUE_0_MASK (0x7f << 0)
+
+/* LPDDR2_MODE_REG_CFG */
+#define EMIF_REG_CS_SHIFT 31
+#define EMIF_REG_CS_MASK (1 << 31)
+#define EMIF_REG_REFRESH_EN_SHIFT 30
+#define EMIF_REG_REFRESH_EN_MASK (1 << 30)
+#define EMIF_REG_ADDRESS_SHIFT 0
+#define EMIF_REG_ADDRESS_MASK (0xff << 0)
+
+/* OCP_CONFIG */
+#define EMIF_REG_SYS_THRESH_MAX_SHIFT 24
+#define EMIF_REG_SYS_THRESH_MAX_MASK (0xf << 24)
+#define EMIF_REG_MPU_THRESH_MAX_SHIFT 20
+#define EMIF_REG_MPU_THRESH_MAX_MASK (0xf << 20)
+#define EMIF_REG_LL_THRESH_MAX_SHIFT 16
+#define EMIF_REG_LL_THRESH_MAX_MASK (0xf << 16)
+#define EMIF_REG_PR_OLD_COUNT_SHIFT 0
+#define EMIF_REG_PR_OLD_COUNT_MASK (0xff << 0)
+
+/* OCP_CFG_VAL_1 */
+#define EMIF_REG_SYS_BUS_WIDTH_SHIFT 30
+#define EMIF_REG_SYS_BUS_WIDTH_MASK (0x3 << 30)
+#define EMIF_REG_LL_BUS_WIDTH_SHIFT 28
+#define EMIF_REG_LL_BUS_WIDTH_MASK (0x3 << 28)
+#define EMIF_REG_WR_FIFO_DEPTH_SHIFT 8
+#define EMIF_REG_WR_FIFO_DEPTH_MASK (0xff << 8)
+#define EMIF_REG_CMD_FIFO_DEPTH_SHIFT 0
+#define EMIF_REG_CMD_FIFO_DEPTH_MASK (0xff << 0)
+
+/* OCP_CFG_VAL_2 */
+#define EMIF_REG_RREG_FIFO_DEPTH_SHIFT 16
+#define EMIF_REG_RREG_FIFO_DEPTH_MASK (0xff << 16)
+#define EMIF_REG_RSD_FIFO_DEPTH_SHIFT 8
+#define EMIF_REG_RSD_FIFO_DEPTH_MASK (0xff << 8)
+#define EMIF_REG_RCMD_FIFO_DEPTH_SHIFT 0
+#define EMIF_REG_RCMD_FIFO_DEPTH_MASK (0xff << 0)
+
+/* IODFT_TLGC */
+#define EMIF_REG_TLEC_SHIFT 16
+#define EMIF_REG_TLEC_MASK (0xffff << 16)
+#define EMIF_REG_MT_SHIFT 14
+#define EMIF_REG_MT_MASK (1 << 14)
+#define EMIF_REG_ACT_CAP_EN_SHIFT 13
+#define EMIF_REG_ACT_CAP_EN_MASK (1 << 13)
+#define EMIF_REG_OPG_LD_SHIFT 12
+#define EMIF_REG_OPG_LD_MASK (1 << 12)
+#define EMIF_REG_RESET_PHY_SHIFT 10
+#define EMIF_REG_RESET_PHY_MASK (1 << 10)
+#define EMIF_REG_MMS_SHIFT 8
+#define EMIF_REG_MMS_MASK (1 << 8)
+#define EMIF_REG_MC_SHIFT 4
+#define EMIF_REG_MC_MASK (0x3 << 4)
+#define EMIF_REG_PC_SHIFT 1
+#define EMIF_REG_PC_MASK (0x7 << 1)
+#define EMIF_REG_TM_SHIFT 0
+#define EMIF_REG_TM_MASK (1 << 0)
+
+/* IODFT_CTRL_MISR_RSLT */
+#define EMIF_REG_DQM_TLMR_SHIFT 16
+#define EMIF_REG_DQM_TLMR_MASK (0x3ff << 16)
+#define EMIF_REG_CTL_TLMR_SHIFT 0
+#define EMIF_REG_CTL_TLMR_MASK (0x7ff << 0)
+
+/* IODFT_ADDR_MISR_RSLT */
+#define EMIF_REG_ADDR_TLMR_SHIFT 0
+#define EMIF_REG_ADDR_TLMR_MASK (0x1fffff << 0)
+
+/* IODFT_DATA_MISR_RSLT_1 */
+#define EMIF_REG_DATA_TLMR_31_0_SHIFT 0
+#define EMIF_REG_DATA_TLMR_31_0_MASK (0xffffffff << 0)
+
+/* IODFT_DATA_MISR_RSLT_2 */
+#define EMIF_REG_DATA_TLMR_63_32_SHIFT 0
+#define EMIF_REG_DATA_TLMR_63_32_MASK (0xffffffff << 0)
+
+/* IODFT_DATA_MISR_RSLT_3 */
+#define EMIF_REG_DATA_TLMR_66_64_SHIFT 0
+#define EMIF_REG_DATA_TLMR_66_64_MASK (0x7 << 0)
+
+/* PERF_CNT_1 */
+#define EMIF_REG_COUNTER1_SHIFT 0
+#define EMIF_REG_COUNTER1_MASK (0xffffffff << 0)
+
+/* PERF_CNT_2 */
+#define EMIF_REG_COUNTER2_SHIFT 0
+#define EMIF_REG_COUNTER2_MASK (0xffffffff << 0)
+
+/* PERF_CNT_CFG */
+#define EMIF_REG_CNTR2_MCONNID_EN_SHIFT 31
+#define EMIF_REG_CNTR2_MCONNID_EN_MASK (1 << 31)
+#define EMIF_REG_CNTR2_REGION_EN_SHIFT 30
+#define EMIF_REG_CNTR2_REGION_EN_MASK (1 << 30)
+#define EMIF_REG_CNTR2_CFG_SHIFT 16
+#define EMIF_REG_CNTR2_CFG_MASK (0xf << 16)
+#define EMIF_REG_CNTR1_MCONNID_EN_SHIFT 15
+#define EMIF_REG_CNTR1_MCONNID_EN_MASK (1 << 15)
+#define EMIF_REG_CNTR1_REGION_EN_SHIFT 14
+#define EMIF_REG_CNTR1_REGION_EN_MASK (1 << 14)
+#define EMIF_REG_CNTR1_CFG_SHIFT 0
+#define EMIF_REG_CNTR1_CFG_MASK (0xf << 0)
+
+/* PERF_CNT_SEL */
+#define EMIF_REG_MCONNID2_SHIFT 24
+#define EMIF_REG_MCONNID2_MASK (0xff << 24)
+#define EMIF_REG_REGION_SEL2_SHIFT 16
+#define EMIF_REG_REGION_SEL2_MASK (0x3 << 16)
+#define EMIF_REG_MCONNID1_SHIFT 8
+#define EMIF_REG_MCONNID1_MASK (0xff << 8)
+#define EMIF_REG_REGION_SEL1_SHIFT 0
+#define EMIF_REG_REGION_SEL1_MASK (0x3 << 0)
+
+/* PERF_CNT_TIM */
+#define EMIF_REG_TOTAL_TIME_SHIFT 0
+#define EMIF_REG_TOTAL_TIME_MASK (0xffffffff << 0)
+
+/* READ_IDLE_CTRL */
+#define EMIF_REG_READ_IDLE_LEN_SHIFT 16
+#define EMIF_REG_READ_IDLE_LEN_MASK (0xf << 16)
+#define EMIF_REG_READ_IDLE_INTERVAL_SHIFT 0
+#define EMIF_REG_READ_IDLE_INTERVAL_MASK (0x1ff << 0)
+
+/* READ_IDLE_CTRL_SHDW */
+#define EMIF_REG_READ_IDLE_LEN_SHDW_SHIFT 16
+#define EMIF_REG_READ_IDLE_LEN_SHDW_MASK (0xf << 16)
+#define EMIF_REG_READ_IDLE_INTERVAL_SHDW_SHIFT 0
+#define EMIF_REG_READ_IDLE_INTERVAL_SHDW_MASK (0x1ff << 0)
+
+/* IRQ_EOI */
+#define EMIF_REG_EOI_SHIFT 0
+#define EMIF_REG_EOI_MASK (1 << 0)
+
+/* IRQSTATUS_RAW_SYS */
+#define EMIF_REG_DNV_SYS_SHIFT 2
+#define EMIF_REG_DNV_SYS_MASK (1 << 2)
+#define EMIF_REG_TA_SYS_SHIFT 1
+#define EMIF_REG_TA_SYS_MASK (1 << 1)
+#define EMIF_REG_ERR_SYS_SHIFT 0
+#define EMIF_REG_ERR_SYS_MASK (1 << 0)
+
+/* IRQSTATUS_RAW_LL */
+#define EMIF_REG_DNV_LL_SHIFT 2
+#define EMIF_REG_DNV_LL_MASK (1 << 2)
+#define EMIF_REG_TA_LL_SHIFT 1
+#define EMIF_REG_TA_LL_MASK (1 << 1)
+#define EMIF_REG_ERR_LL_SHIFT 0
+#define EMIF_REG_ERR_LL_MASK (1 << 0)
+
+/* IRQSTATUS_SYS */
+
+/* IRQSTATUS_LL */
+
+/* IRQENABLE_SET_SYS */
+#define EMIF_REG_EN_DNV_SYS_SHIFT 2
+#define EMIF_REG_EN_DNV_SYS_MASK (1 << 2)
+#define EMIF_REG_EN_TA_SYS_SHIFT 1
+#define EMIF_REG_EN_TA_SYS_MASK (1 << 1)
+#define EMIF_REG_EN_ERR_SYS_SHIFT 0
+#define EMIF_REG_EN_ERR_SYS_MASK (1 << 0)
+
+/* IRQENABLE_SET_LL */
+#define EMIF_REG_EN_DNV_LL_SHIFT 2
+#define EMIF_REG_EN_DNV_LL_MASK (1 << 2)
+#define EMIF_REG_EN_TA_LL_SHIFT 1
+#define EMIF_REG_EN_TA_LL_MASK (1 << 1)
+#define EMIF_REG_EN_ERR_LL_SHIFT 0
+#define EMIF_REG_EN_ERR_LL_MASK (1 << 0)
+
+/* IRQENABLE_CLR_SYS */
+
+/* IRQENABLE_CLR_LL */
+
+/* ZQ_CONFIG */
+#define EMIF_REG_ZQ_CS1EN_SHIFT 31
+#define EMIF_REG_ZQ_CS1EN_MASK (1 << 31)
+#define EMIF_REG_ZQ_CS0EN_SHIFT 30
+#define EMIF_REG_ZQ_CS0EN_MASK (1 << 30)
+#define EMIF_REG_ZQ_DUALCALEN_SHIFT 29
+#define EMIF_REG_ZQ_DUALCALEN_MASK (1 << 29)
+#define EMIF_REG_ZQ_SFEXITEN_SHIFT 28
+#define EMIF_REG_ZQ_SFEXITEN_MASK (1 << 28)
+#define EMIF_REG_ZQ_ZQINIT_MULT_SHIFT 18
+#define EMIF_REG_ZQ_ZQINIT_MULT_MASK (0x3 << 18)
+#define EMIF_REG_ZQ_ZQCL_MULT_SHIFT 16
+#define EMIF_REG_ZQ_ZQCL_MULT_MASK (0x3 << 16)
+#define EMIF_REG_ZQ_REFINTERVAL_SHIFT 0
+#define EMIF_REG_ZQ_REFINTERVAL_MASK (0xffff << 0)
+
+/* TEMP_ALERT_CONFIG */
+#define EMIF_REG_TA_CS1EN_SHIFT 31
+#define EMIF_REG_TA_CS1EN_MASK (1 << 31)
+#define EMIF_REG_TA_CS0EN_SHIFT 30
+#define EMIF_REG_TA_CS0EN_MASK (1 << 30)
+#define EMIF_REG_TA_SFEXITEN_SHIFT 28
+#define EMIF_REG_TA_SFEXITEN_MASK (1 << 28)
+#define EMIF_REG_TA_DEVWDT_SHIFT 26
+#define EMIF_REG_TA_DEVWDT_MASK (0x3 << 26)
+#define EMIF_REG_TA_DEVCNT_SHIFT 24
+#define EMIF_REG_TA_DEVCNT_MASK (0x3 << 24)
+#define EMIF_REG_TA_REFINTERVAL_SHIFT 0
+#define EMIF_REG_TA_REFINTERVAL_MASK (0x3fffff << 0)
+
+/* OCP_ERR_LOG */
+#define EMIF_REG_MADDRSPACE_SHIFT 14
+#define EMIF_REG_MADDRSPACE_MASK (0x3 << 14)
+#define EMIF_REG_MBURSTSEQ_SHIFT 11
+#define EMIF_REG_MBURSTSEQ_MASK (0x7 << 11)
+#define EMIF_REG_MCMD_SHIFT 8
+#define EMIF_REG_MCMD_MASK (0x7 << 8)
+#define EMIF_REG_MCONNID_SHIFT 0
+#define EMIF_REG_MCONNID_MASK (0xff << 0)
+
+/* DDR_PHY_CTRL_1 */
+#define EMIF_REG_DDR_PHY_CTRL_1_SHIFT 4
+#define EMIF_REG_DDR_PHY_CTRL_1_MASK (0xfffffff << 4)
+#define EMIF_REG_READ_LATENCY_SHIFT 0
+#define EMIF_REG_READ_LATENCY_MASK (0xf << 0)
+#define EMIF_REG_DLL_SLAVE_DLY_CTRL_SHIFT 4
+#define EMIF_REG_DLL_SLAVE_DLY_CTRL_MASK (0xFF << 4)
+#define EMIF_EMIF_DDR_PHY_CTRL_1_BASE_VAL_SHIFT 12
+#define EMIF_EMIF_DDR_PHY_CTRL_1_BASE_VAL_MASK (0xFFFFF << 12)
+
+/* DDR_PHY_CTRL_1_SHDW */
+#define EMIF_REG_DDR_PHY_CTRL_1_SHDW_SHIFT 4
+#define EMIF_REG_DDR_PHY_CTRL_1_SHDW_MASK (0xfffffff << 4)
+#define EMIF_REG_READ_LATENCY_SHDW_SHIFT 0
+#define EMIF_REG_READ_LATENCY_SHDW_MASK (0xf << 0)
+#define EMIF_REG_DLL_SLAVE_DLY_CTRL_SHDW_SHIFT 4
+#define EMIF_REG_DLL_SLAVE_DLY_CTRL_SHDW_MASK (0xFF << 4)
+#define EMIF_EMIF_DDR_PHY_CTRL_1_BASE_VAL_SHDW_SHIFT 12
+#define EMIF_EMIF_DDR_PHY_CTRL_1_BASE_VAL_SHDW_MASK (0xFFFFF << 12)
+
+/* DDR_PHY_CTRL_2 */
+#define EMIF_REG_DDR_PHY_CTRL_2_SHIFT 0
+#define EMIF_REG_DDR_PHY_CTRL_2_MASK (0xffffffff << 0)
+
+/* DMM */
+#define DMM_BASE 0x4E000040
+
+/* Memory Adapter */
+#define MA_BASE 0x482AF040
+
+/* DMM_LISA_MAP */
+#define EMIF_SYS_ADDR_SHIFT 24
+#define EMIF_SYS_ADDR_MASK (0xff << 24)
+#define EMIF_SYS_SIZE_SHIFT 20
+#define EMIF_SYS_SIZE_MASK (0x7 << 20)
+#define EMIF_SDRC_INTL_SHIFT 18
+#define EMIF_SDRC_INTL_MASK (0x3 << 18)
+#define EMIF_SDRC_ADDRSPC_SHIFT 16
+#define EMIF_SDRC_ADDRSPC_MASK (0x3 << 16)
+#define EMIF_SDRC_MAP_SHIFT 8
+#define EMIF_SDRC_MAP_MASK (0x3 << 8)
+#define EMIF_SDRC_ADDR_SHIFT 0
+#define EMIF_SDRC_ADDR_MASK (0xff << 0)
+
+/* DMM_LISA_MAP fields */
+#define DMM_SDRC_MAP_UNMAPPED 0
+#define DMM_SDRC_MAP_EMIF1_ONLY 1
+#define DMM_SDRC_MAP_EMIF2_ONLY 2
+#define DMM_SDRC_MAP_EMIF1_AND_EMIF2 3
+
+#define DMM_SDRC_INTL_NONE 0
+#define DMM_SDRC_INTL_128B 1
+#define DMM_SDRC_INTL_256B 2
+#define DMM_SDRC_INTL_512 3
+
+#define DMM_SDRC_ADDR_SPC_SDRAM 0
+#define DMM_SDRC_ADDR_SPC_NVM 1
+#define DMM_SDRC_ADDR_SPC_INVALID 2
+
+#define DMM_LISA_MAP_INTERLEAVED_BASE_VAL (\
+ (DMM_SDRC_MAP_EMIF1_AND_EMIF2 << EMIF_SDRC_MAP_SHIFT) |\
+ (DMM_SDRC_ADDR_SPC_SDRAM << EMIF_SDRC_ADDRSPC_SHIFT) |\
+ (DMM_SDRC_INTL_128B << EMIF_SDRC_INTL_SHIFT) |\
+ (CONFIG_SYS_SDRAM_BASE << EMIF_SYS_ADDR_SHIFT))
+
+#define DMM_LISA_MAP_EMIF1_ONLY_BASE_VAL (\
+ (DMM_SDRC_MAP_EMIF1_ONLY << EMIF_SDRC_MAP_SHIFT)|\
+ (DMM_SDRC_ADDR_SPC_SDRAM << EMIF_SDRC_ADDRSPC_SHIFT)|\
+ (DMM_SDRC_INTL_NONE << EMIF_SDRC_INTL_SHIFT))
+
+#define DMM_LISA_MAP_EMIF2_ONLY_BASE_VAL (\
+ (DMM_SDRC_MAP_EMIF2_ONLY << EMIF_SDRC_MAP_SHIFT)|\
+ (DMM_SDRC_ADDR_SPC_SDRAM << EMIF_SDRC_ADDRSPC_SHIFT)|\
+ (DMM_SDRC_INTL_NONE << EMIF_SDRC_INTL_SHIFT))
+
+/* Trap for invalid TILER PAT entries */
+#define DMM_LISA_MAP_0_INVAL_ADDR_TRAP (\
+ (0 << EMIF_SDRC_ADDR_SHIFT) |\
+ (DMM_SDRC_MAP_EMIF1_ONLY << EMIF_SDRC_MAP_SHIFT)|\
+ (DMM_SDRC_ADDR_SPC_INVALID << EMIF_SDRC_ADDRSPC_SHIFT)|\
+ (DMM_SDRC_INTL_NONE << EMIF_SDRC_INTL_SHIFT)|\
+ (0xFF << EMIF_SYS_ADDR_SHIFT))
+
+
+/* Reg mapping structure */
+struct emif_reg_struct {
+ u32 emif_mod_id_rev;
+ u32 emif_status;
+ u32 emif_sdram_config;
+ u32 emif_lpddr2_nvm_config;
+ u32 emif_sdram_ref_ctrl;
+ u32 emif_sdram_ref_ctrl_shdw;
+ u32 emif_sdram_tim_1;
+ u32 emif_sdram_tim_1_shdw;
+ u32 emif_sdram_tim_2;
+ u32 emif_sdram_tim_2_shdw;
+ u32 emif_sdram_tim_3;
+ u32 emif_sdram_tim_3_shdw;
+ u32 emif_lpddr2_nvm_tim;
+ u32 emif_lpddr2_nvm_tim_shdw;
+ u32 emif_pwr_mgmt_ctrl;
+ u32 emif_pwr_mgmt_ctrl_shdw;
+ u32 emif_lpddr2_mode_reg_data;
+ u32 padding1[1];
+ u32 emif_lpddr2_mode_reg_data_es2;
+ u32 padding11[1];
+ u32 emif_lpddr2_mode_reg_cfg;
+ u32 emif_l3_config;
+ u32 emif_l3_cfg_val_1;
+ u32 emif_l3_cfg_val_2;
+ u32 emif_iodft_tlgc;
+ u32 padding2[7];
+ u32 emif_perf_cnt_1;
+ u32 emif_perf_cnt_2;
+ u32 emif_perf_cnt_cfg;
+ u32 emif_perf_cnt_sel;
+ u32 emif_perf_cnt_tim;
+ u32 padding3;
+ u32 emif_read_idlectrl;
+ u32 emif_read_idlectrl_shdw;
+ u32 padding4;
+ u32 emif_irqstatus_raw_sys;
+ u32 emif_irqstatus_raw_ll;
+ u32 emif_irqstatus_sys;
+ u32 emif_irqstatus_ll;
+ u32 emif_irqenable_set_sys;
+ u32 emif_irqenable_set_ll;
+ u32 emif_irqenable_clr_sys;
+ u32 emif_irqenable_clr_ll;
+ u32 padding5;
+ u32 emif_zq_config;
+ u32 emif_temp_alert_config;
+ u32 emif_l3_err_log;
+ u32 padding6[4];
+ u32 emif_ddr_phy_ctrl_1;
+ u32 emif_ddr_phy_ctrl_1_shdw;
+ u32 emif_ddr_phy_ctrl_2;
+};
+
+struct dmm_lisa_map_regs {
+ u32 dmm_lisa_map_0;
+ u32 dmm_lisa_map_1;
+ u32 dmm_lisa_map_2;
+ u32 dmm_lisa_map_3;
+};
+
+#define CS0 0
+#define CS1 1
+/* The maximum frequency at which the LPDDR2 interface can operate in Hz*/
+#define MAX_LPDDR2_FREQ 400000000 /* 400 MHz */
+
+/*
+ * The period of DDR clk is represented as numerator and denominator for
+ * better accuracy in integer based calculations. However, if the numerator
+ * and denominator are very huge there may be chances of overflow in
+ * calculations. So, as a trade-off keep denominator(and consequently
+ * numerator) within a limit sacrificing some accuracy - but not much
+ * If denominator and numerator are already small (such as at 400 MHz)
+ * no adjustment is needed
+ */
+#define EMIF_PERIOD_DEN_LIMIT 1000
+/*
+ * Maximum number of different frequencies supported by EMIF driver
+ * Determines the number of entries in the pointer array for register
+ * cache
+ */
+#define EMIF_MAX_NUM_FREQUENCIES 6
+/*
+ * Indices into the Addressing Table array.
+ * One entry each for all the different types of devices with different
+ * addressing schemes
+ */
+#define ADDR_TABLE_INDEX64M 0
+#define ADDR_TABLE_INDEX128M 1
+#define ADDR_TABLE_INDEX256M 2
+#define ADDR_TABLE_INDEX512M 3
+#define ADDR_TABLE_INDEX1GS4 4
+#define ADDR_TABLE_INDEX2GS4 5
+#define ADDR_TABLE_INDEX4G 6
+#define ADDR_TABLE_INDEX8G 7
+#define ADDR_TABLE_INDEX1GS2 8
+#define ADDR_TABLE_INDEX2GS2 9
+#define ADDR_TABLE_INDEXMAX 10
+
+/* Number of Row bits */
+#define ROW_9 0
+#define ROW_10 1
+#define ROW_11 2
+#define ROW_12 3
+#define ROW_13 4
+#define ROW_14 5
+#define ROW_15 6
+#define ROW_16 7
+
+/* Number of Column bits */
+#define COL_8 0
+#define COL_9 1
+#define COL_10 2
+#define COL_11 3
+#define COL_7 4 /*Not supported by OMAP included for completeness */
+
+/* Number of Banks*/
+#define BANKS1 0
+#define BANKS2 1
+#define BANKS4 2
+#define BANKS8 3
+
+/* Refresh rate in micro seconds x 10 */
+#define T_REFI_15_6 156
+#define T_REFI_7_8 78
+#define T_REFI_3_9 39
+
+#define EBANK_CS1_DIS 0
+#define EBANK_CS1_EN 1
+
+/* Read Latency used by the device at reset */
+#define RL_BOOT 3
+/* Read Latency for the highest frequency you want to use */
+#ifdef CONFIG_OMAP54XX
+#define RL_FINAL 8
+#else
+#define RL_FINAL 6
+#endif
+
+
+/* Interleaving policies at EMIF level- between banks and Chip Selects */
+#define EMIF_INTERLEAVING_POLICY_MAX_INTERLEAVING 0
+#define EMIF_INTERLEAVING_POLICY_NO_BANK_INTERLEAVING 3
+
+/*
+ * Interleaving policy to be used
+ * Currently set to MAX interleaving for better performance
+ */
+#define EMIF_INTERLEAVING_POLICY EMIF_INTERLEAVING_POLICY_MAX_INTERLEAVING
+
+/* State of the core voltage:
+ * This is important for some parameters such as read idle control and
+ * ZQ calibration timings. Timings are much stricter when voltage ramp
+ * is happening compared to when the voltage is stable.
+ * We need to calculate two sets of values for these parameters and use
+ * them accordingly
+ */
+#define LPDDR2_VOLTAGE_STABLE 0
+#define LPDDR2_VOLTAGE_RAMPING 1
+
+/* Length of the forced read idle period in terms of cycles */
+#define EMIF_REG_READ_IDLE_LEN_VAL 5
+
+/* Interval between forced 'read idles' */
+/* To be used when voltage is changed for DPS/DVFS - 1us */
+#define READ_IDLE_INTERVAL_DVFS (1*1000)
+/*
+ * To be used when voltage is not scaled except by Smart Reflex
+ * 50us - or maximum value will do
+ */
+#define READ_IDLE_INTERVAL_NORMAL (50*1000)
+
+
+/*
+ * Unless voltage is changing due to DVFS one ZQCS command every 50ms should
+ * be enough. This shoule be enough also in the case when voltage is changing
+ * due to smart-reflex.
+ */
+#define EMIF_ZQCS_INTERVAL_NORMAL_IN_US (50*1000)
+/*
+ * If voltage is changing due to DVFS ZQCS should be performed more
+ * often(every 50us)
+ */
+#define EMIF_ZQCS_INTERVAL_DVFS_IN_US 50
+
+/* The interval between ZQCL commands as a multiple of ZQCS interval */
+#define REG_ZQ_ZQCL_MULT 4
+/* The interval between ZQINIT commands as a multiple of ZQCL interval */
+#define REG_ZQ_ZQINIT_MULT 3
+/* Enable ZQ Calibration on exiting Self-refresh */
+#define REG_ZQ_SFEXITEN_ENABLE 1
+/*
+ * ZQ Calibration simultaneously on both chip-selects:
+ * Needs one calibration resistor per CS
+ * None of the boards that we know of have this capability
+ * So disabled by default
+ */
+#define REG_ZQ_DUALCALEN_DISABLE 0
+/*
+ * Enable ZQ Calibration by default on CS0. If we are asked to program
+ * the EMIF there will be something connected to CS0 for sure
+ */
+#define REG_ZQ_CS0EN_ENABLE 1
+
+/* EMIF_PWR_MGMT_CTRL register */
+/* Low power modes */
+#define LP_MODE_DISABLE 0
+#define LP_MODE_CLOCK_STOP 1
+#define LP_MODE_SELF_REFRESH 2
+#define LP_MODE_PWR_DN 3
+
+/* REG_DPD_EN */
+#define DPD_DISABLE 0
+#define DPD_ENABLE 1
+
+/* Maximum delay before Low Power Modes */
+#define REG_CS_TIM 0xF
+#define REG_SR_TIM 0xF
+#define REG_PD_TIM 0xF
+
+/* EMIF_PWR_MGMT_CTRL register */
+#define EMIF_PWR_MGMT_CTRL (\
+ ((REG_CS_TIM << EMIF_REG_CS_TIM_SHIFT) & EMIF_REG_CS_TIM_MASK)|\
+ ((REG_SR_TIM << EMIF_REG_SR_TIM_SHIFT) & EMIF_REG_SR_TIM_MASK)|\
+ ((REG_PD_TIM << EMIF_REG_PD_TIM_SHIFT) & EMIF_REG_PD_TIM_MASK)|\
+ ((REG_PD_TIM << EMIF_REG_PD_TIM_SHIFT) & EMIF_REG_PD_TIM_MASK)|\
+ ((LP_MODE_DISABLE << EMIF_REG_LP_MODE_SHIFT)\
+ & EMIF_REG_LP_MODE_MASK) |\
+ ((DPD_DISABLE << EMIF_REG_DPD_EN_SHIFT)\
+ & EMIF_REG_DPD_EN_MASK))\
+
+#define EMIF_PWR_MGMT_CTRL_SHDW (\
+ ((REG_CS_TIM << EMIF_REG_CS_TIM_SHDW_SHIFT)\
+ & EMIF_REG_CS_TIM_SHDW_MASK) |\
+ ((REG_SR_TIM << EMIF_REG_SR_TIM_SHDW_SHIFT)\
+ & EMIF_REG_SR_TIM_SHDW_MASK) |\
+ ((REG_PD_TIM << EMIF_REG_PD_TIM_SHDW_SHIFT)\
+ & EMIF_REG_PD_TIM_SHDW_MASK) |\
+ ((REG_PD_TIM << EMIF_REG_PD_TIM_SHDW_SHIFT)\
+ & EMIF_REG_PD_TIM_SHDW_MASK))
+
+/* EMIF_L3_CONFIG register value */
+#define EMIF_L3_CONFIG_VAL_SYS_10_LL_0 0x0A0000FF
+#define EMIF_L3_CONFIG_VAL_SYS_10_MPU_3_LL_0 0x0A300000
+#define EMIF_L3_CONFIG_VAL_SYS_10_MPU_5_LL_0 0x0A300000
+
+/*
+ * Value of bits 12:31 of DDR_PHY_CTRL_1 register:
+ * All these fields have magic values dependent on frequency and
+ * determined by PHY and DLL integration with EMIF. Setting the magic
+ * values suggested by hw team.
+ */
+#define EMIF_DDR_PHY_CTRL_1_BASE_VAL 0x049FF
+#define EMIF_DLL_SLAVE_DLY_CTRL_400_MHZ 0x41
+#define EMIF_DLL_SLAVE_DLY_CTRL_200_MHZ 0x80
+#define EMIF_DLL_SLAVE_DLY_CTRL_100_MHZ_AND_LESS 0xFF
+
+/*
+* MR1 value:
+* Burst length : 8
+* Burst type : sequential
+* Wrap : enabled
+* nWR : 3(default). EMIF does not do pre-charge.
+* : So nWR is don't care
+*/
+#define MR1_BL_8_BT_SEQ_WRAP_EN_NWR_3 0x23
+
+/* MR2 */
+#define MR2_RL3_WL1 1
+#define MR2_RL4_WL2 2
+#define MR2_RL5_WL2 3
+#define MR2_RL6_WL3 4
+
+/* MR10: ZQ calibration codes */
+#define MR10_ZQ_ZQCS 0x56
+#define MR10_ZQ_ZQCL 0xAB
+#define MR10_ZQ_ZQINIT 0xFF
+#define MR10_ZQ_ZQRESET 0xC3
+
+/* TEMP_ALERT_CONFIG */
+#define TEMP_ALERT_POLL_INTERVAL_MS 360 /* for temp gradient - 5 C/s */
+#define TEMP_ALERT_CONFIG_DEVCT_1 0
+#define TEMP_ALERT_CONFIG_DEVWDT_32 2
+
+/* MR16 value: refresh full array(no partial array self refresh) */
+#define MR16_REF_FULL_ARRAY 0
+
+/*
+ * Maximum number of entries we keep in our array of timing tables
+ * We need not keep all the speed bins supported by the device
+ * We need to keep timing tables for only the speed bins that we
+ * are interested in
+ */
+#define MAX_NUM_SPEEDBINS 4
+
+/* LPDDR2 Densities */
+#define LPDDR2_DENSITY_64Mb 0
+#define LPDDR2_DENSITY_128Mb 1
+#define LPDDR2_DENSITY_256Mb 2
+#define LPDDR2_DENSITY_512Mb 3
+#define LPDDR2_DENSITY_1Gb 4
+#define LPDDR2_DENSITY_2Gb 5
+#define LPDDR2_DENSITY_4Gb 6
+#define LPDDR2_DENSITY_8Gb 7
+#define LPDDR2_DENSITY_16Gb 8
+#define LPDDR2_DENSITY_32Gb 9
+
+/* LPDDR2 type */
+#define LPDDR2_TYPE_S4 0
+#define LPDDR2_TYPE_S2 1
+#define LPDDR2_TYPE_NVM 2
+
+/* LPDDR2 IO width */
+#define LPDDR2_IO_WIDTH_32 0
+#define LPDDR2_IO_WIDTH_16 1
+#define LPDDR2_IO_WIDTH_8 2
+
+/* Mode register numbers */
+#define LPDDR2_MR0 0
+#define LPDDR2_MR1 1
+#define LPDDR2_MR2 2
+#define LPDDR2_MR3 3
+#define LPDDR2_MR4 4
+#define LPDDR2_MR5 5
+#define LPDDR2_MR6 6
+#define LPDDR2_MR7 7
+#define LPDDR2_MR8 8
+#define LPDDR2_MR9 9
+#define LPDDR2_MR10 10
+#define LPDDR2_MR11 11
+#define LPDDR2_MR16 16
+#define LPDDR2_MR17 17
+#define LPDDR2_MR18 18
+
+/* MR0 */
+#define LPDDR2_MR0_DAI_SHIFT 0
+#define LPDDR2_MR0_DAI_MASK 1
+#define LPDDR2_MR0_DI_SHIFT 1
+#define LPDDR2_MR0_DI_MASK (1 << 1)
+#define LPDDR2_MR0_DNVI_SHIFT 2
+#define LPDDR2_MR0_DNVI_MASK (1 << 2)
+
+/* MR4 */
+#define MR4_SDRAM_REF_RATE_SHIFT 0
+#define MR4_SDRAM_REF_RATE_MASK 7
+#define MR4_TUF_SHIFT 7
+#define MR4_TUF_MASK (1 << 7)
+
+/* MR4 SDRAM Refresh Rate field values */
+#define SDRAM_TEMP_LESS_LOW_SHUTDOWN 0x0
+#define SDRAM_TEMP_LESS_4X_REFRESH_AND_TIMINGS 0x1
+#define SDRAM_TEMP_LESS_2X_REFRESH_AND_TIMINGS 0x2
+#define SDRAM_TEMP_NOMINAL 0x3
+#define SDRAM_TEMP_RESERVED_4 0x4
+#define SDRAM_TEMP_HIGH_DERATE_REFRESH 0x5
+#define SDRAM_TEMP_HIGH_DERATE_REFRESH_AND_TIMINGS 0x6
+#define SDRAM_TEMP_VERY_HIGH_SHUTDOWN 0x7
+
+#define LPDDR2_MANUFACTURER_SAMSUNG 1
+#define LPDDR2_MANUFACTURER_QIMONDA 2
+#define LPDDR2_MANUFACTURER_ELPIDA 3
+#define LPDDR2_MANUFACTURER_ETRON 4
+#define LPDDR2_MANUFACTURER_NANYA 5
+#define LPDDR2_MANUFACTURER_HYNIX 6
+#define LPDDR2_MANUFACTURER_MOSEL 7
+#define LPDDR2_MANUFACTURER_WINBOND 8
+#define LPDDR2_MANUFACTURER_ESMT 9
+#define LPDDR2_MANUFACTURER_SPANSION 11
+#define LPDDR2_MANUFACTURER_SST 12
+#define LPDDR2_MANUFACTURER_ZMOS 13
+#define LPDDR2_MANUFACTURER_INTEL 14
+#define LPDDR2_MANUFACTURER_NUMONYX 254
+#define LPDDR2_MANUFACTURER_MICRON 255
+
+/* MR8 register fields */
+#define MR8_TYPE_SHIFT 0x0
+#define MR8_TYPE_MASK 0x3
+#define MR8_DENSITY_SHIFT 0x2
+#define MR8_DENSITY_MASK (0xF << 0x2)
+#define MR8_IO_WIDTH_SHIFT 0x6
+#define MR8_IO_WIDTH_MASK (0x3 << 0x6)
+
+struct lpddr2_addressing {
+ u8 num_banks;
+ u8 t_REFI_us_x10;
+ u8 row_sz[2]; /* One entry each for x32 and x16 */
+ u8 col_sz[2]; /* One entry each for x32 and x16 */
+};
+
+/* Structure for timings from the DDR datasheet */
+struct lpddr2_ac_timings {
+ u32 max_freq;
+ u8 RL;
+ u8 tRPab;
+ u8 tRCD;
+ u8 tWR;
+ u8 tRASmin;
+ u8 tRRD;
+ u8 tWTRx2;
+ u8 tXSR;
+ u8 tXPx2;
+ u8 tRFCab;
+ u8 tRTPx2;
+ u8 tCKE;
+ u8 tCKESR;
+ u8 tZQCS;
+ u32 tZQCL;
+ u32 tZQINIT;
+ u8 tDQSCKMAXx2;
+ u8 tRASmax;
+ u8 tFAW;
+
+};
+
+/*
+ * Min tCK values for some of the parameters:
+ * If the calculated clock cycles for the respective parameter is
+ * less than the corresponding min tCK value, we need to set the min
+ * tCK value. This may happen at lower frequencies.
+ */
+struct lpddr2_min_tck {
+ u32 tRL;
+ u32 tRP_AB;
+ u32 tRCD;
+ u32 tWR;
+ u32 tRAS_MIN;
+ u32 tRRD;
+ u32 tWTR;
+ u32 tXP;
+ u32 tRTP;
+ u8 tCKE;
+ u32 tCKESR;
+ u32 tFAW;
+};
+
+struct lpddr2_device_details {
+ u8 type;
+ u8 density;
+ u8 io_width;
+ u8 manufacturer;
+};
+
+struct lpddr2_device_timings {
+ const struct lpddr2_ac_timings **ac_timings;
+ const struct lpddr2_min_tck *min_tck;
+};
+
+/* Details of the devices connected to each chip-select of an EMIF instance */
+struct emif_device_details {
+ const struct lpddr2_device_details *cs0_device_details;
+ const struct lpddr2_device_details *cs1_device_details;
+ const struct lpddr2_device_timings *cs0_device_timings;
+ const struct lpddr2_device_timings *cs1_device_timings;
+};
+
+/*
+ * Structure containing shadow of important registers in EMIF
+ * The calculation function fills in this structure to be later used for
+ * initialization and DVFS
+ */
+struct emif_regs {
+ u32 freq;
+ u32 sdram_config_init;
+ u32 sdram_config;
+ u32 ref_ctrl;
+ u32 sdram_tim1;
+ u32 sdram_tim2;
+ u32 sdram_tim3;
+ u32 read_idle_ctrl;
+ u32 zq_config;
+ u32 temp_alert_config;
+ u32 emif_ddr_phy_ctlr_1_init;
+ u32 emif_ddr_phy_ctlr_1;
+};
+
+/* assert macros */
+#if defined(DEBUG)
+#define emif_assert(c) ({ if (!(c)) for (;;); })
+#else
+#define emif_assert(c) ({ if (0) hang(); })
+#endif
+
+#ifdef CONFIG_SYS_EMIF_PRECALCULATED_TIMING_REGS
+void emif_get_reg_dump(u32 emif_nr, const struct emif_regs **regs);
+void emif_get_dmm_regs(const struct dmm_lisa_map_regs **dmm_lisa_regs);
+#else
+struct lpddr2_device_details *emif_get_device_details(u32 emif_nr, u8 cs,
+ struct lpddr2_device_details *lpddr2_dev_details);
+void emif_get_device_timings(u32 emif_nr,
+ const struct lpddr2_device_timings **cs0_device_timings,
+ const struct lpddr2_device_timings **cs1_device_timings);
+#endif
+
+#ifndef CONFIG_SYS_EMIF_PRECALCULATED_TIMING_REGS
+extern u32 *const T_num;
+extern u32 *const T_den;
+extern u32 *const emif_sizes;
+#endif
+
+
+#endif
diff --git a/arch/arm/include/asm/mach-types.h b/arch/arm/include/asm/mach-types.h
index 2549051..2d5c3bc 100644
--- a/arch/arm/include/asm/mach-types.h
+++ b/arch/arm/include/asm/mach-types.h
@@ -1104,6 +1104,7 @@
#define MACH_TYPE_THALES_ADC 3492
#define MACH_TYPE_UBISYS_P9D_EVP 3493
#define MACH_TYPE_ATDGP318 3494
+#define MACH_TYPE_OMAP5_SEVM 3777
#ifdef CONFIG_ARCH_EBSA110
# ifdef machine_arch_type
@@ -14209,6 +14210,18 @@
# define machine_is_atdgp318() (0)
#endif
+#ifdef CONFIG_MACH_OMAP5_SEVM
+# ifdef machine_arch_type
+# undef machine_arch_type
+# define machine_arch_type __machine_arch_type
+# else
+# define machine_arch_type MACH_TYPE_OMAP5_SEVM
+# endif
+# define machine_is_omap5_sevm() (machine_arch_type == MACH_TYPE_OMAP5_SEVM)
+#else
+# define machine_is_omap5_sevm() (0)
+#endif
+
/*
* These have not yet been registered
*/
diff --git a/arch/arm/include/asm/omap_common.h b/arch/arm/include/asm/omap_common.h
index 3f2f004..f1562ea 100644
--- a/arch/arm/include/asm/omap_common.h
+++ b/arch/arm/include/asm/omap_common.h
@@ -37,7 +37,16 @@
void preloader_console_init(void);
/* Boot device */
-#ifdef CONFIG_OMAP44XX /* OMAP4 */
+#ifdef CONFIG_OMAP54XX
+#define BOOT_DEVICE_NONE 0
+#define BOOT_DEVICE_XIP 1
+#define BOOT_DEVICE_XIPWAIT 2
+#define BOOT_DEVICE_NAND 3
+#define BOOT_DEVICE_ONE_NAND 4
+#define BOOT_DEVICE_MMC1 5
+#define BOOT_DEVICE_MMC2 6
+#define BOOT_DEVICE_MMC3 7
+#elif defined(CONFIG_OMAP44XX) /* OMAP4 */
#define BOOT_DEVICE_NONE 0
#define BOOT_DEVICE_XIP 1
#define BOOT_DEVICE_XIPWAIT 2
@@ -71,10 +80,10 @@
extern struct spl_image_info spl_image;
+extern u32* boot_params_ptr;
u32 omap_boot_device(void);
u32 omap_boot_mode(void);
-
/* SPL common function s*/
void spl_parse_image_header(const struct image_header *header);
void omap_rev_string(char *omap_rev_string);
@@ -85,4 +94,22 @@
/* MMC SPL functions */
void spl_mmc_load_image(void);
+/*
+ * silicon revisions.
+ * Moving this to common, so that most of code can be moved to common,
+ * directories.
+ */
+
+/* omap4 */
+#define OMAP4430_SILICON_ID_INVALID 0xFFFFFFFF
+#define OMAP4430_ES1_0 0x44300100
+#define OMAP4430_ES2_0 0x44300200
+#define OMAP4430_ES2_1 0x44300210
+#define OMAP4430_ES2_2 0x44300220
+#define OMAP4430_ES2_3 0x44300230
+#define OMAP4460_ES1_0 0x44600100
+
+/* omap5 */
+#define OMAP5430_SILICON_ID_INVALID 0
+#define OMAP5430_ES1_0 0x54300100
#endif /* _OMAP_COMMON_H_ */
diff --git a/arch/arm/lib/board.c b/arch/arm/lib/board.c
index a482706..3d78274 100644
--- a/arch/arm/lib/board.c
+++ b/arch/arm/lib/board.c
@@ -73,10 +73,6 @@
extern void dataflash_print_info(void);
#endif
-#ifdef CONFIG_DRIVER_RTL8019
-extern void rtl8019_get_enetaddr (uchar * addr);
-#endif
-
#if defined(CONFIG_HARD_I2C) || \
defined(CONFIG_SOFT_I2C)
#include <i2c.h>
diff --git a/arch/blackfin/config.mk b/arch/blackfin/config.mk
index f9d46de..3595aa2 100644
--- a/arch/blackfin/config.mk
+++ b/arch/blackfin/config.mk
@@ -48,9 +48,10 @@
endif
ifeq ($(CONFIG_ENV_IS_EMBEDDED_IN_LDR),y)
CREATE_LDR_ENV = $(obj)tools/envcrc --binary > $(obj)env-ldr.o
-HOSTCFLAGS_NOPED += \
+HOSTCFLAGS_NOPED_ADSP := \
$(shell $(CPP) -dD - -mcpu=$(CONFIG_BFIN_CPU) </dev/null \
| awk '$$2 ~ /ADSP/ { print "-D" $$2 }')
+HOSTCFLAGS_NOPED += $(HOSTCFLAGS_NOPED_ADSP)
else
CREATE_LDR_ENV =
endif
diff --git a/arch/blackfin/cpu/traps.c b/arch/blackfin/cpu/traps.c
index 0cb833a..20aeab8 100644
--- a/arch/blackfin/cpu/traps.c
+++ b/arch/blackfin/cpu/traps.c
@@ -150,7 +150,10 @@
(data ? 'D' : 'I'), (void *)new_cplb_addr);
bfin_panic(regs);
} else
- debug("CPLB addr %p matches map 0x%p - 0x%p\n", new_cplb_addr, bfin_memory_map[i].start, bfin_memory_map[i].end);
+ debug("CPLB addr %p matches map 0x%p - 0x%p\n",
+ (void *)new_cplb_addr,
+ (void *)bfin_memory_map[i].start,
+ (void *)bfin_memory_map[i].end);
new_cplb_data = (data ? bfin_memory_map[i].data_flags : bfin_memory_map[i].inst_flags);
if (data) {
@@ -163,16 +166,17 @@
/* find the next unlocked entry and evict it */
i = last_evicted & 0xF;
- debug("last evicted = %i\n", i);
+ debug("last evicted = %zu\n", i);
CPLB_DATA = CPLB_DATA_BASE + i;
while (*CPLB_DATA & CPLB_LOCK) {
- debug("skipping %i %p - %08X\n", i, CPLB_DATA, *CPLB_DATA);
+ debug("skipping %zu %p - %08X\n", i, CPLB_DATA, *CPLB_DATA);
i = (i + 1) & 0xF; /* wrap around */
CPLB_DATA = CPLB_DATA_BASE + i;
}
CPLB_ADDR = CPLB_ADDR_BASE + i;
- debug("evicting entry %i: 0x%p 0x%08X\n", i, *CPLB_ADDR, *CPLB_DATA);
+ debug("evicting entry %zu: 0x%p 0x%08X\n", i,
+ (void *)*CPLB_ADDR, *CPLB_DATA);
last_evicted = i + 1;
/* need to turn off cplbs whenever we muck with the cplb table */
@@ -190,7 +194,8 @@
CPLB_ADDR = CPLB_ADDR_BASE;
CPLB_DATA = CPLB_DATA_BASE;
for (i = 0; i < 16; ++i)
- debug("%2i 0x%p 0x%08X\n", i, *CPLB_ADDR++, *CPLB_DATA++);
+ debug("%2zu 0x%p 0x%08X\n", i,
+ (void *)*CPLB_ADDR++, *CPLB_DATA++);
break;
}
diff --git a/arch/blackfin/lib/board.c b/arch/blackfin/lib/board.c
index a70473c..e3ee4cd 100644
--- a/arch/blackfin/lib/board.c
+++ b/arch/blackfin/lib/board.c
@@ -308,7 +308,6 @@
void board_init_r(gd_t * id, ulong dest_addr)
{
- char *s;
bd_t *bd;
gd = id;
gd->flags |= GD_FLG_RELOC; /* tell others: relocation done */
diff --git a/arch/nds32/cpu/n1213/ag101/cpu.c b/arch/nds32/cpu/n1213/ag101/cpu.c
index 0ab666e..c2636b1 100644
--- a/arch/nds32/cpu/n1213/ag101/cpu.c
+++ b/arch/nds32/cpu/n1213/ag101/cpu.c
@@ -45,10 +45,6 @@
*/
int cleanup_before_linux(void)
{
-#ifdef CONFIG_MMU
- unsigned long i;
-#endif
-
disable_interrupts();
#ifdef CONFIG_MMU
@@ -123,8 +119,8 @@
void flush_cache(unsigned long addr, unsigned long size)
{
- dcache_flush_range(addr , addr + size);
- icache_inval_range(addr , addr + size);
+ dcache_flush_range(addr, addr + size);
+ icache_inval_range(addr, addr + size);
}
void icache_enable(void)
diff --git a/arch/nds32/cpu/n1213/ag101/timer.c b/arch/nds32/cpu/n1213/ag101/timer.c
index c099c33..caa36b8 100644
--- a/arch/nds32/cpu/n1213/ag101/timer.c
+++ b/arch/nds32/cpu/n1213/ag101/timer.c
@@ -33,7 +33,7 @@
int timer_init(void)
{
- static struct fttmr010 *tmr = (struct fttmr010 *)CONFIG_FTTMR010_BASE;
+ struct fttmr010 *tmr = (struct fttmr010 *)CONFIG_FTTMR010_BASE;
unsigned int cr;
debug("%s()\n", __func__);
@@ -80,7 +80,7 @@
*/
void reset_timer_masked(void)
{
- static struct fttmr010 *tmr = (struct fttmr010 *)CONFIG_FTTMR010_BASE;
+ struct fttmr010 *tmr = (struct fttmr010 *)CONFIG_FTTMR010_BASE;
/* capure current decrementer value time */
#ifdef CONFIG_FTTMR010_EXT_CLK
@@ -104,7 +104,7 @@
*/
ulong get_timer_masked(void)
{
- static struct fttmr010 *tmr = (struct fttmr010 *)CONFIG_FTTMR010_BASE;
+ struct fttmr010 *tmr = (struct fttmr010 *)CONFIG_FTTMR010_BASE;
/* current tick value */
#ifdef CONFIG_FTTMR010_EXT_CLK
@@ -160,7 +160,7 @@
/* delay x useconds AND preserve advance timestamp value */
void __udelay(unsigned long usec)
{
- static struct fttmr010 *tmr = (struct fttmr010 *)CONFIG_FTTMR010_BASE;
+ struct fttmr010 *tmr = (struct fttmr010 *)CONFIG_FTTMR010_BASE;
#ifdef CONFIG_FTTMR010_EXT_CLK
long tmo = usec * (TIMER_CLOCK / 1000) / 1000;
diff --git a/arch/nds32/cpu/n1213/u-boot.lds b/arch/nds32/cpu/n1213/u-boot.lds
index 45221ee..1903420 100644
--- a/arch/nds32/cpu/n1213/u-boot.lds
+++ b/arch/nds32/cpu/n1213/u-boot.lds
@@ -41,7 +41,7 @@
.rodata : { *(SORT_BY_ALIGNMENT(SORT_BY_NAME(.rodata*))) }
. = ALIGN(4);
- .data : { *(.data) }
+ .data : { *(.data*) }
. = ALIGN(4);
diff --git a/arch/nds32/include/asm/io.h b/arch/nds32/include/asm/io.h
index 2c105f7..39c3dc8 100644
--- a/arch/nds32/include/asm/io.h
+++ b/arch/nds32/include/asm/io.h
@@ -165,6 +165,24 @@
#define __raw_base_readw(base, off) __arch_base_getw(base, off)
#define __raw_base_readl(base, off) __arch_base_getl(base, off)
+#define out_arch(type, endian, a, v) __raw_write##type(cpu_to_##endian(v), a)
+#define in_arch(type, endian, a) endian##_to_cpu(__raw_read##type(a))
+
+#define out_le32(a, v) out_arch(l, le32, a, v)
+#define out_le16(a, v) out_arch(w, le16, a, v)
+
+#define in_le32(a) in_arch(l, le32, a)
+#define in_le16(a) in_arch(w, le16, a)
+
+#define out_be32(a, v) out_arch(l, be32, a, v)
+#define out_be16(a, v) out_arch(w, be16, a, v)
+
+#define in_be32(a) in_arch(l, be32, a)
+#define in_be16(a) in_arch(w, be16, a)
+
+#define out_8(a, v) __raw_writeb(v, a)
+#define in_8(a) __raw_readb(a)
+
/*
* Now, pick up the machine-defined IO definitions
* #include <asm/arch/io.h>
diff --git a/arch/nds32/include/asm/mach-types.h b/arch/nds32/include/asm/mach-types.h
index a6f1c93..7b52b98 100644
--- a/arch/nds32/include/asm/mach-types.h
+++ b/arch/nds32/include/asm/mach-types.h
@@ -26,4 +26,18 @@
# define machine_is_adpag101() (0)
#endif
+#define MACH_TYPE_ADPAG101P 1
+
+#ifdef CONFIG_ARCH_ADPAG101P
+# ifdef machine_arch_type
+# undef machine_arch_type
+# define machine_arch_type __machine_arch_type
+# else
+# define machine_arch_type MACH_TYPE_ADPAG101P
+# endif
+# define machine_is_adpag101p() (machine_arch_type == MACH_TYPE_ADPAG101P)
+#else
+# define machine_is_adpag101p() (1)
+#endif
+
#endif /* __ASM_NDS32_MACH_TYPE_H */
diff --git a/arch/nds32/lib/board.c b/arch/nds32/lib/board.c
index 2fd0e93..66e4537 100644
--- a/arch/nds32/lib/board.c
+++ b/arch/nds32/lib/board.c
@@ -351,6 +351,11 @@
nand_init(); /* go init the NAND */
#endif
+#if defined(CONFIG_CMD_IDE)
+ puts("IDE: ");
+ ide_init();
+#endif
+
#ifdef CONFIG_GENERIC_MMC
puts("MMC: ");
mmc_initialize(gd->bd);
diff --git a/arch/nios2/cpu/Makefile b/arch/nios2/cpu/Makefile
index aa41160..402fd74 100644
--- a/arch/nios2/cpu/Makefile
+++ b/arch/nios2/cpu/Makefile
@@ -28,6 +28,7 @@
START = start.o
SOBJS = exceptions.o
COBJS = cpu.o interrupts.o sysid.o traps.o epcs.o
+COBJS += fdt.o
SRCS := $(START:.o=.S) $(SOBJS:.o=.S) $(COBJS:.o=.c)
OBJS := $(addprefix $(obj),$(SOBJS) $(COBJS))
diff --git a/arch/nios2/cpu/cpu.c b/arch/nios2/cpu/cpu.c
index ef360ee..edf25601 100644
--- a/arch/nios2/cpu/cpu.c
+++ b/arch/nios2/cpu/cpu.c
@@ -24,6 +24,7 @@
#include <common.h>
#include <nios2.h>
#include <nios2-io.h>
+#include <asm/cache.h>
#if defined (CONFIG_SYS_NIOS_SYSID_BASE)
extern void display_sysid (void);
@@ -47,3 +48,18 @@
nios2_callr(CONFIG_SYS_RESET_ADDR);
return 0;
}
+
+int dcache_status(void)
+{
+ return 1;
+}
+
+void dcache_enable(void)
+{
+ flush_dcache(CONFIG_SYS_DCACHE_SIZE, CONFIG_SYS_DCACHELINE_SIZE);
+}
+
+void dcache_disable(void)
+{
+ flush_dcache(CONFIG_SYS_DCACHE_SIZE, CONFIG_SYS_DCACHELINE_SIZE);
+}
diff --git a/arch/nios2/cpu/fdt.c b/arch/nios2/cpu/fdt.c
new file mode 100644
index 0000000..b1ed9e1
--- /dev/null
+++ b/arch/nios2/cpu/fdt.c
@@ -0,0 +1,53 @@
+/*
+ * (C) Copyright 2011, Missing Link Electronics
+ * Joachim Foerster <joachim@missinglinkelectronics.com>
+ *
+ * Taken from arch/powerpc/cpu/ppc4xx/fdt.c:
+ *
+ * (C) Copyright 2007-2008
+ * Stefan Roese, DENX Software Engineering, sr@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+
+#if defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_BOARD_SETUP)
+#include <libfdt.h>
+#include <libfdt_env.h>
+#include <fdt_support.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+void __ft_board_setup(void *blob, bd_t *bd)
+{
+ ft_cpu_setup(blob, bd);
+}
+void ft_board_setup(void *blob, bd_t *bd) \
+ __attribute__((weak, alias("__ft_board_setup")));
+
+void ft_cpu_setup(void *blob, bd_t *bd)
+{
+ /*
+ * Fixup all ethernet nodes
+ * Note: aliases in the dts are required for this
+ */
+ fdt_fixup_ethernet(blob);
+}
+#endif /* CONFIG_OF_LIBFDT && CONFIG_OF_BOARD_SETUP */
diff --git a/arch/nios2/include/asm/gpio.h b/arch/nios2/include/asm/gpio.h
index 4b21c8f..908381f 100644
--- a/arch/nios2/include/asm/gpio.h
+++ b/arch/nios2/include/asm/gpio.h
@@ -5,8 +5,8 @@
* bit[0] data
* bit[1] output enable
*
- * when CONFIG_SYS_GPIO_BASE is not defined, board may provide
- * its own driver.
+ * When CONFIG_SYS_GPIO_BASE is not defined, the board may either
+ * provide its own driver or the altera_pio driver may be used.
*
* Copyright (C) 2010 Thomas Chou <thomas@wytron.com.tw>
*
@@ -58,6 +58,15 @@
return ((unsigned)number) < CONFIG_SYS_GPIO_WIDTH;
}
#else
+#ifdef CONFIG_ALTERA_PIO
+extern int altera_pio_init(u32 base, u8 width, char iot,
+ u32 rstval, u32 negmask,
+ const char *label);
+
+extern void altera_pio_info(void);
+#define gpio_status() altera_pio_info()
+#endif
+
extern int gpio_request(unsigned gpio, const char *label);
extern int gpio_free(unsigned gpio);
extern int gpio_direction_input(unsigned gpio);
diff --git a/arch/powerpc/cpu/mpc512x/i2c.c b/arch/powerpc/cpu/mpc512x/i2c.c
index e2d9097..0ea1280 100644
--- a/arch/powerpc/cpu/mpc512x/i2c.c
+++ b/arch/powerpc/cpu/mpc512x/i2c.c
@@ -78,9 +78,8 @@
status = mpc_reg_in (®s->msr);
while (timeout-- && (status & I2C_BB)) {
- volatile int temp;
mpc_reg_out (®s->mcr, I2C_STA, I2C_STA);
- temp = mpc_reg_in (®s->mdr);
+ (void)mpc_reg_in(®s->mdr);
mpc_reg_out (®s->mcr, 0, I2C_STA);
mpc_reg_out (®s->mcr, 0, 0);
mpc_reg_out (®s->mcr, I2C_EN, 0);
diff --git a/arch/powerpc/cpu/mpc512x/pci.c b/arch/powerpc/cpu/mpc512x/pci.c
index 141db8b..16f034d 100644
--- a/arch/powerpc/cpu/mpc512x/pci.c
+++ b/arch/powerpc/cpu/mpc512x/pci.c
@@ -52,7 +52,6 @@
volatile law512x_t *pci_law;
volatile pot512x_t *pci_pot;
volatile pcictrl512x_t *pci_ctrl;
- volatile pciconf512x_t *pci_conf;
u16 reg16;
u32 reg32;
u32 dev;
@@ -73,7 +72,6 @@
pci_law = im->sysconf.pcilaw;
pci_pot = im->ios.pot;
pci_ctrl = &im->pci_ctrl;
- pci_conf = &im->pci_conf;
hose = &pci_hose;
diff --git a/arch/powerpc/cpu/mpc83xx/spd_sdram.c b/arch/powerpc/cpu/mpc83xx/spd_sdram.c
index 3855bfd..04d519a 100644
--- a/arch/powerpc/cpu/mpc83xx/spd_sdram.c
+++ b/arch/powerpc/cpu/mpc83xx/spd_sdram.c
@@ -149,7 +149,7 @@
unsigned int memsize;
unsigned int law_size;
unsigned char caslat, caslat_ctrl;
- unsigned int trfc, trfc_clk, trfc_low, trfc_high;
+ unsigned int trfc, trfc_clk, trfc_low;
unsigned int trcd_clk, trtp_clk;
unsigned char cke_min_clk;
unsigned char add_lat, wr_lat;
@@ -542,7 +542,6 @@
* so preadjust it down 8 first before splitting it up.
*/
trfc_low = (trfc_clk - 8) & 0xf;
- trfc_high = ((trfc_clk - 8) >> 4) & 0x3;
ddr->timing_cfg_1 =
(((picos_to_clk(spd.trp * 250) & 0x07) << 28 ) | /* PRETOACT */
diff --git a/arch/powerpc/cpu/mpc85xx/cmd_errata.c b/arch/powerpc/cpu/mpc85xx/cmd_errata.c
index a09eb91..253bf08 100644
--- a/arch/powerpc/cpu/mpc85xx/cmd_errata.c
+++ b/arch/powerpc/cpu/mpc85xx/cmd_errata.c
@@ -103,6 +103,10 @@
#ifdef CONFIG_SYS_FSL_ERRATUM_NMG_LBC103
puts("Work-around for Erratum NMG_LBC103 enabled\n");
#endif
+#ifdef CONFIG_SYS_FSL_ERRATUM_NMG_ETSEC129
+ if ((SVR_MAJ(svr) == 1) || IS_SVR_REV(svr, 2, 0))
+ puts("Work-around for Erratum NMG ETSEC129 enabled\n");
+#endif
return 0;
}
diff --git a/arch/powerpc/cpu/mpc85xx/cpu_init.c b/arch/powerpc/cpu/mpc85xx/cpu_init.c
index 0a4ce53..b9a8193 100644
--- a/arch/powerpc/cpu/mpc85xx/cpu_init.c
+++ b/arch/powerpc/cpu/mpc85xx/cpu_init.c
@@ -317,7 +317,6 @@
volatile ccsr_l2cache_t *l2cache = (void *)CONFIG_SYS_MPC85xx_L2_ADDR;
volatile uint cache_ctl;
uint svr, ver;
- uint l2srbar;
u32 l2siz_field;
svr = get_svr();
@@ -385,8 +384,8 @@
if (l2cache->l2ctl & MPC85xx_L2CTL_L2E) {
puts("already enabled");
- l2srbar = l2cache->l2srbar0;
#if defined(CONFIG_SYS_INIT_L2_ADDR) && defined(CONFIG_SYS_FLASH_BASE)
+ u32 l2srbar = l2cache->l2srbar0;
if (l2cache->l2ctl & MPC85xx_L2CTL_L2SRAM_ENTIRE
&& l2srbar >= CONFIG_SYS_FLASH_BASE) {
l2srbar = CONFIG_SYS_INIT_L2_ADDR;
diff --git a/arch/powerpc/cpu/mpc85xx/cpu_init_early.c b/arch/powerpc/cpu/mpc85xx/cpu_init_early.c
index 4ef3c9a..091af7c 100644
--- a/arch/powerpc/cpu/mpc85xx/cpu_init_early.c
+++ b/arch/powerpc/cpu/mpc85xx/cpu_init_early.c
@@ -71,7 +71,7 @@
#endif
#if defined(CONFIG_SYS_FSL_ERRATUM_IFC_A003399) && !defined(CONFIG_SYS_RAMBOOT)
ccsr_l2cache_t *l2cache = (void *)CONFIG_SYS_MPC85xx_L2_ADDR;
- u32 *l2srbar, *dst, *src;
+ u32 *dst, *src;
void (*setup_ifc_sram)(void);
#endif
@@ -137,7 +137,7 @@
dst = (u32 *) SRAM_BASE_ADDR;
src = (u32 *) setup_ifc;
for (i = 0; i < 1024; i++)
- *l2srbar++ = *src++;
+ *dst++ = *src++;
setup_ifc_sram();
diff --git a/arch/powerpc/cpu/mpc85xx/fsl_corenet_serdes.c b/arch/powerpc/cpu/mpc85xx/fsl_corenet_serdes.c
index 89ed5b4..4b52dad 100644
--- a/arch/powerpc/cpu/mpc85xx/fsl_corenet_serdes.c
+++ b/arch/powerpc/cpu/mpc85xx/fsl_corenet_serdes.c
@@ -495,7 +495,6 @@
int cfg;
serdes_corenet_t *srds_regs;
int lane, bank, idx;
- enum srds_prtcl lane_prtcl;
int have_bank[SRDS_MAX_BANK] = {};
#ifdef CONFIG_SYS_P4080_ERRATUM_SERDES8
u32 serdes8_devdisr = 0;
@@ -507,6 +506,7 @@
#ifdef CONFIG_SYS_P4080_ERRATUM_SERDES_A001
int need_serdes_a001; /* TRUE == need work-around for SERDES A001 */
#endif
+#ifdef CONFIG_SYS_P4080_ERRATUM_SERDES8
char buffer[HWCONFIG_BUFFER_SIZE];
char *buf = NULL;
@@ -516,6 +516,7 @@
*/
if (getenv_f("hwconfig", buffer, sizeof(buffer)) > 0)
buf = buffer;
+#endif
/* Is serdes enabled at all? */
if (!(in_be32(&gur->rcwsr[5]) & FSL_CORENET_RCWSR5_SRDS_EN))
@@ -617,7 +618,10 @@
}
}
+#if defined(CONFIG_SYS_P4080_ERRATUM_SERDES8) || defined (CONFIG_SYS_P4080_ERRATUM_SERDES9)
for (lane = 0; lane < SRDS_MAX_LANES; lane++) {
+ enum srds_prtcl lane_prtcl;
+
idx = serdes_get_lane_idx(lane);
lane_prtcl = serdes_get_prtcl(cfg, lane);
@@ -729,6 +733,7 @@
#endif
}
+#endif
#ifdef DEBUG
puts("\n");
diff --git a/arch/powerpc/cpu/mpc85xx/start.S b/arch/powerpc/cpu/mpc85xx/start.S
index 5e0d78d..7bd5cc0 100644
--- a/arch/powerpc/cpu/mpc85xx/start.S
+++ b/arch/powerpc/cpu/mpc85xx/start.S
@@ -319,6 +319,55 @@
#endif /* CONFIG_MPC8569 */
/*
+ * Search for the TLB that covers the code we're executing, and shrink it
+ * so that it covers only this 4K page. That will ensure that any other
+ * TLB we create won't interfere with it. We assume that the TLB exists,
+ * which is why we don't check the Valid bit of MAS1.
+ *
+ * This is necessary, for example, when booting from the on-chip ROM,
+ * which (oddly) creates a single 4GB TLB that covers CCSR and DDR.
+ * If we don't shrink this TLB now, then we'll accidentally delete it
+ * in "purge_old_ccsr_tlb" below.
+ */
+ bl nexti /* Find our address */
+nexti: mflr r1 /* R1 = our PC */
+ li r2, 0
+ mtspr MAS6, r2 /* Assume the current PID and AS are 0 */
+ isync
+ msync
+ tlbsx 0, r1 /* This must succeed */
+
+ /* Set the size of the TLB to 4KB */
+ mfspr r3, MAS1
+ li r2, 0xF00
+ andc r3, r3, r2 /* Clear the TSIZE bits */
+ ori r3, r3, MAS1_TSIZE(BOOKE_PAGESZ_4K)@l
+ mtspr MAS1, r3
+
+ /*
+ * Set the base address of the TLB to our PC. We assume that
+ * virtual == physical. We also assume that MAS2_EPN == MAS3_RPN.
+ */
+ lis r3, MAS2_EPN@h
+ ori r3, r3, MAS2_EPN@l /* R3 = MAS2_EPN */
+
+ and r1, r1, r3 /* Our PC, rounded down to the nearest page */
+
+ mfspr r2, MAS2
+ andc r2, r2, r3
+ or r2, r2, r1
+ mtspr MAS2, r2 /* Set the EPN to our PC base address */
+
+ mfspr r2, MAS3
+ andc r2, r2, r3
+ or r2, r2, r1
+ mtspr MAS3, r2 /* Set the RPN to our PC base address */
+
+ isync
+ msync
+ tlbwe
+
+/*
* Relocate CCSR, if necessary. We relocate CCSR if (obviously) the default
* location is not where we want it. This typically happens on a 36-bit
* system, where we want to move CCSR to near the top of 36-bit address space.
@@ -352,6 +401,8 @@
li r1, 0
mtspr MAS6, r1 /* Search the current address space and PID */
+ isync
+ msync
tlbsx 0, r8
mfspr r1, MAS1
andis. r2, r1, MAS1_VALID@h /* Check for the Valid bit */
@@ -359,6 +410,8 @@
rlwinm r1, r1, 0, 1, 31 /* Clear Valid bit */
mtspr MAS1, r1
+ isync
+ msync
tlbwe
1:
@@ -387,7 +440,7 @@
tlbwe
/*
- * Create a TLB for the old location of CCSR. Register R9 is reserved
+ * Create a TLB for the current location of CCSR. Register R9 is reserved
* for the virtual address of this TLB (CONFIG_SYS_CCSRBAR + 0x1000).
*/
create_ccsr_old_tlb:
@@ -407,6 +460,33 @@
msync
tlbwe
+ /*
+ * We have a TLB for what we think is the current (old) CCSR. Let's
+ * verify that, otherwise we won't be able to move it.
+ * CONFIG_SYS_CCSRBAR_DEFAULT is always a 32-bit number, so we only
+ * need to compare the lower 32 bits of CCSRBAR on CoreNet systems.
+ */
+verify_old_ccsr:
+ lis r0, CONFIG_SYS_CCSRBAR_DEFAULT@h
+ ori r0, r0, CONFIG_SYS_CCSRBAR_DEFAULT@l
+#ifdef CONFIG_FSL_CORENET
+ lwz r1, 4(r9) /* CCSRBARL */
+#else
+ lwz r1, 0(r9) /* CCSRBAR, shifted right by 12 */
+ slwi r1, r1, 12
+#endif
+
+ cmpl 0, r0, r1
+
+ /*
+ * If the value we read from CCSRBARL is not what we expect, then
+ * enter an infinite loop. This will at least allow a debugger to
+ * halt execution and examine TLBs, etc. There's no point in going
+ * on.
+ */
+infinite_debug_loop:
+ bne infinite_debug_loop
+
#ifdef CONFIG_FSL_CORENET
#define CCSR_LAWBARH0 (CONFIG_SYS_CCSRBAR + 0x1000)
@@ -446,7 +526,7 @@
*/
read_old_ccsrbar:
lwz r0, 0(r9) /* CCSRBARH */
- lwz r0, 4(r9) /* CCSRBARH */
+ lwz r0, 4(r9) /* CCSRBARL */
isync
/*
diff --git a/arch/powerpc/cpu/mpc85xx/tlb.c b/arch/powerpc/cpu/mpc85xx/tlb.c
index 01a3561..929f6a6 100644
--- a/arch/powerpc/cpu/mpc85xx/tlb.c
+++ b/arch/powerpc/cpu/mpc85xx/tlb.c
@@ -172,7 +172,7 @@
void disable_tlb(u8 esel)
{
- u32 _mas0, _mas1, _mas2, _mas3, _mas7;
+ u32 _mas0, _mas1, _mas2, _mas3;
free_tlb_cam(esel);
@@ -180,14 +180,13 @@
_mas1 = 0;
_mas2 = 0;
_mas3 = 0;
- _mas7 = 0;
mtspr(MAS0, _mas0);
mtspr(MAS1, _mas1);
mtspr(MAS2, _mas2);
mtspr(MAS3, _mas3);
#ifdef CONFIG_ENABLE_36BIT_PHYS
- mtspr(MAS7, _mas7);
+ mtspr(MAS7, 0);
#endif
asm volatile("isync;msync;tlbwe;isync");
@@ -252,16 +251,20 @@
unsigned int tlb_size;
unsigned int wimge = 0;
unsigned int ram_tlb_address = (unsigned int)CONFIG_SYS_DDR_SDRAM_BASE;
- unsigned int max_cam = (mfspr(SPRN_TLB1CFG) >> 16) & 0xf;
+ unsigned int max_cam;
u64 size, memsize = (u64)memsize_in_meg << 20;
#ifdef CONFIG_SYS_PPC_DDR_WIMGE
wimge = CONFIG_SYS_PPC_DDR_WIMGE;
#endif
size = min(memsize, CONFIG_MAX_MEM_MAPPED);
-
- /* Convert (4^max) kB to (2^max) bytes */
- max_cam = max_cam * 2 + 10;
+ if ((mfspr(SPRN_MMUCFG) & MMUCFG_MAVN) == MMUCFG_MAVN_V1) {
+ /* Convert (4^max) kB to (2^max) bytes */
+ max_cam = ((mfspr(SPRN_TLB1CFG) >> 16) & 0xf) * 2 + 10;
+ } else {
+ /* Convert (2^max) kB to (2^max) bytes */
+ max_cam = __ilog2(mfspr(SPRN_TLB1PS)) + 10;
+ }
for (i = 0; size && i < 8; i++) {
int ram_tlb_index = find_free_tlbcam();
diff --git a/arch/powerpc/cpu/mpc8xx/video.c b/arch/powerpc/cpu/mpc8xx/video.c
index 7725c67..1bbf4cc 100644
--- a/arch/powerpc/cpu/mpc8xx/video.c
+++ b/arch/powerpc/cpu/mpc8xx/video.c
@@ -125,6 +125,7 @@
/************************************************************************/
#include <video_font.h> /* Get font data, width and height */
+#include <video_font_data.h>
#ifdef CONFIG_VIDEO_LOGO
#include <video_logo.h> /* Get logo data, width and height */
diff --git a/arch/powerpc/cpu/mpc8xxx/ddr/ctrl_regs.c b/arch/powerpc/cpu/mpc8xxx/ddr/ctrl_regs.c
index 15cd375..2067d53 100644
--- a/arch/powerpc/cpu/mpc8xxx/ddr/ctrl_regs.c
+++ b/arch/powerpc/cpu/mpc8xxx/ddr/ctrl_regs.c
@@ -672,7 +672,6 @@
rcw_en = 1;
ap_en = popts->ap_en;
} else {
- rcw_en = 0;
ap_en = 0;
}
@@ -702,9 +701,7 @@
| ((obc_cfg & 0x1) << 6)
| ((ap_en & 0x1) << 5)
| ((d_init & 0x1) << 4)
-#ifdef CONFIG_FSL_DDR3
| ((rcw_en & 0x1) << 2)
-#endif
| ((md_en & 0x1) << 0)
);
debug("FSLDDR: ddr_sdram_cfg_2 = 0x%08x\n", ddr->ddr_sdram_cfg_2);
@@ -745,7 +742,7 @@
#ifdef CONFIG_FSL_DDR3
if (unq_mrs_en) { /* unique mode registers are supported */
- for (i = 1; i < 4; i++) {
+ for (i = 1; i < CONFIG_CHIP_SELECTS_PER_CTRL; i++) {
if (popts->rtt_override)
rtt_wr = popts->rtt_wr_override_value;
else
@@ -944,7 +941,7 @@
debug("FSLDDR: ddr_sdram_mode = 0x%08x\n", ddr->ddr_sdram_mode);
if (unq_mrs_en) { /* unique mode registers are supported */
- for (i = 1; i < 4; i++) {
+ for (i = 1; i < CONFIG_CHIP_SELECTS_PER_CTRL; i++) {
if (popts->rtt_override)
rtt = popts->rtt_override_value;
else
diff --git a/arch/powerpc/cpu/mpc8xxx/ddr/options.c b/arch/powerpc/cpu/mpc8xxx/ddr/options.c
index 4dc748b..00ec57b 100644
--- a/arch/powerpc/cpu/mpc8xxx/ddr/options.c
+++ b/arch/powerpc/cpu/mpc8xxx/ddr/options.c
@@ -483,7 +483,9 @@
unsigned int i;
char buffer[HWCONFIG_BUFFER_SIZE];
char *buf = NULL;
+#if defined(CONFIG_FSL_DDR3) || defined(CONFIG_FSL_DDR2)
const struct dynamic_odt *pdodt = odt_unknown;
+#endif
ulong ddr_freq;
/*
@@ -493,6 +495,7 @@
if (getenv_f("hwconfig", buffer, sizeof(buffer)) > 0)
buf = buffer;
+#if defined(CONFIG_FSL_DDR3) || defined(CONFIG_FSL_DDR2)
/* Chip select options. */
if (CONFIG_DIMM_SLOTS_PER_CTLR == 1) {
switch (pdimm[0].n_ranks) {
@@ -546,6 +549,7 @@
break;
}
}
+#endif
/* Pick chip-select local options. */
for (i = 0; i < CONFIG_CHIP_SELECTS_PER_CTRL; i++) {
diff --git a/arch/powerpc/cpu/mpc8xxx/fdt.c b/arch/powerpc/cpu/mpc8xxx/fdt.c
index 112c603..d07ae1b 100644
--- a/arch/powerpc/cpu/mpc8xxx/fdt.c
+++ b/arch/powerpc/cpu/mpc8xxx/fdt.c
@@ -87,13 +87,12 @@
#endif /* defined(CONFIG_MPC85xx) || defined(CONFIG_MPC86xx) */
#ifdef CONFIG_HAS_FSL_DR_USB
-static void fdt_fixup_usb_mode_phy_type(void *blob, const char *mode,
- const char *phy_type)
+static int fdt_fixup_usb_mode_phy_type(void *blob, const char *mode,
+ const char *phy_type, int start_offset)
{
const char *compat = "fsl-usb2-dr";
const char *prop_mode = "dr_mode";
const char *prop_type = "phy_type";
- static int start_offset = -1;
int node_offset;
int err;
@@ -102,7 +101,7 @@
if (node_offset < 0) {
printf("WARNING: could not find compatible node %s: %s.\n",
compat, fdt_strerror(node_offset));
- return;
+ return -1;
}
if (mode) {
@@ -121,16 +120,18 @@
prop_type, compat, fdt_strerror(err));
}
- start_offset = node_offset;
+ return node_offset;
}
void fdt_fixup_dr_usb(void *blob, bd_t *bd)
{
const char *modes[] = { "host", "peripheral", "otg" };
- const char *phys[] = { "ulpi", "umti" };
+ const char *phys[] = { "ulpi", "utmi" };
const char *mode = NULL;
const char *phy_type = NULL;
char usb1_defined = 0;
+ int usb_mode_off = -1;
+ int usb_phy_off = -1;
char str[5];
int i, j;
@@ -153,11 +154,11 @@
}
}
if (mode_idx >= 0)
- fdt_fixup_usb_mode_phy_type(blob,
- modes[mode_idx], NULL);
+ usb_mode_off = fdt_fixup_usb_mode_phy_type(blob,
+ modes[mode_idx], NULL, usb_mode_off);
if (phy_idx >= 0)
- fdt_fixup_usb_mode_phy_type(blob,
- NULL, phys[phy_idx]);
+ usb_phy_off = fdt_fixup_usb_mode_phy_type(blob,
+ NULL, phys[phy_idx], usb_phy_off);
if (!strcmp(str, "usb1"))
usb1_defined = 1;
if (mode_idx < 0 && phy_idx < 0)
@@ -165,11 +166,12 @@
}
}
if (!usb1_defined) {
+ int usb_off = -1;
mode = getenv("usb_dr_mode");
phy_type = getenv("usb_phy_type");
if (!mode && !phy_type)
return;
- fdt_fixup_usb_mode_phy_type(blob, mode, phy_type);
+ fdt_fixup_usb_mode_phy_type(blob, mode, phy_type, usb_off);
}
}
#endif /* CONFIG_HAS_FSL_DR_USB */
diff --git a/arch/powerpc/cpu/mpc8xxx/fsl_lbc.c b/arch/powerpc/cpu/mpc8xxx/fsl_lbc.c
index d78962f..587576b 100644
--- a/arch/powerpc/cpu/mpc8xxx/fsl_lbc.c
+++ b/arch/powerpc/cpu/mpc8xxx/fsl_lbc.c
@@ -107,7 +107,7 @@
void upmconfig(uint upm, uint *table, uint size)
{
fsl_lbc_t *lbc = LBC_BASE_ADDR;
- int i, mdr, mad, old_mad = 0;
+ int i, mad, old_mad = 0;
u32 mask = (~MxMR_OP_MSK & ~MxMR_MAD_MSK);
u32 msel = BR_UPMx_TO_MSEL(upm);
u32 *mxmr = &lbc->mamr + upm;
@@ -138,7 +138,7 @@
for (i = 0; i < size; i++) {
out_be32(mxmr, (in_be32(mxmr) & mask) | MxMR_OP_WARR | i);
out_be32(&lbc->mdr, table[i]);
- mdr = in_be32(&lbc->mdr);
+ (void)in_be32(&lbc->mdr);
*dummy = 0;
do {
mad = in_be32(mxmr) & MxMR_MAD_MSK;
diff --git a/arch/powerpc/cpu/ppc4xx/40x_spd_sdram.c b/arch/powerpc/cpu/ppc4xx/40x_spd_sdram.c
index a31b17e..48aa753 100644
--- a/arch/powerpc/cpu/ppc4xx/40x_spd_sdram.c
+++ b/arch/powerpc/cpu/ppc4xx/40x_spd_sdram.c
@@ -116,26 +116,25 @@
{
int tmp,row,col;
int total_size,bank_size,bank_code;
- int ecc_on;
int mode;
int bank_cnt;
int sdram0_pmit=0x07c00000;
+ int sdram0_b0cr;
+ int sdram0_b1cr = 0;
#ifndef CONFIG_405EP /* not on PPC405EP */
+ int sdram0_b2cr = 0;
+ int sdram0_b3cr = 0;
int sdram0_besr0 = -1;
int sdram0_besr1 = -1;
int sdram0_eccesr = -1;
-#endif
int sdram0_ecccfg;
+ int ecc_on;
+#endif
int sdram0_rtr=0;
int sdram0_tr=0;
- int sdram0_b0cr;
- int sdram0_b1cr;
- int sdram0_b2cr;
- int sdram0_b3cr;
-
int sdram0_cfg=0;
int t_rp;
@@ -295,6 +294,7 @@
if (bank_cnt > 4) /* we only have 4 banks to work with */
SPD_ERR("SDRAM - unsupported module rows for this width\n");
+#ifndef CONFIG_405EP /* not on PPC405EP */
/* now check for ECC ability of module. We only support ECC
* on 32 bit wide devices with 8 bit ECC.
*/
@@ -305,6 +305,7 @@
sdram0_ecccfg = 0;
ecc_on = 0;
}
+#endif
/*------------------------------------------------------------------
* calculate total size
@@ -378,9 +379,6 @@
* using the calculated values, compute the bank
* config register values.
* -------------------------------------------------------------------*/
- sdram0_b1cr = 0;
- sdram0_b2cr = 0;
- sdram0_b3cr = 0;
/* compute the size of each bank */
bank_size = total_size / bank_cnt;
@@ -444,8 +442,10 @@
/* SDRAM have a power on delay, 500 micro should do */
udelay(500);
sdram0_cfg = SDRAM0_CFG_DCE | SDRAM0_CFG_BRPF(1) | SDRAM0_CFG_ECCDD | SDRAM0_CFG_EMDULR;
+#ifndef CONFIG_405EP /* not on PPC405EP */
if (ecc_on)
sdram0_cfg |= SDRAM0_CFG_MEMCHK;
+#endif
mtsdram(SDRAM0_CFG, sdram0_cfg);
return (total_size);
diff --git a/arch/powerpc/cpu/ppc4xx/44x_spd_ddr.c b/arch/powerpc/cpu/ppc4xx/44x_spd_ddr.c
index e05daf2..8a20a2b 100644
--- a/arch/powerpc/cpu/ppc4xx/44x_spd_ddr.c
+++ b/arch/powerpc/cpu/ppc4xx/44x_spd_ddr.c
@@ -380,8 +380,6 @@
unsigned char ecc;
unsigned char attributes;
unsigned long data_width;
- unsigned long dimm_32bit;
- unsigned long dimm_64bit;
/*
* get Memory Controller Options 0 data
@@ -423,10 +421,8 @@
(unsigned long)spd_read(iic0_dimm_addr[dimm_num],6) +
(((unsigned long)spd_read(iic0_dimm_addr[dimm_num],7)) << 8);
if (data_width == 64 || data_width == 72) {
- dimm_64bit = TRUE;
cfg0 |= SDRAM_CFG0_DMWD_64;
} else if (data_width == 32 || data_width == 40) {
- dimm_32bit = TRUE;
cfg0 |= SDRAM_CFG0_DMWD_32;
} else {
printf("WARNING: DIMM with datawidth of %lu bits.\n",
diff --git a/arch/powerpc/cpu/ppc4xx/44x_spd_ddr2.c b/arch/powerpc/cpu/ppc4xx/44x_spd_ddr2.c
index 4a2f337..85217ea 100644
--- a/arch/powerpc/cpu/ppc4xx/44x_spd_ddr2.c
+++ b/arch/powerpc/cpu/ppc4xx/44x_spd_ddr2.c
@@ -445,9 +445,6 @@
phys_size_t initdram(int board_type)
{
unsigned char iic0_dimm_addr[] = SPD_EEPROM_ADDRESS;
- unsigned char spd0[MAX_SPD_BYTES];
- unsigned char spd1[MAX_SPD_BYTES];
- unsigned char *dimm_spd[MAXDIMMS];
unsigned long dimm_populated[MAXDIMMS] = {SDRAM_NONE, SDRAM_NONE};
unsigned long num_dimm_banks; /* on board dimm banks */
unsigned long val;
@@ -458,12 +455,6 @@
num_dimm_banks = sizeof(iic0_dimm_addr);
/*------------------------------------------------------------------
- * Set up an array of SPD matrixes.
- *-----------------------------------------------------------------*/
- dimm_spd[0] = spd0;
- dimm_spd[1] = spd1;
-
- /*------------------------------------------------------------------
* Reset the DDR-SDRAM controller.
*-----------------------------------------------------------------*/
mtsdr(SDR0_SRST, SDR0_SRST0_DMC);
@@ -1000,7 +991,6 @@
unsigned long attribute = 0;
unsigned long buf0, buf1; /* TODO: code to be changed for IOP1.6 to support 4 DIMMs */
unsigned long bankcount;
- unsigned long ddrtype;
unsigned long val;
#ifdef CONFIG_DDR_ECC
@@ -1045,8 +1035,6 @@
else /* bank count = 8 */
mcopt1 |= SDRAM_MCOPT1_8_BANKS;
- /* test DDR type */
- ddrtype = (unsigned long)spd_read(iic0_dimm_addr[dimm_num], 2);
/* test for buffered/unbuffered, registered, differential clocks */
registered = (unsigned long)spd_read(iic0_dimm_addr[dimm_num], 20);
attribute = (unsigned long)spd_read(iic0_dimm_addr[dimm_num], 21);
@@ -1500,7 +1488,6 @@
else
sdram_ddr1 = FALSE;
- /* t_wr_ns = max(t_wr_ns, (unsigned long)dimm_spd[dimm_num][36] >> 2); */ /* not used in this loop. */
cas_bit = spd_read(iic0_dimm_addr[dimm_num], 18);
debug("cas_bit[SPD byte 18]=%02lx\n", cas_bit);
@@ -2490,12 +2477,6 @@
unsigned long val;
long rffd_average;
long max_start;
- long min_end;
- unsigned long begin_rqfd[MAXRANKS];
- unsigned long begin_rffd[MAXRANKS];
- unsigned long end_rqfd[MAXRANKS];
- unsigned long end_rffd[MAXRANKS];
- char window_found;
unsigned long dlycal;
unsigned long dly_val;
unsigned long max_pass_length;
@@ -2506,6 +2487,7 @@
unsigned char fail_found;
unsigned char pass_found;
#if !defined(CONFIG_DDR_RQDC_FIXED)
+ int window_found;
u32 rqdc_reg;
u32 rqfd;
u32 rqfd_start;
@@ -2559,16 +2541,6 @@
#endif /* CONFIG_DDR_RQDC_FIXED */
max_start = 0;
- min_end = 0;
- begin_rqfd[0] = 0;
- begin_rffd[0] = 0;
- begin_rqfd[1] = 0;
- begin_rffd[1] = 0;
- end_rqfd[0] = 0;
- end_rffd[0] = 0;
- end_rqfd[1] = 0;
- end_rffd[1] = 0;
- window_found = FALSE;
max_pass_length = 0;
max_start = 0;
@@ -2576,7 +2548,6 @@
current_pass_length = 0;
current_fail_length = 0;
current_start = 0;
- window_found = FALSE;
fail_found = FALSE;
pass_found = FALSE;
@@ -2621,7 +2592,6 @@
if (fail_found == FALSE) {
fail_found = TRUE;
} else if (pass_found == TRUE) {
- window_found = TRUE;
break;
}
}
diff --git a/arch/powerpc/cpu/ppc4xx/4xx_ibm_ddr2_autocalib.c b/arch/powerpc/cpu/ppc4xx/4xx_ibm_ddr2_autocalib.c
index 4b8e65a..3c87bfb 100644
--- a/arch/powerpc/cpu/ppc4xx/4xx_ibm_ddr2_autocalib.c
+++ b/arch/powerpc/cpu/ppc4xx/4xx_ibm_ddr2_autocalib.c
@@ -154,18 +154,20 @@
static u32 *get_membase(int bxcr_num)
{
- ulong bxcf;
u32 *membase;
#if defined(SDRAM_R0BAS)
/* BAS from Memory Queue rank reg. */
membase =
(u32 *)(SDRAM_RXBAS_SDBA_DECODE(mfdcr_any(SDRAM_R0BAS+bxcr_num)));
- bxcf = 0; /* just to satisfy the compiler */
#else
- /* BAS from SDRAM_MBxCF mem rank reg. */
- mfsdram(SDRAM_MB0CF + (bxcr_num<<2), bxcf);
- membase = (u32 *)((bxcf & 0xfff80000) << 3);
+ {
+ ulong bxcf;
+
+ /* BAS from SDRAM_MBxCF mem rank reg. */
+ mfsdram(SDRAM_MB0CF + (bxcr_num<<2), bxcf);
+ membase = (u32 *)((bxcf & 0xfff80000) << 3);
+ }
#endif
return membase;
@@ -719,7 +721,9 @@
static u32 DQS_calibration_methodB(struct ddrautocal *cal)
{
ulong rfdc_reg;
+#ifndef CONFIG_DDR_RFDC_FIXED
ulong rffd;
+#endif
ulong rqdc_reg;
ulong rqfd;
@@ -837,7 +841,6 @@
mtsdram(SDRAM_RFDC, rfdc_reg | SDRAM_RFDC_RFFD_ENCODE(rffd_average));
#endif /* CONFIG_DDR_RFDC_FIXED */
- rffd = rffd_average;
in_window = 0;
curr_win_min = curr_win_max = 0;
diff --git a/arch/powerpc/cpu/ppc4xx/4xx_pcie.c b/arch/powerpc/cpu/ppc4xx/4xx_pcie.c
index a87e93b..43b972f 100644
--- a/arch/powerpc/cpu/ppc4xx/4xx_pcie.c
+++ b/arch/powerpc/cpu/ppc4xx/4xx_pcie.c
@@ -227,7 +227,6 @@
static int pcie_read_config(struct pci_controller *hose, unsigned int devfn,
int offset, int len, u32 *val) {
- u8 *address;
*val = 0;
if (validate_endpoint(hose))
@@ -255,7 +254,7 @@
((PCI_BUS(devfn) == 0) || (PCI_BUS(devfn) == 1)))
return 0;
- address = pcie_get_base(hose, devfn);
+ pcie_get_base(hose, devfn);
offset += devfn << 4;
/*
@@ -287,8 +286,6 @@
static int pcie_write_config(struct pci_controller *hose, unsigned int devfn,
int offset, int len, u32 val) {
- u8 *address;
-
if (validate_endpoint(hose))
return 0; /* No upstream config access */
@@ -307,7 +304,7 @@
((PCI_BUS(devfn) == 0) || (PCI_BUS(devfn) == 1)))
return 0;
- address = pcie_get_base(hose, devfn);
+ pcie_get_base(hose, devfn);
offset += devfn << 4;
/*
@@ -1063,7 +1060,6 @@
void ppc4xx_setup_pcie_rootpoint(struct pci_controller *hose, int port)
{
volatile void *mbase = NULL;
- volatile void *rmbase = NULL;
pci_set_ops(hose,
pcie_read_config_byte,
@@ -1076,18 +1072,15 @@
switch (port) {
case 0:
mbase = (u32 *)CONFIG_SYS_PCIE0_XCFGBASE;
- rmbase = (u32 *)CONFIG_SYS_PCIE0_CFGBASE;
hose->cfg_data = (u8 *)CONFIG_SYS_PCIE0_CFGBASE;
break;
case 1:
mbase = (u32 *)CONFIG_SYS_PCIE1_XCFGBASE;
- rmbase = (u32 *)CONFIG_SYS_PCIE1_CFGBASE;
hose->cfg_data = (u8 *)CONFIG_SYS_PCIE1_CFGBASE;
break;
#if CONFIG_SYS_PCIE_NR_PORTS > 2
case 2:
mbase = (u32 *)CONFIG_SYS_PCIE2_XCFGBASE;
- rmbase = (u32 *)CONFIG_SYS_PCIE2_CFGBASE;
hose->cfg_data = (u8 *)CONFIG_SYS_PCIE2_CFGBASE;
break;
#endif
diff --git a/arch/powerpc/cpu/ppc4xx/cmd_ecctest.c b/arch/powerpc/cpu/ppc4xx/cmd_ecctest.c
index 542ab69..231f69e 100644
--- a/arch/powerpc/cpu/ppc4xx/cmd_ecctest.c
+++ b/arch/powerpc/cpu/ppc4xx/cmd_ecctest.c
@@ -113,8 +113,6 @@
*/
static void inject_ecc_error(void *ptr, int par)
{
- u32 val;
-
/*
* Taken from PPC460EX/EXr/GT users manual (Rev 1.21)
* 22.2.17.13 ECC Diagnostics
@@ -124,7 +122,7 @@
*/
out_be32(ptr, 0x00000000);
- val = in_be32(ptr);
+ in_be32(ptr);
/* 6. Set memory controller to no error checking */
set_mcopt1_mchk(SDRAM_MCOPT1_MCHK_NON);
@@ -136,7 +134,7 @@
out_be32(ptr, in_be32(ptr) ^ 0x00000003);
/* 8. Wait for SDRAM idle */
- val = in_be32(ptr);
+ in_be32(ptr);
set_mcopt1_mchk(SDRAM_MCOPT1_MCHK_CHK_REP);
/* Wait for SDRAM idle */
@@ -151,7 +149,6 @@
u32 end_address;
u32 address_increment;
u32 mcopt1;
- u32 val;
/*
* Fill ECC parity byte again. Otherwise further accesses to
@@ -159,7 +156,7 @@
*/
/* Wait for SDRAM idle */
- val = in_be32(0x00000000);
+ in_be32(0x00000000);
set_mcopt1_mchk(SDRAM_MCOPT1_MCHK_GEN);
/* ECC bit set method for non-cached memory */
diff --git a/arch/powerpc/cpu/ppc4xx/iop480_uart.c b/arch/powerpc/cpu/ppc4xx/iop480_uart.c
index 0e3423f..027ca30 100644
--- a/arch/powerpc/cpu/ppc4xx/iop480_uart.c
+++ b/arch/powerpc/cpu/ppc4xx/iop480_uart.c
@@ -134,7 +134,6 @@
int serial_init (void)
{
- volatile char val;
unsigned short br_reg;
br_reg = ((((CONFIG_CPUCLOCK * 1000000) / 16) / gd->baudrate) - 1);
@@ -149,7 +148,7 @@
out_8((u8 *)SPU_BASE + spu_RxCmd, 0xb0); /* Enable Rx */
out_8((u8 *)SPU_BASE + spu_TxCmd, 0x9c); /* Enable Tx */
out_8((u8 *)SPU_BASE + spu_Handshk_rc, 0xff); /* Clear Handshake */
- val = in_8((u8 *)SPU_BASE + spu_RxBuff); /* Dummy read, to clear receiver */
+ in_8((u8 *)SPU_BASE + spu_RxBuff); /* Dummy read, to clear receiver */
return (0);
}
diff --git a/arch/powerpc/cpu/ppc4xx/usb_ohci.c b/arch/powerpc/cpu/ppc4xx/usb_ohci.c
index fe091e3..065730d 100644
--- a/arch/powerpc/cpu/ppc4xx/usb_ohci.c
+++ b/arch/powerpc/cpu/ppc4xx/usb_ohci.c
@@ -753,10 +753,9 @@
static void dl_transfer_length(td_t * td)
{
- __u32 tdINFO, tdBE, tdCBP;
+ __u32 tdBE, tdCBP;
urb_priv_t *lurb_priv = &urb_priv;
- tdINFO = ohci_cpu_to_le32 (td->hwINFO);
tdBE = ohci_cpu_to_le32 (td->hwBE);
tdCBP = ohci_cpu_to_le32 (td->hwCBP);
diff --git a/arch/powerpc/include/asm/config_mpc85xx.h b/arch/powerpc/include/asm/config_mpc85xx.h
index c3d6ba9..981d639 100644
--- a/arch/powerpc/include/asm/config_mpc85xx.h
+++ b/arch/powerpc/include/asm/config_mpc85xx.h
@@ -64,6 +64,7 @@
#define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000
#define CONFIG_SYS_FSL_ERRATUM_NMG_DDR120
#define CONFIG_SYS_FSL_ERRATUM_NMG_LBC103
+#define CONFIG_SYS_FSL_ERRATUM_NMG_ETSEC129
#elif defined(CONFIG_MPC8555)
#define CONFIG_MAX_CPUS 1
diff --git a/arch/powerpc/include/asm/mmu.h b/arch/powerpc/include/asm/mmu.h
index ef5076b..209103e 100644
--- a/arch/powerpc/include/asm/mmu.h
+++ b/arch/powerpc/include/asm/mmu.h
@@ -392,17 +392,17 @@
*/
#define MAS0_TLBSEL_MSK 0x30000000
-#define MAS0_TLBSEL(x) ((x << 28) & MAS0_TLBSEL_MSK)
+#define MAS0_TLBSEL(x) (((x) << 28) & MAS0_TLBSEL_MSK)
#define MAS0_ESEL_MSK 0x0FFF0000
-#define MAS0_ESEL(x) ((x << 16) & MAS0_ESEL_MSK)
+#define MAS0_ESEL(x) (((x) << 16) & MAS0_ESEL_MSK)
#define MAS0_NV(x) ((x) & 0x00000FFF)
#define MAS1_VALID 0x80000000
#define MAS1_IPROT 0x40000000
-#define MAS1_TID(x) ((x << 16) & 0x3FFF0000)
+#define MAS1_TID(x) (((x) << 16) & 0x3FFF0000)
#define MAS1_TS 0x00001000
-#define MAS1_TSIZE(x) ((x << 8) & 0x00000F00)
-#define TSIZE_TO_BYTES(x) ((phys_addr_t)(1UL << ((tsize * 2) + 10)))
+#define MAS1_TSIZE(x) (((x) << 8) & 0x00000F00)
+#define TSIZE_TO_BYTES(x) (1ULL << (((x) * 2) + 10))
#define MAS2_EPN 0xFFFFF000
#define MAS2_X0 0x00000040
diff --git a/arch/powerpc/include/asm/processor.h b/arch/powerpc/include/asm/processor.h
index 1b96b84..4e32639 100644
--- a/arch/powerpc/include/asm/processor.h
+++ b/arch/powerpc/include/asm/processor.h
@@ -513,7 +513,13 @@
#define SPRN_TLB0CFG 0x2B0 /* TLB 0 Config Register */
#define SPRN_TLB1CFG 0x2B1 /* TLB 1 Config Register */
+#define SPRN_TLB0PS 0x158 /* TLB 0 Page Size Register */
+#define SPRN_TLB1PS 0x159 /* TLB 1 Page Size Register */
#define SPRN_MMUCSR0 0x3f4 /* MMU control and status register 0 */
+#define SPRN_MMUCFG 0x3F7 /* MMU Configuration Register */
+#define MMUCFG_MAVN 0x00000003 /* MMU Architecture Version Number */
+#define MMUCFG_MAVN_V1 0x00000000 /* v1.0 */
+#define MMUCFG_MAVN_V2 0x00000001 /* v2.0 */
#define SPRN_MAS0 0x270 /* MMU Assist Register 0 */
#define SPRN_MAS1 0x271 /* MMU Assist Register 1 */
#define SPRN_MAS2 0x272 /* MMU Assist Register 2 */
diff --git a/board/csb226/Makefile b/board/AndesTech/adp-ag101p/Makefile
similarity index 78%
copy from board/csb226/Makefile
copy to board/AndesTech/adp-ag101p/Makefile
index 6fe9bec..03c3ff4 100644
--- a/board/csb226/Makefile
+++ b/board/AndesTech/adp-ag101p/Makefile
@@ -1,6 +1,7 @@
#
-# (C) Copyright 2000-2006
-# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+# Copyright (C) 2011 Andes Technology Corporation
+# Shawn Lin, Andes Technology Corporation <nobuhiro@andestech.com>
+# Macpaul Lin, Andes Technology Corporation <macpaul@andestech.com>
#
# See file CREDITS for list of people who contributed to this
# project.
@@ -25,12 +26,12 @@
LIB = $(obj)lib$(BOARD).o
-COBJS := csb226.o flash.o
+COBJS := adp-ag101p.o
-SRCS := $(COBJS:.o=.c)
-OBJS := $(addprefix $(obj),$(COBJS))
+SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c)
+OBJS := $(addprefix $(obj),$(COBJS) $(SOBJS))
-$(LIB): $(obj).depend $(OBJS)
+$(LIB): $(OBJS)
$(call cmd_link_o_target, $(OBJS))
#########################################################################
diff --git a/board/AndesTech/adp-ag101p/adp-ag101p.c b/board/AndesTech/adp-ag101p/adp-ag101p.c
new file mode 100644
index 0000000..8dd2043
--- /dev/null
+++ b/board/AndesTech/adp-ag101p/adp-ag101p.c
@@ -0,0 +1,89 @@
+/*
+ * Copyright (C) 2011 Andes Technology Corporation
+ * Shawn Lin, Andes Technology Corporation <nobuhiro@andestech.com>
+ * Macpaul Lin, Andes Technology Corporation <macpaul@andestech.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
+ */
+
+#include <common.h>
+#include <netdev.h>
+#include <asm/io.h>
+
+#include <faraday/ftsdc010.h>
+#include <faraday/ftsmc020.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+/*
+ * Miscellaneous platform dependent initializations
+ */
+
+int board_init(void)
+{
+ /*
+ * refer to BOOT_PARAMETER_PA_BASE within
+ * "linux/arch/nds32/include/asm/misc_spec.h"
+ */
+ gd->bd->bi_arch_number = MACH_TYPE_ADPAG101P;
+ gd->bd->bi_boot_params = PHYS_SDRAM_0 + 0x400;
+
+ ftsmc020_init(); /* initialize Flash */
+ return 0;
+}
+
+int dram_init(void)
+{
+ unsigned long sdram_base = PHYS_SDRAM_0;
+ unsigned long expected_size = PHYS_SDRAM_0_SIZE;
+ unsigned long actual_size;
+
+ actual_size = get_ram_size((void *)sdram_base, expected_size);
+
+ gd->ram_size = actual_size;
+
+ if (expected_size != actual_size) {
+ printf("Warning: Only %lu of %lu MiB SDRAM is working\n",
+ actual_size >> 20, expected_size >> 20);
+ }
+
+ return 0;
+}
+
+int board_eth_init(bd_t *bd)
+{
+ return ftmac100_initialize(bd);
+}
+
+ulong board_flash_get_legacy(ulong base, int banknum, flash_info_t *info)
+{
+ if (banknum == 0) { /* non-CFI boot flash */
+ info->portwidth = FLASH_CFI_8BIT;
+ info->chipwidth = FLASH_CFI_BY8;
+ info->interface = FLASH_CFI_X8;
+ return 1;
+ } else {
+ return 0;
+ }
+}
+
+int board_mmc_init(bd_t *bis)
+{
+ ftsdc010_mmc_init(0);
+ return 0;
+}
diff --git a/board/altera/nios2-generic/Makefile b/board/altera/nios2-generic/Makefile
index 359f590..59fd465 100644
--- a/board/altera/nios2-generic/Makefile
+++ b/board/altera/nios2-generic/Makefile
@@ -32,7 +32,6 @@
COBJS-y := $(BOARD).o
COBJS-$(CONFIG_CMD_IDE) += ../common/cfide.o
COBJS-$(CONFIG_EPLED) += ../common/epled.o
-COBJS-$(CONFIG_GPIO) += gpio.o
COBJS-$(CONFIG_SEVENSEG) += ../common/sevenseg.o
SOBJS-y := text_base.o
diff --git a/board/altera/nios2-generic/custom_fpga.h b/board/altera/nios2-generic/custom_fpga.h
index f7f3853..fd3ec9a 100644
--- a/board/altera/nios2-generic/custom_fpga.h
+++ b/board/altera/nios2-generic/custom_fpga.h
@@ -51,6 +51,7 @@
/* led_pio.s1 is a altera_avalon_pio */
#define LED_PIO_BASE 0x82120870
#define LED_PIO_WIDTH 8
+#define LED_PIO_RSTVAL 0x0
/* high_res_timer.s1 is a altera_avalon_timer */
#define CONFIG_SYS_TIMER_BASE 0x82120820
diff --git a/board/altera/nios2-generic/gpio.c b/board/altera/nios2-generic/gpio.c
deleted file mode 100644
index 4a30564..0000000
--- a/board/altera/nios2-generic/gpio.c
+++ /dev/null
@@ -1,71 +0,0 @@
-/*
- * board gpio driver
- *
- * Copyright (C) 2010 Thomas Chou <thomas@wytron.com.tw>
- * Licensed under the GPL-2 or later.
- */
-#include <common.h>
-#include <asm/io.h>
-
-#ifndef CONFIG_SYS_GPIO_BASE
-
-#define ALTERA_PIO_BASE LED_PIO_BASE
-#define ALTERA_PIO_WIDTH LED_PIO_WIDTH
-#define ALTERA_PIO_DATA (ALTERA_PIO_BASE + 0)
-#define ALTERA_PIO_DIR (ALTERA_PIO_BASE + 4)
-static u32 pio_data_reg;
-static u32 pio_dir_reg;
-
-int gpio_request(unsigned gpio, const char *label)
-{
- return 0;
-}
-
-int gpio_free(unsigned gpio)
-{
- return 0;
-}
-
-int gpio_direction_input(unsigned gpio)
-{
- u32 mask = 1 << gpio;
- writel(pio_dir_reg &= ~mask, ALTERA_PIO_DIR);
- return 0;
-}
-
-int gpio_direction_output(unsigned gpio, int value)
-{
- u32 mask = 1 << gpio;
- if (value)
- pio_data_reg |= mask;
- else
- pio_data_reg &= ~mask;
- writel(pio_data_reg, ALTERA_PIO_DATA);
- writel(pio_dir_reg |= mask, ALTERA_PIO_DIR);
- return 0;
-}
-
-int gpio_get_value(unsigned gpio)
-{
- u32 mask = 1 << gpio;
- if (pio_dir_reg & mask)
- return (pio_data_reg & mask) ? 1 : 0;
- else
- return (readl(ALTERA_PIO_DATA) & mask) ? 1 : 0;
-}
-
-void gpio_set_value(unsigned gpio, int value)
-{
- u32 mask = 1 << gpio;
- if (value)
- pio_data_reg |= mask;
- else
- pio_data_reg &= ~mask;
- writel(pio_data_reg, ALTERA_PIO_DATA);
-}
-
-int gpio_is_valid(int number)
-{
- return ((unsigned)number) < ALTERA_PIO_WIDTH;
-}
-#endif
diff --git a/board/altera/nios2-generic/nios2-generic.c b/board/altera/nios2-generic/nios2-generic.c
index 49ef80d..0f88275 100644
--- a/board/altera/nios2-generic/nios2-generic.c
+++ b/board/altera/nios2-generic/nios2-generic.c
@@ -26,6 +26,7 @@
#include <netdev.h>
#include <mtd/cfi_flash.h>
#include <asm/io.h>
+#include <asm/gpio.h>
void text_base_hook(void); /* nop hook for text_base.S */
@@ -43,6 +44,13 @@
int board_early_init_f(void)
{
text_base_hook();
+#ifdef CONFIG_ALTERA_PIO
+#ifdef LED_PIO_BASE
+ altera_pio_init(LED_PIO_BASE, LED_PIO_WIDTH, 'o',
+ LED_PIO_RSTVAL, (1 << LED_PIO_WIDTH) - 1,
+ "led");
+#endif
+#endif
#if defined(CONFIG_ENV_IS_IN_FLASH) && defined(CONFIG_ENV_ADDR)
early_flash_cmd_reset();
#endif
diff --git a/board/amcc/yucca/cmd_yucca.c b/board/amcc/yucca/cmd_yucca.c
index e9cd333..f45325e 100644
--- a/board/amcc/yucca/cmd_yucca.c
+++ b/board/amcc/yucca/cmd_yucca.c
@@ -51,7 +51,6 @@
uchar chip;
ulong data;
int nbytes;
- extern char console_buffer[];
char sysClock[4];
char cpuClock[4];
diff --git a/board/armltd/integrator/arm-ebi.h b/board/armltd/integrator/arm-ebi.h
new file mode 100644
index 0000000..2d85e3f
--- /dev/null
+++ b/board/armltd/integrator/arm-ebi.h
@@ -0,0 +1,62 @@
+/*
+ * (C) Copyright 2011
+ * Linaro
+ * Linus Walleij <linus.walleij@linaro.org>
+ * Register definitions for the External Bus Interface (EBI)
+ * found in the ARM Integrator AP and CP reference designs
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#ifndef __ARM_EBI_H
+#define __ARM_EBI_H
+
+#define EBI_BASE 0x12000000
+
+#define EBI_CSR0_REG 0x00 /* CS0 = Boot ROM */
+#define EBI_CSR1_REG 0x04 /* CS1 = Flash */
+#define EBI_CSR2_REG 0x08 /* CS2 = SSRAM */
+#define EBI_CSR3_REG 0x0C /* CS3 = Expansion memory */
+/*
+ * The four upper bits are the waitstates for each chip select
+ * 0x00 = 2 cycles, 0x10 = 3 cycles, ... 0xe0 = 16 cycles, 0xf0 = 16 cycles
+ */
+#define EBI_CSR_WAIT_MASK 0xF0
+/* Whether memory is synchronous or asynchronous */
+#define EBI_CSR_SYNC_MASK 0xF7
+#define EBI_CSR_ASYNC 0x00
+#define EBI_CSR_SYNC 0x08
+/* Whether memory is write enabled or not */
+#define EBI_CSR_WREN_MASK 0xFB
+#define EBI_CSR_WREN_DISABLE 0x00
+#define EBI_CSR_WREN_ENABLE 0x04
+/* Memory bit width for each chip select */
+#define EBI_CSR_MEMSIZE_MASK 0xFC
+#define EBI_CSR_MEMSIZE_8BIT 0x00
+#define EBI_CSR_MEMSIZE_16BIT 0x01
+#define EBI_CSR_MEMSIZE_32BIT 0x02
+
+/*
+ * The lock register need to be written with 0xa05f before anything in the
+ * EBI can be changed.
+ */
+#define EBI_LOCK_REG 0x20
+#define EBI_UNLOCK_MAGIC 0xA05F
+
+#endif
diff --git a/board/armltd/integrator/config.mk b/board/armltd/integrator/config.mk
deleted file mode 100644
index 8b57af1..0000000
--- a/board/armltd/integrator/config.mk
+++ /dev/null
@@ -1,5 +0,0 @@
-#
-# image should be loaded at 0x01000000
-#
-
-CONFIG_SYS_TEXT_BASE = 0x01000000
diff --git a/board/armltd/integrator/integrator-sc.h b/board/armltd/integrator/integrator-sc.h
new file mode 100644
index 0000000..279dc55
--- /dev/null
+++ b/board/armltd/integrator/integrator-sc.h
@@ -0,0 +1,91 @@
+/*
+ * (C) Copyright 2011
+ * Linaro
+ * Linus Walleij <linus.walleij@linaro.org>
+ * Register definitions for the System Controller (SC) and
+ * the similar "CP Controller" found in the ARM Integrator/AP and
+ * Integrator/CP reference designs
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#ifndef __ARM_SC_H
+#define __ARM_SC_H
+
+#define SC_BASE 0x11000000
+
+/*
+ * The system controller registers
+ */
+#define SC_ID_OFFSET 0x00
+#define SC_OSC_OFFSET 0x04
+/* Setting this bit switches to 25 MHz mode, clear means 33 MHz */
+#define SC_OSC_DIVXY (1 << 8)
+#define SC_CTRLS_OFFSET 0x08
+#define SC_CTRLC_OFFSET 0x0C
+/* Set bits by writing CTRLS, clear bits by writing CTRLC */
+#define SC_CTRL_SOFTRESET (1 << 0)
+#define SC_CTRL_FLASHVPP (1 << 1)
+#define SC_CTRL_FLASHWP (1 << 2)
+#define SC_CTRL_UART1DTR (1 << 4)
+#define SC_CTRL_UART1RTS (1 << 5)
+#define SC_CTRL_UART0DTR (1 << 6)
+#define SC_CTRL_UART0RTS (1 << 7)
+#define SC_DEC_OFFSET 0x10
+#define SC_ARB_OFFSET 0x14
+#define SC_PCI_OFFSET 0x18
+#define SC_PCI_PCIEN (1 << 0)
+#define SC_PCI_PCIBINT_CLR (1 << 1)
+#define SC_LOCK_OFFSET 0x1C
+#define SC_LBFADDR_OFFSET 0x20
+#define SC_LBFCODE_OFFSET 0x24
+
+#define SC_ID (SC_BASE + SC_ID_OFFSET)
+#define SC_OSC (SC_BASE + SC_OSC_OFFSET)
+#define SC_CTRLS (SC_BASE + SC_CTRLS_OFFSET)
+#define SC_CTRLC (SC_BASE + SC_CTRLC_OFFSET)
+#define SC_DEC (SC_BASE + SC_DEC_OFFSET)
+#define SC_ARB (SC_BASE + SC_ARB_OFFSET)
+#define SC_PCI (SC_BASE + SC_PCI_OFFSET)
+#define SC_LOCK (SC_BASE + SC_LOCK_OFFSET)
+#define SC_LBFADDR (SC_BASE + SC_LBFADDR_OFFSET)
+#define SC_LBFCODE (SC_BASE + SC_LBFCODE_OFFSET)
+
+/*
+ * The Integrator/CP as a smaller set of registers, at a different
+ * offset - probably not to disturb old software.
+ */
+
+#define CP_BASE 0xCB000000
+
+#define CP_IDFIELD_OFFSET 0x00
+#define CP_FLASHPROG_OFFSET 0x04
+#define CP_FLASHPROG_FLVPPEN (1 << 0)
+#define CP_FLASHPROG_FLWREN (1 << 1)
+#define CP_FLASHPROG_FLASHSIZE (1 << 2)
+#define CP_FLASHPROG_EXTRABANK (1 << 3)
+#define CP_INTREG_OFFSET 0x08
+#define CP_DECODE_OFFSET 0x0C
+
+#define CP_IDFIELD (CP_BASE + CP_ID_OFFSET)
+#define CP_FLASHPROG (CP_BASE + CP_FLASHPROG_OFFSET)
+#define CP_INTREG (CP_BASE + CP_INTREG_OFFSET)
+#define CP_DECODE (CP_BASE + CP_DECODE_OFFSET)
+
+#endif
diff --git a/board/armltd/integrator/integrator.c b/board/armltd/integrator/integrator.c
index c8d2bc7..a507c09 100644
--- a/board/armltd/integrator/integrator.c
+++ b/board/armltd/integrator/integrator.c
@@ -35,6 +35,9 @@
#include <common.h>
#include <netdev.h>
+#include <asm/io.h>
+#include "arm-ebi.h"
+#include "integrator-sc.h"
DECLARE_GLOBAL_DATA_PTR;
@@ -55,6 +58,8 @@
int board_init (void)
{
+ u32 val;
+
/* arch number of Integrator Board */
#ifdef CONFIG_ARCH_CINTEGRATOR
gd->bd->bi_arch_number = MACH_TYPE_CINTEGRATOR;
@@ -72,6 +77,37 @@
cm_remap(); /* remaps writeable memory to 0x00000000 */
#endif
+#ifdef CONFIG_ARCH_CINTEGRATOR
+ /*
+ * Flash protection on the Integrator/CP is in a simple register
+ */
+ val = readl(CP_FLASHPROG);
+ val |= (CP_FLASHPROG_FLVPPEN | CP_FLASHPROG_FLWREN);
+ writel(val, CP_FLASHPROG);
+#else
+ /*
+ * The Integrator/AP has some special protection mechanisms
+ * for the external memories, first the External Bus Interface (EBI)
+ * then the system controller (SC).
+ *
+ * The system comes up with the flash memory non-writable and
+ * configuration locked. If we want U-Boot to be used for flash
+ * access we cannot have the flash memory locked.
+ */
+ writel(EBI_UNLOCK_MAGIC, EBI_BASE + EBI_LOCK_REG);
+ val = readl(EBI_BASE + EBI_CSR1_REG);
+ val &= EBI_CSR_WREN_MASK;
+ val |= EBI_CSR_WREN_ENABLE;
+ writel(val, EBI_BASE + EBI_CSR1_REG);
+ writel(0, EBI_BASE + EBI_LOCK_REG);
+
+ /*
+ * Set up the system controller to remove write protection from
+ * the flash memory and enable Vpp
+ */
+ writel(SC_CTRL_FLASHVPP | SC_CTRL_FLASHWP, SC_CTRLS);
+#endif
+
icache_enable ();
return 0;
@@ -86,21 +122,30 @@
return (0);
}
+/*
+ * The Integrator remaps the Flash memory to 0x00000000 and executes U-Boot
+ * from there, which means we cannot test the RAM underneath the ROM at this
+ * point. It will be unmapped later on, when we are executing from the
+ * relocated in RAM U-Boot. We simply assume that this RAM is usable if the
+ * RAM on higher addresses works fine.
+ */
+#define REMAPPED_FLASH_SZ 0x40000
+
int dram_init (void)
{
gd->bd->bi_dram[0].start = CONFIG_SYS_SDRAM_BASE;
#ifdef CONFIG_CM_SPD_DETECT
{
extern void dram_query(void);
- unsigned long cm_reg_sdram;
- unsigned long sdram_shift;
+ u32 cm_reg_sdram;
+ u32 sdram_shift;
dram_query(); /* Assembler accesses to CM registers */
/* Queries the SPD values */
/* Obtain the SDRAM size from the CM SDRAM register */
- cm_reg_sdram = *(volatile ulong *)(CM_BASE + OS_SDRAM);
+ cm_reg_sdram = readl(CM_BASE + OS_SDRAM);
/* Register SDRAM size
*
* 0xXXXXXXbbb000bb 16 MB
@@ -110,16 +155,18 @@
* 0xXXXXXXbbb100bb 256 MB
*
*/
- sdram_shift = ((cm_reg_sdram & 0x0000001C)/4)%4;
- gd->bd->bi_dram[0].size = 0x01000000 << sdram_shift;
- gd->ram_size = get_ram_size((long *)CONFIG_SYS_SDRAM_BASE,
+ sdram_shift = ((cm_reg_sdram & 0x0000001C)/4)%4;
+ gd->ram_size = get_ram_size((long *) CONFIG_SYS_SDRAM_BASE +
+ REMAPPED_FLASH_SZ,
0x01000000 << sdram_shift);
}
#else
- gd->bd->bi_dram[0].size = PHYS_SDRAM_1_SIZE;
- gd->ram_size = get_ram_size((long *)CONFIG_SYS_SDRAM_BASE,
+ gd->ram_size = get_ram_size((long *) CONFIG_SYS_SDRAM_BASE +
+ REMAPPED_FLASH_SZ,
PHYS_SDRAM_1_SIZE);
#endif /* CM_SPD_DETECT */
+ /* We only have one bank of RAM, set it to whatever was detected */
+ gd->bd->bi_dram[0].size = gd->ram_size;
return 0;
}
diff --git a/board/cm4008/flash.c b/board/cm4008/flash.c
index 2e1356f..5522bf0 100644
--- a/board/cm4008/flash.c
+++ b/board/cm4008/flash.c
@@ -206,7 +206,7 @@
int flash_erase (flash_info_t * info, int s_first, int s_last)
{
- int flag, prot, sect;
+ int prot, sect;
ulong type;
int rcode = 0;
ulong start;
@@ -240,7 +240,7 @@
printf ("\n");
/* Disable interrupts which might cause a timeout here */
- flag = disable_interrupts ();
+ disable_interrupts();
/* Start erase on unprotected sectors */
for (sect = s_first; sect <= s_last; sect++) {
@@ -370,7 +370,6 @@
{
volatile unsigned char *addr = (volatile unsigned char *) dest;
ulong status;
- int flag;
ulong start;
/* Check if Flash is (sufficiently) erased */
@@ -380,7 +379,7 @@
return (2);
}
/* Disable interrupts which might cause a timeout here */
- flag = disable_interrupts ();
+ disable_interrupts();
*addr = 0x40; /* write setup */
*addr = data;
diff --git a/board/cm41xx/flash.c b/board/cm41xx/flash.c
index 2e1356f..5522bf0 100644
--- a/board/cm41xx/flash.c
+++ b/board/cm41xx/flash.c
@@ -206,7 +206,7 @@
int flash_erase (flash_info_t * info, int s_first, int s_last)
{
- int flag, prot, sect;
+ int prot, sect;
ulong type;
int rcode = 0;
ulong start;
@@ -240,7 +240,7 @@
printf ("\n");
/* Disable interrupts which might cause a timeout here */
- flag = disable_interrupts ();
+ disable_interrupts();
/* Start erase on unprotected sectors */
for (sect = s_first; sect <= s_last; sect++) {
@@ -370,7 +370,6 @@
{
volatile unsigned char *addr = (volatile unsigned char *) dest;
ulong status;
- int flag;
ulong start;
/* Check if Flash is (sufficiently) erased */
@@ -380,7 +379,7 @@
return (2);
}
/* Disable interrupts which might cause a timeout here */
- flag = disable_interrupts ();
+ disable_interrupts();
*addr = 0x40; /* write setup */
*addr = data;
diff --git a/board/csb226/csb226.c b/board/csb226/csb226.c
deleted file mode 100644
index dd29e62..0000000
--- a/board/csb226/csb226.c
+++ /dev/null
@@ -1,166 +0,0 @@
-/*
- * (C) Copyright 2002
- * Robert Schwebel, Pengutronix, r.schwebel@pengutronix.de
- * Kyle Harris, Nexus Technologies, Inc., kharris@nexus-tech.net
- * Marius Groeger, Sysgo Real-Time Solutions GmbH, mgroeger@sysgo.de
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-#include <common.h>
-#include <netdev.h>
-#include <asm/arch/pxa-regs.h>
-#include <asm/io.h>
-
-DECLARE_GLOBAL_DATA_PTR;
-
-#ifdef CONFIG_SHOW_BOOT_PROGRESS
-# define SHOW_BOOT_PROGRESS(arg) show_boot_progress(arg)
-#else
-# define SHOW_BOOT_PROGRESS(arg)
-#endif
-
-/**
- * misc_init_r: - misc initialisation routines
- */
-
-int misc_init_r(void)
-{
-#if 0
- uchar *str;
-
- /* determine if the software update key is pressed during startup */
- /* not ported yet... */
- if (GPLR0 & 0x00000800) {
- printf("using bootcmd_normal (sw-update button not pressed)\n");
- str = getenv("bootcmd_normal");
- } else {
- printf("using bootcmd_update (sw-update button pressed)\n");
- str = getenv("bootcmd_update");
- }
-
- setenv("bootcmd",str);
-#endif
- return 0;
-}
-
-
-/**
- * board_init: - setup some data structures
- *
- * @return: 0 in case of success
- */
-
-int board_init (void)
-{
- /* We have RAM, disable cache */
- dcache_disable();
- icache_disable();
-
- /* arch number of CSB226 board */
- gd->bd->bi_arch_number = MACH_TYPE_CSB226;
-
- /* adress of boot parameters */
- gd->bd->bi_boot_params = 0xa0000100;
-
- return 0;
-}
-
-
-extern void pxa_dram_init(void);
-int dram_init(void)
-{
- pxa_dram_init();
- gd->ram_size = PHYS_SDRAM_1_SIZE;
- return 0;
-}
-
-void dram_init_banksize(void)
-{
- gd->bd->bi_dram[0].start = PHYS_SDRAM_1;
- gd->bd->bi_dram[0].size = PHYS_SDRAM_1_SIZE;
-}
-
-/**
- * csb226_set_led: - switch LEDs on or off
- *
- * @param led: LED to switch (0,1,2)
- * @param state: switch on (1) or off (0)
- */
-
-void csb226_set_led(int led, int state)
-{
- switch(led) {
-
- case 0: if (state==1) {
- writel(readl(GPCR0) | CSB226_USER_LED0, GPCR0);
- } else if (state==0) {
- writel(readl(GPSR0) | CSB226_USER_LED0, GPSR0);
- }
- break;
-
- case 1: if (state==1) {
- writel(readl(GPCR0) | CSB226_USER_LED1, GPCR0);
- } else if (state==0) {
- writel(readl(GPSR0) | CSB226_USER_LED1, GPSR0);
- }
- break;
-
- case 2: if (state==1) {
- writel(readl(GPCR0) | CSB226_USER_LED2, GPCR0);
- } else if (state==0) {
- writel(readl(GPSR0) | CSB226_USER_LED2, GPSR0);
- }
- break;
- }
-
- return;
-}
-
-
-/**
- * show_boot_progress: - indicate state of the boot process
- *
- * @param status: Status number - see README for details.
- *
- * The CSB226 does only have 3 LEDs, so we switch them on at the most
- * important states (1, 5, 15).
- */
-
-void show_boot_progress (int status)
-{
- switch(status) {
- case 1: csb226_set_led(0,1); break;
- case 5: csb226_set_led(1,1); break;
- case 15: csb226_set_led(2,1); break;
- }
-
- return;
-}
-
-#ifdef CONFIG_CMD_NET
-int board_eth_init(bd_t *bis)
-{
- int rc = 0;
-#ifdef CONFIG_CS8900
- rc = cs8900_initialize(0, CONFIG_CS8900_BASE);
-#endif
- return rc;
-}
-#endif
diff --git a/board/csb226/flash.c b/board/csb226/flash.c
deleted file mode 100644
index e103470..0000000
--- a/board/csb226/flash.c
+++ /dev/null
@@ -1,368 +0,0 @@
-/*
- * (C) Copyright 2002
- * Kyle Harris, Nexus Technologies, Inc. kharris@nexus-tech.net
- *
- * (C) Copyright 2002
- * Sysgo Real-Time Solutions, GmbH <www.elinos.com>
- * Marius Groeger <mgroeger@sysgo.de>
- *
- * (C) Copyright 2002
- * Robert Schwebel, Pengutronix, <r.schwebel@pengutronix.de>
- *
- * (C) Copyright 2003 (2 x 16 bit Flash bank patches)
- * Rolf Peukert, IMMS gGmbH, <rolf.peukert@imms.de>
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-#include <common.h>
-#include <asm/arch/pxa-regs.h>
-
-#define FLASH_BANK_SIZE 0x02000000
-#define MAIN_SECT_SIZE 0x40000 /* 2x16 = 256k per sector */
-
-flash_info_t flash_info[CONFIG_SYS_MAX_FLASH_BANKS];
-
-
-/**
- * flash_init: - initialize data structures for flash chips
- *
- * @return: size of the flash
- */
-
-ulong flash_init(void)
-{
- int i, j;
- ulong size = 0;
-
- for (i = 0; i < CONFIG_SYS_MAX_FLASH_BANKS; i++) {
- ulong flashbase = 0;
- flash_info[i].flash_id =
- (INTEL_MANUFACT & FLASH_VENDMASK) |
- (INTEL_ID_28F128J3 & FLASH_TYPEMASK);
- flash_info[i].size = FLASH_BANK_SIZE;
- flash_info[i].sector_count = CONFIG_SYS_MAX_FLASH_SECT;
- memset(flash_info[i].protect, 0, CONFIG_SYS_MAX_FLASH_SECT);
-
- switch (i) {
- case 0:
- flashbase = PHYS_FLASH_1;
- break;
- default:
- panic("configured too many flash banks!\n");
- break;
- }
- for (j = 0; j < flash_info[i].sector_count; j++) {
- flash_info[i].start[j] = flashbase + j*MAIN_SECT_SIZE;
- }
- size += flash_info[i].size;
- }
-
- /* Protect monitor and environment sectors */
- flash_protect(FLAG_PROTECT_SET,
- CONFIG_SYS_FLASH_BASE,
- CONFIG_SYS_FLASH_BASE + monitor_flash_len - 1,
- &flash_info[0]);
-
- flash_protect(FLAG_PROTECT_SET,
- CONFIG_ENV_ADDR,
- CONFIG_ENV_ADDR + CONFIG_ENV_SIZE - 1,
- &flash_info[0]);
-
- return size;
-}
-
-
-/**
- * flash_print_info: - print information about the flash situation
- */
-
-void flash_print_info (flash_info_t *info)
-{
- int i, j;
-
- for (j=0; j<CONFIG_SYS_MAX_FLASH_BANKS; j++) {
-
- switch (info->flash_id & FLASH_VENDMASK) {
- case (INTEL_MANUFACT & FLASH_VENDMASK):
- printf ("Intel: ");
- break;
- default:
- printf ("Unknown Vendor ");
- break;
- }
-
- switch (info->flash_id & FLASH_TYPEMASK) {
- case (INTEL_ID_28F128J3 & FLASH_TYPEMASK):
- printf("28F128J3 (128Mbit)\n");
- break;
- default:
- printf("Unknown Chip Type\n");
- return;
- }
-
- printf(" Size: %ld MB in %d Sectors\n",
- info->size >> 20, info->sector_count);
-
- printf(" Sector Start Addresses:");
- for (i = 0; i < info->sector_count; i++) {
- if ((i % 5) == 0) printf ("\n ");
-
- printf (" %08lX%s", info->start[i],
- info->protect[i] ? " (RO)" : " ");
- }
- printf ("\n");
- info++;
- }
-}
-
-
-/**
- * flash_erase: - erase flash sectors
- */
-
-int flash_erase(flash_info_t *info, int s_first, int s_last)
-{
- int flag, prot, sect;
- int rc = ERR_OK;
- ulong start;
-
- if (info->flash_id == FLASH_UNKNOWN)
- return ERR_UNKNOWN_FLASH_TYPE;
-
- if ((s_first < 0) || (s_first > s_last)) {
- return ERR_INVAL;
- }
-
- if ((info->flash_id & FLASH_VENDMASK) != (INTEL_MANUFACT & FLASH_VENDMASK))
- return ERR_UNKNOWN_FLASH_VENDOR;
-
- prot = 0;
- for (sect=s_first; sect<=s_last; ++sect) {
- if (info->protect[sect]) prot++;
- }
-
- if (prot) return ERR_PROTECTED;
-
- /*
- * Disable interrupts which might cause a timeout
- * here. Remember that our exception vectors are
- * at address 0 in the flash, and we don't want a
- * (ticker) exception to happen while the flash
- * chip is in programming mode.
- */
-
- flag = disable_interrupts();
-
- /* Start erase on unprotected sectors */
- for (sect = s_first; sect<=s_last && !ctrlc(); sect++) {
-
- printf("Erasing sector %2d ... ", sect);
-
- /* arm simple, non interrupt dependent timer */
- start = get_timer(0);
-
- if (info->protect[sect] == 0) { /* not protected */
- u32 * volatile addr = (u32 * volatile)(info->start[sect]);
-
- /* erase sector: */
- /* The strata flashs are aligned side by side on */
- /* the data bus, so we have to write the commands */
- /* to both chips here: */
-
- *addr = 0x00200020; /* erase setup */
- *addr = 0x00D000D0; /* erase confirm */
-
- while ((*addr & 0x00800080) != 0x00800080) {
- if (get_timer(start) > CONFIG_SYS_FLASH_ERASE_TOUT) {
- *addr = 0x00B000B0; /* suspend erase*/
- *addr = 0x00FF00FF; /* read mode */
- rc = ERR_TIMOUT;
- goto outahere;
- }
- }
- *addr = 0x00500050; /* clear status register cmd. */
- *addr = 0x00FF00FF; /* reset to read mode */
- }
- printf("ok.\n");
- }
- if (ctrlc()) printf("User Interrupt!\n");
-
-outahere:
- /* allow flash to settle - wait 10 ms */
- udelay_masked(10000);
-
- if (flag) enable_interrupts();
-
- return rc;
-}
-
-/**
- * write_long: - copy memory to flash, assume a bank of 2 devices with 16bit each
- */
-
-static int write_long (flash_info_t *info, ulong dest, ulong data)
-{
- u32 * volatile addr = (u32 * volatile)dest, val;
- int rc = ERR_OK;
- int flag;
- ulong start;
-
- /* read array command - just for the case... */
- *addr = 0x00FF00FF;
-
- /* Check if Flash is (sufficiently) erased */
- if ((*addr & data) != data) return ERR_NOT_ERASED;
-
- /*
- * Disable interrupts which might cause a timeout
- * here. Remember that our exception vectors are
- * at address 0 in the flash, and we don't want a
- * (ticker) exception to happen while the flash
- * chip is in programming mode.
- */
- flag = disable_interrupts();
-
- /* clear status register command */
- *addr = 0x00500050;
-
- /* program set-up command */
- *addr = 0x00400040;
-
- /* latch address/data */
- *addr = data;
-
- /* arm simple, non interrupt dependent timer */
- start = get_timer(0);
-
- /* wait while polling the status register */
- while(((val = *addr) & 0x00800080) != 0x00800080) {
- if (get_timer(start) > CONFIG_SYS_FLASH_WRITE_TOUT) {
- rc = ERR_TIMOUT;
- /* suspend program command */
- *addr = 0x00B000B0;
- goto outahere;
- }
- }
-
- /* check for errors */
- if(val & 0x001A001A) {
- printf("\nFlash write error %02x at address %08lx\n",
- (int)val, (unsigned long)dest);
- if(val & 0x00080008) {
- printf("Voltage range error.\n");
- rc = ERR_PROG_ERROR;
- goto outahere;
- }
- if(val & 0x00020002) {
- printf("Device protect error.\n");
- rc = ERR_PROTECTED;
- goto outahere;
- }
- if(val & 0x00100010) {
- printf("Programming error.\n");
- rc = ERR_PROG_ERROR;
- goto outahere;
- }
- rc = ERR_PROG_ERROR;
- goto outahere;
- }
-
-outahere:
- /* read array command */
- *addr = 0x00FF00FF;
- if (flag) enable_interrupts();
-
- return rc;
-}
-
-
-/**
- * write_buf: - Copy memory to flash.
- *
- * @param info:
- * @param src: source of copy transaction
- * @param addr: where to copy to
- * @param cnt: number of bytes to copy
- *
- * @return error code
- */
-
-/* "long" version, uses 32bit words */
-int write_buff (flash_info_t *info, uchar *src, ulong addr, ulong cnt)
-{
- ulong cp, wp;
- ulong data;
- int l;
- int i, rc;
-
- wp = (addr & ~3); /* get lower word aligned address */
-
- /*
- * handle unaligned start bytes
- */
- if ((l = addr - wp) != 0) {
- data = 0;
- for (i=0, cp=wp; i<l; ++i, ++cp) {
- data = (data >> 8) | (*(uchar *)cp << 24);
- }
- for (; i<4 && cnt>0; ++i) {
- data = (data >> 8) | (*src++ << 24);
- --cnt;
- ++cp;
- }
- for (; cnt==0 && i<4; ++i, ++cp) {
- data = (data >> 8) | (*(uchar *)cp << 24);
- }
-
- if ((rc = write_long(info, wp, data)) != 0) {
- return (rc);
- }
- wp += 4;
- }
-
- /*
- * handle word aligned part
- */
- while (cnt >= 4) {
- data = *((ulong*)src);
- if ((rc = write_long(info, wp, data)) != 0) {
- return (rc);
- }
- src += 4;
- wp += 4;
- cnt -= 4;
- }
-
- if (cnt == 0) return ERR_OK;
-
- /*
- * handle unaligned tail bytes
- */
- data = 0;
- for (i=0, cp=wp; i<4 && cnt>0; ++i, ++cp) {
- data = (data >> 8) | (*src++ << 24);
- --cnt;
- }
- for (; i<4; ++i, ++cp) {
- data = (data >> 8) | (*(uchar *)cp << 24);
- }
-
- return write_long(info, wp, data);
-}
diff --git a/board/davedenx/qong/qong.c b/board/davedenx/qong/qong.c
index 665aedf..c41f11d 100644
--- a/board/davedenx/qong/qong.c
+++ b/board/davedenx/qong/qong.c
@@ -231,7 +231,7 @@
mxc_setup_weimcs(3, &cs3);
- __REG(IOMUXC_GPR) |= 1 << 13;
+ mx31_set_gpr(MUX_SDCTL_CSD1_SEL, 1);
mx31_gpio_mux(IOMUX_MODE(MUX_CTL_NFC_WP, MUX_CTL_IN_GPIO));
mx31_gpio_mux(IOMUX_MODE(MUX_CTL_NFC_CE, MUX_CTL_IN_GPIO));
diff --git a/board/davinci/dm6467evm/dm6467evm.c b/board/davinci/dm6467evm/dm6467evm.c
index 1a01c3c..ac82d5c 100644
--- a/board/davinci/dm6467evm/dm6467evm.c
+++ b/board/davinci/dm6467evm/dm6467evm.c
@@ -24,6 +24,26 @@
DECLARE_GLOBAL_DATA_PTR;
+#define REV_DM6467EVM 0
+#define REV_DM6467TEVM 1
+/*
+ * get_board_rev() - setup to pass kernel board revision information
+ * Returns:
+ * bit[0-3] System clock frequency
+ * 0000b - 27 MHz
+ * 0001b - 33 MHz
+ */
+u32 get_board_rev(void)
+{
+
+#ifdef DAVINCI_DM6467TEVM
+ return REV_DM6467TEVM;
+#else
+ return REV_DM6467EVM;
+#endif
+
+}
+
int board_init(void)
{
gd->bd->bi_arch_number = MACH_TYPE_DAVINCI_DM6467_EVM;
diff --git a/board/csb226/Makefile b/board/denx/m28evk/Makefile
similarity index 84%
copy from board/csb226/Makefile
copy to board/denx/m28evk/Makefile
index 6fe9bec..b6f002f 100644
--- a/board/csb226/Makefile
+++ b/board/denx/m28evk/Makefile
@@ -25,7 +25,13 @@
LIB = $(obj)lib$(BOARD).o
-COBJS := csb226.o flash.o
+ifndef CONFIG_SPL_BUILD
+COBJS := m28evk.o
+endif
+
+ifdef CONFIG_SPL_BUILD
+COBJS := mem_init.o mmc_boot.o power_init.o memsize.o
+endif
SRCS := $(COBJS:.o=.c)
OBJS := $(addprefix $(obj),$(COBJS))
@@ -33,6 +39,13 @@
$(LIB): $(obj).depend $(OBJS)
$(call cmd_link_o_target, $(OBJS))
+all: $(ALL)
+
+ifdef CONFIG_SPL_BUILD
+memsize.c:
+ ln -sf $(TOPDIR)/common/memsize.c $@
+endif
+
#########################################################################
# defines $(obj).depend target
diff --git a/board/denx/m28evk/m28_init.h b/board/denx/m28evk/m28_init.h
new file mode 100644
index 0000000..98d3631
--- /dev/null
+++ b/board/denx/m28evk/m28_init.h
@@ -0,0 +1,41 @@
+/*
+ * Freescale i.MX28 SPL functions
+ *
+ * Copyright (C) 2011 Marek Vasut <marek.vasut@gmail.com>
+ * on behalf of DENX Software Engineering GmbH
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#ifndef __M28_INIT_H__
+#define __M28_INIT_H__
+
+void early_delay(int delay);
+
+void mx28_power_init(void);
+
+#ifdef CONFIG_SPL_MX28_PSWITCH_WAIT
+void mx28_power_wait_pswitch(void);
+#else
+static inline void mx28_power_wait_pswitch(void) { }
+#endif
+
+void mx28_mem_init(void);
+
+#endif /* __M28_INIT_H__ */
diff --git a/board/denx/m28evk/m28evk.c b/board/denx/m28evk/m28evk.c
new file mode 100644
index 0000000..8cf3dc9
--- /dev/null
+++ b/board/denx/m28evk/m28evk.c
@@ -0,0 +1,216 @@
+/*
+ * DENX M28 module
+ *
+ * Copyright (C) 2011 Marek Vasut <marek.vasut@gmail.com>
+ * on behalf of DENX Software Engineering GmbH
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <asm/gpio.h>
+#include <asm/io.h>
+#include <asm/arch/imx-regs.h>
+#include <asm/arch/iomux-mx28.h>
+#include <asm/arch/clock.h>
+#include <asm/arch/sys_proto.h>
+#include <linux/mii.h>
+#include <miiphy.h>
+#include <netdev.h>
+#include <errno.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+/*
+ * Functions
+ */
+int board_early_init_f(void)
+{
+ /* IO0 clock at 480MHz */
+ mx28_set_ioclk(MXC_IOCLK0, 480000);
+ /* IO1 clock at 480MHz */
+ mx28_set_ioclk(MXC_IOCLK1, 480000);
+
+ /* SSP0 clock at 96MHz */
+ mx28_set_sspclk(MXC_SSPCLK0, 96000, 0);
+ /* SSP2 clock at 96MHz */
+ mx28_set_sspclk(MXC_SSPCLK2, 96000, 0);
+
+#ifdef CONFIG_CMD_USB
+ mxs_iomux_setup_pad(MX28_PAD_SSP2_SS1__USB1_OVERCURRENT);
+ mxs_iomux_setup_pad(MX28_PAD_AUART3_TX__GPIO_3_13 |
+ MXS_PAD_12MA | MXS_PAD_3V3 | MXS_PAD_PULLUP);
+ gpio_direction_output(MX28_PAD_AUART3_TX__GPIO_3_13, 0);
+#endif
+
+ return 0;
+}
+
+int board_init(void)
+{
+ /* Adress of boot parameters */
+ gd->bd->bi_boot_params = PHYS_SDRAM_1 + 0x100;
+
+ return 0;
+}
+
+#define HW_DIGCTRL_SCRATCH0 0x8001c280
+#define HW_DIGCTRL_SCRATCH1 0x8001c290
+int dram_init(void)
+{
+ uint32_t sz[2];
+
+ sz[0] = readl(HW_DIGCTRL_SCRATCH0);
+ sz[1] = readl(HW_DIGCTRL_SCRATCH1);
+
+ if (sz[0] != sz[1]) {
+ printf("MX28:\n"
+ "Error, the RAM size in HW_DIGCTRL_SCRATCH0 and\n"
+ "HW_DIGCTRL_SCRATCH1 is not the same. Please\n"
+ "verify these two registers contain valid RAM size!\n");
+ hang();
+ }
+
+ gd->ram_size = sz[0];
+ return 0;
+}
+
+#ifdef CONFIG_CMD_MMC
+static int m28_mmc_wp(int id)
+{
+ if (id != 0) {
+ printf("MXS MMC: Invalid card selected (card id = %d)\n", id);
+ return 1;
+ }
+
+ return gpio_get_value(MX28_PAD_AUART2_CTS__GPIO_3_10);
+}
+
+int board_mmc_init(bd_t *bis)
+{
+ /* Configure WP as output */
+ gpio_direction_input(MX28_PAD_AUART2_CTS__GPIO_3_10);
+
+ return mxsmmc_initialize(bis, 0, m28_mmc_wp);
+}
+#endif
+
+#ifdef CONFIG_CMD_NET
+
+#define MII_OPMODE_STRAP_OVERRIDE 0x16
+#define MII_PHY_CTRL1 0x1e
+#define MII_PHY_CTRL2 0x1f
+
+int fecmxc_mii_postcall(int phy)
+{
+ miiphy_write("FEC1", phy, MII_BMCR, 0x9000);
+ miiphy_write("FEC1", phy, MII_OPMODE_STRAP_OVERRIDE, 0x0202);
+ if (phy == 3)
+ miiphy_write("FEC1", 3, MII_PHY_CTRL2, 0x8180);
+ return 0;
+}
+
+int board_eth_init(bd_t *bis)
+{
+ struct mx28_clkctrl_regs *clkctrl_regs =
+ (struct mx28_clkctrl_regs *)MXS_CLKCTRL_BASE;
+ struct eth_device *dev;
+ int ret;
+
+ ret = cpu_eth_init(bis);
+
+ clrsetbits_le32(&clkctrl_regs->hw_clkctrl_enet,
+ CLKCTRL_ENET_TIME_SEL_MASK | CLKCTRL_ENET_CLK_OUT_EN,
+ CLKCTRL_ENET_TIME_SEL_RMII_CLK);
+
+ ret = fecmxc_initialize_multi(bis, 0, 0, MXS_ENET0_BASE);
+ if (ret) {
+ printf("FEC MXS: Unable to init FEC0\n");
+ return ret;
+ }
+
+ ret = fecmxc_initialize_multi(bis, 1, 3, MXS_ENET1_BASE);
+ if (ret) {
+ printf("FEC MXS: Unable to init FEC1\n");
+ return ret;
+ }
+
+ dev = eth_get_dev_by_name("FEC0");
+ if (!dev) {
+ printf("FEC MXS: Unable to get FEC0 device entry\n");
+ return -EINVAL;
+ }
+
+ ret = fecmxc_register_mii_postcall(dev, fecmxc_mii_postcall);
+ if (ret) {
+ printf("FEC MXS: Unable to register FEC0 mii postcall\n");
+ return ret;
+ }
+
+ dev = eth_get_dev_by_name("FEC1");
+ if (!dev) {
+ printf("FEC MXS: Unable to get FEC1 device entry\n");
+ return -EINVAL;
+ }
+
+ ret = fecmxc_register_mii_postcall(dev, fecmxc_mii_postcall);
+ if (ret) {
+ printf("FEC MXS: Unable to register FEC1 mii postcall\n");
+ return ret;
+ }
+
+ return ret;
+}
+
+#ifdef CONFIG_M28_FEC_MAC_IN_OCOTP
+
+#define MXS_OCOTP_MAX_TIMEOUT 1000000
+void imx_get_mac_from_fuse(char *mac)
+{
+ struct mx28_ocotp_regs *ocotp_regs =
+ (struct mx28_ocotp_regs *)MXS_OCOTP_BASE;
+ uint32_t data;
+
+ memset(mac, 0, 6);
+
+ writel(OCOTP_CTRL_RD_BANK_OPEN, &ocotp_regs->hw_ocotp_ctrl_set);
+
+ if (mx28_wait_mask_clr(&ocotp_regs->hw_ocotp_ctrl_reg, OCOTP_CTRL_BUSY,
+ MXS_OCOTP_MAX_TIMEOUT)) {
+ printf("MXS FEC: Can't get MAC from OCOTP\n");
+ return;
+ }
+
+ data = readl(&ocotp_regs->hw_ocotp_cust0);
+
+ mac[0] = 0x00;
+ mac[1] = 0x04;
+ mac[2] = (data >> 24) & 0xff;
+ mac[3] = (data >> 16) & 0xff;
+ mac[4] = (data >> 8) & 0xff;
+ mac[5] = data & 0xff;
+}
+#else
+void imx_get_mac_from_fuse(char *mac)
+{
+ memset(mac, 0, 6);
+}
+#endif
+
+#endif
diff --git a/board/denx/m28evk/mem_init.c b/board/denx/m28evk/mem_init.c
new file mode 100644
index 0000000..17d1f9b
--- /dev/null
+++ b/board/denx/m28evk/mem_init.c
@@ -0,0 +1,240 @@
+/*
+ * Freescale i.MX28 RAM init
+ *
+ * Copyright (C) 2011 Marek Vasut <marek.vasut@gmail.com>
+ * on behalf of DENX Software Engineering GmbH
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <config.h>
+#include <asm/io.h>
+#include <asm/arch/iomux-mx28.h>
+#include <asm/arch/imx-regs.h>
+
+#include "m28_init.h"
+
+uint32_t dram_vals[] = {
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ 0x00000000, 0x00000000, 0x00000100, 0x00000000, 0x00000000,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ 0x00000000, 0x00010101, 0x01010101, 0x000f0f01, 0x0f02020a,
+ 0x00000000, 0x00010101, 0x00000100, 0x00000100, 0x00000000,
+ 0x00000002, 0x01010000, 0x05060302, 0x06005003, 0x0a0000c8,
+ 0x02009c40, 0x0000030c, 0x0036a609, 0x031a0612, 0x02030202,
+ 0x00c8001c, 0x00000000, 0x00000000, 0x00012100, 0xffff0303,
+ 0x00012100, 0xffff0303, 0x00012100, 0xffff0303, 0x00012100,
+ 0xffff0303, 0x00000003, 0x00000000, 0x00000000, 0x00000000,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ 0x00000000, 0x00000612, 0x01000F02, 0x06120612, 0x00000200,
+ 0x00020007, 0xf5014b27, 0xf5014b27, 0xf5014b27, 0xf5014b27,
+ 0x07000300, 0x07000300, 0x07000300, 0x07000300, 0x00000006,
+ 0x00000000, 0x00000000, 0x01000000, 0x01020408, 0x08040201,
+ 0x000f1133, 0x00000000, 0x00001f04, 0x00001f04, 0x00001f04,
+ 0x00001f04, 0x00001f04, 0x00001f04, 0x00001f04, 0x00001f04,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ 0x00000000, 0x00000000, 0x00010000, 0x00020304, 0x00000004,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ 0x00000000, 0x01010000, 0x01000000, 0x03030000, 0x00010303,
+ 0x01020202, 0x00000000, 0x02040303, 0x21002103, 0x00061200,
+ 0x06120612, 0x04320432, 0x04320432, 0x00040004, 0x00040004,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00010001
+};
+
+void init_m28_200mhz_ddr2(void)
+{
+ int i;
+
+ for (i = 0; i < ARRAY_SIZE(dram_vals); i++)
+ writel(dram_vals[i], MXS_DRAM_BASE + (4 * i));
+}
+
+void mx28_mem_init_clock(void)
+{
+ struct mx28_clkctrl_regs *clkctrl_regs =
+ (struct mx28_clkctrl_regs *)MXS_CLKCTRL_BASE;
+
+ /* Gate EMI clock */
+ writel(CLKCTRL_FRAC0_CLKGATEEMI,
+ &clkctrl_regs->hw_clkctrl_frac0_set);
+
+ /* EMI = 205MHz */
+ writel(CLKCTRL_FRAC0_EMIFRAC_MASK,
+ &clkctrl_regs->hw_clkctrl_frac0_set);
+ writel((0x2a << CLKCTRL_FRAC0_EMIFRAC_OFFSET) &
+ CLKCTRL_FRAC0_EMIFRAC_MASK,
+ &clkctrl_regs->hw_clkctrl_frac0_clr);
+
+ /* Ungate EMI clock */
+ writel(CLKCTRL_FRAC0_CLKGATEEMI,
+ &clkctrl_regs->hw_clkctrl_frac0_clr);
+
+ early_delay(11000);
+
+ writel((2 << CLKCTRL_EMI_DIV_EMI_OFFSET) |
+ (1 << CLKCTRL_EMI_DIV_XTAL_OFFSET),
+ &clkctrl_regs->hw_clkctrl_emi);
+
+ /* Unbypass EMI */
+ writel(CLKCTRL_CLKSEQ_BYPASS_EMI,
+ &clkctrl_regs->hw_clkctrl_clkseq_clr);
+
+ early_delay(10000);
+}
+
+void mx28_mem_setup_cpu_and_hbus(void)
+{
+ struct mx28_clkctrl_regs *clkctrl_regs =
+ (struct mx28_clkctrl_regs *)MXS_CLKCTRL_BASE;
+
+ /* CPU = 454MHz and ungate CPU clock */
+ clrsetbits_le32(&clkctrl_regs->hw_clkctrl_frac0,
+ CLKCTRL_FRAC0_CPUFRAC_MASK | CLKCTRL_FRAC0_CLKGATECPU,
+ 19 << CLKCTRL_FRAC0_CPUFRAC_OFFSET);
+
+ /* Set CPU bypass */
+ writel(CLKCTRL_CLKSEQ_BYPASS_CPU,
+ &clkctrl_regs->hw_clkctrl_clkseq_set);
+
+ /* HBUS = 151MHz */
+ writel(CLKCTRL_HBUS_DIV_MASK, &clkctrl_regs->hw_clkctrl_hbus_set);
+ writel(((~3) << CLKCTRL_HBUS_DIV_OFFSET) & CLKCTRL_HBUS_DIV_MASK,
+ &clkctrl_regs->hw_clkctrl_hbus_clr);
+
+ early_delay(10000);
+
+ /* CPU clock divider = 1 */
+ clrsetbits_le32(&clkctrl_regs->hw_clkctrl_cpu,
+ CLKCTRL_CPU_DIV_CPU_MASK, 1);
+
+ /* Disable CPU bypass */
+ writel(CLKCTRL_CLKSEQ_BYPASS_CPU,
+ &clkctrl_regs->hw_clkctrl_clkseq_clr);
+}
+
+void mx28_mem_setup_vdda(void)
+{
+ struct mx28_power_regs *power_regs =
+ (struct mx28_power_regs *)MXS_POWER_BASE;
+
+ writel((0xc << POWER_VDDACTRL_TRG_OFFSET) |
+ (0x7 << POWER_VDDACTRL_BO_OFFSET_OFFSET) |
+ POWER_VDDACTRL_LINREG_OFFSET_1STEPS_BELOW,
+ &power_regs->hw_power_vddactrl);
+}
+
+void mx28_mem_setup_vddd(void)
+{
+ struct mx28_power_regs *power_regs =
+ (struct mx28_power_regs *)MXS_POWER_BASE;
+
+ writel((0x1c << POWER_VDDDCTRL_TRG_OFFSET) |
+ (0x7 << POWER_VDDDCTRL_BO_OFFSET_OFFSET) |
+ POWER_VDDDCTRL_LINREG_OFFSET_1STEPS_BELOW,
+ &power_regs->hw_power_vdddctrl);
+}
+
+#define HW_DIGCTRL_SCRATCH0 0x8001c280
+#define HW_DIGCTRL_SCRATCH1 0x8001c290
+void data_abort_memdetect_handler(void) __attribute__((naked));
+void data_abort_memdetect_handler(void)
+{
+ asm volatile("subs pc, r14, #4");
+}
+
+void mx28_mem_get_size(void)
+{
+ uint32_t sz, da;
+ uint32_t *vt = (uint32_t *)0x20;
+
+ /* Replace the DABT handler. */
+ da = vt[4];
+ vt[4] = (uint32_t)&data_abort_memdetect_handler;
+
+ sz = get_ram_size((long *)PHYS_SDRAM_1, PHYS_SDRAM_1_SIZE);
+ writel(sz, HW_DIGCTRL_SCRATCH0);
+ writel(sz, HW_DIGCTRL_SCRATCH1);
+
+ /* Restore the old DABT handler. */
+ vt[4] = da;
+}
+
+void mx28_mem_init(void)
+{
+ struct mx28_clkctrl_regs *clkctrl_regs =
+ (struct mx28_clkctrl_regs *)MXS_CLKCTRL_BASE;
+ struct mx28_pinctrl_regs *pinctrl_regs =
+ (struct mx28_pinctrl_regs *)MXS_PINCTRL_BASE;
+
+ /* Set DDR2 mode */
+ writel(PINCTRL_EMI_DS_CTRL_DDR_MODE_DDR2,
+ &pinctrl_regs->hw_pinctrl_emi_ds_ctrl_set);
+
+ /* Power up PLL0 */
+ writel(CLKCTRL_PLL0CTRL0_POWER,
+ &clkctrl_regs->hw_clkctrl_pll0ctrl0_set);
+
+ early_delay(11000);
+
+ mx28_mem_init_clock();
+
+ mx28_mem_setup_vdda();
+
+ /*
+ * Configure the DRAM registers
+ */
+
+ /* Clear START bit from DRAM_CTL16 */
+ clrbits_le32(MXS_DRAM_BASE + 0x40, 1);
+
+ init_m28_200mhz_ddr2();
+
+ /* Clear SREFRESH bit from DRAM_CTL17 */
+ clrbits_le32(MXS_DRAM_BASE + 0x44, 1);
+
+ /* Set START bit in DRAM_CTL16 */
+ setbits_le32(MXS_DRAM_BASE + 0x40, 1);
+
+ /* Wait for bit 20 (DRAM init complete) in DRAM_CTL58 */
+ while (!(readl(MXS_DRAM_BASE + 0xe8) & (1 << 20)))
+ ;
+
+ mx28_mem_setup_vddd();
+
+ early_delay(10000);
+
+ mx28_mem_setup_cpu_and_hbus();
+
+ mx28_mem_get_size();
+}
diff --git a/board/denx/m28evk/mmc_boot.c b/board/denx/m28evk/mmc_boot.c
new file mode 100644
index 0000000..86d3ab5
--- /dev/null
+++ b/board/denx/m28evk/mmc_boot.c
@@ -0,0 +1,273 @@
+/*
+ * Freescale i.MX28 Boot setup
+ *
+ * Copyright (C) 2011 Marek Vasut <marek.vasut@gmail.com>
+ * on behalf of DENX Software Engineering GmbH
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <config.h>
+#include <asm/io.h>
+#include <asm/arch/iomux-mx28.h>
+
+#include "m28_init.h"
+
+/*
+ * This delay function is intended to be used only in early stage of boot, where
+ * clock are not set up yet. The timer used here is reset on every boot and
+ * takes a few seconds to roll. The boot doesn't take that long, so to keep the
+ * code simple, it doesn't take rolling into consideration.
+ */
+#define HW_DIGCTRL_MICROSECONDS 0x8001c0c0
+void early_delay(int delay)
+{
+ uint32_t st = readl(HW_DIGCTRL_MICROSECONDS);
+ st += delay;
+ while (st > readl(HW_DIGCTRL_MICROSECONDS))
+ ;
+}
+
+#define MUX_CONFIG_LED (MXS_PAD_3V3 | MXS_PAD_4MA | MXS_PAD_NOPULL)
+#define MUX_CONFIG_LCD (MXS_PAD_3V3 | MXS_PAD_4MA)
+#define MUX_CONFIG_TSC (MXS_PAD_3V3 | MXS_PAD_8MA | MXS_PAD_PULLUP)
+#define MUX_CONFIG_SSP0 (MXS_PAD_3V3 | MXS_PAD_12MA | MXS_PAD_PULLUP)
+#define MUX_CONFIG_SSP2 (MXS_PAD_3V3 | MXS_PAD_4MA | MXS_PAD_PULLUP)
+#define MUX_CONFIG_GPMI (MXS_PAD_1V8 | MXS_PAD_4MA | MXS_PAD_NOPULL)
+#define MUX_CONFIG_ENET (MXS_PAD_3V3 | MXS_PAD_4MA | MXS_PAD_PULLUP)
+#define MUX_CONFIG_EMI (MXS_PAD_3V3 | MXS_PAD_12MA | MXS_PAD_NOPULL)
+
+const iomux_cfg_t iomux_setup[] = {
+ /* LED */
+ MX28_PAD_ENET0_RXD3__GPIO_4_10 | MUX_CONFIG_LED,
+
+ /* framebuffer */
+ MX28_PAD_LCD_D00__LCD_D0 | MUX_CONFIG_LCD,
+ MX28_PAD_LCD_D01__LCD_D1 | MUX_CONFIG_LCD,
+ MX28_PAD_LCD_D02__LCD_D2 | MUX_CONFIG_LCD,
+ MX28_PAD_LCD_D03__LCD_D3 | MUX_CONFIG_LCD,
+ MX28_PAD_LCD_D04__LCD_D4 | MUX_CONFIG_LCD,
+ MX28_PAD_LCD_D05__LCD_D5 | MUX_CONFIG_LCD,
+ MX28_PAD_LCD_D06__LCD_D6 | MUX_CONFIG_LCD,
+ MX28_PAD_LCD_D07__LCD_D7 | MUX_CONFIG_LCD,
+ MX28_PAD_LCD_D08__LCD_D8 | MUX_CONFIG_LCD,
+ MX28_PAD_LCD_D09__LCD_D9 | MUX_CONFIG_LCD,
+ MX28_PAD_LCD_D10__LCD_D10 | MUX_CONFIG_LCD,
+ MX28_PAD_LCD_D11__LCD_D11 | MUX_CONFIG_LCD,
+ MX28_PAD_LCD_D12__LCD_D12 | MUX_CONFIG_LCD,
+ MX28_PAD_LCD_D13__LCD_D13 | MUX_CONFIG_LCD,
+ MX28_PAD_LCD_D14__LCD_D14 | MUX_CONFIG_LCD,
+ MX28_PAD_LCD_D15__LCD_D15 | MUX_CONFIG_LCD,
+ MX28_PAD_LCD_D16__LCD_D16 | MUX_CONFIG_LCD,
+ MX28_PAD_LCD_D17__LCD_D17 | MUX_CONFIG_LCD,
+ MX28_PAD_LCD_D18__LCD_D18 | MUX_CONFIG_LCD,
+ MX28_PAD_LCD_D19__LCD_D19 | MUX_CONFIG_LCD,
+ MX28_PAD_LCD_D20__LCD_D20 | MUX_CONFIG_LCD,
+ MX28_PAD_LCD_D21__LCD_D21 | MUX_CONFIG_LCD,
+ MX28_PAD_LCD_D22__LCD_D22 | MUX_CONFIG_LCD,
+ MX28_PAD_LCD_D23__LCD_D23 | MUX_CONFIG_LCD,
+ MX28_PAD_LCD_RD_E__LCD_VSYNC | MUX_CONFIG_LCD,
+ MX28_PAD_LCD_WR_RWN__LCD_HSYNC | MUX_CONFIG_LCD,
+ MX28_PAD_LCD_RS__LCD_DOTCLK | MUX_CONFIG_LCD,
+ MX28_PAD_LCD_CS__LCD_CS | MUX_CONFIG_LCD,
+ MX28_PAD_LCD_VSYNC__LCD_VSYNC | MUX_CONFIG_LCD,
+ MX28_PAD_LCD_HSYNC__LCD_HSYNC | MUX_CONFIG_LCD,
+ MX28_PAD_LCD_DOTCLK__LCD_DOTCLK | MUX_CONFIG_LCD,
+ MX28_PAD_LCD_ENABLE__GPIO_1_31 | MUX_CONFIG_LCD,
+ MX28_PAD_LCD_RESET__GPIO_3_30 | MUX_CONFIG_LCD,
+
+ /* UART1 */
+ MX28_PAD_PWM0__DUART_RX,
+ MX28_PAD_PWM1__DUART_TX,
+ MX28_PAD_AUART0_TX__DUART_RTS,
+ MX28_PAD_AUART0_RX__DUART_CTS,
+
+ /* UART2 */
+ MX28_PAD_AUART1_RX__AUART1_RX,
+ MX28_PAD_AUART1_TX__AUART1_TX,
+ MX28_PAD_AUART1_RTS__AUART1_RTS,
+ MX28_PAD_AUART1_CTS__AUART1_CTS,
+
+ /* CAN */
+ MX28_PAD_GPMI_RDY2__CAN0_TX,
+ MX28_PAD_GPMI_RDY3__CAN0_RX,
+
+ /* I2C */
+ MX28_PAD_I2C0_SCL__I2C0_SCL,
+ MX28_PAD_I2C0_SDA__I2C0_SDA,
+
+ /* TSC2007 */
+ MX28_PAD_SAIF0_MCLK__GPIO_3_20 | MUX_CONFIG_TSC,
+
+ /* MMC0 */
+ MX28_PAD_SSP0_DATA0__SSP0_D0 | MUX_CONFIG_SSP0,
+ MX28_PAD_SSP0_DATA1__SSP0_D1 | MUX_CONFIG_SSP0,
+ MX28_PAD_SSP0_DATA2__SSP0_D2 | MUX_CONFIG_SSP0,
+ MX28_PAD_SSP0_DATA3__SSP0_D3 | MUX_CONFIG_SSP0,
+ MX28_PAD_SSP0_DATA4__SSP0_D4 | MUX_CONFIG_SSP0,
+ MX28_PAD_SSP0_DATA5__SSP0_D5 | MUX_CONFIG_SSP0,
+ MX28_PAD_SSP0_DATA6__SSP0_D6 | MUX_CONFIG_SSP0,
+ MX28_PAD_SSP0_DATA7__SSP0_D7 | MUX_CONFIG_SSP0,
+ MX28_PAD_SSP0_CMD__SSP0_CMD | MUX_CONFIG_SSP0,
+ MX28_PAD_SSP0_DETECT__SSP0_CARD_DETECT |
+ (MXS_PAD_3V3 | MXS_PAD_12MA | MXS_PAD_NOPULL),
+ MX28_PAD_SSP0_SCK__SSP0_SCK |
+ (MXS_PAD_3V3 | MXS_PAD_12MA | MXS_PAD_NOPULL),
+ MX28_PAD_PWM3__GPIO_3_28 | MUX_CONFIG_SSP0, /* Power .. FIXME */
+ MX28_PAD_AUART2_CTS__GPIO_3_10, /* WP ... FIXME */
+
+ /* GPMI NAND */
+ MX28_PAD_GPMI_D00__GPMI_D0 | MUX_CONFIG_GPMI,
+ MX28_PAD_GPMI_D01__GPMI_D1 | MUX_CONFIG_GPMI,
+ MX28_PAD_GPMI_D02__GPMI_D2 | MUX_CONFIG_GPMI,
+ MX28_PAD_GPMI_D03__GPMI_D3 | MUX_CONFIG_GPMI,
+ MX28_PAD_GPMI_D04__GPMI_D4 | MUX_CONFIG_GPMI,
+ MX28_PAD_GPMI_D05__GPMI_D5 | MUX_CONFIG_GPMI,
+ MX28_PAD_GPMI_D06__GPMI_D6 | MUX_CONFIG_GPMI,
+ MX28_PAD_GPMI_D07__GPMI_D7 | MUX_CONFIG_GPMI,
+ MX28_PAD_GPMI_CE0N__GPMI_CE0N | MUX_CONFIG_GPMI,
+ MX28_PAD_GPMI_RDY0__GPMI_READY0 | MUX_CONFIG_GPMI,
+ MX28_PAD_GPMI_RDN__GPMI_RDN |
+ (MXS_PAD_1V8 | MXS_PAD_8MA | MXS_PAD_PULLUP),
+ MX28_PAD_GPMI_WRN__GPMI_WRN | MUX_CONFIG_GPMI,
+ MX28_PAD_GPMI_ALE__GPMI_ALE | MUX_CONFIG_GPMI,
+ MX28_PAD_GPMI_CLE__GPMI_CLE | MUX_CONFIG_GPMI,
+ MX28_PAD_GPMI_RESETN__GPMI_RESETN | MUX_CONFIG_GPMI,
+
+ /* FEC Ethernet */
+ MX28_PAD_ENET0_MDC__ENET0_MDC | MUX_CONFIG_ENET,
+ MX28_PAD_ENET0_MDIO__ENET0_MDIO | MUX_CONFIG_ENET,
+ MX28_PAD_ENET0_RX_EN__ENET0_RX_EN | MUX_CONFIG_ENET,
+ MX28_PAD_ENET0_TX_EN__ENET0_TX_EN | MUX_CONFIG_ENET,
+ MX28_PAD_ENET0_RXD0__ENET0_RXD0 | MUX_CONFIG_ENET,
+ MX28_PAD_ENET0_RXD1__ENET0_RXD1 | MUX_CONFIG_ENET,
+ MX28_PAD_ENET0_TXD0__ENET0_TXD0 | MUX_CONFIG_ENET,
+ MX28_PAD_ENET0_TXD1__ENET0_TXD1 | MUX_CONFIG_ENET,
+ MX28_PAD_ENET_CLK__CLKCTRL_ENET | MUX_CONFIG_ENET,
+
+ MX28_PAD_ENET0_COL__ENET1_TX_EN | MUX_CONFIG_ENET,
+ MX28_PAD_ENET0_CRS__ENET1_RX_EN | MUX_CONFIG_ENET,
+ MX28_PAD_ENET0_RXD2__ENET1_RXD0 | MUX_CONFIG_ENET,
+ MX28_PAD_ENET0_RXD3__ENET1_RXD1 | MUX_CONFIG_ENET,
+ MX28_PAD_ENET0_TXD2__ENET1_TXD0 | MUX_CONFIG_ENET,
+ MX28_PAD_ENET0_TXD3__ENET1_TXD1 | MUX_CONFIG_ENET,
+
+ /* I2C */
+ MX28_PAD_I2C0_SCL__I2C0_SCL,
+ MX28_PAD_I2C0_SDA__I2C0_SDA,
+
+ /* EMI */
+ MX28_PAD_EMI_D00__EMI_DATA0 | MUX_CONFIG_EMI,
+ MX28_PAD_EMI_D01__EMI_DATA1 | MUX_CONFIG_EMI,
+ MX28_PAD_EMI_D02__EMI_DATA2 | MUX_CONFIG_EMI,
+ MX28_PAD_EMI_D03__EMI_DATA3 | MUX_CONFIG_EMI,
+ MX28_PAD_EMI_D04__EMI_DATA4 | MUX_CONFIG_EMI,
+ MX28_PAD_EMI_D05__EMI_DATA5 | MUX_CONFIG_EMI,
+ MX28_PAD_EMI_D06__EMI_DATA6 | MUX_CONFIG_EMI,
+ MX28_PAD_EMI_D07__EMI_DATA7 | MUX_CONFIG_EMI,
+ MX28_PAD_EMI_D08__EMI_DATA8 | MUX_CONFIG_EMI,
+ MX28_PAD_EMI_D09__EMI_DATA9 | MUX_CONFIG_EMI,
+ MX28_PAD_EMI_D10__EMI_DATA10 | MUX_CONFIG_EMI,
+ MX28_PAD_EMI_D11__EMI_DATA11 | MUX_CONFIG_EMI,
+ MX28_PAD_EMI_D12__EMI_DATA12 | MUX_CONFIG_EMI,
+ MX28_PAD_EMI_D13__EMI_DATA13 | MUX_CONFIG_EMI,
+ MX28_PAD_EMI_D14__EMI_DATA14 | MUX_CONFIG_EMI,
+ MX28_PAD_EMI_D15__EMI_DATA15 | MUX_CONFIG_EMI,
+ MX28_PAD_EMI_ODT0__EMI_ODT0 | MUX_CONFIG_EMI,
+ MX28_PAD_EMI_DQM0__EMI_DQM0 | MUX_CONFIG_EMI,
+ MX28_PAD_EMI_ODT1__EMI_ODT1 | MUX_CONFIG_EMI,
+ MX28_PAD_EMI_DQM1__EMI_DQM1 | MUX_CONFIG_EMI,
+ MX28_PAD_EMI_DDR_OPEN_FB__EMI_DDR_OPEN_FEEDBACK | MUX_CONFIG_EMI,
+ MX28_PAD_EMI_CLK__EMI_CLK | MUX_CONFIG_EMI,
+ MX28_PAD_EMI_DQS0__EMI_DQS0 | MUX_CONFIG_EMI,
+ MX28_PAD_EMI_DQS1__EMI_DQS1 | MUX_CONFIG_EMI,
+ MX28_PAD_EMI_DDR_OPEN__EMI_DDR_OPEN | MUX_CONFIG_EMI,
+
+ MX28_PAD_EMI_A00__EMI_ADDR0 | MUX_CONFIG_EMI,
+ MX28_PAD_EMI_A01__EMI_ADDR1 | MUX_CONFIG_EMI,
+ MX28_PAD_EMI_A02__EMI_ADDR2 | MUX_CONFIG_EMI,
+ MX28_PAD_EMI_A03__EMI_ADDR3 | MUX_CONFIG_EMI,
+ MX28_PAD_EMI_A04__EMI_ADDR4 | MUX_CONFIG_EMI,
+ MX28_PAD_EMI_A05__EMI_ADDR5 | MUX_CONFIG_EMI,
+ MX28_PAD_EMI_A06__EMI_ADDR6 | MUX_CONFIG_EMI,
+ MX28_PAD_EMI_A07__EMI_ADDR7 | MUX_CONFIG_EMI,
+ MX28_PAD_EMI_A08__EMI_ADDR8 | MUX_CONFIG_EMI,
+ MX28_PAD_EMI_A09__EMI_ADDR9 | MUX_CONFIG_EMI,
+ MX28_PAD_EMI_A10__EMI_ADDR10 | MUX_CONFIG_EMI,
+ MX28_PAD_EMI_A11__EMI_ADDR11 | MUX_CONFIG_EMI,
+ MX28_PAD_EMI_A12__EMI_ADDR12 | MUX_CONFIG_EMI,
+ MX28_PAD_EMI_A13__EMI_ADDR13 | MUX_CONFIG_EMI,
+ MX28_PAD_EMI_A14__EMI_ADDR14 | MUX_CONFIG_EMI,
+ MX28_PAD_EMI_BA0__EMI_BA0 | MUX_CONFIG_EMI,
+ MX28_PAD_EMI_BA1__EMI_BA1 | MUX_CONFIG_EMI,
+ MX28_PAD_EMI_BA2__EMI_BA2 | MUX_CONFIG_EMI,
+ MX28_PAD_EMI_CASN__EMI_CASN | MUX_CONFIG_EMI,
+ MX28_PAD_EMI_RASN__EMI_RASN | MUX_CONFIG_EMI,
+ MX28_PAD_EMI_WEN__EMI_WEN | MUX_CONFIG_EMI,
+ MX28_PAD_EMI_CE0N__EMI_CE0N | MUX_CONFIG_EMI,
+ MX28_PAD_EMI_CE1N__EMI_CE1N | MUX_CONFIG_EMI,
+ MX28_PAD_EMI_CKE__EMI_CKE | MUX_CONFIG_EMI,
+
+ /* SPI2 (for flash) */
+ MX28_PAD_SSP2_SCK__SSP2_SCK | MUX_CONFIG_SSP2,
+ MX28_PAD_SSP2_MOSI__SSP2_CMD | MUX_CONFIG_SSP2,
+ MX28_PAD_SSP2_MISO__SSP2_D0 | MUX_CONFIG_SSP2,
+ MX28_PAD_SSP2_SS0__SSP2_D3 |
+ (MXS_PAD_3V3 | MXS_PAD_8MA | MXS_PAD_PULLUP),
+};
+
+void board_init_ll(void)
+{
+ mxs_iomux_setup_multiple_pads(iomux_setup, ARRAY_SIZE(iomux_setup));
+ mx28_power_init();
+ mx28_mem_init();
+ mx28_power_wait_pswitch();
+}
+
+/* Support aparatus */
+inline void board_init_f(unsigned long bootflag)
+{
+ for (;;)
+ ;
+}
+
+inline void board_init_r(gd_t *id, ulong dest_addr)
+{
+ for (;;)
+ ;
+}
+
+inline int printf(const char *fmt, ...)
+{
+ return 0;
+}
+
+inline void __coloured_LED_init(void) {}
+inline void __red_LED_on(void) {}
+void coloured_LED_init(void)
+ __attribute__((weak, alias("__coloured_LED_init")));
+void red_LED_on(void)
+ __attribute__((weak, alias("__red_LED_on")));
+void hang(void) __attribute__ ((noreturn));
+void hang(void)
+{
+ for (;;)
+ ;
+}
diff --git a/board/denx/m28evk/power_init.c b/board/denx/m28evk/power_init.c
new file mode 100644
index 0000000..27322b4
--- /dev/null
+++ b/board/denx/m28evk/power_init.c
@@ -0,0 +1,913 @@
+/*
+ * Freescale i.MX28 Boot PMIC init
+ *
+ * Copyright (C) 2011 Marek Vasut <marek.vasut@gmail.com>
+ * on behalf of DENX Software Engineering GmbH
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <config.h>
+#include <asm/io.h>
+#include <asm/arch/imx-regs.h>
+
+#include "m28_init.h"
+
+void mx28_power_clock2xtal(void)
+{
+ struct mx28_clkctrl_regs *clkctrl_regs =
+ (struct mx28_clkctrl_regs *)MXS_CLKCTRL_BASE;
+
+ /* Set XTAL as CPU reference clock */
+ writel(CLKCTRL_CLKSEQ_BYPASS_CPU,
+ &clkctrl_regs->hw_clkctrl_clkseq_set);
+}
+
+void mx28_power_clock2pll(void)
+{
+ struct mx28_clkctrl_regs *clkctrl_regs =
+ (struct mx28_clkctrl_regs *)MXS_CLKCTRL_BASE;
+
+ writel(CLKCTRL_PLL0CTRL0_POWER,
+ &clkctrl_regs->hw_clkctrl_pll0ctrl0_set);
+ early_delay(100);
+ writel(CLKCTRL_CLKSEQ_BYPASS_CPU,
+ &clkctrl_regs->hw_clkctrl_clkseq_clr);
+}
+
+void mx28_power_clear_auto_restart(void)
+{
+ struct mx28_rtc_regs *rtc_regs =
+ (struct mx28_rtc_regs *)MXS_RTC_BASE;
+
+ writel(RTC_CTRL_SFTRST, &rtc_regs->hw_rtc_ctrl_clr);
+ while (readl(&rtc_regs->hw_rtc_ctrl) & RTC_CTRL_SFTRST)
+ ;
+
+ writel(RTC_CTRL_CLKGATE, &rtc_regs->hw_rtc_ctrl_clr);
+ while (readl(&rtc_regs->hw_rtc_ctrl) & RTC_CTRL_CLKGATE)
+ ;
+
+ /*
+ * Due to the hardware design bug of mx28 EVK-A
+ * we need to set the AUTO_RESTART bit.
+ */
+ if (readl(&rtc_regs->hw_rtc_persistent0) & RTC_PERSISTENT0_AUTO_RESTART)
+ return;
+
+ while (readl(&rtc_regs->hw_rtc_stat) & RTC_STAT_NEW_REGS_MASK)
+ ;
+
+ setbits_le32(&rtc_regs->hw_rtc_persistent0,
+ RTC_PERSISTENT0_AUTO_RESTART);
+ writel(RTC_CTRL_FORCE_UPDATE, &rtc_regs->hw_rtc_ctrl_set);
+ writel(RTC_CTRL_FORCE_UPDATE, &rtc_regs->hw_rtc_ctrl_clr);
+ while (readl(&rtc_regs->hw_rtc_stat) & RTC_STAT_NEW_REGS_MASK)
+ ;
+ while (readl(&rtc_regs->hw_rtc_stat) & RTC_STAT_STALE_REGS_MASK)
+ ;
+}
+
+void mx28_power_set_linreg(void)
+{
+ struct mx28_power_regs *power_regs =
+ (struct mx28_power_regs *)MXS_POWER_BASE;
+
+ /* Set linear regulator 25mV below switching converter */
+ clrsetbits_le32(&power_regs->hw_power_vdddctrl,
+ POWER_VDDDCTRL_LINREG_OFFSET_MASK,
+ POWER_VDDDCTRL_LINREG_OFFSET_1STEPS_BELOW);
+
+ clrsetbits_le32(&power_regs->hw_power_vddactrl,
+ POWER_VDDACTRL_LINREG_OFFSET_MASK,
+ POWER_VDDACTRL_LINREG_OFFSET_1STEPS_BELOW);
+
+ clrsetbits_le32(&power_regs->hw_power_vddioctrl,
+ POWER_VDDIOCTRL_LINREG_OFFSET_MASK,
+ POWER_VDDIOCTRL_LINREG_OFFSET_1STEPS_BELOW);
+}
+
+void mx28_power_setup_5v_detect(void)
+{
+ struct mx28_power_regs *power_regs =
+ (struct mx28_power_regs *)MXS_POWER_BASE;
+
+ /* Start 5V detection */
+ clrsetbits_le32(&power_regs->hw_power_5vctrl,
+ POWER_5VCTRL_VBUSVALID_TRSH_MASK,
+ POWER_5VCTRL_VBUSVALID_TRSH_4V4 |
+ POWER_5VCTRL_PWRUP_VBUS_CMPS);
+}
+
+void mx28_src_power_init(void)
+{
+ struct mx28_power_regs *power_regs =
+ (struct mx28_power_regs *)MXS_POWER_BASE;
+
+ /* Improve efficieny and reduce transient ripple */
+ writel(POWER_LOOPCTRL_TOGGLE_DIF | POWER_LOOPCTRL_EN_CM_HYST |
+ POWER_LOOPCTRL_EN_DF_HYST, &power_regs->hw_power_loopctrl_set);
+
+ clrsetbits_le32(&power_regs->hw_power_dclimits,
+ POWER_DCLIMITS_POSLIMIT_BUCK_MASK,
+ 0x30 << POWER_DCLIMITS_POSLIMIT_BUCK_OFFSET);
+
+ setbits_le32(&power_regs->hw_power_battmonitor,
+ POWER_BATTMONITOR_EN_BATADJ);
+
+ /* Increase the RCSCALE level for quick DCDC response to dynamic load */
+ clrsetbits_le32(&power_regs->hw_power_loopctrl,
+ POWER_LOOPCTRL_EN_RCSCALE_MASK,
+ POWER_LOOPCTRL_RCSCALE_THRESH |
+ POWER_LOOPCTRL_EN_RCSCALE_8X);
+
+ clrsetbits_le32(&power_regs->hw_power_minpwr,
+ POWER_MINPWR_HALFFETS, POWER_MINPWR_DOUBLE_FETS);
+
+ /* 5V to battery handoff ... FIXME */
+ setbits_le32(&power_regs->hw_power_5vctrl, POWER_5VCTRL_DCDC_XFER);
+ early_delay(30);
+ clrbits_le32(&power_regs->hw_power_5vctrl, POWER_5VCTRL_DCDC_XFER);
+}
+
+void mx28_power_init_4p2_params(void)
+{
+ struct mx28_power_regs *power_regs =
+ (struct mx28_power_regs *)MXS_POWER_BASE;
+
+ /* Setup 4P2 parameters */
+ clrsetbits_le32(&power_regs->hw_power_dcdc4p2,
+ POWER_DCDC4P2_CMPTRIP_MASK | POWER_DCDC4P2_TRG_MASK,
+ POWER_DCDC4P2_TRG_4V2 | (31 << POWER_DCDC4P2_CMPTRIP_OFFSET));
+
+ clrsetbits_le32(&power_regs->hw_power_5vctrl,
+ POWER_5VCTRL_HEADROOM_ADJ_MASK,
+ 0x4 << POWER_5VCTRL_HEADROOM_ADJ_OFFSET);
+
+ clrsetbits_le32(&power_regs->hw_power_dcdc4p2,
+ POWER_DCDC4P2_DROPOUT_CTRL_MASK,
+ POWER_DCDC4P2_DROPOUT_CTRL_100MV |
+ POWER_DCDC4P2_DROPOUT_CTRL_SRC_SEL);
+
+ clrsetbits_le32(&power_regs->hw_power_5vctrl,
+ POWER_5VCTRL_CHARGE_4P2_ILIMIT_MASK,
+ 0x3f << POWER_5VCTRL_CHARGE_4P2_ILIMIT_OFFSET);
+}
+
+void mx28_enable_4p2_dcdc_input(int xfer)
+{
+ struct mx28_power_regs *power_regs =
+ (struct mx28_power_regs *)MXS_POWER_BASE;
+ uint32_t tmp, vbus_thresh, vbus_5vdetect, pwd_bo;
+ uint32_t prev_5v_brnout, prev_5v_droop;
+
+ prev_5v_brnout = readl(&power_regs->hw_power_5vctrl) &
+ POWER_5VCTRL_PWDN_5VBRNOUT;
+ prev_5v_droop = readl(&power_regs->hw_power_ctrl) &
+ POWER_CTRL_ENIRQ_VDD5V_DROOP;
+
+ clrbits_le32(&power_regs->hw_power_5vctrl, POWER_5VCTRL_PWDN_5VBRNOUT);
+ writel(POWER_RESET_UNLOCK_KEY | POWER_RESET_PWD_OFF,
+ &power_regs->hw_power_reset);
+
+ clrbits_le32(&power_regs->hw_power_ctrl, POWER_CTRL_ENIRQ_VDD5V_DROOP);
+
+ if (xfer && (readl(&power_regs->hw_power_5vctrl) &
+ POWER_5VCTRL_ENABLE_DCDC)) {
+ return;
+ }
+
+ /*
+ * Recording orignal values that will be modified temporarlily
+ * to handle a chip bug. See chip errata for CQ ENGR00115837
+ */
+ tmp = readl(&power_regs->hw_power_5vctrl);
+ vbus_thresh = tmp & POWER_5VCTRL_VBUSVALID_TRSH_MASK;
+ vbus_5vdetect = tmp & POWER_5VCTRL_VBUSVALID_5VDETECT;
+
+ pwd_bo = readl(&power_regs->hw_power_minpwr) & POWER_MINPWR_PWD_BO;
+
+ /*
+ * Disable mechanisms that get erroneously tripped by when setting
+ * the DCDC4P2 EN_DCDC
+ */
+ clrbits_le32(&power_regs->hw_power_5vctrl,
+ POWER_5VCTRL_VBUSVALID_5VDETECT |
+ POWER_5VCTRL_VBUSVALID_TRSH_MASK);
+
+ writel(POWER_MINPWR_PWD_BO, &power_regs->hw_power_minpwr_set);
+
+ if (xfer) {
+ setbits_le32(&power_regs->hw_power_5vctrl,
+ POWER_5VCTRL_DCDC_XFER);
+ early_delay(20);
+ clrbits_le32(&power_regs->hw_power_5vctrl,
+ POWER_5VCTRL_DCDC_XFER);
+
+ setbits_le32(&power_regs->hw_power_5vctrl,
+ POWER_5VCTRL_ENABLE_DCDC);
+ } else {
+ setbits_le32(&power_regs->hw_power_dcdc4p2,
+ POWER_DCDC4P2_ENABLE_DCDC);
+ }
+
+ early_delay(25);
+
+ clrsetbits_le32(&power_regs->hw_power_5vctrl,
+ POWER_5VCTRL_VBUSVALID_TRSH_MASK, vbus_thresh);
+
+ if (vbus_5vdetect)
+ writel(vbus_5vdetect, &power_regs->hw_power_5vctrl_set);
+
+ if (!pwd_bo)
+ clrbits_le32(&power_regs->hw_power_minpwr, POWER_MINPWR_PWD_BO);
+
+ while (readl(&power_regs->hw_power_ctrl) & POWER_CTRL_VBUS_VALID_IRQ)
+ clrbits_le32(&power_regs->hw_power_ctrl,
+ POWER_CTRL_VBUS_VALID_IRQ);
+
+ if (prev_5v_brnout) {
+ writel(POWER_5VCTRL_PWDN_5VBRNOUT,
+ &power_regs->hw_power_5vctrl_set);
+ writel(POWER_RESET_UNLOCK_KEY,
+ &power_regs->hw_power_reset);
+ } else {
+ writel(POWER_5VCTRL_PWDN_5VBRNOUT,
+ &power_regs->hw_power_5vctrl_clr);
+ writel(POWER_RESET_UNLOCK_KEY | POWER_RESET_PWD_OFF,
+ &power_regs->hw_power_reset);
+ }
+
+ while (readl(&power_regs->hw_power_ctrl) & POWER_CTRL_VDD5V_DROOP_IRQ)
+ clrbits_le32(&power_regs->hw_power_ctrl,
+ POWER_CTRL_VDD5V_DROOP_IRQ);
+
+ if (prev_5v_droop)
+ clrbits_le32(&power_regs->hw_power_ctrl,
+ POWER_CTRL_ENIRQ_VDD5V_DROOP);
+ else
+ setbits_le32(&power_regs->hw_power_ctrl,
+ POWER_CTRL_ENIRQ_VDD5V_DROOP);
+}
+
+void mx28_power_init_4p2_regulator(void)
+{
+ struct mx28_power_regs *power_regs =
+ (struct mx28_power_regs *)MXS_POWER_BASE;
+ uint32_t tmp, tmp2;
+
+ setbits_le32(&power_regs->hw_power_dcdc4p2, POWER_DCDC4P2_ENABLE_4P2);
+
+ writel(POWER_CHARGE_ENABLE_LOAD, &power_regs->hw_power_charge_set);
+
+ writel(POWER_5VCTRL_CHARGE_4P2_ILIMIT_MASK,
+ &power_regs->hw_power_5vctrl_clr);
+ clrbits_le32(&power_regs->hw_power_dcdc4p2, POWER_DCDC4P2_TRG_MASK);
+
+ /* Power up the 4p2 rail and logic/control */
+ writel(POWER_5VCTRL_PWD_CHARGE_4P2_MASK,
+ &power_regs->hw_power_5vctrl_clr);
+
+ /*
+ * Start charging up the 4p2 capacitor. We ramp of this charge
+ * gradually to avoid large inrush current from the 5V cable which can
+ * cause transients/problems
+ */
+ mx28_enable_4p2_dcdc_input(0);
+
+ if (readl(&power_regs->hw_power_ctrl) & POWER_CTRL_VBUS_VALID_IRQ) {
+ /*
+ * If we arrived here, we were unable to recover from mx23 chip
+ * errata 5837. 4P2 is disabled and sufficient battery power is
+ * not present. Exiting to not enable DCDC power during 5V
+ * connected state.
+ */
+ clrbits_le32(&power_regs->hw_power_dcdc4p2,
+ POWER_DCDC4P2_ENABLE_DCDC);
+ writel(POWER_5VCTRL_PWD_CHARGE_4P2_MASK,
+ &power_regs->hw_power_5vctrl_set);
+ hang();
+ }
+
+ /*
+ * Here we set the 4p2 brownout level to something very close to 4.2V.
+ * We then check the brownout status. If the brownout status is false,
+ * the voltage is already close to the target voltage of 4.2V so we
+ * can go ahead and set the 4P2 current limit to our max target limit.
+ * If the brownout status is true, we need to ramp us the current limit
+ * so that we don't cause large inrush current issues. We step up the
+ * current limit until the brownout status is false or until we've
+ * reached our maximum defined 4p2 current limit.
+ */
+ clrsetbits_le32(&power_regs->hw_power_dcdc4p2,
+ POWER_DCDC4P2_BO_MASK,
+ 22 << POWER_DCDC4P2_BO_OFFSET); /* 4.15V */
+
+ if (!(readl(&power_regs->hw_power_sts) & POWER_STS_DCDC_4P2_BO)) {
+ setbits_le32(&power_regs->hw_power_5vctrl,
+ 0x3f << POWER_5VCTRL_CHARGE_4P2_ILIMIT_OFFSET);
+ } else {
+ tmp = (readl(&power_regs->hw_power_5vctrl) &
+ POWER_5VCTRL_CHARGE_4P2_ILIMIT_MASK) >>
+ POWER_5VCTRL_CHARGE_4P2_ILIMIT_OFFSET;
+ while (tmp < 0x3f) {
+ if (!(readl(&power_regs->hw_power_sts) &
+ POWER_STS_DCDC_4P2_BO)) {
+ tmp = readl(&power_regs->hw_power_5vctrl);
+ tmp |= POWER_5VCTRL_CHARGE_4P2_ILIMIT_MASK;
+ early_delay(100);
+ writel(tmp, &power_regs->hw_power_5vctrl);
+ break;
+ } else {
+ tmp++;
+ tmp2 = readl(&power_regs->hw_power_5vctrl);
+ tmp2 &= ~POWER_5VCTRL_CHARGE_4P2_ILIMIT_MASK;
+ tmp2 |= tmp <<
+ POWER_5VCTRL_CHARGE_4P2_ILIMIT_OFFSET;
+ writel(tmp2, &power_regs->hw_power_5vctrl);
+ early_delay(100);
+ }
+ }
+ }
+
+ clrbits_le32(&power_regs->hw_power_dcdc4p2, POWER_DCDC4P2_BO_MASK);
+ writel(POWER_CTRL_DCDC4P2_BO_IRQ, &power_regs->hw_power_ctrl_clr);
+}
+
+void mx28_power_init_dcdc_4p2_source(void)
+{
+ struct mx28_power_regs *power_regs =
+ (struct mx28_power_regs *)MXS_POWER_BASE;
+
+ if (!(readl(&power_regs->hw_power_dcdc4p2) &
+ POWER_DCDC4P2_ENABLE_DCDC)) {
+ hang();
+ }
+
+ mx28_enable_4p2_dcdc_input(1);
+
+ if (readl(&power_regs->hw_power_ctrl) & POWER_CTRL_VBUS_VALID_IRQ) {
+ clrbits_le32(&power_regs->hw_power_dcdc4p2,
+ POWER_DCDC4P2_ENABLE_DCDC);
+ writel(POWER_5VCTRL_ENABLE_DCDC,
+ &power_regs->hw_power_5vctrl_clr);
+ writel(POWER_5VCTRL_PWD_CHARGE_4P2_MASK,
+ &power_regs->hw_power_5vctrl_set);
+ }
+}
+
+void mx28_power_enable_4p2(void)
+{
+ struct mx28_power_regs *power_regs =
+ (struct mx28_power_regs *)MXS_POWER_BASE;
+ uint32_t vdddctrl, vddactrl, vddioctrl;
+ uint32_t tmp;
+
+ vdddctrl = readl(&power_regs->hw_power_vdddctrl);
+ vddactrl = readl(&power_regs->hw_power_vddactrl);
+ vddioctrl = readl(&power_regs->hw_power_vddioctrl);
+
+ setbits_le32(&power_regs->hw_power_vdddctrl,
+ POWER_VDDDCTRL_DISABLE_FET | POWER_VDDDCTRL_ENABLE_LINREG |
+ POWER_VDDDCTRL_PWDN_BRNOUT);
+
+ setbits_le32(&power_regs->hw_power_vddactrl,
+ POWER_VDDACTRL_DISABLE_FET | POWER_VDDACTRL_ENABLE_LINREG |
+ POWER_VDDACTRL_PWDN_BRNOUT);
+
+ setbits_le32(&power_regs->hw_power_vddioctrl,
+ POWER_VDDIOCTRL_DISABLE_FET | POWER_VDDIOCTRL_PWDN_BRNOUT);
+
+ mx28_power_init_4p2_params();
+ mx28_power_init_4p2_regulator();
+
+ /* Shutdown battery (none present) */
+ clrbits_le32(&power_regs->hw_power_dcdc4p2, POWER_DCDC4P2_BO_MASK);
+ writel(POWER_CTRL_DCDC4P2_BO_IRQ, &power_regs->hw_power_ctrl_clr);
+ writel(POWER_CTRL_ENIRQ_DCDC4P2_BO, &power_regs->hw_power_ctrl_clr);
+
+ mx28_power_init_dcdc_4p2_source();
+
+ writel(vdddctrl, &power_regs->hw_power_vdddctrl);
+ early_delay(20);
+ writel(vddactrl, &power_regs->hw_power_vddactrl);
+ early_delay(20);
+ writel(vddioctrl, &power_regs->hw_power_vddioctrl);
+
+ /*
+ * Check if FET is enabled on either powerout and if so,
+ * disable load.
+ */
+ tmp = 0;
+ tmp |= !(readl(&power_regs->hw_power_vdddctrl) &
+ POWER_VDDDCTRL_DISABLE_FET);
+ tmp |= !(readl(&power_regs->hw_power_vddactrl) &
+ POWER_VDDACTRL_DISABLE_FET);
+ tmp |= !(readl(&power_regs->hw_power_vddioctrl) &
+ POWER_VDDIOCTRL_DISABLE_FET);
+ if (tmp)
+ writel(POWER_CHARGE_ENABLE_LOAD,
+ &power_regs->hw_power_charge_clr);
+}
+
+void mx28_boot_valid_5v(void)
+{
+ struct mx28_power_regs *power_regs =
+ (struct mx28_power_regs *)MXS_POWER_BASE;
+
+ /*
+ * Use VBUSVALID level instead of VDD5V_GT_VDDIO level to trigger a 5V
+ * disconnect event. FIXME
+ */
+ writel(POWER_5VCTRL_VBUSVALID_5VDETECT,
+ &power_regs->hw_power_5vctrl_set);
+
+ /* Configure polarity to check for 5V disconnection. */
+ writel(POWER_CTRL_POLARITY_VBUSVALID |
+ POWER_CTRL_POLARITY_VDD5V_GT_VDDIO,
+ &power_regs->hw_power_ctrl_clr);
+
+ writel(POWER_CTRL_VBUS_VALID_IRQ | POWER_CTRL_VDD5V_GT_VDDIO_IRQ,
+ &power_regs->hw_power_ctrl_clr);
+
+ mx28_power_enable_4p2();
+}
+
+void mx28_powerdown(void)
+{
+ struct mx28_power_regs *power_regs =
+ (struct mx28_power_regs *)MXS_POWER_BASE;
+ writel(POWER_RESET_UNLOCK_KEY, &power_regs->hw_power_reset);
+ writel(POWER_RESET_UNLOCK_KEY | POWER_RESET_PWD_OFF,
+ &power_regs->hw_power_reset);
+}
+
+void mx28_handle_5v_conflict(void)
+{
+ struct mx28_power_regs *power_regs =
+ (struct mx28_power_regs *)MXS_POWER_BASE;
+ uint32_t tmp;
+
+ setbits_le32(&power_regs->hw_power_vddioctrl,
+ POWER_VDDIOCTRL_BO_OFFSET_MASK);
+
+ for (;;) {
+ tmp = readl(&power_regs->hw_power_sts);
+
+ if (tmp & POWER_STS_VDDIO_BO) {
+ mx28_powerdown();
+ break;
+ }
+
+ if (tmp & POWER_STS_VDD5V_GT_VDDIO) {
+ mx28_boot_valid_5v();
+ break;
+ } else {
+ mx28_powerdown();
+ break;
+ }
+ }
+}
+
+int mx28_get_batt_volt(void)
+{
+ struct mx28_power_regs *power_regs =
+ (struct mx28_power_regs *)MXS_POWER_BASE;
+ uint32_t volt = readl(&power_regs->hw_power_battmonitor);
+ volt &= POWER_BATTMONITOR_BATT_VAL_MASK;
+ volt >>= POWER_BATTMONITOR_BATT_VAL_OFFSET;
+ volt *= 8;
+ return volt;
+}
+
+int mx28_is_batt_ready(void)
+{
+ return (mx28_get_batt_volt() >= 3600);
+}
+
+void mx28_5v_boot(void)
+{
+ struct mx28_power_regs *power_regs =
+ (struct mx28_power_regs *)MXS_POWER_BASE;
+
+ /*
+ * NOTE: In original IMX-Bootlets, this also checks for VBUSVALID,
+ * but their implementation always returns 1 so we omit it here.
+ */
+ if (readl(&power_regs->hw_power_sts) & POWER_STS_VDD5V_GT_VDDIO) {
+ mx28_boot_valid_5v();
+ return;
+ }
+
+ early_delay(1000);
+ if (readl(&power_regs->hw_power_sts) & POWER_STS_VDD5V_GT_VDDIO) {
+ mx28_boot_valid_5v();
+ return;
+ }
+
+ mx28_handle_5v_conflict();
+}
+
+void mx28_init_batt_bo(void)
+{
+ struct mx28_power_regs *power_regs =
+ (struct mx28_power_regs *)MXS_POWER_BASE;
+
+ /* Brownout at 3V */
+ clrsetbits_le32(&power_regs->hw_power_battmonitor,
+ POWER_BATTMONITOR_BRWNOUT_LVL_MASK,
+ 15 << POWER_BATTMONITOR_BRWNOUT_LVL_OFFSET);
+
+ writel(POWER_CTRL_BATT_BO_IRQ, &power_regs->hw_power_ctrl_clr);
+ writel(POWER_CTRL_ENIRQ_BATT_BO, &power_regs->hw_power_ctrl_clr);
+}
+
+void mx28_switch_vddd_to_dcdc_source(void)
+{
+ struct mx28_power_regs *power_regs =
+ (struct mx28_power_regs *)MXS_POWER_BASE;
+
+ clrsetbits_le32(&power_regs->hw_power_vdddctrl,
+ POWER_VDDDCTRL_LINREG_OFFSET_MASK,
+ POWER_VDDDCTRL_LINREG_OFFSET_1STEPS_BELOW);
+
+ clrbits_le32(&power_regs->hw_power_vdddctrl,
+ POWER_VDDDCTRL_DISABLE_FET | POWER_VDDDCTRL_ENABLE_LINREG |
+ POWER_VDDDCTRL_DISABLE_STEPPING);
+}
+
+int mx28_is_batt_good(void)
+{
+ struct mx28_power_regs *power_regs =
+ (struct mx28_power_regs *)MXS_POWER_BASE;
+ uint32_t volt;
+
+ volt = readl(&power_regs->hw_power_battmonitor);
+ volt &= POWER_BATTMONITOR_BATT_VAL_MASK;
+ volt >>= POWER_BATTMONITOR_BATT_VAL_OFFSET;
+ volt *= 8;
+
+ if ((volt >= 2400) && (volt <= 4300))
+ return 1;
+
+ clrsetbits_le32(&power_regs->hw_power_5vctrl,
+ POWER_5VCTRL_CHARGE_4P2_ILIMIT_MASK,
+ 0x3 << POWER_5VCTRL_CHARGE_4P2_ILIMIT_OFFSET);
+ writel(POWER_5VCTRL_PWD_CHARGE_4P2_MASK,
+ &power_regs->hw_power_5vctrl_clr);
+
+ clrsetbits_le32(&power_regs->hw_power_charge,
+ POWER_CHARGE_STOP_ILIMIT_MASK | POWER_CHARGE_BATTCHRG_I_MASK,
+ POWER_CHARGE_STOP_ILIMIT_10MA | 0x3);
+
+ writel(POWER_CHARGE_PWD_BATTCHRG, &power_regs->hw_power_charge_clr);
+ writel(POWER_5VCTRL_PWD_CHARGE_4P2_MASK,
+ &power_regs->hw_power_5vctrl_clr);
+
+ early_delay(500000);
+
+ volt = readl(&power_regs->hw_power_battmonitor);
+ volt &= POWER_BATTMONITOR_BATT_VAL_MASK;
+ volt >>= POWER_BATTMONITOR_BATT_VAL_OFFSET;
+ volt *= 8;
+
+ if (volt >= 3500)
+ return 0;
+
+ if (volt >= 2400)
+ return 1;
+
+ writel(POWER_CHARGE_STOP_ILIMIT_MASK | POWER_CHARGE_BATTCHRG_I_MASK,
+ &power_regs->hw_power_charge_clr);
+ writel(POWER_CHARGE_PWD_BATTCHRG, &power_regs->hw_power_charge_set);
+
+ return 0;
+}
+
+void mx28_power_configure_power_source(void)
+{
+ mx28_src_power_init();
+
+ mx28_5v_boot();
+ mx28_power_clock2pll();
+
+ mx28_init_batt_bo();
+ mx28_switch_vddd_to_dcdc_source();
+}
+
+void mx28_enable_output_rail_protection(void)
+{
+ struct mx28_power_regs *power_regs =
+ (struct mx28_power_regs *)MXS_POWER_BASE;
+
+ writel(POWER_CTRL_VDDD_BO_IRQ | POWER_CTRL_VDDA_BO_IRQ |
+ POWER_CTRL_VDDIO_BO_IRQ, &power_regs->hw_power_ctrl_clr);
+
+ setbits_le32(&power_regs->hw_power_vdddctrl,
+ POWER_VDDDCTRL_PWDN_BRNOUT);
+
+ setbits_le32(&power_regs->hw_power_vddactrl,
+ POWER_VDDACTRL_PWDN_BRNOUT);
+
+ setbits_le32(&power_regs->hw_power_vddioctrl,
+ POWER_VDDIOCTRL_PWDN_BRNOUT);
+}
+
+int mx28_get_vddio_power_source_off(void)
+{
+ struct mx28_power_regs *power_regs =
+ (struct mx28_power_regs *)MXS_POWER_BASE;
+ uint32_t tmp;
+
+ if (readl(&power_regs->hw_power_sts) & POWER_STS_VDD5V_GT_VDDIO) {
+ tmp = readl(&power_regs->hw_power_vddioctrl);
+ if (tmp & POWER_VDDIOCTRL_DISABLE_FET) {
+ if ((tmp & POWER_VDDIOCTRL_LINREG_OFFSET_MASK) ==
+ POWER_VDDDCTRL_LINREG_OFFSET_0STEPS) {
+ return 1;
+ }
+ }
+
+ if (!(readl(&power_regs->hw_power_5vctrl) &
+ POWER_5VCTRL_ENABLE_DCDC)) {
+ if ((tmp & POWER_VDDIOCTRL_LINREG_OFFSET_MASK) ==
+ POWER_VDDDCTRL_LINREG_OFFSET_0STEPS) {
+ return 1;
+ }
+ }
+ }
+
+ return 0;
+
+}
+
+int mx28_get_vddd_power_source_off(void)
+{
+ struct mx28_power_regs *power_regs =
+ (struct mx28_power_regs *)MXS_POWER_BASE;
+ uint32_t tmp;
+
+ tmp = readl(&power_regs->hw_power_vdddctrl);
+ if (tmp & POWER_VDDDCTRL_DISABLE_FET) {
+ if ((tmp & POWER_VDDDCTRL_LINREG_OFFSET_MASK) ==
+ POWER_VDDDCTRL_LINREG_OFFSET_0STEPS) {
+ return 1;
+ }
+ }
+
+ if (readl(&power_regs->hw_power_sts) & POWER_STS_VDD5V_GT_VDDIO) {
+ if (!(readl(&power_regs->hw_power_5vctrl) &
+ POWER_5VCTRL_ENABLE_DCDC)) {
+ return 1;
+ }
+ }
+
+ if (!(tmp & POWER_VDDDCTRL_ENABLE_LINREG)) {
+ if ((tmp & POWER_VDDDCTRL_LINREG_OFFSET_MASK) ==
+ POWER_VDDDCTRL_LINREG_OFFSET_1STEPS_BELOW) {
+ return 1;
+ }
+ }
+
+ return 0;
+}
+
+void mx28_power_set_vddio(uint32_t new_target, uint32_t new_brownout)
+{
+ struct mx28_power_regs *power_regs =
+ (struct mx28_power_regs *)MXS_POWER_BASE;
+ uint32_t cur_target, diff, bo_int = 0;
+ uint32_t powered_by_linreg = 0;
+
+ new_brownout = new_target - new_brownout;
+
+ cur_target = readl(&power_regs->hw_power_vddioctrl);
+ cur_target &= POWER_VDDIOCTRL_TRG_MASK;
+ cur_target *= 50; /* 50 mV step*/
+ cur_target += 2800; /* 2800 mV lowest */
+
+ powered_by_linreg = mx28_get_vddio_power_source_off();
+ if (new_target > cur_target) {
+
+ if (powered_by_linreg) {
+ bo_int = readl(&power_regs->hw_power_vddioctrl);
+ clrbits_le32(&power_regs->hw_power_vddioctrl,
+ POWER_CTRL_ENIRQ_VDDIO_BO);
+ }
+
+ setbits_le32(&power_regs->hw_power_vddioctrl,
+ POWER_VDDIOCTRL_BO_OFFSET_MASK);
+ do {
+ if (new_target - cur_target > 100)
+ diff = cur_target + 100;
+ else
+ diff = new_target;
+
+ diff -= 2800;
+ diff /= 50;
+
+ clrsetbits_le32(&power_regs->hw_power_vddioctrl,
+ POWER_VDDIOCTRL_TRG_MASK, diff);
+
+ if (powered_by_linreg)
+ early_delay(1500);
+ else {
+ while (!(readl(&power_regs->hw_power_sts) &
+ POWER_STS_DC_OK))
+ ;
+
+ }
+
+ cur_target = readl(&power_regs->hw_power_vddioctrl);
+ cur_target &= POWER_VDDIOCTRL_TRG_MASK;
+ cur_target *= 50; /* 50 mV step*/
+ cur_target += 2800; /* 2800 mV lowest */
+ } while (new_target > cur_target);
+
+ if (powered_by_linreg) {
+ writel(POWER_CTRL_VDDIO_BO_IRQ,
+ &power_regs->hw_power_ctrl_clr);
+ if (bo_int & POWER_CTRL_ENIRQ_VDDIO_BO)
+ setbits_le32(&power_regs->hw_power_vddioctrl,
+ POWER_CTRL_ENIRQ_VDDIO_BO);
+ }
+ } else {
+ do {
+ if (cur_target - new_target > 100)
+ diff = cur_target - 100;
+ else
+ diff = new_target;
+
+ diff -= 2800;
+ diff /= 50;
+
+ clrsetbits_le32(&power_regs->hw_power_vddioctrl,
+ POWER_VDDIOCTRL_TRG_MASK, diff);
+
+ if (powered_by_linreg)
+ early_delay(1500);
+ else {
+ while (!(readl(&power_regs->hw_power_sts) &
+ POWER_STS_DC_OK))
+ ;
+
+ }
+
+ cur_target = readl(&power_regs->hw_power_vddioctrl);
+ cur_target &= POWER_VDDIOCTRL_TRG_MASK;
+ cur_target *= 50; /* 50 mV step*/
+ cur_target += 2800; /* 2800 mV lowest */
+ } while (new_target < cur_target);
+ }
+
+ clrsetbits_le32(&power_regs->hw_power_vddioctrl,
+ POWER_VDDDCTRL_BO_OFFSET_MASK,
+ new_brownout << POWER_VDDDCTRL_BO_OFFSET_OFFSET);
+}
+
+void mx28_power_set_vddd(uint32_t new_target, uint32_t new_brownout)
+{
+ struct mx28_power_regs *power_regs =
+ (struct mx28_power_regs *)MXS_POWER_BASE;
+ uint32_t cur_target, diff, bo_int = 0;
+ uint32_t powered_by_linreg = 0;
+
+ new_brownout = new_target - new_brownout;
+
+ cur_target = readl(&power_regs->hw_power_vdddctrl);
+ cur_target &= POWER_VDDDCTRL_TRG_MASK;
+ cur_target *= 25; /* 25 mV step*/
+ cur_target += 800; /* 800 mV lowest */
+
+ powered_by_linreg = mx28_get_vddd_power_source_off();
+ if (new_target > cur_target) {
+ if (powered_by_linreg) {
+ bo_int = readl(&power_regs->hw_power_vdddctrl);
+ clrbits_le32(&power_regs->hw_power_vdddctrl,
+ POWER_CTRL_ENIRQ_VDDD_BO);
+ }
+
+ setbits_le32(&power_regs->hw_power_vdddctrl,
+ POWER_VDDDCTRL_BO_OFFSET_MASK);
+
+ do {
+ if (new_target - cur_target > 100)
+ diff = cur_target + 100;
+ else
+ diff = new_target;
+
+ diff -= 800;
+ diff /= 25;
+
+ clrsetbits_le32(&power_regs->hw_power_vdddctrl,
+ POWER_VDDDCTRL_TRG_MASK, diff);
+
+ if (powered_by_linreg)
+ early_delay(1500);
+ else {
+ while (!(readl(&power_regs->hw_power_sts) &
+ POWER_STS_DC_OK))
+ ;
+
+ }
+
+ cur_target = readl(&power_regs->hw_power_vdddctrl);
+ cur_target &= POWER_VDDDCTRL_TRG_MASK;
+ cur_target *= 25; /* 25 mV step*/
+ cur_target += 800; /* 800 mV lowest */
+ } while (new_target > cur_target);
+
+ if (powered_by_linreg) {
+ writel(POWER_CTRL_VDDD_BO_IRQ,
+ &power_regs->hw_power_ctrl_clr);
+ if (bo_int & POWER_CTRL_ENIRQ_VDDD_BO)
+ setbits_le32(&power_regs->hw_power_vdddctrl,
+ POWER_CTRL_ENIRQ_VDDD_BO);
+ }
+ } else {
+ do {
+ if (cur_target - new_target > 100)
+ diff = cur_target - 100;
+ else
+ diff = new_target;
+
+ diff -= 800;
+ diff /= 25;
+
+ clrsetbits_le32(&power_regs->hw_power_vdddctrl,
+ POWER_VDDDCTRL_TRG_MASK, diff);
+
+ if (powered_by_linreg)
+ early_delay(1500);
+ else {
+ while (!(readl(&power_regs->hw_power_sts) &
+ POWER_STS_DC_OK))
+ ;
+
+ }
+
+ cur_target = readl(&power_regs->hw_power_vdddctrl);
+ cur_target &= POWER_VDDDCTRL_TRG_MASK;
+ cur_target *= 25; /* 25 mV step*/
+ cur_target += 800; /* 800 mV lowest */
+ } while (new_target < cur_target);
+ }
+
+ clrsetbits_le32(&power_regs->hw_power_vdddctrl,
+ POWER_VDDDCTRL_BO_OFFSET_MASK,
+ new_brownout << POWER_VDDDCTRL_BO_OFFSET_OFFSET);
+}
+
+void mx28_power_init(void)
+{
+ struct mx28_power_regs *power_regs =
+ (struct mx28_power_regs *)MXS_POWER_BASE;
+
+ mx28_power_clock2xtal();
+ mx28_power_clear_auto_restart();
+ mx28_power_set_linreg();
+ mx28_power_setup_5v_detect();
+ mx28_power_configure_power_source();
+ mx28_enable_output_rail_protection();
+
+ mx28_power_set_vddio(3300, 3150);
+
+ mx28_power_set_vddd(1350, 1200);
+
+ writel(POWER_CTRL_VDDD_BO_IRQ | POWER_CTRL_VDDA_BO_IRQ |
+ POWER_CTRL_VDDIO_BO_IRQ | POWER_CTRL_VDD5V_DROOP_IRQ |
+ POWER_CTRL_VBUS_VALID_IRQ | POWER_CTRL_BATT_BO_IRQ |
+ POWER_CTRL_DCDC4P2_BO_IRQ, &power_regs->hw_power_ctrl_clr);
+
+ writel(POWER_5VCTRL_PWDN_5VBRNOUT, &power_regs->hw_power_5vctrl_set);
+
+ early_delay(1000);
+}
+
+#ifdef CONFIG_SPL_MX28_PSWITCH_WAIT
+void mx28_power_wait_pswitch(void)
+{
+ struct mx28_power_regs *power_regs =
+ (struct mx28_power_regs *)MXS_POWER_BASE;
+
+ while (!(readl(&power_regs->hw_power_sts) & POWER_STS_PSWITCH_MASK))
+ ;
+}
+#endif
diff --git a/board/denx/m28evk/start.S b/board/denx/m28evk/start.S
new file mode 100644
index 0000000..94696d6
--- /dev/null
+++ b/board/denx/m28evk/start.S
@@ -0,0 +1,234 @@
+/*
+ * armboot - Startup Code for ARM926EJS CPU-core
+ *
+ * Copyright (c) 2003 Texas Instruments
+ *
+ * ----- Adapted for OMAP1610 OMAP730 from ARM925t code ------
+ *
+ * Copyright (c) 2001 Marius Groger <mag@sysgo.de>
+ * Copyright (c) 2002 Alex Zupke <azu@sysgo.de>
+ * Copyright (c) 2002 Gary Jennejohn <garyj@denx.de>
+ * Copyright (c) 2003 Richard Woodruff <r-woodruff2@ti.com>
+ * Copyright (c) 2003 Kshitij <kshitij@ti.com>
+ * Copyright (c) 2010 Albert Aribaud <albert.u.boot@aribaud.net>
+ *
+ * Change to support call back into iMX28 bootrom
+ * Copyright (c) 2011 Marek Vasut <marek.vasut@gmail.com>
+ * on behalf of DENX Software Engineering GmbH
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <asm-offsets.h>
+#include <config.h>
+#include <common.h>
+#include <version.h>
+
+#if defined(CONFIG_OMAP1610)
+#include <./configs/omap1510.h>
+#elif defined(CONFIG_OMAP730)
+#include <./configs/omap730.h>
+#endif
+
+/*
+ *************************************************************************
+ *
+ * Jump vector table as in table 3.1 in [1]
+ *
+ *************************************************************************
+ */
+
+
+.globl _start
+_start:
+ b reset
+ b undefined_instruction
+ b software_interrupt
+ b prefetch_abort
+ b data_abort
+ b not_used
+ b irq
+ b fiq
+
+/*
+ * Vector table, located at address 0x20.
+ * This table allows the code running AFTER SPL, the U-Boot, to install it's
+ * interrupt handlers here. The problem is that the U-Boot is loaded into RAM,
+ * including it's interrupt vectoring table and the table at 0x0 is still the
+ * SPLs. So if interrupt happens in U-Boot, the SPLs interrupt vectoring table
+ * is still used.
+ */
+_vt_reset:
+ .word _reset
+_vt_undefined_instruction:
+ .word _hang
+_vt_software_interrupt:
+ .word _hang
+_vt_prefetch_abort:
+ .word _hang
+_vt_data_abort:
+ .word _hang
+_vt_not_used:
+ .word _reset
+_vt_irq:
+ .word _hang
+_vt_fiq:
+ .word _hang
+
+reset:
+ ldr pc, _vt_reset
+undefined_instruction:
+ ldr pc, _vt_undefined_instruction
+software_interrupt:
+ ldr pc, _vt_software_interrupt
+prefetch_abort:
+ ldr pc, _vt_prefetch_abort
+data_abort:
+ ldr pc, _vt_data_abort
+not_used:
+ ldr pc, _vt_not_used
+irq:
+ ldr pc, _vt_irq
+fiq:
+ ldr pc, _vt_fiq
+
+ .balignl 16,0xdeadbeef
+
+/*
+ *************************************************************************
+ *
+ * Startup Code (reset vector)
+ *
+ * do important init only if we don't start from memory!
+ * setup Memory and board specific bits prior to relocation.
+ * relocate armboot to ram
+ * setup stack
+ *
+ *************************************************************************
+ */
+
+.globl _TEXT_BASE
+_TEXT_BASE:
+ .word CONFIG_SYS_TEXT_BASE
+
+/*
+ * These are defined in the board-specific linker script.
+ * Subtracting _start from them lets the linker put their
+ * relative position in the executable instead of leaving
+ * them null.
+ */
+.globl _bss_start_ofs
+_bss_start_ofs:
+ .word __bss_start - _start
+
+.globl _bss_end_ofs
+_bss_end_ofs:
+ .word __bss_end__ - _start
+
+.globl _end_ofs
+_end_ofs:
+ .word _end - _start
+
+#ifdef CONFIG_USE_IRQ
+/* IRQ stack memory (calculated at run-time) */
+.globl IRQ_STACK_START
+IRQ_STACK_START:
+ .word 0x0badc0de
+
+/* IRQ stack memory (calculated at run-time) */
+.globl FIQ_STACK_START
+FIQ_STACK_START:
+ .word 0x0badc0de
+#endif
+
+/* IRQ stack memory (calculated at run-time) + 8 bytes */
+.globl IRQ_STACK_START_IN
+IRQ_STACK_START_IN:
+ .word 0x0badc0de
+
+/*
+ * the actual reset code
+ */
+
+_reset:
+ /*
+ * Store all registers on old stack pointer, this will allow us later to
+ * return to the BootROM and let the BootROM load U-Boot into RAM.
+ */
+ push {r0-r12,r14}
+
+ /*
+ * set the cpu to SVC32 mode
+ */
+ mrs r0,cpsr
+ bic r0,r0,#0x1f
+ orr r0,r0,#0xd3
+ msr cpsr,r0
+
+ /*
+ * we do sys-critical inits only at reboot,
+ * not when booting from ram!
+ */
+#ifndef CONFIG_SKIP_LOWLEVEL_INIT
+ bl cpu_init_crit
+#endif
+
+ bl board_init_ll
+
+ pop {r0-r12,r14}
+ bx lr
+
+/*
+ *************************************************************************
+ *
+ * CPU_init_critical registers
+ *
+ * setup important registers
+ * setup memory timing
+ *
+ *************************************************************************
+ */
+#ifndef CONFIG_SKIP_LOWLEVEL_INIT
+cpu_init_crit:
+ /*
+ * flush v4 I/D caches
+ */
+ mov r0, #0
+ mcr p15, 0, r0, c7, c7, 0 /* flush v3/v4 cache */
+ mcr p15, 0, r0, c8, c7, 0 /* flush v4 TLB */
+
+ /*
+ * disable MMU stuff and caches
+ */
+ mrc p15, 0, r0, c1, c0, 0
+ bic r0, r0, #0x00002300 /* clear bits 13, 9:8 (--V- --RS) */
+ bic r0, r0, #0x00000087 /* clear bits 7, 2:0 (B--- -CAM) */
+ orr r0, r0, #0x00000002 /* set bit 2 (A) Align */
+ orr r0, r0, #0x00001000 /* set bit 12 (I) I-Cache */
+ mcr p15, 0, r0, c1, c0, 0
+
+ mov pc, lr /* back to my caller */
+
+ .align 5
+#endif /* CONFIG_SKIP_LOWLEVEL_INIT */
+
+_hang:
+ ldr sp, _TEXT_BASE /* switch to abort stack */
+1:
+ bl 1b /* hang and never return */
diff --git a/board/denx/m28evk/u-boot-spl.lds b/board/denx/m28evk/u-boot-spl.lds
new file mode 100644
index 0000000..e296a92
--- /dev/null
+++ b/board/denx/m28evk/u-boot-spl.lds
@@ -0,0 +1,87 @@
+/*
+ * Copyright (C) 2011 Marek Vasut <marek.vasut@gmail.com>
+ * on behalf of DENX Software Engineering GmbH
+ *
+ * January 2004 - Changed to support H4 device
+ * Copyright (c) 2004-2008 Texas Instruments
+ *
+ * (C) Copyright 2002
+ * Gary Jennejohn, DENX Software Engineering, <garyj@denx.de>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm")
+OUTPUT_ARCH(arm)
+ENTRY(_start)
+SECTIONS
+{
+ . = 0x00000000;
+
+ . = ALIGN(4);
+ .text :
+ {
+ board/denx/m28evk/start.o (.text)
+ *(.text)
+ }
+
+ . = ALIGN(4);
+ .rodata : { *(SORT_BY_ALIGNMENT(SORT_BY_NAME(.rodata*))) }
+
+ . = ALIGN(4);
+ .data : {
+ *(.data)
+ }
+
+ . = ALIGN(4);
+ __u_boot_cmd_start = .;
+ .u_boot_cmd : { *(.u_boot_cmd) }
+ __u_boot_cmd_end = .;
+
+ . = ALIGN(4);
+
+ .rel.dyn : {
+ __rel_dyn_start = .;
+ *(.rel*)
+ __rel_dyn_end = .;
+ }
+
+ .dynsym : {
+ __dynsym_start = .;
+ *(.dynsym)
+ }
+
+ _end = .;
+
+ .bss __rel_dyn_start (OVERLAY) : {
+ __bss_start = .;
+ *(.bss)
+ . = ALIGN(4);
+ __bss_end__ = .;
+ }
+
+ /DISCARD/ : { *(.bss*) }
+ /DISCARD/ : { *(.dynstr*) }
+ /DISCARD/ : { *(.dynsym*) }
+ /DISCARD/ : { *(.dynamic*) }
+ /DISCARD/ : { *(.hash*) }
+ /DISCARD/ : { *(.plt*) }
+ /DISCARD/ : { *(.interp*) }
+ /DISCARD/ : { *(.gnu*) }
+}
diff --git a/board/denx/m28evk/u-boot.bd b/board/denx/m28evk/u-boot.bd
new file mode 100644
index 0000000..3ce7f92
--- /dev/null
+++ b/board/denx/m28evk/u-boot.bd
@@ -0,0 +1,14 @@
+sources {
+ u_boot_spl="spl/u-boot-spl.bin";
+ u_boot="u-boot.bin";
+}
+
+section (0) {
+ load u_boot_spl > 0x0000;
+ load ivt (entry = 0x0014) > 0x8000;
+ hab call 0x8000;
+
+ load u_boot > 0x40000100;
+ load ivt (entry = 0x40000100) > 0x8000;
+ hab call 0x8000;
+}
diff --git a/board/eltec/bab7xx/misc.c b/board/eltec/bab7xx/misc.c
index bc6eb40..d05e226 100644
--- a/board/eltec/bab7xx/misc.c
+++ b/board/eltec/bab7xx/misc.c
@@ -31,7 +31,6 @@
#include "srom.h"
/* imports */
-extern char console_buffer[CONFIG_SYS_CBSIZE];
extern int l2_cache_enable (int l2control);
extern void *nvram_read (void *dest, const short src, size_t count);
extern void nvram_write (short dest, const void *src, size_t count);
diff --git a/board/eltec/elppc/misc.c b/board/eltec/elppc/misc.c
index cbaf10b..d476cd5 100644
--- a/board/eltec/elppc/misc.c
+++ b/board/eltec/elppc/misc.c
@@ -29,7 +29,6 @@
#include "srom.h"
/* imports */
-extern char console_buffer[CONFIG_SYS_CBSIZE];
extern int l2_cache_enable (int l2control);
extern int eepro100_write_eeprom (struct eth_device *dev, int location,
int addr_len, unsigned short data);
diff --git a/board/eltec/mhpc/mhpc.c b/board/eltec/mhpc/mhpc.c
index 7cca6b2..e806b3e 100644
--- a/board/eltec/mhpc/mhpc.c
+++ b/board/eltec/mhpc/mhpc.c
@@ -35,9 +35,6 @@
#include "mpc8xx.h"
#include <video_fb.h>
-/* imports from common/main.c */
-extern char console_buffer[CONFIG_SYS_CBSIZE];
-
extern void eeprom_init (void);
extern int eeprom_read (unsigned dev_addr, unsigned offset,
unsigned char *buffer, unsigned cnt);
diff --git a/board/esd/common/auto_update.c b/board/esd/common/auto_update.c
index 4dfea71..fc60545 100644
--- a/board/esd/common/auto_update.c
+++ b/board/esd/common/auto_update.c
@@ -91,7 +91,6 @@
int au_check_header_valid(int i, long nbytes)
{
image_header_t *hdr;
- unsigned long checksum;
hdr = (image_header_t *)LOAD_ADDR;
#if defined(CONFIG_FIT)
@@ -127,9 +126,6 @@
return -1;
}
- /* recycle checksum */
- checksum = image_get_data_size (hdr);
-
return 0;
}
@@ -397,7 +393,7 @@
{
block_dev_desc_t *stor_dev = NULL;
long sz;
- int i, res, cnt, old_ctrlc, got_ctrlc;
+ int i, res, cnt, old_ctrlc;
char buffer[32];
char str[80];
int n;
@@ -473,8 +469,6 @@
/* let the user break out of the loop */
if (ctrlc() || had_ctrlc ()) {
clear_ctrlc ();
- if (res < 0)
- got_ctrlc = 1;
break;
}
cnt++;
diff --git a/board/esd/cpci750/cpci750.c b/board/esd/cpci750/cpci750.c
index f27d65e..08311c9 100644
--- a/board/esd/cpci750/cpci750.c
+++ b/board/esd/cpci750/cpci750.c
@@ -566,7 +566,7 @@
volatile unsigned int *ptr;
int count = 0;
int count2 = 0;
- int status;
+ int status = 0;
char addr[16];
char str[] = "\\|/-";
char *local_args[2];
@@ -622,7 +622,7 @@
break;
}
- return 0;
+ return status;
}
U_BOOT_CMD(
diff --git a/board/esd/cpci750/sdram_init.c b/board/esd/cpci750/sdram_init.c
index 615e32a..9767cf2 100644
--- a/board/esd/cpci750/sdram_init.c
+++ b/board/esd/cpci750/sdram_init.c
@@ -47,18 +47,6 @@
DECLARE_GLOBAL_DATA_PTR;
-#undef DEBUG
-/* #define DEBUG */
-#ifdef CONFIG_PCI
-#define MAP_PCI
-#endif /* of CONFIG_PCI */
-
-#ifdef DEBUG
-#define DP(x) x
-#else
-#define DP(x)
-#endif
-
int set_dfcdlInit(void); /* setup delay line of Mv64360 */
/* ------------------------------------------------------------------------- */
@@ -250,8 +238,6 @@
/* static int check_dimm(uchar slot, AUX_MEM_DIMM_INFO *info) */
static int check_dimm (uchar slot, AUX_MEM_DIMM_INFO * dimmInfo)
{
- unsigned long spd_checksum;
-
uchar addr = slot == 0 ? DIMM0_I2C_ADDR : DIMM1_I2C_ADDR;
int ret;
unsigned int i, j, density = 1, devicesForErrCheck = 0;
@@ -264,7 +250,7 @@
uchar supp_cal, cal_val;
ulong memclk, tmemclk;
ulong tmp;
- uchar trp_clocks = 0, trcd_clocks, tras_clocks, trrd_clocks;
+ uchar trp_clocks = 0, tras_clocks;
uchar data[128];
memclk = gd->bus_clk;
@@ -275,11 +261,11 @@
ret = 0;
- DP (puts ("before i2c read\n"));
+ debug("before i2c read\n");
ret = i2c_read (addr, 0, 2, data, 128);
- DP (puts ("after i2c read\n"));
+ debug("after i2c read\n");
if ((data[64] != 'e') || (data[65] != 's') || (data[66] != 'd')
|| (data[67] != '-') || (data[68] != 'g') || (data[69] != 'm')
@@ -345,7 +331,7 @@
}
if (ret) {
- DP (printf ("No DIMM in slot %d [err = %x]\n", slot, ret));
+ debug("No DIMM in slot %d [err = %x]\n", slot, ret);
return 0;
} else
dimmInfo->slot = slot; /* start to fill up dimminfo for this "slot" */
@@ -402,8 +388,9 @@
/*------------------------------------------------------------------------------------------------------------------------------*/
/* calculate SPD checksum */
/*------------------------------------------------------------------------------------------------------------------------------*/
- spd_checksum = 0;
#if 0 /* test-only */
+ spd_checksum = 0;
+
for (i = 0; i <= 62; i++) {
spd_checksum += data[i];
}
@@ -424,46 +411,40 @@
dimmInfo->memoryType = (data[i] == 0x7) ? DDR : SDRAM;
#ifdef DEBUG
if (dimmInfo->memoryType == 0)
- DP (printf
- ("Dram_type in slot %d is: SDRAM\n",
- dimmInfo->slot));
+ debug("Dram_type in slot %d is: SDRAM\n",
+ dimmInfo->slot);
if (dimmInfo->memoryType == 1)
- DP (printf
- ("Dram_type in slot %d is: DDRAM\n",
- dimmInfo->slot));
+ debug("Dram_type in slot %d is: DDRAM\n",
+ dimmInfo->slot);
#endif
break;
/*------------------------------------------------------------------------------------------------------------------------------*/
case 3: /* Number Of Row Addresses */
dimmInfo->numOfRowAddresses = data[i];
- DP (printf
- ("Module Number of row addresses: %d\n",
- dimmInfo->numOfRowAddresses));
+ debug("Module Number of row addresses: %d\n",
+ dimmInfo->numOfRowAddresses);
break;
/*------------------------------------------------------------------------------------------------------------------------------*/
case 4: /* Number Of Column Addresses */
dimmInfo->numOfColAddresses = data[i];
- DP (printf
- ("Module Number of col addresses: %d\n",
- dimmInfo->numOfColAddresses));
+ debug("Module Number of col addresses: %d\n",
+ dimmInfo->numOfColAddresses);
break;
/*------------------------------------------------------------------------------------------------------------------------------*/
case 5: /* Number Of Module Banks */
dimmInfo->numOfModuleBanks = data[i];
- DP (printf
- ("Number of Banks on Mod. : %d\n",
- dimmInfo->numOfModuleBanks));
+ debug("Number of Banks on Mod. : %d\n",
+ dimmInfo->numOfModuleBanks);
break;
/*------------------------------------------------------------------------------------------------------------------------------*/
case 6: /* Data Width */
dimmInfo->dataWidth = data[i];
- DP (printf
- ("Module Data Width: %d\n",
- dimmInfo->dataWidth));
+ debug("Module Data Width: %d\n",
+ dimmInfo->dataWidth);
break;
/*------------------------------------------------------------------------------------------------------------------------------*/
@@ -471,33 +452,27 @@
switch (data[i]) {
case 0x0:
dimmInfo->voltageInterface = TTL_5V_TOLERANT;
- DP (printf
- ("Module is TTL_5V_TOLERANT\n"));
+ debug("Module is TTL_5V_TOLERANT\n");
break;
case 0x1:
dimmInfo->voltageInterface = LVTTL;
- DP (printf
- ("Module is LVTTL\n"));
+ debug("Module is LVTTL\n");
break;
case 0x2:
dimmInfo->voltageInterface = HSTL_1_5V;
- DP (printf
- ("Module is TTL_5V_TOLERANT\n"));
+ debug("Module is TTL_5V_TOLERANT\n");
break;
case 0x3:
dimmInfo->voltageInterface = SSTL_3_3V;
- DP (printf
- ("Module is HSTL_1_5V\n"));
+ debug("Module is HSTL_1_5V\n");
break;
case 0x4:
dimmInfo->voltageInterface = SSTL_2_5V;
- DP (printf
- ("Module is SSTL_2_5V\n"));
+ debug("Module is SSTL_2_5V\n");
break;
default:
dimmInfo->voltageInterface = VOLTAGE_UNKNOWN;
- DP (printf
- ("Module is VOLTAGE_UNKNOWN\n"));
+ debug("Module is VOLTAGE_UNKNOWN\n");
break;
}
break;
@@ -516,9 +491,8 @@
leftOfPoint;
dimmInfo->minimumCycleTimeAtMaxCasLatancy_RoP =
rightOfPoint;
- DP (printf
- ("Minimum Cycle Time At Max CasLatancy: %d.%d [ns]\n",
- leftOfPoint, rightOfPoint));
+ debug("Minimum Cycle Time At Max CasLatancy: %d.%d [ns]\n",
+ leftOfPoint, rightOfPoint);
break;
/*------------------------------------------------------------------------------------------------------------------------------*/
@@ -531,9 +505,8 @@
rightOfPoint = time_tmp % div;
dimmInfo->clockToDataOut_LoP = leftOfPoint;
dimmInfo->clockToDataOut_RoP = rightOfPoint;
- DP (printf
- ("Clock To Data Out: %d.%2d [ns]\n",
- leftOfPoint, rightOfPoint));
+ debug("Clock To Data Out: %d.%2d [ns]\n",
+ leftOfPoint, rightOfPoint);
/*dimmInfo->clockToDataOut */
break;
/*------------------------------------------------------------------------------------------------------------------------------*/
@@ -541,42 +514,37 @@
#ifdef CONFIG_MV64360_ECC
case 11: /* Error Check Type */
dimmInfo->errorCheckType = data[i];
- DP (printf
- ("Error Check Type (0=NONE): %d\n",
- dimmInfo->errorCheckType));
+ debug("Error Check Type (0=NONE): %d\n",
+ dimmInfo->errorCheckType);
break;
#endif /* of ifdef CONFIG_MV64360_ECC */
/*------------------------------------------------------------------------------------------------------------------------------*/
case 12: /* Refresh Interval */
dimmInfo->RefreshInterval = data[i];
- DP (printf
- ("RefreshInterval (80= Self refresh Normal, 15.625us) : %x\n",
- dimmInfo->RefreshInterval));
+ debug("RefreshInterval (80= Self refresh Normal, 15.625us) : %x\n",
+ dimmInfo->RefreshInterval);
break;
/*------------------------------------------------------------------------------------------------------------------------------*/
case 13: /* Sdram Width */
dimmInfo->sdramWidth = data[i];
- DP (printf
- ("Sdram Width: %d\n",
- dimmInfo->sdramWidth));
+ debug("Sdram Width: %d\n",
+ dimmInfo->sdramWidth);
break;
/*------------------------------------------------------------------------------------------------------------------------------*/
case 14: /* Error Check Data Width */
dimmInfo->errorCheckDataWidth = data[i];
- DP (printf
- ("Error Check Data Width: %d\n",
- dimmInfo->errorCheckDataWidth));
+ debug("Error Check Data Width: %d\n",
+ dimmInfo->errorCheckDataWidth);
break;
/*------------------------------------------------------------------------------------------------------------------------------*/
case 15: /* Minimum Clock Delay */
dimmInfo->minClkDelay = data[i];
- DP (printf
- ("Minimum Clock Delay: %d\n",
- dimmInfo->minClkDelay));
+ debug("Minimum Clock Delay: %d\n",
+ dimmInfo->minClkDelay);
break;
/*------------------------------------------------------------------------------------------------------------------------------*/
@@ -592,26 +560,24 @@
dimmInfo->burstLengthSupported = data[i];
#ifdef DEBUG
- DP (printf
- ("Burst Length Supported: "));
+ debug("Burst Length Supported: ");
if (dimmInfo->burstLengthSupported & 0x01)
- DP (printf ("1, "));
+ debug("1, ");
if (dimmInfo->burstLengthSupported & 0x02)
- DP (printf ("2, "));
+ debug("2, ");
if (dimmInfo->burstLengthSupported & 0x04)
- DP (printf ("4, "));
+ debug("4, ");
if (dimmInfo->burstLengthSupported & 0x08)
- DP (printf ("8, "));
- DP (printf (" Bit \n"));
+ debug("8, ");
+ debug(" Bit \n");
#endif
break;
/*------------------------------------------------------------------------------------------------------------------------------*/
case 17: /* Number Of Banks On Each Device */
dimmInfo->numOfBanksOnEachDevice = data[i];
- DP (printf
- ("Number Of Banks On Each Chip: %d\n",
- dimmInfo->numOfBanksOnEachDevice));
+ debug("Number Of Banks On Each Chip: %d\n",
+ dimmInfo->numOfBanksOnEachDevice);
break;
/*------------------------------------------------------------------------------------------------------------------------------*/
@@ -631,34 +597,32 @@
********************************************************/
dimmInfo->suportedCasLatencies = data[i];
#ifdef DEBUG
- DP (printf
- ("Suported Cas Latencies: (CL) "));
+ debug("Suported Cas Latencies: (CL) ");
if (dimmInfo->memoryType == 0) { /* SDRAM */
for (k = 0; k <= 7; k++) {
if (dimmInfo->
suportedCasLatencies & (1 << k))
- DP (printf
- ("%d, ",
- k + 1));
+ debug("%d, ",
+ k + 1);
}
} else { /* DDR-RAM */
if (dimmInfo->suportedCasLatencies & 1)
- DP (printf ("1, "));
+ debug("1, ");
if (dimmInfo->suportedCasLatencies & 2)
- DP (printf ("1.5, "));
+ debug("1.5, ");
if (dimmInfo->suportedCasLatencies & 4)
- DP (printf ("2, "));
+ debug("2, ");
if (dimmInfo->suportedCasLatencies & 8)
- DP (printf ("2.5, "));
+ debug("2.5, ");
if (dimmInfo->suportedCasLatencies & 16)
- DP (printf ("3, "));
+ debug("3, ");
if (dimmInfo->suportedCasLatencies & 32)
- DP (printf ("3.5, "));
+ debug("3.5, ");
}
- DP (printf ("\n"));
+ debug("\n");
#endif
/* Calculating MAX CAS latency */
for (j = 7; j > 0; j--) {
@@ -670,8 +634,7 @@
/* CAS latency 1, 1.5, 2, 2.5, 3, 3.5 */
switch (j) {
case 7:
- DP (printf
- ("Max. Cas Latencies (DDR): ERROR !!!\n"));
+ debug("Max. Cas Latencies (DDR): ERROR !!!\n");
dimmInfo->
maxClSupported_DDR
=
@@ -679,8 +642,7 @@
hang ();
break;
case 6:
- DP (printf
- ("Max. Cas Latencies (DDR): ERROR !!!\n"));
+ debug("Max. Cas Latencies (DDR): ERROR !!!\n");
dimmInfo->
maxClSupported_DDR
=
@@ -688,36 +650,31 @@
hang ();
break;
case 5:
- DP (printf
- ("Max. Cas Latencies (DDR): 3.5 clk's\n"));
+ debug("Max. Cas Latencies (DDR): 3.5 clk's\n");
dimmInfo->
maxClSupported_DDR
= DDR_CL_3_5;
break;
case 4:
- DP (printf
- ("Max. Cas Latencies (DDR): 3 clk's \n"));
+ debug("Max. Cas Latencies (DDR): 3 clk's \n");
dimmInfo->
maxClSupported_DDR
= DDR_CL_3;
break;
case 3:
- DP (printf
- ("Max. Cas Latencies (DDR): 2.5 clk's \n"));
+ debug("Max. Cas Latencies (DDR): 2.5 clk's \n");
dimmInfo->
maxClSupported_DDR
= DDR_CL_2_5;
break;
case 2:
- DP (printf
- ("Max. Cas Latencies (DDR): 2 clk's \n"));
+ debug("Max. Cas Latencies (DDR): 2 clk's \n");
dimmInfo->
maxClSupported_DDR
= DDR_CL_2;
break;
case 1:
- DP (printf
- ("Max. Cas Latencies (DDR): 1.5 clk's \n"));
+ debug("Max. Cas Latencies (DDR): 1.5 clk's \n");
dimmInfo->
maxClSupported_DDR
= DDR_CL_1_5;
@@ -736,32 +693,29 @@
dimmInfo->
maxCASlatencySupported_RoP
= 0;
- DP (printf
- ("Max. Cas Latencies (DDR LoP.RoP Notation): %d.%d \n",
+ debug("Max. Cas Latencies (DDR LoP.RoP Notation): %d.%d \n",
dimmInfo->
maxCASlatencySupported_LoP,
dimmInfo->
- maxCASlatencySupported_RoP));
+ maxCASlatencySupported_RoP);
break;
case SDRAM:
/* CAS latency 1, 2, 3, 4, 5, 6, 7 */
dimmInfo->maxClSupported_SD = j; /* Cas Latency DDR-RAM Coded */
- DP (printf
- ("Max. Cas Latencies (SD): %d\n",
+ debug("Max. Cas Latencies (SD): %d\n",
dimmInfo->
- maxClSupported_SD));
+ maxClSupported_SD);
dimmInfo->
maxCASlatencySupported_LoP
= j;
dimmInfo->
maxCASlatencySupported_RoP
= 0;
- DP (printf
- ("Max. Cas Latencies (DDR LoP.RoP Notation): %d.%d \n",
+ debug("Max. Cas Latencies (DDR LoP.RoP Notation): %d.%d \n",
dimmInfo->
maxCASlatencySupported_LoP,
dimmInfo->
- maxCASlatencySupported_RoP));
+ maxCASlatencySupported_RoP);
break;
}
break;
@@ -771,7 +725,7 @@
/*------------------------------------------------------------------------------------------------------------------------------*/
case 21: /* Buffered Address And Control Inputs */
- DP (printf ("\nModul Attributes (SPD Byte 21): \n"));
+ debug("\nModul Attributes (SPD Byte 21): \n");
dimmInfo->bufferedAddrAndControlInputs =
data[i] & BIT0;
dimmInfo->registeredAddrAndControlInputs =
@@ -784,62 +738,47 @@
(data[i] & BIT5) >> 5;
dimmInfo->redundantRowAddressing =
(data[i] & BIT6) >> 6;
-#ifdef DEBUG
+
if (dimmInfo->bufferedAddrAndControlInputs == 1)
- DP (printf
- (" - Buffered Address/Control Input: Yes \n"));
+ debug(" - Buffered Address/Control Input: Yes \n");
else
- DP (printf
- (" - Buffered Address/Control Input: No \n"));
+ debug(" - Buffered Address/Control Input: No \n");
if (dimmInfo->registeredAddrAndControlInputs == 1)
- DP (printf
- (" - Registered Address/Control Input: Yes \n"));
+ debug(" - Registered Address/Control Input: Yes \n");
else
- DP (printf
- (" - Registered Address/Control Input: No \n"));
+ debug(" - Registered Address/Control Input: No \n");
if (dimmInfo->onCardPLL == 1)
- DP (printf
- (" - On-Card PLL (clock): Yes \n"));
+ debug(" - On-Card PLL (clock): Yes \n");
else
- DP (printf
- (" - On-Card PLL (clock): No \n"));
+ debug(" - On-Card PLL (clock): No \n");
if (dimmInfo->bufferedDQMBinputs == 1)
- DP (printf
- (" - Bufferd DQMB Inputs: Yes \n"));
+ debug(" - Bufferd DQMB Inputs: Yes \n");
else
- DP (printf
- (" - Bufferd DQMB Inputs: No \n"));
+ debug(" - Bufferd DQMB Inputs: No \n");
if (dimmInfo->registeredDQMBinputs == 1)
- DP (printf
- (" - Registered DQMB Inputs: Yes \n"));
+ debug(" - Registered DQMB Inputs: Yes \n");
else
- DP (printf
- (" - Registered DQMB Inputs: No \n"));
+ debug(" - Registered DQMB Inputs: No \n");
if (dimmInfo->differentialClockInput == 1)
- DP (printf
- (" - Differential Clock Input: Yes \n"));
+ debug(" - Differential Clock Input: Yes \n");
else
- DP (printf
- (" - Differential Clock Input: No \n"));
+ debug(" - Differential Clock Input: No \n");
if (dimmInfo->redundantRowAddressing == 1)
- DP (printf
- (" - redundant Row Addressing: Yes \n"));
+ debug(" - redundant Row Addressing: Yes \n");
else
- DP (printf
- (" - redundant Row Addressing: No \n"));
+ debug(" - redundant Row Addressing: No \n");
-#endif
break;
/*------------------------------------------------------------------------------------------------------------------------------*/
case 22: /* Suported AutoPreCharge */
- DP (printf ("\nModul Attributes (SPD Byte 22): \n"));
+ debug("\nModul Attributes (SPD Byte 22): \n");
dimmInfo->suportedEarlyRasPreCharge = data[i] & BIT0;
dimmInfo->suportedAutoPreCharge =
(data[i] & BIT1) >> 1;
@@ -851,50 +790,37 @@
(data[i] & BIT4) >> 4;
dimmInfo->suported5PercentUpperVCC =
(data[i] & BIT5) >> 5;
-#ifdef DEBUG
+
if (dimmInfo->suportedEarlyRasPreCharge == 1)
- DP (printf
- (" - Early Ras Precharge: Yes \n"));
+ debug(" - Early Ras Precharge: Yes \n");
else
- DP (printf
- (" - Early Ras Precharge: No \n"));
+ debug(" - Early Ras Precharge: No \n");
if (dimmInfo->suportedAutoPreCharge == 1)
- DP (printf
- (" - AutoPreCharge: Yes \n"));
+ debug(" - AutoPreCharge: Yes \n");
else
- DP (printf
- (" - AutoPreCharge: No \n"));
+ debug(" - AutoPreCharge: No \n");
if (dimmInfo->suportedPreChargeAll == 1)
- DP (printf
- (" - Precharge All: Yes \n"));
+ debug(" - Precharge All: Yes \n");
else
- DP (printf
- (" - Precharge All: No \n"));
+ debug(" - Precharge All: No \n");
if (dimmInfo->suportedWrite1ReadBurst == 1)
- DP (printf
- (" - Write 1/ReadBurst: Yes \n"));
+ debug(" - Write 1/ReadBurst: Yes \n");
else
- DP (printf
- (" - Write 1/ReadBurst: No \n"));
+ debug(" - Write 1/ReadBurst: No \n");
if (dimmInfo->suported5PercentLowVCC == 1)
- DP (printf
- (" - lower VCC tolerance: 5 Percent \n"));
+ debug(" - lower VCC tolerance: 5 Percent \n");
else
- DP (printf
- (" - lower VCC tolerance: 10 Percent \n"));
+ debug(" - lower VCC tolerance: 10 Percent \n");
if (dimmInfo->suported5PercentUpperVCC == 1)
- DP (printf
- (" - upper VCC tolerance: 5 Percent \n"));
+ debug(" - upper VCC tolerance: 5 Percent \n");
else
- DP (printf
- (" - upper VCC tolerance: 10 Percent \n"));
+ debug(" - upper VCC tolerance: 10 Percent \n");
-#endif
break;
/*------------------------------------------------------------------------------------------------------------------------------*/
@@ -911,9 +837,8 @@
leftOfPoint;
dimmInfo->minimumCycleTimeAtMaxCasLatancyMinus1_RoP =
rightOfPoint;
- DP (printf
- ("Minimum Cycle Time At 2nd highest CasLatancy (0 = Not supported): %d.%d [ns]\n",
- leftOfPoint, rightOfPoint));
+ debug("Minimum Cycle Time At 2nd highest CasLatancy (0 = Not supported): %d.%d [ns]\n",
+ leftOfPoint, rightOfPoint);
/*dimmInfo->minimumCycleTimeAtMaxCasLatancy */
break;
/*------------------------------------------------------------------------------------------------------------------------------*/
@@ -927,9 +852,8 @@
rightOfPoint = time_tmp % div;
dimmInfo->clockToDataOutMinus1_LoP = leftOfPoint;
dimmInfo->clockToDataOutMinus1_RoP = rightOfPoint;
- DP (printf
- ("Clock To Data Out (2nd CL value): %d.%2d [ns]\n",
- leftOfPoint, rightOfPoint));
+ debug("Clock To Data Out (2nd CL value): %d.%2d [ns]\n",
+ leftOfPoint, rightOfPoint);
break;
/*------------------------------------------------------------------------------------------------------------------------------*/
@@ -946,9 +870,8 @@
leftOfPoint;
dimmInfo->minimumCycleTimeAtMaxCasLatancyMinus2_RoP =
rightOfPoint;
- DP (printf
- ("Minimum Cycle Time At 3rd highest CasLatancy (0 = Not supported): %d.%d [ns]\n",
- leftOfPoint, rightOfPoint));
+ debug("Minimum Cycle Time At 3rd highest CasLatancy (0 = Not supported): %d.%d [ns]\n",
+ leftOfPoint, rightOfPoint);
/*dimmInfo->minimumCycleTimeAtMaxCasLatancy */
break;
/*------------------------------------------------------------------------------------------------------------------------------*/
@@ -962,9 +885,8 @@
rightOfPoint = time_tmp % div;
dimmInfo->clockToDataOutMinus2_LoP = leftOfPoint;
dimmInfo->clockToDataOutMinus2_RoP = rightOfPoint;
- DP (printf
- ("Clock To Data Out (3rd CL value): %d.%2d [ns]\n",
- leftOfPoint, rightOfPoint));
+ debug("Clock To Data Out (3rd CL value): %d.%2d [ns]\n",
+ leftOfPoint, rightOfPoint);
break;
/*------------------------------------------------------------------------------------------------------------------------------*/
@@ -981,12 +903,10 @@
trp_clocks =
(dimmInfo->minRowPrechargeTime +
(tmemclk - 1)) / tmemclk;
- DP (printf
- ("*** 1 clock cycle = %ld 10ps intervalls = %ld.%ld ns****\n",
- tmemclk, tmemclk / 100, tmemclk % 100));
- DP (printf
- ("Minimum Row Precharge Time [ns]: %d.%2d = in Clk cycles %d\n",
- leftOfPoint, rightOfPoint, trp_clocks));
+ debug("*** 1 clock cycle = %ld 10ps intervalls = %ld.%ld ns****\n",
+ tmemclk, tmemclk / 100, tmemclk % 100);
+ debug("Minimum Row Precharge Time [ns]: %d.%2d = in Clk cycles %d\n",
+ leftOfPoint, rightOfPoint, trp_clocks);
break;
/*------------------------------------------------------------------------------------------------------------------------------*/
@@ -1000,12 +920,8 @@
rightOfPoint = (data[i] & maskRightOfPoint) * 25;
dimmInfo->minRowActiveRowActiveDelay = ((leftOfPoint * 100) + rightOfPoint); /* measured in 100ns Intervals */
- trrd_clocks =
- (dimmInfo->minRowActiveRowActiveDelay +
- (tmemclk - 1)) / tmemclk;
- DP (printf
- ("Minimum Row Active -To- Row Active Delay [ns]: %d.%2d = in Clk cycles %d\n",
- leftOfPoint, rightOfPoint, trp_clocks));
+ debug("Minimum Row Active -To- Row Active Delay [ns]: %d.%2d = in Clk cycles %d\n",
+ leftOfPoint, rightOfPoint, trp_clocks);
break;
/*------------------------------------------------------------------------------------------------------------------------------*/
@@ -1019,12 +935,8 @@
rightOfPoint = (data[i] & maskRightOfPoint) * 25;
dimmInfo->minRowActiveRowActiveDelay = ((leftOfPoint * 100) + rightOfPoint); /* measured in 100ns Intervals */
- trcd_clocks =
- (dimmInfo->minRowActiveRowActiveDelay +
- (tmemclk - 1)) / tmemclk;
- DP (printf
- ("Minimum Ras-To-Cas Delay [ns]: %d.%2d = in Clk cycles %d\n",
- leftOfPoint, rightOfPoint, trp_clocks));
+ debug("Minimum Ras-To-Cas Delay [ns]: %d.%2d = in Clk cycles %d\n",
+ leftOfPoint, rightOfPoint, trp_clocks);
break;
/*------------------------------------------------------------------------------------------------------------------------------*/
@@ -1033,41 +945,38 @@
tras_clocks =
(NSto10PS (data[i]) +
(tmemclk - 1)) / tmemclk;
- DP (printf
- ("Minimum Ras Pulse Width [ns]: %d = in Clk cycles %d\n",
- dimmInfo->minRasPulseWidth, tras_clocks));
+ debug("Minimum Ras Pulse Width [ns]: %d = in Clk cycles %d\n",
+ dimmInfo->minRasPulseWidth, tras_clocks);
break;
/*------------------------------------------------------------------------------------------------------------------------------*/
case 31: /* Module Bank Density */
dimmInfo->moduleBankDensity = data[i];
- DP (printf
- ("Module Bank Density: %d\n",
- dimmInfo->moduleBankDensity));
+ debug("Module Bank Density: %d\n",
+ dimmInfo->moduleBankDensity);
#ifdef DEBUG
- DP (printf
- ("*** Offered Densities (more than 1 = Multisize-Module): "));
+ debug("*** Offered Densities (more than 1 = Multisize-Module): ");
{
if (dimmInfo->moduleBankDensity & 1)
- DP (printf ("4MB, "));
+ debug("4MB, ");
if (dimmInfo->moduleBankDensity & 2)
- DP (printf ("8MB, "));
+ debug("8MB, ");
if (dimmInfo->moduleBankDensity & 4)
- DP (printf ("16MB, "));
+ debug("16MB, ");
if (dimmInfo->moduleBankDensity & 8)
- DP (printf ("32MB, "));
+ debug("32MB, ");
if (dimmInfo->moduleBankDensity & 16)
- DP (printf ("64MB, "));
+ debug("64MB, ");
if (dimmInfo->moduleBankDensity & 32)
- DP (printf ("128MB, "));
+ debug("128MB, ");
if ((dimmInfo->moduleBankDensity & 64)
|| (dimmInfo->moduleBankDensity & 128)) {
- DP (printf ("ERROR, "));
+ debug("ERROR, ");
hang ();
}
}
- DP (printf ("\n"));
+ debug("\n");
#endif
break;
/*------------------------------------------------------------------------------------------------------------------------------*/
@@ -1093,9 +1002,8 @@
}
dimmInfo->addrAndCommandSetupTime =
(leftOfPoint * 100 + rightOfPoint) * sign;
- DP (printf
- ("Address And Command Setup Time [ns]: %d.%d\n",
- sign * leftOfPoint, rightOfPoint));
+ debug("Address And Command Setup Time [ns]: %d.%d\n",
+ sign * leftOfPoint, rightOfPoint);
break;
/*------------------------------------------------------------------------------------------------------------------------------*/
@@ -1120,9 +1028,8 @@
}
dimmInfo->addrAndCommandHoldTime =
(leftOfPoint * 100 + rightOfPoint) * sign;
- DP (printf
- ("Address And Command Hold Time [ns]: %d.%d\n",
- sign * leftOfPoint, rightOfPoint));
+ debug("Address And Command Hold Time [ns]: %d.%d\n",
+ sign * leftOfPoint, rightOfPoint);
break;
/*------------------------------------------------------------------------------------------------------------------------------*/
@@ -1147,9 +1054,8 @@
}
dimmInfo->dataInputSetupTime =
(leftOfPoint * 100 + rightOfPoint) * sign;
- DP (printf
- ("Data Input Setup Time [ns]: %d.%d\n",
- sign * leftOfPoint, rightOfPoint));
+ debug("Data Input Setup Time [ns]: %d.%d\n",
+ sign * leftOfPoint, rightOfPoint);
break;
/*------------------------------------------------------------------------------------------------------------------------------*/
@@ -1174,9 +1080,8 @@
}
dimmInfo->dataInputHoldTime =
(leftOfPoint * 100 + rightOfPoint) * sign;
- DP (printf
- ("Data Input Hold Time [ns]: %d.%d\n\n",
- sign * leftOfPoint, rightOfPoint));
+ debug("Data Input Hold Time [ns]: %d.%d\n\n",
+ sign * leftOfPoint, rightOfPoint);
break;
/*------------------------------------------------------------------------------------------------------------------------------*/
}
@@ -1213,7 +1118,7 @@
tmp *= dimmInfo->sdramWidth;
tmp = tmp >> 24; /* div by 0x4000000 (64M) */
dimmInfo->drb_size = (uchar) tmp;
- DP (printf ("Module DRB size (n*64Mbit): %d\n", dimmInfo->drb_size));
+ debug("Module DRB size (n*64Mbit): %d\n", dimmInfo->drb_size);
/* try a CAS latency of 3 first... */
@@ -1236,11 +1141,11 @@
cal_val = 4;
}
- DP (printf ("cal_val = %d\n", cal_val * 5));
+ debug("cal_val = %d\n", cal_val * 5);
/* bummer, did't work... */
if (cal_val == 0) {
- DP (printf ("Couldn't find a good CAS latency\n"));
+ debug("Couldn't find a good CAS latency\n");
hang ();
return 0;
}
@@ -1267,81 +1172,74 @@
/* Program the GT with the discovered data */
if (info->registeredAddrAndControlInputs == true)
- DP (printf
- ("Module is registered, but we do not support registered Modules !!!\n"));
+ debug("Module is registered, but we do not support registered Modules !!!\n");
/* delay line */
set_dfcdlInit (); /* may be its not needed */
- DP (printf ("Delay line set done\n"));
+ debug("Delay line set done\n");
/* set SDRAM mode NOP */ /* To_do check it */
GT_REG_WRITE (SDRAM_OPERATION, 0x5);
while (GTREGREAD (SDRAM_OPERATION) != 0) {
- DP (printf
- ("\n*** SDRAM_OPERATION 1418: Module still busy ... please wait... ***\n"));
+ debug("\n*** SDRAM_OPERATION 1418: Module still busy ... please wait... ***\n");
}
#ifdef CONFIG_MV64360_ECC
if ((info->errorCheckType == 0x2) && (CPCI750_ECC_TEST)) {
/* DRAM has ECC, so turn it on */
sdram_config_reg |= BIT18;
- DP(printf("Enabling ECC\n"));
+ debug("Enabling ECC\n");
}
#endif /* of ifdef CONFIG_MV64360_ECC */
/* SDRAM configuration */
GT_REG_WRITE(SDRAM_CONFIG, sdram_config_reg);
- DP (printf ("sdram_conf 0x1400: %08x\n", GTREGREAD (SDRAM_CONFIG)));
+ debug("sdram_conf 0x1400: %08x\n", GTREGREAD (SDRAM_CONFIG));
/* SDRAM open pages controll keep open as much as I can */
GT_REG_WRITE (SDRAM_OPEN_PAGES_CONTROL, 0x0);
- DP (printf
- ("sdram_open_pages_controll 0x1414: %08x\n",
- GTREGREAD (SDRAM_OPEN_PAGES_CONTROL)));
+ debug("sdram_open_pages_controll 0x1414: %08x\n",
+ GTREGREAD (SDRAM_OPEN_PAGES_CONTROL));
/* SDRAM D_UNIT_CONTROL_LOW 0x1404 */
tmp = (GTREGREAD (D_UNIT_CONTROL_LOW) & 0x01); /* Clock Domain Sync from power on reset */
if (tmp == 0)
- DP (printf ("Core Signals are sync (by HW-Setting)!!!\n"));
+ debug("Core Signals are sync (by HW-Setting)!!!\n");
else
- DP (printf
- ("Core Signals syncs. are bypassed (by HW-Setting)!!!\n"));
+ debug("Core Signals syncs. are bypassed (by HW-Setting)!!!\n");
/* SDRAM set CAS Lentency according to SPD information */
switch (info->memoryType) {
case SDRAM:
- DP (printf ("### SD-RAM not supported yet !!!\n"));
+ debug("### SD-RAM not supported yet !!!\n");
hang ();
/* ToDo fill SD-RAM if needed !!!!! */
break;
case DDR:
- DP (printf ("### SET-CL for DDR-RAM\n"));
+ debug("### SET-CL for DDR-RAM\n");
switch (info->maxClSupported_DDR) {
case DDR_CL_3:
tmp_dunit_control_low = 0x3c000000; /* Read-Data sampled on falling edge of Clk */
tmp_sdram_mode = 0x32; /* CL=3 Burstlength = 4 */
- DP (printf
- ("Max. CL is 3 CLKs 0x141c= %08lx, 0x1404 = %08lx\n",
- tmp_sdram_mode, tmp_dunit_control_low));
+ debug("Max. CL is 3 CLKs 0x141c= %08lx, 0x1404 = %08lx\n",
+ tmp_sdram_mode, tmp_dunit_control_low);
break;
case DDR_CL_2_5:
if (tmp == 1) { /* clocks sync */
tmp_dunit_control_low = 0x24000000; /* Read-Data sampled on falling edge of Clk */
tmp_sdram_mode = 0x62; /* CL=2,5 Burstlength = 4 */
- DP (printf
- ("Max. CL is 2,5s CLKs 0x141c= %08lx, 0x1404 = %08lx\n",
- tmp_sdram_mode, tmp_dunit_control_low));
+ debug("Max. CL is 2,5s CLKs 0x141c= %08lx, 0x1404 = %08lx\n",
+ tmp_sdram_mode, tmp_dunit_control_low);
} else { /* clk sync. bypassed */
tmp_dunit_control_low = 0x03000000; /* Read-Data sampled on rising edge of Clk */
tmp_sdram_mode = 0x62; /* CL=2,5 Burstlength = 4 */
- DP (printf
- ("Max. CL is 2,5 CLKs 0x141c= %08lx, 0x1404 = %08lx\n",
- tmp_sdram_mode, tmp_dunit_control_low));
+ debug("Max. CL is 2,5 CLKs 0x141c= %08lx, 0x1404 = %08lx\n",
+ tmp_sdram_mode, tmp_dunit_control_low);
}
break;
@@ -1349,16 +1247,14 @@
if (tmp == 1) { /* Sync */
tmp_dunit_control_low = 0x03000000; /* Read-Data sampled on rising edge of Clk */
tmp_sdram_mode = 0x22; /* CL=2 Burstlength = 4 */
- DP (printf
- ("Max. CL is 2s CLKs 0x141c= %08lx, 0x1404 = %08lx\n",
- tmp_sdram_mode, tmp_dunit_control_low));
+ debug("Max. CL is 2s CLKs 0x141c= %08lx, 0x1404 = %08lx\n",
+ tmp_sdram_mode, tmp_dunit_control_low);
} else { /* Not sync. */
tmp_dunit_control_low = 0x3b000000; /* Read-Data sampled on rising edge of Clk */
tmp_sdram_mode = 0x22; /* CL=2 Burstlength = 4 */
- DP (printf
- ("Max. CL is 2 CLKs 0x141c= %08lx, 0x1404 = %08lx\n",
- tmp_sdram_mode, tmp_dunit_control_low));
+ debug("Max. CL is 2 CLKs 0x141c= %08lx, 0x1404 = %08lx\n",
+ tmp_sdram_mode, tmp_dunit_control_low);
}
break;
@@ -1366,16 +1262,14 @@
if (tmp == 1) { /* Sync */
tmp_dunit_control_low = 0x23000000; /* Read-Data sampled on falling edge of Clk */
tmp_sdram_mode = 0x52; /* CL=1,5 Burstlength = 4 */
- DP (printf
- ("Max. CL is 1,5s CLKs 0x141c= %08lx, 0x1404 = %08lx\n",
- tmp_sdram_mode, tmp_dunit_control_low));
+ debug("Max. CL is 1,5s CLKs 0x141c= %08lx, 0x1404 = %08lx\n",
+ tmp_sdram_mode, tmp_dunit_control_low);
} else { /* not sync */
tmp_dunit_control_low = 0x1a000000; /* Read-Data sampled on rising edge of Clk */
tmp_sdram_mode = 0x52; /* CL=1,5 Burstlength = 4 */
- DP (printf
- ("Max. CL is 1,5 CLKs 0x141c= %08lx, 0x1404 = %08lx\n",
- tmp_sdram_mode, tmp_dunit_control_low));
+ debug("Max. CL is 1,5 CLKs 0x141c= %08lx, 0x1404 = %08lx\n",
+ tmp_sdram_mode, tmp_dunit_control_low);
}
break;
@@ -1393,8 +1287,7 @@
/* set SDRAM mode SetCommand 0x1418 */
GT_REG_WRITE (SDRAM_OPERATION, 0x3);
while (GTREGREAD (SDRAM_OPERATION) != 0) {
- DP (printf
- ("\n*** SDRAM_OPERATION 1418 after SDRAM_MODE: Module still busy ... please wait... ***\n"));
+ debug("\n*** SDRAM_OPERATION 1418 after SDRAM_MODE: Module still busy ... please wait... ***\n");
}
@@ -1415,8 +1308,7 @@
/* set SDRAM mode SetCommand 0x1418 */
GT_REG_WRITE (SDRAM_OPERATION, 0x3);
while (GTREGREAD (SDRAM_OPERATION) != 0) {
- DP (printf
- ("\n*** SDRAM_OPERATION 1418 after D_UNIT_CONTROL_LOW: Module still busy ... please wait... ***\n"));
+ debug("\n*** SDRAM_OPERATION 1418 after D_UNIT_CONTROL_LOW: Module still busy ... please wait... ***\n");
}
/*------------------------------------------------------------------------------ */
@@ -1428,41 +1320,39 @@
tmp = 0x02;
- DP (printf ("drb_size (n*64Mbit): %d\n", info->drb_size));
+ debug("drb_size (n*64Mbit): %d\n", info->drb_size);
switch (info->drb_size) {
case 1: /* 64 Mbit */
case 2: /* 128 Mbit */
- DP (printf ("RAM-Device_size 64Mbit or 128Mbit)\n"));
+ debug("RAM-Device_size 64Mbit or 128Mbit)\n");
tmp |= (0x00 << 4);
break;
case 4: /* 256 Mbit */
case 8: /* 512 Mbit */
- DP (printf ("RAM-Device_size 256Mbit or 512Mbit)\n"));
+ debug("RAM-Device_size 256Mbit or 512Mbit)\n");
tmp |= (0x01 << 4);
break;
case 16: /* 1 Gbit */
case 32: /* 2 Gbit */
- DP (printf ("RAM-Device_size 1Gbit or 2Gbit)\n"));
+ debug("RAM-Device_size 1Gbit or 2Gbit)\n");
tmp |= (0x02 << 4);
break;
default:
printf ("Error in dram size calculation\n");
- DP (printf ("Assume: RAM-Device_size 1Gbit or 2Gbit)\n"));
+ debug("Assume: RAM-Device_size 1Gbit or 2Gbit)\n");
tmp |= (0x02 << 4);
return 1;
}
/* SDRAM bank parameters */
/* the param registers for slot 1 (banks 2+3) are offset by 0x8 */
- DP (printf
- ("setting up slot %d config with: %08lx \n", info->slot, tmp));
+ debug("setting up slot %d config with: %08lx \n", info->slot, tmp);
GT_REG_WRITE (SDRAM_ADDR_CONTROL, tmp);
/* ------------------------------------------------------------------------------ */
- DP (printf
- ("setting up sdram_timing_control_low with: %08x \n",
- 0x11511220));
+ debug("setting up sdram_timing_control_low with: %08x \n",
+ 0x11511220);
GT_REG_WRITE (SDRAM_TIMING_CONTROL_LOW, 0x11511220);
@@ -1474,38 +1364,33 @@
if (info->registeredAddrAndControlInputs
|| info->registeredDQMBinputs) {
tmp |= (1 << 17);
- DP (printf
- ("SPD says: registered Addr. and Cont.: %d; registered DQMBinputs: %d\n",
+ debug("SPD says: registered Addr. and Cont.: %d; registered DQMBinputs: %d\n",
info->registeredAddrAndControlInputs,
- info->registeredDQMBinputs));
+ info->registeredDQMBinputs);
}
/* Use buffer 1 to return read data to the CPU
* Page 426 MV64360 */
tmp |= (1 << 26);
- DP (printf
- ("Before Buffer assignment - sdram_conf: %08x\n",
- GTREGREAD (SDRAM_CONFIG)));
- DP (printf
- ("After Buffer assignment - sdram_conf: %08x\n",
- GTREGREAD (SDRAM_CONFIG)));
+ debug("Before Buffer assignment - sdram_conf: %08x\n",
+ GTREGREAD (SDRAM_CONFIG));
+ debug("After Buffer assignment - sdram_conf: %08x\n",
+ GTREGREAD (SDRAM_CONFIG));
/* SDRAM timing To_do: */
tmp = GTREGREAD (SDRAM_TIMING_CONTROL_HIGH);
- DP (printf ("# sdram_timing_control_high is : %08lx \n", tmp));
+ debug("# sdram_timing_control_high is : %08lx \n", tmp);
/* SDRAM address decode register */
/* program this with the default value */
tmp = GTREGREAD (SDRAM_ADDR_CONTROL);
- DP (printf
- ("SDRAM address control (before: decode): %08x ",
- GTREGREAD (SDRAM_ADDR_CONTROL)));
+ debug("SDRAM address control (before: decode): %08x ",
+ GTREGREAD (SDRAM_ADDR_CONTROL));
GT_REG_WRITE (SDRAM_ADDR_CONTROL, (tmp | 0x2));
- DP (printf
- ("SDRAM address control (after: decode): %08x\n",
- GTREGREAD (SDRAM_ADDR_CONTROL)));
+ debug("SDRAM address control (after: decode): %08x\n",
+ GTREGREAD (SDRAM_ADDR_CONTROL));
/* set the SDRAM configuration for each bank */
@@ -1514,8 +1399,7 @@
int l, l1;
i = info->slot;
- DP (printf
- ("\n*** Running a MRS cycle for bank %d ***\n", i));
+ debug("\n*** Running a MRS cycle for bank %d ***\n", i);
/* map the bank */
memory_map_bank (i, 0, GB / 4);
@@ -1525,15 +1409,13 @@
GT_REG_WRITE (EXTENDED_DRAM_MODE, 0x0);
GT_REG_WRITE (SDRAM_OPERATION, 0x4);
while (GTREGREAD (SDRAM_OPERATION) != 0) {
- DP (printf
- ("\n*** SDRAM_OPERATION 1418 after SDRAM_MODE: Module still busy ... please wait... ***\n"));
+ debug("\n*** SDRAM_OPERATION 1418 after SDRAM_MODE: Module still busy ... please wait... ***\n");
}
GT_REG_WRITE (SDRAM_MODE, tmp | 0x80);
GT_REG_WRITE (SDRAM_OPERATION, 0x3);
while (GTREGREAD (SDRAM_OPERATION) != 0) {
- DP (printf
- ("\n*** SDRAM_OPERATION 1418 after SDRAM_MODE: Module still busy ... please wait... ***\n"));
+ debug("\n*** SDRAM_OPERATION 1418 after SDRAM_MODE: Module still busy ... please wait... ***\n");
}
l1 = 0;
for (l=0;l<200;l++)
@@ -1542,15 +1424,13 @@
GT_REG_WRITE (SDRAM_MODE, tmp);
GT_REG_WRITE (SDRAM_OPERATION, 0x3);
while (GTREGREAD (SDRAM_OPERATION) != 0) {
- DP (printf
- ("\n*** SDRAM_OPERATION 1418 after SDRAM_MODE: Module still busy ... please wait... ***\n"));
+ debug("\n*** SDRAM_OPERATION 1418 after SDRAM_MODE: Module still busy ... please wait... ***\n");
}
/* switch back to normal operation mode */
GT_REG_WRITE (SDRAM_OPERATION, 0x5);
while (GTREGREAD (SDRAM_OPERATION) != 0) {
- DP (printf
- ("\n*** SDRAM_OPERATION 1418 after SDRAM_MODE: Module still busy ... please wait... ***\n"));
+ debug("\n*** SDRAM_OPERATION 1418 after SDRAM_MODE: Module still busy ... please wait... ***\n");
}
#endif /* test only */
@@ -1597,7 +1477,7 @@
*b=save2;
if (val != cnt) {
- DP(printf("Found %08x at Address %08x (failure)\n", (unsigned int)val, (unsigned int) addr));
+ debug("Found %08x at Address %08x (failure)\n", (unsigned int)val, (unsigned int) addr);
/* fix boundary condition.. STARTVAL means zero */
if(cnt==STARTVAL/sizeof(long)) cnt=0;
return (cnt * sizeof(long));
@@ -1690,7 +1570,6 @@
phys_size_t
initdram(int board_type)
{
- int s0 = 0, s1 = 0;
int checkbank[4] = { [0 ... 3] = 0 };
ulong realsize, total, check;
AUX_MEM_DIMM_INFO dimmInfo1;
@@ -1709,10 +1588,10 @@
printf("Skipping SD- DDRRAM setup due to NHR bit being set\n");
} else {
/* DIMM0 */
- s0 = check_dimm(0, &dimmInfo1);
+ (void)check_dimm(0, &dimmInfo1);
/* DIMM1 */
- s1 = check_dimm(1, &dimmInfo2);
+ (void)check_dimm(1, &dimmInfo2);
memory_map_bank(0, 0, 0);
memory_map_bank(1, 0, 0);
diff --git a/board/esd/dasa_sim/cmd_dasa_sim.c b/board/esd/dasa_sim/cmd_dasa_sim.c
index 4946538..0014808 100644
--- a/board/esd/dasa_sim/cmd_dasa_sim.c
+++ b/board/esd/dasa_sim/cmd_dasa_sim.c
@@ -132,8 +132,6 @@
static void updatePci9054 (void)
{
- int val;
-
/*
* Set EEPROM write-protect register to 0
*/
@@ -141,44 +139,44 @@
in_be32 ((void *)(pci9054_iobase + 0x0c)) & 0xffff00ff);
/* Long Serial EEPROM Load Registers... */
- val = PciEepromWriteLongVPD (0x00, 0x905410b5);
- val = PciEepromWriteLongVPD (0x04, 0x09800001); /* other input controller */
- val = PciEepromWriteLongVPD (0x08, 0x28140100);
+ PciEepromWriteLongVPD (0x00, 0x905410b5);
+ PciEepromWriteLongVPD (0x04, 0x09800001); /* other input controller */
+ PciEepromWriteLongVPD (0x08, 0x28140100);
- val = PciEepromWriteLongVPD (0x0c, 0x00000000); /* MBOX0... */
- val = PciEepromWriteLongVPD (0x10, 0x00000000);
+ PciEepromWriteLongVPD (0x0c, 0x00000000); /* MBOX0... */
+ PciEepromWriteLongVPD (0x10, 0x00000000);
/* las0: fpga access (0x0000.0000 ... 0x0003.ffff) */
- val = PciEepromWriteLongVPD (0x14, 0xfffc0000); /* LAS0RR... */
- val = PciEepromWriteLongVPD (0x18, 0x00000001); /* LAS0BA */
+ PciEepromWriteLongVPD (0x14, 0xfffc0000); /* LAS0RR... */
+ PciEepromWriteLongVPD (0x18, 0x00000001); /* LAS0BA */
- val = PciEepromWriteLongVPD (0x1c, 0x00200000); /* MARBR... */
- val = PciEepromWriteLongVPD (0x20, 0x00300500); /* LMISC/BIGEND */
+ PciEepromWriteLongVPD (0x1c, 0x00200000); /* MARBR... */
+ PciEepromWriteLongVPD (0x20, 0x00300500); /* LMISC/BIGEND */
- val = PciEepromWriteLongVPD (0x24, 0x00000000); /* EROMRR... */
- val = PciEepromWriteLongVPD (0x28, 0x00000000); /* EROMBA */
+ PciEepromWriteLongVPD (0x24, 0x00000000); /* EROMRR... */
+ PciEepromWriteLongVPD (0x28, 0x00000000); /* EROMBA */
- val = PciEepromWriteLongVPD (0x2c, 0x43030000); /* LBRD0... */
+ PciEepromWriteLongVPD (0x2c, 0x43030000); /* LBRD0... */
- val = PciEepromWriteLongVPD (0x30, 0x00000000); /* DMRR... */
- val = PciEepromWriteLongVPD (0x34, 0x00000000);
- val = PciEepromWriteLongVPD (0x38, 0x00000000);
+ PciEepromWriteLongVPD (0x30, 0x00000000); /* DMRR... */
+ PciEepromWriteLongVPD (0x34, 0x00000000);
+ PciEepromWriteLongVPD (0x38, 0x00000000);
- val = PciEepromWriteLongVPD (0x3c, 0x00000000); /* DMPBAM... */
- val = PciEepromWriteLongVPD (0x40, 0x00000000);
+ PciEepromWriteLongVPD (0x3c, 0x00000000); /* DMPBAM... */
+ PciEepromWriteLongVPD (0x40, 0x00000000);
/* Extra Long Serial EEPROM Load Registers... */
- val = PciEepromWriteLongVPD (0x44, 0x010212fe); /* PCISID... */
+ PciEepromWriteLongVPD (0x44, 0x010212fe); /* PCISID... */
/* las1: 505-sram access (0x0004.0000 ... 0x001f.ffff) */
/* Offset to LAS1: Group 1: 0x00040000 */
/* Group 2: 0x00080000 */
/* Group 3: 0x000c0000 */
- val = PciEepromWriteLongVPD (0x48, 0xffe00000); /* LAS1RR */
- val = PciEepromWriteLongVPD (0x4c, 0x00040001); /* LAS1BA */
- val = PciEepromWriteLongVPD (0x50, 0x00000208); /* LBRD1 */ /* so wars bisher */
+ PciEepromWriteLongVPD (0x48, 0xffe00000); /* LAS1RR */
+ PciEepromWriteLongVPD (0x4c, 0x00040001); /* LAS1BA */
+ PciEepromWriteLongVPD (0x50, 0x00000208); /* LBRD1 */ /* so wars bisher */
- val = PciEepromWriteLongVPD (0x54, 0x00004c06); /* HotSwap... */
+ PciEepromWriteLongVPD (0x54, 0x00004c06); /* HotSwap... */
printf ("Finished writing defaults into PLX PCI9054 EEPROM!\n");
}
@@ -186,8 +184,6 @@
static void clearPci9054 (void)
{
- int val;
-
/*
* Set EEPROM write-protect register to 0
*/
@@ -195,8 +191,8 @@
in_be32 ((void *)(pci9054_iobase + 0x0c)) & 0xffff00ff);
/* Long Serial EEPROM Load Registers... */
- val = PciEepromWriteLongVPD (0x00, 0xffffffff);
- val = PciEepromWriteLongVPD (0x04, 0xffffffff); /* other input controller */
+ PciEepromWriteLongVPD (0x00, 0xffffffff);
+ PciEepromWriteLongVPD (0x04, 0xffffffff); /* other input controller */
printf ("Finished clearing PLX PCI9054 EEPROM!\n");
}
diff --git a/board/esd/pci405/cmd_pci405.c b/board/esd/pci405/cmd_pci405.c
index 13f9019..f570ef3 100644
--- a/board/esd/pci405/cmd_pci405.c
+++ b/board/esd/pci405/cmd_pci405.c
@@ -42,7 +42,6 @@
unsigned int *ptr = 0;
int count = 0;
int count2 = 0;
- int status;
int i;
char addr[16];
char str[] = "\\|/-";
@@ -99,7 +98,7 @@
local_args[0] = argv[0];
local_args[1] = NULL;
- status = do_bootm (cmdtp, 0, 1, local_args);
+ do_bootm (cmdtp, 0, 1, local_args);
}
return 0;
diff --git a/board/evb64260/eth.c b/board/evb64260/eth.c
index 1492ffc..c02a9cd 100644
--- a/board/evb64260/eth.c
+++ b/board/evb64260/eth.c
@@ -127,31 +127,32 @@
#endif
if(icr&0x10000000) {
- unsigned int psr;
- psr=GTREGREAD(ETHERNET0_PORT_STATUS_REGISTER + p->reg_base);
#ifdef DEBUG
+ unsigned int psr;
+
+ psr=GTREGREAD(ETHERNET0_PORT_STATUS_REGISTER + p->reg_base);
printf("PHY state change:\n"
" GT:%s:%s:%s:%s\n",
- psr&1?"100":" 10",
- psr&8?" Link":"nLink",
- psr&2?"FD":"HD",
- psr&4?" FC":"nFC");
+ psr & 1 ? "100" : " 10",
+ psr & 8 ? " Link" : "nLink",
+ psr & 2 ? "FD" : "HD",
+ psr & 4 ? " FC" : "nFC");
#ifdef CONFIG_INTEL_LXT97X /* non-standard mii reg (intel lxt972a) */
{
- unsigned short mii_11;
- mii_11=miiphy_read_ret(ether_port_phy_addr[p->dev],0x11);
+ unsigned short mii_11;
+ mii_11 = miiphy_read_ret(ether_port_phy_addr[p->dev], 0x11);
- printf(" mii:%s:%s:%s:%s %s:%s %s\n",
- mii_11&(1<<14)?"100":" 10",
- mii_11&(1<<10)?" Link":"nLink",
- mii_11&(1<<9)?"FD":"HD",
- mii_11&(1<<4)?" FC":"nFC",
+ printf(" mii:%s:%s:%s:%s %s:%s %s\n",
+ mii_11 & (1 << 14) ? "100" : " 10",
+ mii_11 & (1 << 10) ? " Link" : "nLink",
+ mii_11 & (1 << 9) ? "FD" : "HD",
+ mii_11 & (1 << 4) ? " FC" : "nFC",
- mii_11&(1<<7)?"ANc":"ANnc",
- mii_11&(1<<8)?"AN":"Manual",
- ""
- );
+ mii_11 & (1 << 7) ? "ANc" : "ANnc",
+ mii_11 & (1 << 8) ? "AN" : "Manual",
+ ""
+ );
}
#endif /* CONFIG_INTEL_LXT97X */
#endif /* DEBUG */
diff --git a/board/evb64260/evb64260.c b/board/evb64260/evb64260.c
index 80756a5..393320a 100644
--- a/board/evb64260/evb64260.c
+++ b/board/evb64260/evb64260.c
@@ -32,6 +32,7 @@
#include <galileo/gt64260R.h>
#include <net.h>
#include <netdev.h>
+#include <linux/compiler.h>
#include <asm/io.h>
#include "eth.h"
@@ -360,7 +361,7 @@
{
#if !defined(CONFIG_ZUMA_V2) && !defined(CONFIG_P3G4)
volatile int *addr = NULL;
- int dummy;
+ __maybe_unused int dummy;
if (mode == 1) {
switch (led) {
diff --git a/board/evb64260/i2c.c b/board/evb64260/i2c.c
index 88d0dac..8119fce 100644
--- a/board/evb64260/i2c.c
+++ b/board/evb64260/i2c.c
@@ -20,29 +20,25 @@
i2c_init(int speed, int slaveaddr)
{
unsigned int n, m, freq, margin, power;
- unsigned int actualFreq, actualN=0, actualM=0;
+ unsigned int actualn = 0, actualm = 0;
unsigned int control, status;
- unsigned int minMargin = 0xffffffff;
+ unsigned int minmargin = 0xffffffff;
unsigned int tclk = 125000000;
DP(puts("i2c_init\n"));
- for(n = 0 ; n < 8 ; n++)
- {
- for(m = 0 ; m < 16 ; m++)
- {
- power = 2<<n; /* power = 2^(n+1) */
- freq = tclk/(10*(m+1)*power);
+ for (n = 0 ; n < 8 ; n++) {
+ for (m = 0 ; m < 16 ; m++) {
+ power = 2 << n; /* power = 2^(n+1) */
+ freq = tclk / (10 * (m + 1) * power);
if (speed > freq)
margin = speed - freq;
else
margin = freq - speed;
- if(margin < minMargin)
- {
- minMargin = margin;
- actualFreq = freq;
- actualN = n;
- actualM = m;
+ if (margin < minmargin) {
+ minmargin = margin;
+ actualn = n;
+ actualm = m;
}
}
}
@@ -59,7 +55,7 @@
DP(puts("set baudrate\n"));
- GT_REG_WRITE(I2C_STATUS_BAUDE_RATE, (actualM << 3) | actualN);
+ GT_REG_WRITE(I2C_STATUS_BAUDE_RATE, (actualm << 3) | actualn);
GT_REG_WRITE(I2C_CONTROL, (0x1 << 2) | (0x1 << 6));
udelay(I2C_DELAY * 10);
@@ -91,13 +87,13 @@
udelay(I2C_DELAY);
if (count > 20) {
GT_REG_WRITE(I2C_CONTROL, (0x1 << 4)); /*stop*/
- return (status);
+ return status;
}
GT_REG_READ(I2C_STATUS_BAUDE_RATE, &status);
count++;
}
- return (0);
+ return 0;
}
static uchar
@@ -110,9 +106,8 @@
/* Output slave address */
- if (ten_bit) {
+ if (ten_bit)
bits = 10;
- }
data = (dev_addr << 1);
/* set the read bit */
@@ -129,7 +124,7 @@
udelay(I2C_DELAY);
if (count > 20) {
GT_REG_WRITE(I2C_CONTROL, (0x1 << 4)); /*stop*/
- return(status);
+ return status;
}
GT_REG_READ(I2C_STATUS_BAUDE_RATE, &status);
count++;
@@ -137,14 +132,14 @@
if (bits == 10) {
printf("10 bit I2C addressing not yet implemented\n");
- return (0xff);
+ return 0xff;
}
- return (0);
+ return 0;
}
static uchar
-i2c_get_data(uchar* return_data, int len) {
+i2c_get_data(uchar *return_data, int len) {
unsigned int data, status = 0;
int count = 0;
@@ -163,7 +158,7 @@
count++;
while ((status & 0xff) != 0x50) {
udelay(I2C_DELAY);
- if(count > 2) {
+ if (count > 2) {
GT_REG_WRITE(I2C_CONTROL, (0x1 << 4)); /*stop*/
return 0;
}
@@ -178,16 +173,16 @@
RESET_REG_BITS(I2C_CONTROL, BIT2|BIT3);
while ((status & 0xff) != 0x58) {
udelay(I2C_DELAY);
- if(count > 200) {
+ if (count > 200) {
GT_REG_WRITE(I2C_CONTROL, (0x1 << 4)); /*stop*/
- return (status);
+ return status;
}
GT_REG_READ(I2C_STATUS_BAUDE_RATE, &status);
count++;
}
GT_REG_WRITE(I2C_CONTROL, (0x1 << 4)); /* stop */
- return (0);
+ return 0;
}
static uchar
@@ -213,9 +208,9 @@
count++;
while ((status & 0xff) != 0x28) {
udelay(I2C_DELAY);
- if(count > 20) {
+ if (count > 20) {
GT_REG_WRITE(I2C_CONTROL, (0x1 << 4)); /*stop*/
- return (status);
+ return status;
}
GT_REG_READ(I2C_STATUS_BAUDE_RATE, &status);
count++;
@@ -227,7 +222,7 @@
udelay(I2C_DELAY * 10);
- return (0);
+ return 0;
}
static uchar
@@ -254,19 +249,19 @@
return status;
}
- return (0);
+ return 0;
}
uchar
-i2c_read(uchar dev_addr, unsigned int offset, int len, uchar* data,
+i2c_read(uchar dev_addr, unsigned int offset, int len, uchar *data,
int ten_bit)
{
uchar status = 0;
- unsigned int i2cFreq = 400000;
+ unsigned int i2cfreq = 400000;
DP(puts("i2c_read\n"));
- i2c_init(i2cFreq,0);
+ i2c_init(i2cfreq, 0);
status = i2c_start();
@@ -285,7 +280,7 @@
return status;
}
- i2c_init(i2cFreq,0);
+ i2c_init(i2cfreq, 0);
status = i2c_start();
if (status) {
diff --git a/board/evb64260/sdram_init.c b/board/evb64260/sdram_init.c
index e2f0769..6f725f6 100644
--- a/board/evb64260/sdram_init.c
+++ b/board/evb64260/sdram_init.c
@@ -29,6 +29,7 @@
#include <galileo/pci.h>
#include <galileo/gt64260R.h>
#include <net.h>
+#include <linux/compiler.h>
#include "eth.h"
#include "mpsc.h"
@@ -330,7 +331,8 @@
static int setup_sdram_common (sdram_info_t info[2])
{
ulong tmp;
- int tpar = 2, tras_clocks = 5, registered = 1, ecc = 2;
+ int tpar = 2, tras_clocks = 5, registered = 1;
+ __maybe_unused int ecc = 2;
if (!info[0].banks && !info[1].banks)
return 0;
@@ -407,8 +409,9 @@
/* sets up the GT properly with information passed in */
static int setup_sdram (sdram_info_t * info)
{
- ulong tmp, check;
+ ulong tmp;
ulong *addr = 0;
+ __maybe_unused ulong check;
int i;
/* sanity checking */
diff --git a/board/evb64260/zuma_pbb_mbox.c b/board/evb64260/zuma_pbb_mbox.c
index 8e38102..621c64c 100644
--- a/board/evb64260/zuma_pbb_mbox.c
+++ b/board/evb64260/zuma_pbb_mbox.c
@@ -12,57 +12,62 @@
static int zuma_mbox_write(struct _zuma_mbox_dev *dev, unsigned int data)
{
- unsigned int status, count = 0, i;
+ unsigned int status, count = 0, i;
- status = (volatile int)le32_to_cpu(dev->sip->mbox_status);
+ status = (volatile int) le32_to_cpu(dev->sip->mbox_status);
- while((status & OUT_PENDING) && count < 1000) {
- count++;
- for(i=0;i<1000;i++);
- status = (volatile int)le32_to_cpu(dev->sip->mbox_status);
- }
- if(count < 1000) {
- /* if SET it means msg pending */
- /* printf("mbox real write %08x\n",data); */
- dev->sip->mbox_out = cpu_to_le32(data);
- return 4;
- }
+ while ((status & OUT_PENDING) && count < 1000) {
+ count++;
+ for (i = 0; i < 1000; i++)
+ ;
+ status = (volatile int) le32_to_cpu(dev->sip->mbox_status);
+ }
+ if (count < 1000) {
+ /* if SET it means msg pending */
+ /* printf("mbox real write %08x\n",data); */
+ dev->sip->mbox_out = cpu_to_le32(data);
+ return 4;
+ }
- printf("mbox tx timeout\n");
- return 0;
+ printf("mbox tx timeout\n");
+ return 0;
}
static int zuma_mbox_read(struct _zuma_mbox_dev *dev, unsigned int *data)
{
- unsigned int status, count = 0, i;
+ unsigned int status, count = 0, i;
- status = (volatile int)le32_to_cpu(dev->sip->mbox_status);
+ status = (volatile int) le32_to_cpu(dev->sip->mbox_status);
- while(!(status & IN_VALID) && count < 1000) {
- count++;
- for(i=0;i<1000;i++);
- status = (volatile int)le32_to_cpu(dev->sip->mbox_status);
- }
- if(count < 1000) {
- /* if SET it means msg pending */
- *data=le32_to_cpu(dev->sip->mbox_in);
- /*printf("mbox real read %08x\n", *data); */
- return 4;
- }
- printf("mbox rx timeout\n");
- return 0;
+ while (!(status & IN_VALID) && count < 1000) {
+ count++;
+ for (i = 0; i < 1000; i++)
+ ;
+ status = (volatile int) le32_to_cpu(dev->sip->mbox_status);
+ }
+ if (count < 1000) {
+ /* if SET it means msg pending */
+ *data = le32_to_cpu(dev->sip->mbox_in);
+ /*printf("mbox real read %08x\n", *data); */
+ return 4;
+ }
+ printf("mbox rx timeout\n");
+ return 0;
}
static int zuma_mbox_do_one_mailbox(unsigned int out, unsigned int *in)
{
- int ret;
- ret=zuma_mbox_write(&zuma_mbox_dev,out);
- /*printf("write 0x%08x (%d bytes)\n", out, ret); */
- if(ret!=4) return -1;
- ret=zuma_mbox_read(&zuma_mbox_dev,in);
- /*printf("read 0x%08x (%d bytes)\n", *in, ret); */
- if(ret!=4) return -1;
- return 0;
+ int ret;
+
+ ret = zuma_mbox_write(&zuma_mbox_dev, out);
+ /*printf("write 0x%08x (%d bytes)\n", out, ret); */
+ if (ret != 4)
+ return -1;
+ ret = zuma_mbox_read(&zuma_mbox_dev, in);
+ /*printf("read 0x%08x (%d bytes)\n", *in, ret); */
+ if (ret != 4)
+ return -1;
+ return 0;
}
@@ -70,81 +75,93 @@
static int zuma_mbox_do_all_mailbox(void)
{
- unsigned int data_in;
- unsigned short sdata_in;
+ unsigned int data_in;
+ unsigned short sdata_in;
- RET_IF_FAILED(zuma_mbox_do_one_mailbox(ZUMA_MBOXMSG_START, &data_in));
+ RET_IF_FAILED(zuma_mbox_do_one_mailbox(ZUMA_MBOXMSG_START, &data_in));
- RET_IF_FAILED(zuma_mbox_do_one_mailbox(ZUMA_MBOXMSG_MACL, &data_in));
- memcpy(zuma_acc_mac+2,&data_in,4);
- RET_IF_FAILED(zuma_mbox_do_one_mailbox(ZUMA_MBOXMSG_MACH, &data_in));
- sdata_in=data_in&0xffff;
- memcpy(zuma_acc_mac,&sdata_in,2);
+ RET_IF_FAILED(zuma_mbox_do_one_mailbox(ZUMA_MBOXMSG_MACL, &data_in));
+ memcpy(zuma_acc_mac + 2, &data_in, 4);
+ RET_IF_FAILED(zuma_mbox_do_one_mailbox(ZUMA_MBOXMSG_MACH, &data_in));
+ sdata_in = data_in & 0xffff;
+ memcpy(zuma_acc_mac, &sdata_in, 2);
- RET_IF_FAILED(zuma_mbox_do_one_mailbox(ZUMA_MBOXMSG_IP, &data_in));
- zuma_ip=data_in;
+ RET_IF_FAILED(zuma_mbox_do_one_mailbox(ZUMA_MBOXMSG_IP, &data_in));
+ zuma_ip = data_in;
- RET_IF_FAILED(zuma_mbox_do_one_mailbox(ZUMA_MBOXMSG_SLOT, &data_in));
- zuma_slot_bac=data_in>>3;
+ RET_IF_FAILED(zuma_mbox_do_one_mailbox(ZUMA_MBOXMSG_SLOT, &data_in));
+ zuma_slot_bac = data_in >> 3;
- RET_IF_FAILED(zuma_mbox_do_one_mailbox(ZUMA_MBOXMSG_BAUD, &data_in));
- zuma_console_baud = data_in & 0xffff;
- zuma_debug_baud = data_in >> 16;
+ RET_IF_FAILED(zuma_mbox_do_one_mailbox(ZUMA_MBOXMSG_BAUD, &data_in));
+ zuma_console_baud = data_in & 0xffff;
+ zuma_debug_baud = data_in >> 16;
- RET_IF_FAILED(zuma_mbox_do_one_mailbox(ZUMA_MBOXMSG_ENG_PRV_MACL, &data_in));
- memcpy(zuma_prv_mac+2,&data_in,4);
- RET_IF_FAILED(zuma_mbox_do_one_mailbox(ZUMA_MBOXMSG_ENG_PRV_MACH, &data_in));
- sdata_in=data_in&0xffff;
- memcpy(zuma_prv_mac,&sdata_in,2);
+ RET_IF_FAILED(zuma_mbox_do_one_mailbox
+ (ZUMA_MBOXMSG_ENG_PRV_MACL, &data_in));
+ memcpy(zuma_prv_mac + 2, &data_in, 4);
+ RET_IF_FAILED(zuma_mbox_do_one_mailbox
+ (ZUMA_MBOXMSG_ENG_PRV_MACH, &data_in));
+ sdata_in = data_in & 0xffff;
+ memcpy(zuma_prv_mac, &sdata_in, 2);
- RET_IF_FAILED(zuma_mbox_do_one_mailbox(ZUMA_MBOXMSG_DONE, &data_in));
+ RET_IF_FAILED(zuma_mbox_do_one_mailbox(ZUMA_MBOXMSG_DONE, &data_in));
- return 0;
+ return 0;
}
-static void
-zuma_mbox_dump(void)
+static void zuma_mbox_dump(void)
{
- printf("ACC MAC=%04x%08x\n",*(unsigned short *)(&zuma_acc_mac),*(unsigned int *)((char *)&zuma_acc_mac+2));
- printf("PRV MAC=%04x%08x\n",*(unsigned short *)(&zuma_prv_mac),*(unsigned int *)((char *)&zuma_prv_mac+2));
- printf("slot:bac=%d:%d\n",(zuma_slot_bac>>2)&0xf, zuma_slot_bac & 0x3);
- printf("BAUD1=%d BAUD2=%d\n",zuma_console_baud,zuma_debug_baud);
+ unsigned short s;
+ unsigned int i;
+
+ memcpy(&s, &zuma_acc_mac, sizeof(s));
+ memcpy(&i, &zuma_acc_mac[2], sizeof(i));
+ printf("ACC MAC=%04x%08x\n", s, i);
+
+ memcpy(&s, &zuma_prv_mac, sizeof(s));
+ memcpy(&s, &zuma_prv_mac[2], sizeof(i));
+ printf("PRV MAC=%04x%08x\n", s, i);
+
+ printf("slot:bac=%d:%d\n",
+ (zuma_slot_bac >> 2) & 0xf,
+ zuma_slot_bac & 0x3);
+
+ printf("BAUD1=%d BAUD2=%d\n",
+ zuma_console_baud,
+ zuma_debug_baud);
}
-static void
-zuma_mbox_setenv(void)
+static void zuma_mbox_setenv(void)
{
- char *data, buf[32];
- unsigned char save = 0;
+ char *data, buf[32];
+ unsigned char save = 0;
- data = getenv("baudrate");
+ data = getenv("baudrate");
- if(!data || (zuma_console_baud != simple_strtoul(data, NULL, 10))) {
- sprintf(buf, "%6d", zuma_console_baud);
- setenv("baudrate", buf);
- save=1;
- printf("baudrate doesn't match from mbox\n");
- }
+ if (!data || (zuma_console_baud != simple_strtoul(data, NULL, 10))) {
+ sprintf(buf, "%6d", zuma_console_baud);
+ setenv("baudrate", buf);
+ save = 1;
+ printf("baudrate doesn't match from mbox\n");
+ }
- ip_to_string(zuma_ip, buf);
- setenv("ipaddr", buf);
+ ip_to_string(zuma_ip, buf);
+ setenv("ipaddr", buf);
- sprintf(buf,"%02x:%02x:%02x:%02x:%02x:%02x",
- zuma_prv_mac[0],
- zuma_prv_mac[1],
- zuma_prv_mac[2],
- zuma_prv_mac[3],
- zuma_prv_mac[4],
- zuma_prv_mac[5]);
- setenv("ethaddr", buf);
+ sprintf(buf, "%02x:%02x:%02x:%02x:%02x:%02x",
+ zuma_prv_mac[0],
+ zuma_prv_mac[1],
+ zuma_prv_mac[2],
+ zuma_prv_mac[3], zuma_prv_mac[4], zuma_prv_mac[5]);
+ setenv("ethaddr", buf);
- sprintf(buf,"%02x",zuma_slot_bac);
- setenv("bacslot", buf);
+ sprintf(buf, "%02x", zuma_slot_bac);
+ setenv("bacslot", buf);
- if(save)
- saveenv();
+ if (save)
+ saveenv();
}
/**
@@ -153,37 +170,39 @@
int zuma_mbox_init(void)
{
- unsigned int iobase;
- memset(&zuma_mbox_dev, 0, sizeof(struct _zuma_mbox_dev));
+ unsigned int iobase;
- zuma_mbox_dev.dev = pci_find_device(VENDOR_ID_ZUMA, DEVICE_ID_ZUMA_PBB, 0);
+ memset(&zuma_mbox_dev, 0, sizeof(struct _zuma_mbox_dev));
- if(zuma_mbox_dev.dev == -1) {
- printf("no zuma pbb\n");
- return -1;
- }
+ zuma_mbox_dev.dev =
+ pci_find_device(VENDOR_ID_ZUMA, DEVICE_ID_ZUMA_PBB, 0);
- pci_read_config_dword(zuma_mbox_dev.dev, PCI_BASE_ADDRESS_0, &iobase);
+ if (zuma_mbox_dev.dev == -1) {
+ printf("no zuma pbb\n");
+ return -1;
+ }
- iobase &= PCI_BASE_ADDRESS_MEM_MASK;
+ pci_read_config_dword(zuma_mbox_dev.dev, PCI_BASE_ADDRESS_0, &iobase);
- zuma_mbox_dev.sip = (PBB_DMA_REG_MAP *)iobase;
+ iobase &= PCI_BASE_ADDRESS_MEM_MASK;
- zuma_mbox_dev.sip->int_mask.word=0;
+ zuma_mbox_dev.sip = (PBB_DMA_REG_MAP *) iobase;
- printf("pbb @ %p v%d.%d, timestamp %08x\n", zuma_mbox_dev.sip,
- zuma_mbox_dev.sip->version.pci_bits.rev_major,
- zuma_mbox_dev.sip->version.pci_bits.rev_minor,
- zuma_mbox_dev.sip->timestamp);
+ zuma_mbox_dev.sip->int_mask.word = 0;
- if (zuma_mbox_do_all_mailbox() == -1) {
- printf("mailbox failed.. no ACC?\n");
- return -1;
- }
+ printf("pbb @ %p v%d.%d, timestamp %08x\n", zuma_mbox_dev.sip,
+ zuma_mbox_dev.sip->version.pci_bits.rev_major,
+ zuma_mbox_dev.sip->version.pci_bits.rev_minor,
+ zuma_mbox_dev.sip->timestamp);
- zuma_mbox_dump();
+ if (zuma_mbox_do_all_mailbox() == -1) {
+ printf("mailbox failed.. no ACC?\n");
+ return -1;
+ }
- zuma_mbox_setenv();
+ zuma_mbox_dump();
- return 0;
+ zuma_mbox_setenv();
+
+ return 0;
}
diff --git a/board/freescale/common/cds_pci_ft.c b/board/freescale/common/cds_pci_ft.c
index 6f221af..8a09f99 100644
--- a/board/freescale/common/cds_pci_ft.c
+++ b/board/freescale/common/cds_pci_ft.c
@@ -28,13 +28,12 @@
#if defined(CONFIG_OF_BOARD_SETUP)
static void cds_pci_fixup(void *blob)
{
- int node, tmp[2];
+ int node;
const char *path;
int len, slot, i;
u32 *map = NULL;
node = fdt_path_offset(blob, "/aliases");
- tmp[0] = 0;
if (node >= 0) {
path = fdt_getprop(blob, node, "pci0", NULL);
if (path) {
diff --git a/board/freescale/common/ics307_clk.c b/board/freescale/common/ics307_clk.c
index 89d8810..6acbc36 100644
--- a/board/freescale/common/ics307_clk.c
+++ b/board/freescale/common/ics307_clk.c
@@ -31,12 +31,81 @@
#include "pixis.h"
#endif
+/* define for SYS CLK or CLK1Frequency */
+#define TTL 1
+#define CLK2 0
+#define CRYSTAL 0
+#define MAX_VDW (511 + 8)
+#define MAX_RDW (127 + 2)
+#define MIN_VDW (4 + 8)
+#define MIN_RDW (1 + 2)
+#define NUM_OD_SETTING 8
+/*
+ * These defines cover the industrial temperature range part,
+ * for commercial, change below to 400000 and 55000, respectively
+ */
+#define MAX_VCO 360000
+#define MIN_VCO 60000
+
/* decode S[0-2] to Output Divider (OD) */
static u8 ics307_s_to_od[] = {
10, 2, 8, 4, 5, 7, 3, 6
};
/*
+ * Find one solution to generate required frequency for SYSCLK
+ * out_freq: KHz, required frequency to the SYSCLK
+ * the result will be retuned with component RDW, VDW, OD, TTL,
+ * CLK2 and crystal
+ */
+unsigned long ics307_sysclk_calculator(unsigned long out_freq)
+{
+ const unsigned long input_freq = CONFIG_ICS307_REFCLK_HZ;
+ unsigned long vdw, rdw, odp, s_vdw = 0, s_rdw = 0, s_odp = 0, od;
+ unsigned long tmp_out, diff, result = 0;
+ int found = 0;
+
+ for (odp = 0; odp < NUM_OD_SETTING; odp++) {
+ od = ics307_s_to_od[odp];
+ if (od * out_freq < MIN_VCO || od * out_freq > MAX_VCO)
+ continue;
+ for (rdw = MIN_RDW; rdw <= MAX_RDW; rdw++) {
+ /* Calculate the VDW */
+ vdw = out_freq * 1000 * od * rdw / (input_freq * 2);
+ if (vdw > MAX_VDW)
+ vdw = MAX_VDW;
+ if (vdw < MIN_VDW)
+ continue;
+ /* Calculate the temp out frequency */
+ tmp_out = input_freq * 2 * vdw / (rdw * od * 1000);
+ diff = MAX(out_freq, tmp_out) - MIN(out_freq, tmp_out);
+ /*
+ * calculate the percent, the precision is 1/1000
+ * If greater than 1/1000, continue
+ * otherwise, we think the solution is we required
+ */
+ if (diff * 1000 / out_freq > 1)
+ continue;
+ else {
+ s_vdw = vdw;
+ s_rdw = rdw;
+ s_odp = odp;
+ found = 1;
+ break;
+ }
+ }
+ }
+
+ if (found)
+ result = (s_rdw - 2) | (s_vdw - 8) << 7 | s_odp << 16 |
+ CLK2 << 19 | TTL << 21 | CRYSTAL << 22;
+
+ debug("ICS307-02: RDW: %ld, VDW: %ld, OD: %d\n", s_rdw - 2, s_vdw - 8,
+ ics307_s_to_od[s_odp]);
+ return result;
+}
+
+/*
* Calculate frequency being generated by ICS307-02 clock chip based upon
* the control bytes being programmed into it.
*/
diff --git a/board/freescale/common/ics307_clk.h b/board/freescale/common/ics307_clk.h
index db3dbc4..3757912 100644
--- a/board/freescale/common/ics307_clk.h
+++ b/board/freescale/common/ics307_clk.h
@@ -1,5 +1,5 @@
/*
- * Copyright 2010 Freescale Semiconductor, Inc.
+ * Copyright 2010-2011 Freescale Semiconductor, Inc.
*
* See file CREDITS for list of people who contributed to this
* project.
@@ -23,8 +23,10 @@
#define __ICS_CLK_H_ 1
#ifndef __ASSEMBLY__
+
extern unsigned long get_board_sys_clk(void);
extern unsigned long get_board_ddr_clk(void);
+extern unsigned long ics307_sysclk_calculator(unsigned long out_freq);
#endif
#endif /* __ICS_CLK_H_ */
diff --git a/board/freescale/common/ngpixis.c b/board/freescale/common/ngpixis.c
index 765f035..276ae3c 100644
--- a/board/freescale/common/ngpixis.c
+++ b/board/freescale/common/ngpixis.c
@@ -156,9 +156,29 @@
}
#endif
+void pixis_sysclk_set(unsigned long sysclk)
+{
+ unsigned long freq_word;
+ u8 sclk0, sclk1, sclk2;
+
+ freq_word = ics307_sysclk_calculator(sysclk);
+ sclk2 = freq_word & 0xff;
+ sclk1 = (freq_word >> 8) & 0xff;
+ sclk0 = (freq_word >> 16) & 0xff;
+
+ /* set SYSCLK enable bit */
+ PIXIS_WRITE(vcfgen0, 0x01);
+
+ /* SYSCLK to required frequency */
+ PIXIS_WRITE(sclk[0], sclk0);
+ PIXIS_WRITE(sclk[1], sclk1);
+ PIXIS_WRITE(sclk[2], sclk2);
+}
+
int pixis_reset_cmd(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
{
unsigned int i;
+ unsigned long sysclk;
char *p_altbank = NULL;
#ifdef DEBUG
char *p_dump = NULL;
@@ -182,6 +202,12 @@
continue;
}
#endif
+ if (strcmp(argv[i], "sysclk") == 0) {
+ sysclk = simple_strtoul(argv[i + 1], NULL, 0);
+ i += 1;
+ pixis_sysclk_set(sysclk);
+ continue;
+ }
unknown_param = argv[i];
}
@@ -219,4 +245,5 @@
#ifdef DEBUG
"pixis_reset dump - display the PIXIS registers\n"
#endif
+ "pixis_reset sysclk <SYSCLK_freq> - reset with SYSCLK frequency(KHz)\n"
);
diff --git a/board/freescale/common/pixis.c b/board/freescale/common/pixis.c
index a35b5cf..8d07061 100644
--- a/board/freescale/common/pixis.c
+++ b/board/freescale/common/pixis.c
@@ -380,7 +380,7 @@
{
int i, j;
int mulconst;
- int intarr_len, no_dec = 0;
+ int no_dec = 0;
unsigned long intval = 0, decval = 0;
char intarr[3], decarr[3];
@@ -399,8 +399,6 @@
i++;
}
- /* Assign length of integer part to intarr_len. */
- intarr_len = i;
intarr[i] = '\0';
if (no_dec) {
diff --git a/board/freescale/corenet_ds/eth_hydra.c b/board/freescale/corenet_ds/eth_hydra.c
index a7a5e13..962f380 100644
--- a/board/freescale/corenet_ds/eth_hydra.c
+++ b/board/freescale/corenet_ds/eth_hydra.c
@@ -377,7 +377,6 @@
int board_eth_init(bd_t *bis)
{
#ifdef CONFIG_FMAN_ENET
- struct dtsec *tsec = (void *)CONFIG_SYS_FSL_FM1_DTSEC1_ADDR;
struct fsl_pq_mdio_info dtsec_mdio_info;
struct tgec_mdio_info tgec_mdio_info;
unsigned int i, slot;
@@ -387,13 +386,6 @@
initialize_lane_to_slot();
- /*
- * Set TBIPA on FM1@DTSEC1. This is needed for configurations
- * where FM1@DTSEC1 isn't used directly, since it provides
- * MDIO for other ports.
- */
- out_be32(&tsec->tbipa, CONFIG_SYS_TBIPA_VALUE);
-
/* We want to use the PIXIS to configure MUX routing, not GPIOs. */
setbits_8(&pixis->brdcfg2, BRDCFG2_REG_GPIO_SEL);
diff --git a/board/freescale/corenet_ds/eth_p4080.c b/board/freescale/corenet_ds/eth_p4080.c
index 7ff00d1..1f00c14 100644
--- a/board/freescale/corenet_ds/eth_p4080.c
+++ b/board/freescale/corenet_ds/eth_p4080.c
@@ -301,7 +301,6 @@
{
#ifdef CONFIG_FMAN_ENET
ccsr_gpio_t *pgpio = (void *)(CONFIG_SYS_MPC85xx_GPIO_ADDR);
- struct dtsec *tsec = (void *)CONFIG_SYS_FSL_FM1_DTSEC1_ADDR;
int i;
struct fsl_pq_mdio_info dtsec_mdio_info;
struct tgec_mdio_info tgec_mdio_info;
@@ -327,13 +326,6 @@
SLOT5, /* 17 - Bank 3:D */
};
- /*
- * Set TBIPA on FM1@DTSEC1. This is needed for configurations
- * where FM1@DTSEC1 isn't used directly, since it provides
- * MDIO for other ports.
- */
- out_be32(&tsec->tbipa, CONFIG_SYS_TBIPA_VALUE);
-
/* Initialize the mdio_mux array so we can recognize empty elements */
for (i = 0; i < NUM_FM_PORTS; i++)
mdio_mux[i] = EMI_NONE;
diff --git a/board/freescale/mpc8360emds/mpc8360emds.c b/board/freescale/mpc8360emds/mpc8360emds.c
index be76774..bdd1293 100644
--- a/board/freescale/mpc8360emds/mpc8360emds.c
+++ b/board/freescale/mpc8360emds/mpc8360emds.c
@@ -172,10 +172,11 @@
if (board_handle_erratum2()) {
int i;
- for (i = 0; i < ARRAY_SIZE(uec_info); i++)
+ for (i = 0; i < ARRAY_SIZE(uec_info); i++) {
uec_info[i].enet_interface_type =
PHY_INTERFACE_MODE_RGMII_RXID;
uec_info[i].speed = SPEED_1000;
+ }
}
return uec_eth_init(bd, uec_info, ARRAY_SIZE(uec_info));
}
diff --git a/board/freescale/mpc8548cds/mpc8548cds.c b/board/freescale/mpc8548cds/mpc8548cds.c
index a8d57cd..e5563f7 100644
--- a/board/freescale/mpc8548cds/mpc8548cds.c
+++ b/board/freescale/mpc8548cds/mpc8548cds.c
@@ -33,6 +33,9 @@
#include <miiphy.h>
#include <libfdt.h>
#include <fdt_support.h>
+#include <tsec.h>
+#include <fsl_mdio.h>
+#include <netdev.h>
#include "../common/cadmus.h"
#include "../common/eeprom.h"
@@ -81,12 +84,10 @@
volatile fsl_lbc_t *lbc = LBC_BASE_ADDR;
uint clkdiv;
- uint lbc_hz;
sys_info_t sysinfo;
get_sys_info(&sysinfo);
clkdiv = (lbc->lcrr & LCRR_CLKDIV) * 2;
- lbc_hz = sysinfo.freqSystemBus / 1000000 / clkdiv;
gur->lbiuiplldcr1 = 0x00078080;
if (clkdiv == 16) {
@@ -115,7 +116,6 @@
uint idx;
volatile fsl_lbc_t *lbc = LBC_BASE_ADDR;
uint *sdram_addr = (uint *)CONFIG_SYS_LBC_SDRAM_BASE;
- uint cpu_board_rev;
uint lsdmr_common;
puts("LBC SDRAM: ");
@@ -137,7 +137,6 @@
/*
* MPC8548 uses "new" 15-16 style addressing.
*/
- cpu_board_rev = get_cpu_board_revision();
lsdmr_common = CONFIG_SYS_LBC_LSDMR_COMMON;
lsdmr_common |= LSDMR_BSMA1516;
@@ -287,7 +286,7 @@
fsl_pcie_init_board(first_free_busno);
}
-int last_stage_init(void)
+void configure_rgmii(void)
{
unsigned short temp;
@@ -295,29 +294,77 @@
/* This is needed to get the RGMII working for the 1.3+
* CDS cards */
if (get_board_version() == 0x13) {
- miiphy_write(CONFIG_TSEC1_NAME,
+ miiphy_write(DEFAULT_MII_NAME,
TSEC1_PHY_ADDR, 29, 18);
- miiphy_read(CONFIG_TSEC1_NAME,
+ miiphy_read(DEFAULT_MII_NAME,
TSEC1_PHY_ADDR, 30, &temp);
temp = (temp & 0xf03f);
temp |= 2 << 9; /* 36 ohm */
temp |= 2 << 6; /* 39 ohm */
- miiphy_write(CONFIG_TSEC1_NAME,
+ miiphy_write(DEFAULT_MII_NAME,
TSEC1_PHY_ADDR, 30, temp);
- miiphy_write(CONFIG_TSEC1_NAME,
+ miiphy_write(DEFAULT_MII_NAME,
TSEC1_PHY_ADDR, 29, 3);
- miiphy_write(CONFIG_TSEC1_NAME,
+ miiphy_write(DEFAULT_MII_NAME,
TSEC1_PHY_ADDR, 30, 0x8000);
}
- return 0;
+ return;
}
+#ifdef CONFIG_TSEC_ENET
+int board_eth_init(bd_t *bis)
+{
+ struct fsl_pq_mdio_info mdio_info;
+ struct tsec_info_struct tsec_info[4];
+ int num = 0;
+
+#ifdef CONFIG_TSEC1
+ SET_STD_TSEC_INFO(tsec_info[num], 1);
+ num++;
+#endif
+#ifdef CONFIG_TSEC2
+ SET_STD_TSEC_INFO(tsec_info[num], 2);
+ num++;
+#endif
+#ifdef CONFIG_TSEC3
+ /* initialize TSEC3 only if Carrier is 1.3 or above on CDS */
+ if (get_board_version() >= 0x13) {
+ SET_STD_TSEC_INFO(tsec_info[num], 3);
+ tsec_info[num].interface = PHY_INTERFACE_MODE_RGMII_ID;
+ num++;
+ }
+#endif
+#ifdef CONFIG_TSEC4
+ /* initialize TSEC4 only if Carrier is 1.3 or above on CDS */
+ if (get_board_version() >= 0x13) {
+ SET_STD_TSEC_INFO(tsec_info[num], 4);
+ tsec_info[num].interface = PHY_INTERFACE_MODE_RGMII_ID;
+ num++;
+ }
+#endif
+
+ if (!num) {
+ printf("No TSECs initialized\n");
+
+ return 0;
+ }
+
+ mdio_info.regs = (struct tsec_mii_mng *)CONFIG_SYS_MDIO_BASE_ADDR;
+ mdio_info.name = DEFAULT_MII_NAME;
+ fsl_pq_mdio_init(bis, &mdio_info);
+
+ tsec_eth_init(bis, tsec_info, num);
+ configure_rgmii();
+
+ return pci_eth_init(bis);
+}
+#endif
#if defined(CONFIG_OF_BOARD_SETUP)
void ft_pci_setup(void *blob, bd_t *bd)
diff --git a/board/freescale/mpc8568mds/mpc8568mds.c b/board/freescale/mpc8568mds/mpc8568mds.c
index 225c5d8..6e3945e 100644
--- a/board/freescale/mpc8568mds/mpc8568mds.c
+++ b/board/freescale/mpc8568mds/mpc8568mds.c
@@ -147,12 +147,10 @@
volatile fsl_lbc_t *lbc = LBC_BASE_ADDR;
uint clkdiv;
- uint lbc_hz;
sys_info_t sysinfo;
get_sys_info(&sysinfo);
clkdiv = (lbc->lcrr & LCRR_CLKDIV) * 2;
- lbc_hz = sysinfo.freqSystemBus / 1000000 / clkdiv;
gur->lbiuiplldcr1 = 0x00078080;
if (clkdiv == 16) {
@@ -302,6 +300,7 @@
i2c_write(0x27, 0x3, 1, &val8, 1);
asm("eieio");
+ i2c_set_bus_num(orig_i2c_bus);
}
#ifdef CONFIG_PCI
diff --git a/board/freescale/mpc8569mds/mpc8569mds.c b/board/freescale/mpc8569mds/mpc8569mds.c
index 89557d2..d119c65 100644
--- a/board/freescale/mpc8569mds/mpc8569mds.c
+++ b/board/freescale/mpc8569mds/mpc8569mds.c
@@ -303,12 +303,10 @@
volatile fsl_lbc_t *lbc = LBC_BASE_ADDR;
uint clkdiv;
- uint lbc_hz;
sys_info_t sysinfo;
get_sys_info(&sysinfo);
clkdiv = (lbc->lcrr & LCRR_CLKDIV) * 2;
- lbc_hz = sysinfo.freqSystemBus / 1000000 / clkdiv;
out_be32(&gur->lbiuiplldcr1, 0x00078080);
if (clkdiv == 16)
diff --git a/board/freescale/mpc8572ds/tlb.c b/board/freescale/mpc8572ds/tlb.c
index 575bdb5..6d60513 100644
--- a/board/freescale/mpc8572ds/tlb.c
+++ b/board/freescale/mpc8572ds/tlb.c
@@ -58,6 +58,7 @@
MAS3_SX|MAS3_SR, MAS2_W|MAS2_G,
0, 2, BOOKE_PAGESZ_256M, 1),
+#ifndef CONFIG_NAND_SPL
/* *I*G* - PCI */
SET_TLB_ENTRY(1, CONFIG_SYS_PCIE3_MEM_VIRT, CONFIG_SYS_PCIE3_MEM_PHYS,
MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
@@ -76,6 +77,7 @@
SET_TLB_ENTRY(1, CONFIG_SYS_PCIE3_IO_VIRT, CONFIG_SYS_PCIE3_IO_PHYS,
MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
0, 6, BOOKE_PAGESZ_256K, 1),
+#endif
/* *I*G - NAND */
SET_TLB_ENTRY(1, CONFIG_SYS_NAND_BASE, CONFIG_SYS_NAND_BASE_PHYS,
diff --git a/board/freescale/p1010rdb/p1010rdb.c b/board/freescale/p1010rdb/p1010rdb.c
index 03e9da1..b9e66f7 100644
--- a/board/freescale/p1010rdb/p1010rdb.c
+++ b/board/freescale/p1010rdb/p1010rdb.c
@@ -275,7 +275,9 @@
fdt_fixup_memory(blob, (u64)base, (u64)size);
+#if defined(CONFIG_HAS_FSL_DR_USB)
fdt_fixup_dr_usb(blob, bd);
+#endif
/* P1014 and it's derivatives don't support CAN and eTSEC3 */
if (cpu->soc_ver == SVR_P1014 || cpu->soc_ver == SVR_P1014_E) {
diff --git a/board/freescale/p1_p2_rdb/p1_p2_rdb.c b/board/freescale/p1_p2_rdb/p1_p2_rdb.c
index 864b3ce..cfbae69 100644
--- a/board/freescale/p1_p2_rdb/p1_p2_rdb.c
+++ b/board/freescale/p1_p2_rdb/p1_p2_rdb.c
@@ -264,7 +264,9 @@
fdt_fixup_memory(blob, (u64)base, (u64)size);
+#if defined(CONFIG_HAS_FSL_DR_USB)
fdt_fixup_dr_usb(blob, bd);
+#endif
#if defined(CONFIG_SDCARD) || defined(CONFIG_SPIFLASH)
/* Delete eLBC node as it is muxed with USB2 controller */
diff --git a/board/freescale/p1_p2_rdb_pc/law.c b/board/freescale/p1_p2_rdb_pc/law.c
index 5ff6ea6..7968919 100644
--- a/board/freescale/p1_p2_rdb_pc/law.c
+++ b/board/freescale/p1_p2_rdb_pc/law.c
@@ -25,15 +25,17 @@
#include <asm/mmu.h>
struct law_entry law_table[] = {
- SET_LAW(CONFIG_SYS_FLASH_BASE_PHYS, LAW_SIZE_64M, LAW_TRGT_IF_LBC),
+#ifndef CONFIG_NAND_SPL
SET_LAW(CONFIG_SYS_CPLD_BASE_PHYS, LAW_SIZE_1M, LAW_TRGT_IF_LBC),
SET_LAW(CONFIG_SYS_PMC_BASE_PHYS, LAW_SIZE_64K, LAW_TRGT_IF_LBC),
-#ifdef CONFIG_SYS_NAND_BASE_PHYS
- SET_LAW(CONFIG_SYS_NAND_BASE_PHYS, LAW_SIZE_1M, LAW_TRGT_IF_LBC),
-#endif
#ifdef CONFIG_VSC7385_ENET
SET_LAW(CONFIG_SYS_VSC7385_BASE_PHYS, LAW_SIZE_1M, LAW_TRGT_IF_LBC),
#endif
+#endif
+ SET_LAW(CONFIG_SYS_FLASH_BASE_PHYS, LAW_SIZE_64M, LAW_TRGT_IF_LBC),
+#ifdef CONFIG_SYS_NAND_BASE_PHYS
+ SET_LAW(CONFIG_SYS_NAND_BASE_PHYS, LAW_SIZE_1M, LAW_TRGT_IF_LBC),
+#endif
};
int num_law_entries = ARRAY_SIZE(law_table);
diff --git a/board/freescale/p1_p2_rdb_pc/p1_p2_rdb_pc.c b/board/freescale/p1_p2_rdb_pc/p1_p2_rdb_pc.c
index 4671128..a60c5a2 100644
--- a/board/freescale/p1_p2_rdb_pc/p1_p2_rdb_pc.c
+++ b/board/freescale/p1_p2_rdb_pc/p1_p2_rdb_pc.c
@@ -444,6 +444,9 @@
fdt_board_fixup_qe_pins(blob);
#endif
#endif
+
+#if defined(CONFIG_HAS_FSL_DR_USB)
fdt_fixup_dr_usb(blob, bd);
+#endif
}
#endif
diff --git a/board/freescale/p2041rdb/eth.c b/board/freescale/p2041rdb/eth.c
index 0a1dfa7..4b0d577 100644
--- a/board/freescale/p2041rdb/eth.c
+++ b/board/freescale/p2041rdb/eth.c
@@ -139,7 +139,6 @@
int board_eth_init(bd_t *bis)
{
#ifdef CONFIG_FMAN_ENET
- struct dtsec *tsec = (void *)CONFIG_SYS_FSL_FM1_DTSEC1_ADDR;
struct fsl_pq_mdio_info dtsec_mdio_info;
struct tgec_mdio_info tgec_mdio_info;
unsigned int i, slot;
@@ -149,13 +148,6 @@
initialize_lane_to_slot();
- /*
- * Set TBIPA on FM1@DTSEC1. This is needed for configurations
- * where FM1@DTSEC1 isn't used directly, since it provides
- * MDIO for other ports.
- */
- out_be32(&tsec->tbipa, CONFIG_SYS_TBIPA_VALUE);
-
dtsec_mdio_info.regs =
(struct tsec_mii_mng *)CONFIG_SYS_FM1_DTSEC1_MDIO_ADDR;
dtsec_mdio_info.name = DEFAULT_FM_MDIO_NAME;
diff --git a/board/gdsys/405ep/dlvision-10g.c b/board/gdsys/405ep/dlvision-10g.c
index ecba66e..f55afbd 100644
--- a/board/gdsys/405ep/dlvision-10g.c
+++ b/board/gdsys/405ep/dlvision-10g.c
@@ -87,7 +87,6 @@
u16 fpga_features = in_le16(&fpga->fpga_features);
unsigned unit_type;
unsigned hardware_version;
- unsigned feature_compression;
unsigned feature_rs232;
unsigned feature_audio;
unsigned feature_sysclock;
@@ -111,7 +110,6 @@
unit_type = (versions >> 4) & 0x000f;
hardware_version = versions & 0x000f;
- feature_compression = (fpga_features >> 13) & 0x0003;
feature_rs232 = fpga_features & (1<<11);
feature_audio = (fpga_features >> 9) & 0x0003;
feature_sysclock = (fpga_features >> 7) & 0x0003;
diff --git a/board/hymod/input.c b/board/hymod/input.c
index 1a2b8d2..0a58015 100644
--- a/board/hymod/input.c
+++ b/board/hymod/input.c
@@ -23,9 +23,6 @@
#include <common.h>
-/* imports from common/main.c */
-extern char console_buffer[CONFIG_SYS_CBSIZE];
-
int
hymod_get_serno (const char *prompt)
{
diff --git a/board/innokom/Makefile b/board/innokom/Makefile
deleted file mode 100644
index 8b58b7f..0000000
--- a/board/innokom/Makefile
+++ /dev/null
@@ -1,43 +0,0 @@
-#
-# (C) Copyright 2000-2006
-# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
-#
-# See file CREDITS for list of people who contributed to this
-# project.
-#
-# This program is free software; you can redistribute it and/or
-# modify it under the terms of the GNU General Public License as
-# published by the Free Software Foundation; either version 2 of
-# the License, or (at your option) any later version.
-#
-# This program is distributed in the hope that it will be useful,
-# but WITHOUT ANY WARRANTY; without even the implied warranty of
-# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-# GNU General Public License for more details.
-#
-# You should have received a copy of the GNU General Public License
-# along with this program; if not, write to the Free Software
-# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
-# MA 02111-1307 USA
-#
-
-include $(TOPDIR)/config.mk
-
-LIB = $(obj)lib$(BOARD).o
-
-COBJS := innokom.o flash.o
-
-SRCS := $(COBJS:.o=.c)
-OBJS := $(addprefix $(obj),$(COBJS))
-
-$(LIB): $(obj).depend $(OBJS)
- $(call cmd_link_o_target, $(OBJS))
-
-#########################################################################
-
-# defines $(obj).depend target
-include $(SRCTREE)/rules.mk
-
-sinclude $(obj).depend
-
-#########################################################################
diff --git a/board/innokom/flash.c b/board/innokom/flash.c
deleted file mode 100644
index ed4b987..0000000
--- a/board/innokom/flash.c
+++ /dev/null
@@ -1,421 +0,0 @@
-/*
- * (C) Copyright 2002
- * Kyle Harris, Nexus Technologies, Inc. kharris@nexus-tech.net
- *
- * (C) Copyright 2002
- * Sysgo Real-Time Solutions, GmbH <www.elinos.com>
- * Marius Groeger <mgroeger@sysgo.de>
- *
- * (C) Copyright 2002
- * Robert Schwebel, Pengutronix, <r.schwebel@pengutronix.de>
- *
- * (C) Copyright 2002
- * Auerswald GmbH & Co KG, Germany
- * Kai-Uwe Bloem <kai-uwe.bloem@auerswald.de>
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-#include <common.h>
-#include <asm/arch/pxa-regs.h>
-
-/* Debugging macros ------------------------------------------------------ */
-
-#undef FLASH_DEBUG
-
-/* Some debug macros */
-#if (FLASH_DEBUG > 2 )
-#define PRINTK3(args...) printf(args)
-#else
-#define PRINTK3(args...)
-#endif
-
-#if FLASH_DEBUG > 1
-#define PRINTK2(args...) printf(args)
-#else
-#define PRINTK2(args...)
-#endif
-
-#ifdef FLASH_DEBUG
-#define PRINTK(args...) printf(args)
-#else
-#define PRINTK(args...)
-#endif
-
-/* ------------------------------------------------------------------------ */
-
-/* Development system: we have only 16 MB Flash */
-#ifdef CONFIG_MTD_INNOKOM_16MB
-#define FLASH_BANK_SIZE 0x01000000 /* 16 MB (during development) */
-#define MAIN_SECT_SIZE 0x00020000 /* 128k per sector */
-#endif
-
-/* Production system: we have 64 MB Flash */
-#ifdef CONFIG_MTD_INNOKOM_64MB
-#define FLASH_BANK_SIZE 0x04000000 /* 64 MB */
-#define MAIN_SECT_SIZE 0x00020000 /* 128k per sector */
-#endif
-
-flash_info_t flash_info[CONFIG_SYS_MAX_FLASH_BANKS];
-
-/**
- * flash_init: - initialize data structures for flash chips
- *
- * @return: size of the flash
- */
-
-ulong flash_init(void)
-{
- int i, j;
- ulong size = 0;
-
- for (i = 0; i < CONFIG_SYS_MAX_FLASH_BANKS; i++) {
- ulong flashbase = 0;
- flash_info[i].flash_id =
- (INTEL_MANUFACT & FLASH_VENDMASK) |
- (INTEL_ID_28F128J3 & FLASH_TYPEMASK);
- flash_info[i].size = FLASH_BANK_SIZE;
- flash_info[i].sector_count = CONFIG_SYS_MAX_FLASH_SECT;
- memset(flash_info[i].protect, 0, CONFIG_SYS_MAX_FLASH_SECT);
-
- switch (i) {
- case 0:
- flashbase = PHYS_FLASH_1;
- break;
- default:
- panic("configured too many flash banks!\n");
- break;
- }
- for (j = 0; j < flash_info[i].sector_count; j++) {
- flash_info[i].start[j] = flashbase + j*MAIN_SECT_SIZE;
- }
- size += flash_info[i].size;
- }
-
- /* Protect u-boot sectors */
- flash_protect(FLAG_PROTECT_SET,
- CONFIG_SYS_FLASH_BASE,
- CONFIG_SYS_FLASH_BASE + (256*1024) - 1,
- &flash_info[0]);
-
-#ifdef CONFIG_ENV_IS_IN_FLASH
- flash_protect(FLAG_PROTECT_SET,
- CONFIG_ENV_ADDR,
- CONFIG_ENV_ADDR + CONFIG_ENV_SIZE - 1,
- &flash_info[0]);
-#endif
-
- return size;
-}
-
-
-/**
- * flash_print_info: - print information about the flash situation
- *
- * @param info:
- */
-
-void flash_print_info (flash_info_t *info)
-{
- int i, j;
-
- for (j=0; j<CONFIG_SYS_MAX_FLASH_BANKS; j++) {
-
- switch (info->flash_id & FLASH_VENDMASK) {
-
- case (INTEL_MANUFACT & FLASH_VENDMASK):
- printf("Intel: ");
- break;
- default:
- printf("Unknown Vendor ");
- break;
- }
-
- switch (info->flash_id & FLASH_TYPEMASK) {
-
- case (INTEL_ID_28F128J3 & FLASH_TYPEMASK):
- printf("28F128J3 (128Mbit)\n");
- break;
- default:
- printf("Unknown Chip Type\n");
- return;
- }
-
- printf(" Size: %ld MB in %d Sectors\n",
- info->size >> 20, info->sector_count);
-
- printf(" Sector Start Addresses:");
- for (i = 0; i < info->sector_count; i++) {
- if ((i % 5) == 0) printf ("\n ");
-
- printf (" %08lX%s", info->start[i],
- info->protect[i] ? " (RO)" : " ");
- }
- printf ("\n");
- info++;
- }
-}
-
-
-/**
- * flash_erase: - erase flash sectors
- *
- */
-
-int flash_erase(flash_info_t *info, int s_first, int s_last)
-{
- int flag, prot, sect;
- int rc = ERR_OK;
- ulong start;
-
- if (info->flash_id == FLASH_UNKNOWN)
- return ERR_UNKNOWN_FLASH_TYPE;
-
- if ((s_first < 0) || (s_first > s_last)) {
- return ERR_INVAL;
- }
-
- if ((info->flash_id & FLASH_VENDMASK) != (INTEL_MANUFACT & FLASH_VENDMASK))
- return ERR_UNKNOWN_FLASH_VENDOR;
-
- prot = 0;
- for (sect=s_first; sect<=s_last; ++sect) {
- if (info->protect[sect]) prot++;
- }
-
- if (prot) return ERR_PROTECTED;
-
- /*
- * Disable interrupts which might cause a timeout
- * here. Remember that our exception vectors are
- * at address 0 in the flash, and we don't want a
- * (ticker) exception to happen while the flash
- * chip is in programming mode.
- */
-
- flag = disable_interrupts();
-
- /* Start erase on unprotected sectors */
- for (sect = s_first; sect<=s_last && !ctrlc(); sect++) {
-
- printf("Erasing sector %2d ... ", sect);
-
- PRINTK("\n");
-
- /* arm simple, non interrupt dependent timer */
- start = get_timer(0);
-
- if (info->protect[sect] == 0) { /* not protected */
- u16 * volatile addr = (u16 * volatile)(info->start[sect]);
-
- PRINTK("unlocking sector\n");
- *addr = 0x0060;
- *addr = 0x00d0;
- *addr = 0x00ff;
-
- PRINTK("erasing sector\n");
- *addr = 0x0020;
- PRINTK("confirming erase\n");
- *addr = 0x00D0;
-
- while ((*addr & 0x0080) != 0x0080) {
- PRINTK(".");
- if (get_timer(start) > CONFIG_SYS_FLASH_ERASE_TOUT) {
- *addr = 0x00B0; /* suspend erase*/
- *addr = 0x00FF; /* read mode */
- rc = ERR_TIMOUT;
- goto outahere;
- }
- }
-
- PRINTK("clearing status register\n");
- *addr = 0x0050;
- PRINTK("resetting to read mode");
- *addr = 0x00FF;
- }
-
- printf("ok.\n");
- }
-
- if (ctrlc()) printf("User Interrupt!\n");
-
- outahere:
-
- /* allow flash to settle - wait 10 ms */
- udelay_masked(10000);
-
- if (flag) enable_interrupts();
-
- return rc;
-}
-
-
-/**
- * write_word: - copy memory to flash
- *
- * @param info:
- * @param dest:
- * @param data:
- * @return:
- */
-
-static int write_word (flash_info_t *info, ulong dest, ushort data)
-{
- volatile u16 *addr = (u16 *)dest, val;
- int rc = ERR_OK;
- int flag;
- ulong start;
-
- /* Check if Flash is (sufficiently) erased */
- if ((*addr & data) != data) return ERR_NOT_ERASED;
-
- /*
- * Disable interrupts which might cause a timeout
- * here. Remember that our exception vectors are
- * at address 0 in the flash, and we don't want a
- * (ticker) exception to happen while the flash
- * chip is in programming mode.
- */
- flag = disable_interrupts();
-
- /* clear status register command */
- *addr = 0x50;
-
- /* program set-up command */
- *addr = 0x40;
-
- /* latch address/data */
- *addr = data;
-
- /* arm simple, non interrupt dependent timer */
- start = get_timer(0);
-
- /* wait while polling the status register */
- while(((val = *addr) & 0x80) != 0x80) {
- if (get_timer(start) > CONFIG_SYS_FLASH_WRITE_TOUT) {
- rc = ERR_TIMOUT;
- *addr = 0xB0; /* suspend program command */
- goto outahere;
- }
- }
-
- if(val & 0x1A) { /* check for error */
- printf("\nFlash write error %02x at address %08lx\n",
- (int)val, (unsigned long)dest);
- if(val & (1<<3)) {
- printf("Voltage range error.\n");
- rc = ERR_PROG_ERROR;
- goto outahere;
- }
- if(val & (1<<1)) {
- printf("Device protect error.\n");
- rc = ERR_PROTECTED;
- goto outahere;
- }
- if(val & (1<<4)) {
- printf("Programming error.\n");
- rc = ERR_PROG_ERROR;
- goto outahere;
- }
- rc = ERR_PROG_ERROR;
- goto outahere;
- }
-
- outahere:
-
- *addr = 0xFF; /* read array command */
- if (flag) enable_interrupts();
-
- return rc;
-}
-
-
-/**
- * write_buf: - Copy memory to flash.
- *
- * @param info:
- * @param src: source of copy transaction
- * @param addr: where to copy to
- * @param cnt: number of bytes to copy
- *
- * @return error code
- */
-
-int write_buff (flash_info_t *info, uchar *src, ulong addr, ulong cnt)
-{
- ulong cp, wp;
- ushort data;
- int l;
- int i, rc;
-
- wp = (addr & ~1); /* get lower word aligned address */
-
- /*
- * handle unaligned start bytes
- */
- if ((l = addr - wp) != 0) {
- data = 0;
- for (i=0, cp=wp; i<l; ++i, ++cp) {
- data = (data >> 8) | (*(uchar *)cp << 8);
- }
- for (; i<2 && cnt>0; ++i) {
- data = (data >> 8) | (*src++ << 8);
- --cnt;
- ++cp;
- }
- for (; cnt==0 && i<2; ++i, ++cp) {
- data = (data >> 8) | (*(uchar *)cp << 8);
- }
-
- if ((rc = write_word(info, wp, data)) != 0) {
- return (rc);
- }
- wp += 2;
- }
-
- /*
- * handle word aligned part
- */
- while (cnt >= 2) {
- /* data = *((vushort*)src); */
- data = *((ushort*)src);
- if ((rc = write_word(info, wp, data)) != 0) {
- return (rc);
- }
- src += 2;
- wp += 2;
- cnt -= 2;
- }
-
- if (cnt == 0) return ERR_OK;
-
- /*
- * handle unaligned tail bytes
- */
- data = 0;
- for (i=0, cp=wp; i<2 && cnt>0; ++i, ++cp) {
- data = (data >> 8) | (*src++ << 8);
- --cnt;
- }
- for (; i<2; ++i, ++cp) {
- data = (data >> 8) | (*(uchar *)cp << 8);
- }
-
- return write_word(info, wp, data);
-}
diff --git a/board/innokom/innokom.c b/board/innokom/innokom.c
deleted file mode 100644
index 22de7e3..0000000
--- a/board/innokom/innokom.c
+++ /dev/null
@@ -1,190 +0,0 @@
-/*
- * (C) Copyright 2002
- * Robert Schwebel, Pengutronix, r.schwebel@pengutronix.de
- * Kyle Harris, Nexus Technologies, Inc., kharris@nexus-tech.net
- * Marius Groeger, Sysgo Real-Time Solutions GmbH, mgroeger@sysgo.de
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-#include <common.h>
-#include <netdev.h>
-#include <asm/arch/pxa-regs.h>
-#include <asm/mach-types.h>
-#include <asm/io.h>
-
-DECLARE_GLOBAL_DATA_PTR;
-
-#ifdef CONFIG_SHOW_BOOT_PROGRESS
-# define SHOW_BOOT_PROGRESS(arg) show_boot_progress(arg)
-#else
-# define SHOW_BOOT_PROGRESS(arg)
-#endif
-
-/**
- * i2c_init_board - reset i2c bus. When the board is powercycled during a
- * bus transfer it might hang; for details see doc/I2C_Edge_Conditions.
- * The Innokom board has GPIO70 connected to SCLK which can be toggled
- * until all chips think that their current cycles are finished.
- */
-int i2c_init_board(void)
-{
- int i;
-
- /* set gpio pin low _before_ we change direction to output */
- writel(GPIO_bit(70), GPCR(70));
-
- /* now toggle between output=low and high-impedance */
- for (i = 0; i < 20; i++) {
- writel(readl(GPDR(70)) | GPIO_bit(70), GPDR(70)); /* output */
- udelay(10);
- writel(readl(GPDR(70)) & ~GPIO_bit(70), GPDR(70)); /* input */
- udelay(10);
- }
-
- return 0;
-}
-
-
-/**
- * misc_init_r: - misc initialisation routines
- */
-
-int misc_init_r(void)
-{
- char *str;
-
- /* determine if the software update key is pressed during startup */
- if (readl(GPLR0) & 0x00000800) {
- printf("using bootcmd_normal (sw-update button not pressed)\n");
- str = getenv("bootcmd_normal");
- } else {
- printf("using bootcmd_update (sw-update button pressed)\n");
- str = getenv("bootcmd_update");
- }
-
- setenv("bootcmd",str);
-
- return 0;
-}
-
-
-/**
- * board_init: - setup some data structures
- *
- * @return: 0 in case of success
- */
-
-int board_init (void)
-{
- /* We have RAM, disable cache */
- dcache_disable();
- icache_disable();
-
- gd->bd->bi_arch_number = MACH_TYPE_INNOKOM;
- gd->bd->bi_boot_params = 0xa0000100;
- gd->bd->bi_baudrate = CONFIG_BAUDRATE;
-
- return 0;
-}
-
-extern void pxa_dram_init(void);
-int dram_init(void)
-{
- pxa_dram_init();
- gd->ram_size = PHYS_SDRAM_1_SIZE;
- return 0;
-}
-
-void dram_init_banksize(void)
-{
- gd->bd->bi_dram[0].start = PHYS_SDRAM_1;
- gd->bd->bi_dram[0].size = PHYS_SDRAM_1_SIZE;
-}
-
-/**
- * innokom_set_led: - switch LEDs on or off
- *
- * @param led: LED to switch (0,1,2)
- * @param state: switch on (1) or off (0)
- */
-
-void innokom_set_led(int led, int state)
-{
- switch(led) {
-/*
- case 0: if (state==1) {
- GPCR0 |= CSB226_USER_LED0;
- } else if (state==0) {
- GPSR0 |= CSB226_USER_LED0;
- }
- break;
-
- case 1: if (state==1) {
- GPCR0 |= CSB226_USER_LED1;
- } else if (state==0) {
- GPSR0 |= CSB226_USER_LED1;
- }
- break;
-
- case 2: if (state==1) {
- GPCR0 |= CSB226_USER_LED2;
- } else if (state==0) {
- GPSR0 |= CSB226_USER_LED2;
- }
- break;
-*/
- }
-
- return;
-}
-
-
-/**
- * show_boot_progress: - indicate state of the boot process
- *
- * @param status: Status number - see README for details.
- *
- * The CSB226 does only have 3 LEDs, so we switch them on at the most
- * important states (1, 5, 15).
- */
-
-void show_boot_progress (int status)
-{
- switch(status) {
-/*
- case 1: csb226_set_led(0,1); break;
- case 5: csb226_set_led(1,1); break;
- case 15: csb226_set_led(2,1); break;
-*/
- }
-
- return;
-}
-
-#ifdef CONFIG_CMD_NET
-int board_eth_init(bd_t *bis)
-{
- int rc = 0;
-#ifdef CONFIG_SMC91111
- rc = smc91111_initialize(0, CONFIG_SMC91111_BASE);
-#endif
- return rc;
-}
-#endif
diff --git a/board/keymile/km83xx/km83xx_i2c.c b/board/keymile/km83xx/km83xx_i2c.c
index be17775..8df92d8 100644
--- a/board/keymile/km83xx/km83xx_i2c.c
+++ b/board/keymile/km83xx/km83xx_i2c.c
@@ -41,7 +41,6 @@
{
struct fsl_i2c *dev;
dev = (struct fsl_i2c *) (CONFIG_SYS_IMMR + CONFIG_SYS_I2C_OFFSET);
- uchar dummy;
uchar last;
int nbr_read = 0;
int i = 0;
@@ -52,7 +51,7 @@
udelay(DELAY_ABORT_SEQ);
out_8(&dev->cr, (I2C_CR_MEN | I2C_CR_MSTA));
udelay(DELAY_ABORT_SEQ);
- dummy = in_8(&dev->dr);
+ in_8(&dev->dr);
udelay(DELAY_ABORT_SEQ);
last = in_8(&dev->dr);
nbr_read++;
diff --git a/board/mcc200/lcd.c b/board/mcc200/lcd.c
index 726366d..d8f754c 100644
--- a/board/mcc200/lcd.c
+++ b/board/mcc200/lcd.c
@@ -55,6 +55,9 @@
#define PSOC_RETRIES 10 /* each of PSOC_WAIT_TIME */
#define PSOC_WAIT_TIME 10 /* usec */
+#include <video_font.h>
+#define FONT_WIDTH VIDEO_FONT_WIDTH
+
DECLARE_GLOBAL_DATA_PTR;
/*
@@ -185,7 +188,6 @@
}
#ifdef CONFIG_PROGRESSBAR
-#define FONT_WIDTH 8 /* the same as VIDEO_FONT_WIDTH in video_font.h */
void show_progress (int size, int tot)
{
int cnt;
diff --git a/board/mpl/mip405/mip405.c b/board/mpl/mip405/mip405.c
index e93d994..9d0db64 100644
--- a/board/mpl/mip405/mip405.c
+++ b/board/mpl/mip405/mip405.c
@@ -246,8 +246,7 @@
unsigned char trp_clocks,
trcd_clocks,
tras_clocks,
- trc_clocks,
- tctp_clocks;
+ trc_clocks;
unsigned char cal_val;
unsigned char bc;
unsigned long sdram_tim, sdram_bank;
@@ -345,7 +344,6 @@
trcd_clocks = sdram_table[i].trcd; /* 20ns /7.5 ns (datain[29]) */
tras_clocks = sdram_table[i].tras; /* 44ns /7.5 ns (datain[30]) */
/* ctp = ((trp + tras) - trp - trcd) => tras - trcd */
- tctp_clocks = sdram_table[i].tctp; /* 44 - 20ns = 24ns */
/* trc_clocks is sum of trp_clocks + tras_clocks */
trc_clocks = trp_clocks + tras_clocks;
/* get SDRAM timing register */
@@ -626,10 +624,9 @@
{
unsigned long bank_reg[4], tmp, bank_size;
- int i, ds;
+ int i;
unsigned long TotalSize;
- ds = 0;
/* since the DRAM controller is allready set up, calculate the size with the
bank registers */
mtdcr (SDRAM0_CFGADDR, SDRAM0_B0CR);
@@ -646,8 +643,7 @@
tmp = (bank_reg[i] >> 17) & 0x7;
bank_size = 4 << tmp;
TotalSize += bank_size;
- } else
- ds = 1;
+ }
}
mtdcr (SDRAM0_CFGADDR, SDRAM0_ECCCFG);
tmp = mfdcr (SDRAM0_CFGDATA);
diff --git a/board/mpl/pip405/pip405.c b/board/mpl/pip405/pip405.c
index 7b48c06..a1f0b65 100644
--- a/board/mpl/pip405/pip405.c
+++ b/board/mpl/pip405/pip405.c
@@ -179,7 +179,6 @@
int board_early_init_f (void)
{
- unsigned char dataout[1];
unsigned char datain[128];
unsigned long sdram_size = 0;
SDRAM_SETUP *t = (SDRAM_SETUP *) sdram_setup_table;
@@ -189,9 +188,13 @@
unsigned short i;
unsigned char rows, cols, banks, sdram_banks, density;
unsigned char supported_cal, trp_clocks, trcd_clocks, tras_clocks,
- trc_clocks, tctp_clocks;
+ trc_clocks;
unsigned char cal_index, cal_val, spd_version, spd_chksum;
unsigned char buf[8];
+#ifdef SDRAM_DEBUG
+ unsigned char tctp_clocks;
+#endif
+
/* set up the config port */
mtdcr (EBC0_CFGADDR, PB7AP);
mtdcr (EBC0_CFGDATA, CONFIG_PORT_AP);
@@ -210,7 +213,6 @@
/* Read Serial Presence Detect Information */
i2c_init (CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE);
- dataout[0] = 0;
for (i = 0; i < 128; i++)
datain[i] = 127;
i2c_read(SPD_EEPROM_ADDRESS,0,1,datain,128);
@@ -307,12 +309,13 @@
/* trc_clocks is sum of trp_clocks + tras_clocks */
trc_clocks = trp_clocks + tras_clocks;
+
+#ifdef SDRAM_DEBUG
/* ctp = ((trp + tras) - trp - trcd) => tras - trcd */
tctp_clocks =
((NSto10PS (datain[30]) - NSto10PS (datain[29])) +
(tmemclk - 1)) / tmemclk;
-#ifdef SDRAM_DEBUG
serial_puts ("c_RP: ");
write_hex (trp_clocks);
serial_puts ("\nc_RCD: ");
diff --git a/board/mpl/vcma9/vcma9.c b/board/mpl/vcma9/vcma9.c
index e63625b..9f259c2 100644
--- a/board/mpl/vcma9/vcma9.c
+++ b/board/mpl/vcma9/vcma9.c
@@ -72,9 +72,6 @@
int board_init(void)
{
- /* arch number of VCMA9-Board */
- gd->bd->bi_arch_number = MACH_TYPE_MPL_VCMA9;
-
/* adress of boot parameters */
gd->bd->bi_boot_params = 0x30000100;
diff --git a/board/ronetix/pm9261/pm9261.c b/board/ronetix/pm9261/pm9261.c
index 871b94a..b26e33a 100644
--- a/board/ronetix/pm9261/pm9261.c
+++ b/board/ronetix/pm9261/pm9261.c
@@ -248,9 +248,6 @@
1 << ATMEL_ID_PIOC,
&pmc->pcer);
- /* arch number of PM9261-Board */
- gd->bd->bi_arch_number = MACH_TYPE_PM9261;
-
/* adress of boot parameters */
gd->bd->bi_boot_params = PHYS_SDRAM + 0x100;
diff --git a/board/ronetix/pm9263/pm9263.c b/board/ronetix/pm9263/pm9263.c
index 4b6fd66..335efba 100644
--- a/board/ronetix/pm9263/pm9263.c
+++ b/board/ronetix/pm9263/pm9263.c
@@ -348,9 +348,6 @@
(1 << ATMEL_ID_PIOB),
&pmc->pcer);
- /* arch number of AT91SAM9263EK-Board */
- gd->bd->bi_arch_number = MACH_TYPE_PM9263;
-
/* adress of boot parameters */
gd->bd->bi_boot_params = PHYS_SDRAM + 0x100;
diff --git a/board/ronetix/pm9g45/pm9g45.c b/board/ronetix/pm9g45/pm9g45.c
index f3374a4..961d193 100644
--- a/board/ronetix/pm9g45/pm9g45.c
+++ b/board/ronetix/pm9g45/pm9g45.c
@@ -139,8 +139,6 @@
(1 << ATMEL_ID_PIOC) |
(1 << ATMEL_ID_PIODE), &pmc->pcer);
- /* arch number of AT91SAM9M10G45EK-Board */
- gd->bd->bi_arch_number = MACH_TYPE_PM9G45;
/* adress of boot parameters */
gd->bd->bi_boot_params = PHYS_SDRAM + 0x100;
diff --git a/board/sbc8548/sbc8548.c b/board/sbc8548/sbc8548.c
index e1a3ea3..26095a5 100644
--- a/board/sbc8548/sbc8548.c
+++ b/board/sbc8548/sbc8548.c
@@ -77,12 +77,10 @@
volatile fsl_lbc_t *lbc = LBC_BASE_ADDR;
uint clkdiv;
- uint lbc_hz;
sys_info_t sysinfo;
get_sys_info(&sysinfo);
clkdiv = (in_be32(&lbc->lcrr) & LCRR_CLKDIV) * 2;
- lbc_hz = sysinfo.freqSystemBus / 1000000 / clkdiv;
out_be32(&gur->lbiuiplldcr1, 0x00078080);
if (clkdiv == 16) {
diff --git a/board/sbc8560/sbc8560.c b/board/sbc8560/sbc8560.c
index c5fe92e..98bc7df 100644
--- a/board/sbc8560/sbc8560.c
+++ b/board/sbc8560/sbc8560.c
@@ -348,7 +348,7 @@
void
ft_board_setup(void *blob, bd_t *bd)
{
- int node, tmp[2];
+ int node;
#ifdef CONFIG_PCI
const char *path;
#endif
@@ -356,7 +356,6 @@
ft_cpu_setup(blob, bd);
node = fdt_path_offset(blob, "/aliases");
- tmp[0] = 0;
if (node >= 0) {
#ifdef CONFIG_PCI
path = fdt_getprop(blob, node, "pci0", NULL);
diff --git a/board/syteco/zmx25/zmx25.c b/board/syteco/zmx25/zmx25.c
index a89ee1a..c56b195 100644
--- a/board/syteco/zmx25/zmx25.c
+++ b/board/syteco/zmx25/zmx25.c
@@ -128,7 +128,6 @@
#ifdef CONFIG_FEC_MXC
struct iomuxc_mux_ctl *muxctl;
- struct iomuxc_pad_ctl *padctl;
u32 gpio_mux_mode2 = MX25_PIN_MUX_MODE(2);
u32 gpio_mux_mode5 = MX25_PIN_MUX_MODE(5);
@@ -144,7 +143,6 @@
* FEC_RX_ERR: FEC_RX_ERR is ALT 2 mode of pin R2
*/
muxctl = (struct iomuxc_mux_ctl *)IMX_IOPADMUX_BASE;
- padctl = (struct iomuxc_pad_ctl *)IMX_IOPADCTL_BASE;
writel(gpio_mux_mode5, &muxctl->pad_upll_bypclk);
writel(gpio_mux_mode2, &muxctl->pad_uart2_cts);
diff --git a/board/csb226/Makefile b/board/ti/omap5_evm/Makefile
similarity index 85%
copy from board/csb226/Makefile
copy to board/ti/omap5_evm/Makefile
index 6fe9bec..fa81d64 100644
--- a/board/csb226/Makefile
+++ b/board/ti/omap5_evm/Makefile
@@ -1,5 +1,5 @@
#
-# (C) Copyright 2000-2006
+# (C) Copyright 2000, 2001, 2002
# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
#
# See file CREDITS for list of people who contributed to this
@@ -12,7 +12,7 @@
#
# This program is distributed in the hope that it will be useful,
# but WITHOUT ANY WARRANTY; without even the implied warranty of
-# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
# GNU General Public License for more details.
#
# You should have received a copy of the GNU General Public License
@@ -25,7 +25,7 @@
LIB = $(obj)lib$(BOARD).o
-COBJS := csb226.o flash.o
+COBJS := evm.o
SRCS := $(COBJS:.o=.c)
OBJS := $(addprefix $(obj),$(COBJS))
@@ -33,6 +33,12 @@
$(LIB): $(obj).depend $(OBJS)
$(call cmd_link_o_target, $(OBJS))
+clean:
+ rm -f $(OBJS)
+
+distclean: clean
+ rm -f $(LIB) core *.bak $(obj).depend
+
#########################################################################
# defines $(obj).depend target
diff --git a/board/ti/omap5_evm/evm.c b/board/ti/omap5_evm/evm.c
new file mode 100644
index 0000000..ea0cb13
--- /dev/null
+++ b/board/ti/omap5_evm/evm.c
@@ -0,0 +1,101 @@
+/*
+ * (C) Copyright 2010
+ * Texas Instruments Incorporated, <www.ti.com>
+ * Aneesh V <aneesh@ti.com>
+ * Steve Sakoman <steve@sakoman.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+#include <common.h>
+#include <twl6030.h>
+#include <asm/arch/sys_proto.h>
+#include <asm/arch/mmc_host_def.h>
+
+#include "mux_data.h"
+
+DECLARE_GLOBAL_DATA_PTR;
+
+const struct omap_sysinfo sysinfo = {
+ "Board: OMAP5430 EVM\n"
+};
+
+/**
+ * @brief board_init
+ *
+ * @return 0
+ */
+int board_init(void)
+{
+ gpmc_init();
+ gd->bd->bi_arch_number = MACH_TYPE_OMAP5_SEVM;
+ gd->bd->bi_boot_params = (0x80000000 + 0x100); /* boot param addr */
+
+ return 0;
+}
+
+int board_eth_init(bd_t *bis)
+{
+ return 0;
+}
+
+/**
+ * @brief misc_init_r - Configure EVM board specific configurations
+ * such as power configurations, ethernet initialization as phase2 of
+ * boot sequence
+ *
+ * @return 0
+ */
+int misc_init_r(void)
+{
+#ifdef CONFIG_TWL6030_POWER
+ twl6030_init_battery_charging();
+#endif
+ return 0;
+}
+
+void set_muxconf_regs_essential(void)
+{
+ do_set_mux(CONTROL_PADCONF_CORE, core_padconf_array_essential,
+ sizeof(core_padconf_array_essential) /
+ sizeof(struct pad_conf_entry));
+
+ do_set_mux(CONTROL_PADCONF_WKUP, wkup_padconf_array_essential,
+ sizeof(wkup_padconf_array_essential) /
+ sizeof(struct pad_conf_entry));
+}
+
+void set_muxconf_regs_non_essential(void)
+{
+ do_set_mux(CONTROL_PADCONF_CORE, core_padconf_array_non_essential,
+ sizeof(core_padconf_array_non_essential) /
+ sizeof(struct pad_conf_entry));
+
+ do_set_mux(CONTROL_PADCONF_WKUP, wkup_padconf_array_non_essential,
+ sizeof(wkup_padconf_array_non_essential) /
+ sizeof(struct pad_conf_entry));
+}
+
+#if !defined(CONFIG_SPL_BUILD) && defined(CONFIG_GENERIC_MMC)
+int board_mmc_init(bd_t *bis)
+{
+ omap_mmc_init(0);
+ omap_mmc_init(1);
+ return 0;
+}
+#endif
diff --git a/board/ti/omap5_evm/mux_data.h b/board/ti/omap5_evm/mux_data.h
new file mode 100644
index 0000000..18f4729
--- /dev/null
+++ b/board/ti/omap5_evm/mux_data.h
@@ -0,0 +1,275 @@
+/*
+ * (C) Copyright 2010
+ * Texas Instruments Incorporated, <www.ti.com>
+ *
+ * Balaji Krishnamoorthy <balajitk@ti.com>
+ * Aneesh V <aneesh@ti.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+#ifndef _EVM5430_MUX_DATA_H
+#define _EVM5430_MUX_DATA_H
+
+#include <asm/arch/mux_omap5.h>
+
+const struct pad_conf_entry core_padconf_array_essential[] = {
+
+{GPMC_AD0, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M1)}, /* sdmmc2_dat0 */
+{GPMC_AD1, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M1)}, /* sdmmc2_dat1 */
+{GPMC_AD2, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M1)}, /* sdmmc2_dat2 */
+{GPMC_AD3, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M1)}, /* sdmmc2_dat3 */
+{GPMC_AD4, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M1)}, /* sdmmc2_dat4 */
+{GPMC_AD5, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M1)}, /* sdmmc2_dat5 */
+{GPMC_AD6, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M1)}, /* sdmmc2_dat6 */
+{GPMC_AD7, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M1)}, /* sdmmc2_dat7 */
+{GPMC_NOE, (PTU | IEN | OFF_EN | OFF_OUT_PTD | M1)}, /* sdmmc2_clk */
+{GPMC_NWE, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M1)}, /* sdmmc2_cmd */
+{SDMMC1_CLK, (PTU | OFF_EN | OFF_OUT_PTD | M0)}, /* sdmmc1_clk */
+{SDMMC1_CMD, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M0)}, /* sdmmc1_cmd */
+{SDMMC1_DAT0, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M0)}, /* sdmmc1_dat0 */
+{SDMMC1_DAT1, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M0)}, /* sdmmc1_dat1 */
+{SDMMC1_DAT2, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M0)}, /* sdmmc1_dat2 */
+{SDMMC1_DAT3, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M0)}, /* sdmmc1_dat3 */
+{SDMMC1_DAT4, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M0)}, /* sdmmc1_dat4 */
+{SDMMC1_DAT5, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M0)}, /* sdmmc1_dat5 */
+{SDMMC1_DAT6, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M0)}, /* sdmmc1_dat6 */
+{SDMMC1_DAT7, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M0)}, /* sdmmc1_dat7 */
+{UART3_CTS_RCTX, (PTU | IEN | M0)}, /* uart3_tx */
+{UART3_RTS_SD, (M0)}, /* uart3_rts_sd */
+{UART3_RX_IRRX, (IEN | M0)}, /* uart3_rx */
+{UART3_TX_IRTX, (M0)} /* uart3_tx */
+
+};
+
+const struct pad_conf_entry wkup_padconf_array_essential[] = {
+
+{PAD1_SR_SCL, (PTU | IEN | M0)}, /* sr_scl */
+{PAD0_SR_SDA, (PTU | IEN | M0)}, /* sr_sda */
+{PAD1_SYS_32K, (IEN | M0)} /* sys_32k */
+
+};
+
+const struct pad_conf_entry core_padconf_array_non_essential[] = {
+ {GPMC_AD8, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M3)}, /* gpio_32 */
+ {GPMC_AD9, (PTU | IEN | M3)}, /* gpio_33 */
+ {GPMC_AD10, (PTU | IEN | M3)}, /* gpio_34 */
+ {GPMC_AD11, (PTU | IEN | M3)}, /* gpio_35 */
+ {GPMC_AD12, (PTU | IEN | M3)}, /* gpio_36 */
+ {GPMC_AD13, (PTD | OFF_EN | OFF_PD | OFF_OUT_PTD | M3)}, /* gpio_37 */
+ {GPMC_AD14, (PTD | OFF_EN | OFF_PD | OFF_OUT_PTD | M3)}, /* gpio_38 */
+ {GPMC_AD15, (PTD | OFF_EN | OFF_PD | OFF_OUT_PTD | M3)}, /* gpio_39 */
+ {GPMC_A16, (M3)}, /* gpio_40 */
+ {GPMC_A17, (PTD | M3)}, /* gpio_41 */
+ {GPMC_A18, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M1)}, /* kpd_row6 */
+ {GPMC_A19, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M1)}, /* kpd_row7 */
+ {GPMC_A20, (IEN | M3)}, /* gpio_44 */
+ {GPMC_A21, (M3)}, /* gpio_45 */
+ {GPMC_A22, (OFF_EN | OFF_PD | OFF_IN | M1)}, /* kpd_col6 */
+ {GPMC_A23, (OFF_EN | OFF_PD | OFF_IN | M1)}, /* kpd_col7 */
+ {GPMC_A24, (PTD | M3)}, /* gpio_48 */
+ {GPMC_A25, (PTD | M3)}, /* gpio_49 */
+ {GPMC_NCS0, (M3)}, /* gpio_50 */
+ {GPMC_NCS1, (IEN | M3)}, /* gpio_51 */
+ {GPMC_NCS2, (IEN | M3)}, /* gpio_52 */
+ {GPMC_NCS3, (IEN | M3)}, /* gpio_53 */
+ {GPMC_NWP, (M3)}, /* gpio_54 */
+ {GPMC_CLK, (PTD | M3)}, /* gpio_55 */
+ {GPMC_NADV_ALE, (M3)}, /* gpio_56 */
+ {GPMC_NBE0_CLE, (M3)}, /* gpio_59 */
+ {GPMC_NBE1, (PTD | M3)}, /* gpio_60 */
+ {GPMC_WAIT0, (PTU | IEN | M3)}, /* gpio_61 */
+ {GPMC_WAIT1, (IEN | M3)}, /* gpio_62 */
+ {C2C_DATA11, (PTD | M3)}, /* gpio_100 */
+ {C2C_DATA12, (M1)}, /* dsi1_te0 */
+ {C2C_DATA13, (PTD | M3)}, /* gpio_102 */
+ {C2C_DATA14, (M1)}, /* dsi2_te0 */
+ {C2C_DATA15, (PTD | M3)}, /* gpio_104 */
+ {HDMI_HPD, (M0)}, /* hdmi_hpd */
+ {HDMI_CEC, (M0)}, /* hdmi_cec */
+ {HDMI_DDC_SCL, (PTU | M0)}, /* hdmi_ddc_scl */
+ {HDMI_DDC_SDA, (PTU | IEN | M0)}, /* hdmi_ddc_sda */
+ {CSI21_DX0, (IEN | M0)}, /* csi21_dx0 */
+ {CSI21_DY0, (IEN | M0)}, /* csi21_dy0 */
+ {CSI21_DX1, (IEN | M0)}, /* csi21_dx1 */
+ {CSI21_DY1, (IEN | M0)}, /* csi21_dy1 */
+ {CSI21_DX2, (IEN | M0)}, /* csi21_dx2 */
+ {CSI21_DY2, (IEN | M0)}, /* csi21_dy2 */
+ {CSI21_DX3, (PTD | M7)}, /* csi21_dx3 */
+ {CSI21_DY3, (PTD | M7)}, /* csi21_dy3 */
+ {CSI21_DX4, (PTD | OFF_EN | OFF_PD | OFF_IN | M7)}, /* csi21_dx4 */
+ {CSI21_DY4, (PTD | OFF_EN | OFF_PD | OFF_IN | M7)}, /* csi21_dy4 */
+ {CSI22_DX0, (IEN | M0)}, /* csi22_dx0 */
+ {CSI22_DY0, (IEN | M0)}, /* csi22_dy0 */
+ {CSI22_DX1, (IEN | M0)}, /* csi22_dx1 */
+ {CSI22_DY1, (IEN | M0)}, /* csi22_dy1 */
+ {CAM_SHUTTER, (OFF_EN | OFF_PD | OFF_OUT_PTD | M0)}, /* cam_shutter */
+ {CAM_STROBE, (OFF_EN | OFF_PD | OFF_OUT_PTD | M0)}, /* cam_strobe */
+ {CAM_GLOBALRESET, (PTD | OFF_EN | OFF_PD | OFF_OUT_PTD | M3)}, /* gpio_83 */
+ {USBB1_ULPITLL_CLK, (IEN | OFF_EN | OFF_IN | M1)}, /* hsi1_cawake */
+ {USBB1_ULPITLL_STP, (IEN | OFF_EN | OFF_IN | M1)}, /* hsi1_cadata */
+ {USBB1_ULPITLL_DIR, (IEN | OFF_EN | OFF_IN | M1)}, /* hsi1_caflag */
+ {USBB1_ULPITLL_NXT, (OFF_EN | M1)}, /* hsi1_acready */
+ {USBB1_ULPITLL_DAT0, (OFF_EN | M1)}, /* hsi1_acwake */
+ {USBB1_ULPITLL_DAT1, (OFF_EN | M1)}, /* hsi1_acdata */
+ {USBB1_ULPITLL_DAT2, (OFF_EN | M1)}, /* hsi1_acflag */
+ {USBB1_ULPITLL_DAT3, (IEN | OFF_EN | OFF_IN | M1)}, /* hsi1_caready */
+ {USBB1_ULPITLL_DAT4, (IEN | OFF_EN | OFF_PD | OFF_IN | M4)}, /* usbb1_ulpiphy_dat4 */
+ {USBB1_ULPITLL_DAT5, (IEN | OFF_EN | OFF_PD | OFF_IN | M4)}, /* usbb1_ulpiphy_dat5 */
+ {USBB1_ULPITLL_DAT6, (IEN | OFF_EN | OFF_PD | OFF_IN | M4)}, /* usbb1_ulpiphy_dat6 */
+ {USBB1_ULPITLL_DAT7, (IEN | OFF_EN | OFF_PD | OFF_IN | M4)}, /* usbb1_ulpiphy_dat7 */
+ {USBB1_HSIC_DATA, (IEN | OFF_EN | OFF_PD | OFF_IN | M0)}, /* usbb1_hsic_data */
+ {USBB1_HSIC_STROBE, (IEN | OFF_EN | OFF_PD | OFF_IN | M0)}, /* usbb1_hsic_strobe */
+ {USBC1_ICUSB_DP, (IEN | M0)}, /* usbc1_icusb_dp */
+ {USBC1_ICUSB_DM, (IEN | M0)}, /* usbc1_icusb_dm */
+ {ABE_MCBSP2_CLKX, (IEN | OFF_EN | OFF_PD | OFF_IN | M0)}, /* abe_mcbsp2_clkx */
+ {ABE_MCBSP2_DR, (IEN | OFF_EN | OFF_OUT_PTD | M0)}, /* abe_mcbsp2_dr */
+ {ABE_MCBSP2_DX, (OFF_EN | OFF_OUT_PTD | M0)}, /* abe_mcbsp2_dx */
+ {ABE_MCBSP2_FSX, (IEN | OFF_EN | OFF_PD | OFF_IN | M0)}, /* abe_mcbsp2_fsx */
+ {ABE_MCBSP1_CLKX, (IEN | OFF_EN | OFF_PD | OFF_IN | M0)}, /* abe_mcbsp1_clkx */
+ {ABE_MCBSP1_DR, (IEN | OFF_EN | OFF_OUT_PTD | M0)}, /* abe_mcbsp1_dr */
+ {ABE_MCBSP1_DX, (OFF_EN | OFF_OUT_PTD | M0)}, /* abe_mcbsp1_dx */
+ {ABE_MCBSP1_FSX, (IEN | OFF_EN | OFF_PD | OFF_IN | M0)}, /* abe_mcbsp1_fsx */
+ {ABE_PDM_UL_DATA, (PTD | IEN | OFF_EN | OFF_PD | OFF_IN | M0)}, /* abe_pdm_ul_data */
+ {ABE_PDM_DL_DATA, (PTD | IEN | OFF_EN | OFF_PD | OFF_IN | M0)}, /* abe_pdm_dl_data */
+ {ABE_PDM_FRAME, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M0)}, /* abe_pdm_frame */
+ {ABE_PDM_LB_CLK, (PTD | IEN | OFF_EN | OFF_PD | OFF_IN | M0)}, /* abe_pdm_lb_clk */
+ {ABE_CLKS, (PTD | IEN | OFF_EN | OFF_PD | OFF_IN | M0)}, /* abe_clks */
+ {ABE_DMIC_CLK1, (M0)}, /* abe_dmic_clk1 */
+ {ABE_DMIC_DIN1, (IEN | M0)}, /* abe_dmic_din1 */
+ {ABE_DMIC_DIN2, (IEN | M0)}, /* abe_dmic_din2 */
+ {ABE_DMIC_DIN3, (IEN | M0)}, /* abe_dmic_din3 */
+ {UART2_CTS, (PTU | IEN | M0)}, /* uart2_cts */
+ {UART2_RTS, (M0)}, /* uart2_rts */
+ {UART2_RX, (PTU | IEN | M0)}, /* uart2_rx */
+ {UART2_TX, (M0)}, /* uart2_tx */
+ {HDQ_SIO, (M3)}, /* gpio_127 */
+ {MCSPI1_CLK, (IEN | OFF_EN | OFF_PD | OFF_IN | M0)}, /* mcspi1_clk */
+ {MCSPI1_SOMI, (IEN | OFF_EN | OFF_PD | OFF_IN | M0)}, /* mcspi1_somi */
+ {MCSPI1_SIMO, (IEN | OFF_EN | OFF_PD | OFF_IN | M0)}, /* mcspi1_simo */
+ {MCSPI1_CS0, (PTD | IEN | OFF_EN | OFF_PD | OFF_IN | M0)}, /* mcspi1_cs0 */
+ {MCSPI1_CS1, (PTD | IEN | OFF_EN | OFF_PD | OFF_IN | M3)}, /* mcspi1_cs1 */
+ {MCSPI1_CS2, (PTU | OFF_EN | OFF_OUT_PTU | M3)}, /* gpio_139 */
+ {MCSPI1_CS3, (PTU | IEN | M3)}, /* gpio_140 */
+ {SDMMC5_CLK, (PTU | IEN | OFF_EN | OFF_OUT_PTD | M0)}, /* sdmmc5_clk */
+ {SDMMC5_CMD, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M0)}, /* sdmmc5_cmd */
+ {SDMMC5_DAT0, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M0)}, /* sdmmc5_dat0 */
+ {SDMMC5_DAT1, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M0)}, /* sdmmc5_dat1 */
+ {SDMMC5_DAT2, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M0)}, /* sdmmc5_dat2 */
+ {SDMMC5_DAT3, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M0)}, /* sdmmc5_dat3 */
+ {MCSPI4_CLK, (IEN | OFF_EN | OFF_PD | OFF_IN | M0)}, /* mcspi4_clk */
+ {MCSPI4_SIMO, (IEN | OFF_EN | OFF_PD | OFF_IN | M0)}, /* mcspi4_simo */
+ {MCSPI4_SOMI, (IEN | OFF_EN | OFF_PD | OFF_IN | M0)}, /* mcspi4_somi */
+ {MCSPI4_CS0, (PTD | IEN | OFF_EN | OFF_PD | OFF_IN | M0)}, /* mcspi4_cs0 */
+ {UART4_RX, (IEN | M0)}, /* uart4_rx */
+ {UART4_TX, (M0)}, /* uart4_tx */
+ {USBB2_ULPITLL_CLK, (PTD | IEN | M3)}, /* gpio_157 */
+ {USBB2_ULPITLL_STP, (IEN | M5)}, /* dispc2_data23 */
+ {USBB2_ULPITLL_DIR, (IEN | M5)}, /* dispc2_data22 */
+ {USBB2_ULPITLL_NXT, (IEN | M5)}, /* dispc2_data21 */
+ {USBB2_ULPITLL_DAT0, (IEN | M5)}, /* dispc2_data20 */
+ {USBB2_ULPITLL_DAT1, (IEN | M5)}, /* dispc2_data19 */
+ {USBB2_ULPITLL_DAT2, (IEN | M5)}, /* dispc2_data18 */
+ {USBB2_ULPITLL_DAT3, (IEN | M5)}, /* dispc2_data15 */
+ {USBB2_ULPITLL_DAT4, (IEN | M5)}, /* dispc2_data14 */
+ {USBB2_ULPITLL_DAT5, (IEN | M5)}, /* dispc2_data13 */
+ {USBB2_ULPITLL_DAT6, (IEN | M5)}, /* dispc2_data12 */
+ {USBB2_ULPITLL_DAT7, (IEN | M5)}, /* dispc2_data11 */
+ {USBB2_HSIC_DATA, (PTD | OFF_EN | OFF_OUT_PTU | M3)}, /* gpio_169 */
+ {USBB2_HSIC_STROBE, (PTD | OFF_EN | OFF_OUT_PTU | M3)}, /* gpio_170 */
+ {UNIPRO_TX0, (OFF_EN | OFF_PD | OFF_IN | M1)}, /* kpd_col0 */
+ {UNIPRO_TY0, (OFF_EN | OFF_PD | OFF_IN | M1)}, /* kpd_col1 */
+ {UNIPRO_TX1, (OFF_EN | OFF_PD | OFF_IN | M1)}, /* kpd_col2 */
+ {UNIPRO_TY1, (OFF_EN | OFF_PD | OFF_IN | M1)}, /* kpd_col3 */
+ {UNIPRO_TX2, (OFF_EN | OFF_PD | OFF_IN | M1)}, /* kpd_col4 */
+ {UNIPRO_TY2, (OFF_EN | OFF_PD | OFF_IN | M1)}, /* kpd_col5 */
+ {UNIPRO_RX0, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M1)}, /* kpd_row0 */
+ {UNIPRO_RY0, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M1)}, /* kpd_row1 */
+ {UNIPRO_RX1, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M1)}, /* kpd_row2 */
+ {UNIPRO_RY1, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M1)}, /* kpd_row3 */
+ {UNIPRO_RX2, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M1)}, /* kpd_row4 */
+ {UNIPRO_RY2, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M1)}, /* kpd_row5 */
+ {USBA0_OTG_CE, (PTD | OFF_EN | OFF_PD | OFF_OUT_PTD | M0)}, /* usba0_otg_ce */
+ {USBA0_OTG_DP, (IEN | OFF_EN | OFF_PD | OFF_IN | M0)}, /* usba0_otg_dp */
+ {USBA0_OTG_DM, (IEN | OFF_EN | OFF_PD | OFF_IN | M0)}, /* usba0_otg_dm */
+ {FREF_CLK1_OUT, (M0)}, /* fref_clk1_out */
+ {FREF_CLK2_OUT, (M0)}, /* fref_clk2_out */
+ {SYS_NIRQ1, (PTU | IEN | M0)}, /* sys_nirq1 */
+ {SYS_NIRQ2, (M7)}, /* sys_nirq2 */
+ {SYS_BOOT0, (PTU | IEN | M3)}, /* gpio_184 */
+ {SYS_BOOT1, (M3)}, /* gpio_185 */
+ {SYS_BOOT2, (PTD | IEN | M3)}, /* gpio_186 */
+ {SYS_BOOT3, (PTD | IEN | M3)}, /* gpio_187 */
+ {SYS_BOOT4, (M3)}, /* gpio_188 */
+ {SYS_BOOT5, (PTD | IEN | M3)}, /* gpio_189 */
+ {DPM_EMU0, (IEN | M0)}, /* dpm_emu0 */
+ {DPM_EMU1, (IEN | M0)}, /* dpm_emu1 */
+ {DPM_EMU2, (IEN | M0)}, /* dpm_emu2 */
+ {DPM_EMU3, (IEN | M5)}, /* dispc2_data10 */
+ {DPM_EMU4, (IEN | M5)}, /* dispc2_data9 */
+ {DPM_EMU5, (IEN | M5)}, /* dispc2_data16 */
+ {DPM_EMU6, (IEN | M5)}, /* dispc2_data17 */
+ {DPM_EMU7, (IEN | M5)}, /* dispc2_hsync */
+ {DPM_EMU8, (IEN | M5)}, /* dispc2_pclk */
+ {DPM_EMU9, (IEN | M5)}, /* dispc2_vsync */
+ {DPM_EMU10, (IEN | M5)}, /* dispc2_de */
+ {DPM_EMU11, (IEN | M5)}, /* dispc2_data8 */
+ {DPM_EMU12, (IEN | M5)}, /* dispc2_data7 */
+ {DPM_EMU13, (IEN | M5)}, /* dispc2_data6 */
+ {DPM_EMU14, (IEN | M5)}, /* dispc2_data5 */
+ {DPM_EMU15, (IEN | M5)}, /* dispc2_data4 */
+ {DPM_EMU16, (M3)}, /* gpio_27 */
+ {DPM_EMU17, (IEN | M5)}, /* dispc2_data2 */
+ {DPM_EMU18, (IEN | M5)}, /* dispc2_data1 */
+ {DPM_EMU19, (IEN | M5)}, /* dispc2_data0 */
+ {I2C1_SCL, (PTU | IEN | M0)}, /* i2c1_scl */
+ {I2C1_SDA, (PTU | IEN | M0)}, /* i2c1_sda */
+ {I2C2_SCL, (PTU | IEN | M0)}, /* i2c2_scl */
+ {I2C2_SDA, (PTU | IEN | M0)}, /* i2c2_sda */
+ {I2C3_SCL, (PTU | IEN | M0)}, /* i2c3_scl */
+ {I2C3_SDA, (PTU | IEN | M0)}, /* i2c3_sda */
+ {I2C4_SCL, (PTU | IEN | M0)}, /* i2c4_scl */
+ {I2C4_SDA, (PTU | IEN | M0)} /* i2c4_sda */
+};
+
+const struct pad_conf_entry wkup_padconf_array_non_essential[] = {
+ {PAD0_SIM_IO, (IEN | M0)}, /* sim_io */
+ {PAD1_SIM_CLK, (M0)}, /* sim_clk */
+ {PAD0_SIM_RESET, (M0)}, /* sim_reset */
+ {PAD1_SIM_CD, (PTU | IEN | M0)}, /* sim_cd */
+ {PAD0_SIM_PWRCTRL, (M0)}, /* sim_pwrctrl */
+ {PAD1_FREF_XTAL_IN, (M0)}, /* # */
+ {PAD0_FREF_SLICER_IN, (M0)}, /* fref_slicer_in */
+ {PAD1_FREF_CLK_IOREQ, (M0)}, /* fref_clk_ioreq */
+ {PAD0_FREF_CLK0_OUT, (M2)}, /* sys_drm_msecure */
+ {PAD1_FREF_CLK3_REQ, (PTU | IEN | M0)}, /* # */
+ {PAD0_FREF_CLK3_OUT, (M0)}, /* fref_clk3_out */
+ {PAD1_FREF_CLK4_REQ, (PTU | IEN | M0)}, /* # */
+ {PAD0_FREF_CLK4_OUT, (M0)}, /* # */
+ {PAD0_SYS_NRESPWRON, (M0)}, /* sys_nrespwron */
+ {PAD1_SYS_NRESWARM, (M0)}, /* sys_nreswarm */
+ {PAD0_SYS_PWR_REQ, (PTU | M0)}, /* sys_pwr_req */
+ {PAD1_SYS_PWRON_RESET, (M3)}, /* gpio_wk29 */
+ {PAD0_SYS_BOOT6, (IEN | M3)}, /* gpio_wk9 */
+ {PAD1_SYS_BOOT7, (IEN | M3)}, /* gpio_wk10 */
+ {PAD1_FREF_CLK3_REQ, (M3)}, /* gpio_wk30 */
+ {PAD1_FREF_CLK4_REQ, (M3)}, /* gpio_wk7 */
+ {PAD0_FREF_CLK4_OUT, (M3)}, /* gpio_wk8 */
+};
+
+#endif /* _EVM4430_MUX_DATA_H */
diff --git a/board/ti/panda/Makefile b/board/ti/panda/Makefile
index ec493f5..b299e2f 100644
--- a/board/ti/panda/Makefile
+++ b/board/ti/panda/Makefile
@@ -25,9 +25,7 @@
LIB = $(obj)lib$(BOARD).o
-ifndef CONFIG_SPL_BUILD
COBJS := panda.o
-endif
SRCS := $(COBJS:.o=.c)
OBJS := $(addprefix $(obj),$(COBJS))
diff --git a/board/ti/panda/panda.c b/board/ti/panda/panda.c
index 97320cb..b4271fb 100644
--- a/board/ti/panda/panda.c
+++ b/board/ti/panda/panda.c
@@ -65,6 +65,23 @@
return 0;
}
+void set_muxconf_regs_essential(void)
+{
+ do_set_mux(CONTROL_PADCONF_CORE, core_padconf_array_essential,
+ sizeof(core_padconf_array_essential) /
+ sizeof(struct pad_conf_entry));
+
+ do_set_mux(CONTROL_PADCONF_WKUP, wkup_padconf_array_essential,
+ sizeof(wkup_padconf_array_essential) /
+ sizeof(struct pad_conf_entry));
+
+ if (omap_revision() >= OMAP4460_ES1_0)
+ do_set_mux(CONTROL_PADCONF_WKUP,
+ wkup_padconf_array_essential_4460,
+ sizeof(wkup_padconf_array_essential_4460) /
+ sizeof(struct pad_conf_entry));
+}
+
void set_muxconf_regs_non_essential(void)
{
do_set_mux(CONTROL_PADCONF_CORE, core_padconf_array_non_essential,
@@ -93,10 +110,18 @@
sizeof(struct pad_conf_entry));
}
-#ifdef CONFIG_GENERIC_MMC
+#if !defined(CONFIG_SPL_BUILD) && defined(CONFIG_GENERIC_MMC)
int board_mmc_init(bd_t *bis)
{
omap_mmc_init(0);
return 0;
}
#endif
+
+/*
+ * get_board_rev() - get board revision
+ */
+u32 get_board_rev(void)
+{
+ return 0x20;
+}
diff --git a/board/ti/panda/panda_mux_data.h b/board/ti/panda/panda_mux_data.h
index 83d0c3f..c05170e 100644
--- a/board/ti/panda/panda_mux_data.h
+++ b/board/ti/panda/panda_mux_data.h
@@ -28,6 +28,58 @@
#include <asm/arch/mux_omap4.h>
+
+const struct pad_conf_entry core_padconf_array_essential[] = {
+
+{GPMC_AD0, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M1)}, /* sdmmc2_dat0 */
+{GPMC_AD1, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M1)}, /* sdmmc2_dat1 */
+{GPMC_AD2, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M1)}, /* sdmmc2_dat2 */
+{GPMC_AD3, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M1)}, /* sdmmc2_dat3 */
+{GPMC_AD4, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M1)}, /* sdmmc2_dat4 */
+{GPMC_AD5, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M1)}, /* sdmmc2_dat5 */
+{GPMC_AD6, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M1)}, /* sdmmc2_dat6 */
+{GPMC_AD7, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M1)}, /* sdmmc2_dat7 */
+{GPMC_NOE, (PTU | IEN | OFF_EN | OFF_OUT_PTD | M1)}, /* sdmmc2_clk */
+{GPMC_NWE, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M1)}, /* sdmmc2_cmd */
+{SDMMC1_CLK, (PTU | OFF_EN | OFF_OUT_PTD | M0)}, /* sdmmc1_clk */
+{SDMMC1_CMD, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M0)}, /* sdmmc1_cmd */
+{SDMMC1_DAT0, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M0)}, /* sdmmc1_dat0 */
+{SDMMC1_DAT1, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M0)}, /* sdmmc1_dat1 */
+{SDMMC1_DAT2, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M0)}, /* sdmmc1_dat2 */
+{SDMMC1_DAT3, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M0)}, /* sdmmc1_dat3 */
+{SDMMC1_DAT4, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M0)}, /* sdmmc1_dat4 */
+{SDMMC1_DAT5, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M0)}, /* sdmmc1_dat5 */
+{SDMMC1_DAT6, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M0)}, /* sdmmc1_dat6 */
+{SDMMC1_DAT7, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M0)}, /* sdmmc1_dat7 */
+{I2C1_SCL, (PTU | IEN | M0)}, /* i2c1_scl */
+{I2C1_SDA, (PTU | IEN | M0)}, /* i2c1_sda */
+{I2C2_SCL, (PTU | IEN | M0)}, /* i2c2_scl */
+{I2C2_SDA, (PTU | IEN | M0)}, /* i2c2_sda */
+{I2C3_SCL, (PTU | IEN | M0)}, /* i2c3_scl */
+{I2C3_SDA, (PTU | IEN | M0)}, /* i2c3_sda */
+{I2C4_SCL, (PTU | IEN | M0)}, /* i2c4_scl */
+{I2C4_SDA, (PTU | IEN | M0)}, /* i2c4_sda */
+{UART3_CTS_RCTX, (PTU | IEN | M0)}, /* uart3_tx */
+{UART3_RTS_SD, (M0)}, /* uart3_rts_sd */
+{UART3_RX_IRRX, (IEN | M0)}, /* uart3_rx */
+{UART3_TX_IRTX, (M0)} /* uart3_tx */
+
+};
+
+const struct pad_conf_entry wkup_padconf_array_essential[] = {
+
+{PAD1_SR_SCL, (PTU | IEN | M0)}, /* sr_scl */
+{PAD0_SR_SDA, (PTU | IEN | M0)}, /* sr_sda */
+{PAD1_SYS_32K, (IEN | M0)} /* sys_32k */
+
+};
+
+const struct pad_conf_entry wkup_padconf_array_essential_4460[] = {
+
+{PAD1_FREF_CLK4_REQ, (M3)}, /* gpio_wk7, TPS */
+
+};
+
const struct pad_conf_entry core_padconf_array_non_essential[] = {
{GPMC_AD8, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M3)}, /* gpio_32 */
{GPMC_AD9, (PTU | IEN | M3)}, /* gpio_33 */
@@ -219,7 +271,7 @@
{PAD0_FREF_SLICER_IN, (M0)}, /* fref_slicer_in */
{PAD1_FREF_CLK_IOREQ, (M0)}, /* fref_clk_ioreq */
{PAD0_FREF_CLK0_OUT, (M2)}, /* sys_drm_msecure */
- {PAD1_FREF_CLK3_REQ, M7}, /* safe mode */
+ {PAD1_FREF_CLK3_REQ, M7}, /* safe mode */
{PAD0_FREF_CLK3_OUT, (M0)}, /* fref_clk3_out */
{PAD0_FREF_CLK4_OUT, (PTU | M3)}, /* led status_2 */
{PAD0_SYS_NRESPWRON, (M0)}, /* sys_nrespwron */
diff --git a/board/ti/sdp4430/Makefile b/board/ti/sdp4430/Makefile
index 806fdf4..72ad3eb 100644
--- a/board/ti/sdp4430/Makefile
+++ b/board/ti/sdp4430/Makefile
@@ -25,8 +25,10 @@
LIB = $(obj)lib$(BOARD).o
+COBJS := sdp.o
+
ifndef CONFIG_SPL_BUILD
-COBJS := sdp.o cmd_bat.o
+COBJS += cmd_bat.o
endif
SRCS := $(COBJS:.o=.c)
diff --git a/board/ti/sdp4430/sdp.c b/board/ti/sdp4430/sdp.c
index a5ea682..e1b853c 100644
--- a/board/ti/sdp4430/sdp.c
+++ b/board/ti/sdp4430/sdp.c
@@ -70,6 +70,23 @@
return 0;
}
+void set_muxconf_regs_essential(void)
+{
+ do_set_mux(CONTROL_PADCONF_CORE, core_padconf_array_essential,
+ sizeof(core_padconf_array_essential) /
+ sizeof(struct pad_conf_entry));
+
+ do_set_mux(CONTROL_PADCONF_WKUP, wkup_padconf_array_essential,
+ sizeof(wkup_padconf_array_essential) /
+ sizeof(struct pad_conf_entry));
+
+ if (omap_revision() >= OMAP4460_ES1_0)
+ do_set_mux(CONTROL_PADCONF_WKUP,
+ wkup_padconf_array_essential_4460,
+ sizeof(wkup_padconf_array_essential_4460) /
+ sizeof(struct pad_conf_entry));
+}
+
void set_muxconf_regs_non_essential(void)
{
do_set_mux(CONTROL_PADCONF_CORE, core_padconf_array_non_essential,
@@ -81,7 +98,7 @@
sizeof(struct pad_conf_entry));
}
-#ifdef CONFIG_GENERIC_MMC
+#if !defined(CONFIG_SPL_BUILD) && defined(CONFIG_GENERIC_MMC)
int board_mmc_init(bd_t *bis)
{
omap_mmc_init(0);
@@ -89,3 +106,11 @@
return 0;
}
#endif
+
+/*
+ * get_board_rev() - get board revision
+ */
+u32 get_board_rev(void)
+{
+ return 0x20;
+}
diff --git a/board/ti/sdp4430/sdp4430_mux_data.h b/board/ti/sdp4430/sdp4430_mux_data.h
index 06efaea..1c6e0ee 100644
--- a/board/ti/sdp4430/sdp4430_mux_data.h
+++ b/board/ti/sdp4430/sdp4430_mux_data.h
@@ -28,6 +28,49 @@
#include <asm/arch/mux_omap4.h>
+const struct pad_conf_entry core_padconf_array_essential[] = {
+
+{GPMC_AD0, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M1)}, /* sdmmc2_dat0 */
+{GPMC_AD1, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M1)}, /* sdmmc2_dat1 */
+{GPMC_AD2, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M1)}, /* sdmmc2_dat2 */
+{GPMC_AD3, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M1)}, /* sdmmc2_dat3 */
+{GPMC_AD4, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M1)}, /* sdmmc2_dat4 */
+{GPMC_AD5, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M1)}, /* sdmmc2_dat5 */
+{GPMC_AD6, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M1)}, /* sdmmc2_dat6 */
+{GPMC_AD7, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M1)}, /* sdmmc2_dat7 */
+{GPMC_NOE, (PTU | IEN | OFF_EN | OFF_OUT_PTD | M1)}, /* sdmmc2_clk */
+{GPMC_NWE, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M1)}, /* sdmmc2_cmd */
+{SDMMC1_CLK, (PTU | OFF_EN | OFF_OUT_PTD | M0)}, /* sdmmc1_clk */
+{SDMMC1_CMD, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M0)}, /* sdmmc1_cmd */
+{SDMMC1_DAT0, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M0)}, /* sdmmc1_dat0 */
+{SDMMC1_DAT1, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M0)}, /* sdmmc1_dat1 */
+{SDMMC1_DAT2, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M0)}, /* sdmmc1_dat2 */
+{SDMMC1_DAT3, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M0)}, /* sdmmc1_dat3 */
+{SDMMC1_DAT4, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M0)}, /* sdmmc1_dat4 */
+{SDMMC1_DAT5, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M0)}, /* sdmmc1_dat5 */
+{SDMMC1_DAT6, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M0)}, /* sdmmc1_dat6 */
+{SDMMC1_DAT7, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M0)}, /* sdmmc1_dat7 */
+{UART3_CTS_RCTX, (PTU | IEN | M0)}, /* uart3_tx */
+{UART3_RTS_SD, (M0)}, /* uart3_rts_sd */
+{UART3_RX_IRRX, (IEN | M0)}, /* uart3_rx */
+{UART3_TX_IRTX, (M0)} /* uart3_tx */
+
+};
+
+const struct pad_conf_entry wkup_padconf_array_essential[] = {
+
+{PAD1_SR_SCL, (PTU | IEN | M0)}, /* sr_scl */
+{PAD0_SR_SDA, (PTU | IEN | M0)}, /* sr_sda */
+{PAD1_SYS_32K, (IEN | M0)} /* sys_32k */
+
+};
+
+const struct pad_conf_entry wkup_padconf_array_essential_4460[] = {
+
+{PAD1_FREF_CLK4_REQ, (M3)}, /* gpio_wk7, TPS */
+
+};
+
const struct pad_conf_entry core_padconf_array_non_essential[] = {
{GPMC_AD8, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M3)}, /* gpio_32 */
{GPMC_AD9, (PTU | IEN | M3)}, /* gpio_33 */
@@ -200,6 +243,15 @@
{DPM_EMU17, (IEN | M5)}, /* dispc2_data2 */
{DPM_EMU18, (IEN | M5)}, /* dispc2_data1 */
{DPM_EMU19, (IEN | M5)}, /* dispc2_data0 */
+ {I2C1_SCL, (PTU | IEN | M0)}, /* i2c1_scl */
+ {I2C1_SDA, (PTU | IEN | M0)}, /* i2c1_sda */
+ {I2C2_SCL, (PTU | IEN | M0)}, /* i2c2_scl */
+ {I2C2_SDA, (PTU | IEN | M0)}, /* i2c2_sda */
+ {I2C3_SCL, (PTU | IEN | M0)}, /* i2c3_scl */
+ {I2C3_SDA, (PTU | IEN | M0)}, /* i2c3_sda */
+ {I2C4_SCL, (PTU | IEN | M0)}, /* i2c4_scl */
+ {I2C4_SDA, (PTU | IEN | M0)} /* i2c4_sda */
+
};
const struct pad_conf_entry wkup_padconf_array_non_essential[] = {
@@ -214,7 +266,6 @@
{PAD0_FREF_CLK0_OUT, (M2)}, /* sys_drm_msecure */
{PAD1_FREF_CLK3_REQ, (M3)}, /* gpio_wk30 - Debug led-1 */
{PAD0_FREF_CLK3_OUT, (M0)}, /* fref_clk3_out */
- {PAD1_FREF_CLK4_REQ, (M3)}, /* gpio_wk7 - Debug led-2 */
{PAD0_FREF_CLK4_OUT, (M3)}, /* gpio_wk8 - Debug led-3 */
{PAD0_SYS_NRESPWRON, (M0)}, /* sys_nrespwron */
{PAD1_SYS_NRESWARM, (M0)}, /* sys_nreswarm */
diff --git a/board/vpac270/vpac270.c b/board/vpac270/vpac270.c
index 43bbdff..cf8e7b6 100644
--- a/board/vpac270/vpac270.c
+++ b/board/vpac270/vpac270.c
@@ -21,6 +21,7 @@
#include <common.h>
#include <asm/arch/hardware.h>
+#include <asm/arch/regs-mmc.h>
#include <netdev.h>
#include <serial.h>
#include <asm/io.h>
@@ -72,6 +73,14 @@
#endif
}
+#ifdef CONFIG_CMD_MMC
+int board_mmc_init(bd_t *bis)
+{
+ pxa_mmc_register(0);
+ return 0;
+}
+#endif
+
#ifdef CONFIG_CMD_USB
int usb_board_init(void)
{
diff --git a/board/zeus/zeus.c b/board/zeus/zeus.c
index 18cb85f..272e59b 100644
--- a/board/zeus/zeus.c
+++ b/board/zeus/zeus.c
@@ -40,7 +40,6 @@
extern flash_info_t flash_info[CONFIG_SYS_MAX_FLASH_BANKS]; /* info for FLASH chips */
extern env_t *env_ptr;
-extern uchar default_environment[];
ulong flash_get_size(ulong base, int banknum);
void env_crc_update(void);
diff --git a/boards.cfg b/boards.cfg
index 8b7a03b..c83d861 100644
--- a/boards.cfg
+++ b/boards.cfg
@@ -35,7 +35,7 @@
# Target ARCH CPU Board name Vendor SoC Options
###########################################################################################################
-integratorcp_cm1136 arm arm1136 integrator armltd - integratorcp
+integratorcp_cm1136 arm arm1136 integrator armltd - integratorcp:CM1136
qong arm arm1136 - davedenx mx31
mx31ads arm arm1136 - freescale mx31
imx31_litekit arm arm1136 - logicpd mx31
@@ -47,9 +47,9 @@
mx35pdk arm arm1136 - freescale mx35
omap2420h4 arm arm1136 - ti omap24xx
tnetv107x_evm arm arm1176 tnetv107xevm ti tnetv107x
-integratorap_cm720t arm arm720t integrator armltd - integratorap
-integratorap_cm920t arm arm920t integrator armltd - integratorap
-integratorcp_cm920t arm arm920t integrator armltd - integratorcp
+integratorap_cm720t arm arm720t integrator armltd - integratorap:CM720T
+integratorap_cm920t arm arm920t integrator armltd - integratorap:CM920T
+integratorcp_cm920t arm arm920t integrator armltd - integratorcp:CM920T
a320evb arm arm920t - faraday a320
at91rm9200ek arm arm920t at91rm9200ek atmel at91 at91rm9200ek
at91rm9200ek_ram arm arm920t at91rm9200ek atmel at91 at91rm9200ek:RAMBOOT
@@ -63,8 +63,8 @@
VCMA9 arm arm920t vcma9 mpl s3c24x0
smdk2410 arm arm920t - samsung s3c24x0
omap1510inn arm arm925t - ti
-integratorap_cm926ejs arm arm926ejs integrator armltd - integratorap
-integratorcp_cm926ejs arm arm926ejs integrator armltd - integratorcp
+integratorap_cm926ejs arm arm926ejs integrator armltd - integratorap:CM926EJ_S
+integratorcp_cm926ejs arm arm926ejs integrator armltd - integratorcp:CM924EJ_S
versatileqemu arm arm926ejs versatile armltd versatile versatile:ARCH_VERSATILE_QEMU,ARCH_VERSATILE_PB
versatilepb arm arm926ejs versatile armltd versatile versatile:ARCH_VERSATILE_PB
versatileab arm arm926ejs versatile armltd versatile versatile:ARCH_VERSATILE_AB
@@ -121,6 +121,7 @@
pm9g45 arm arm926ejs pm9g45 ronetix at91 pm9g45:AT91SAM9G45
da830evm arm arm926ejs da8xxevm davinci davinci
da850evm arm arm926ejs da8xxevm davinci davinci
+da850_am18xxevm arm arm926ejs da8xxevm davinci davinci
cam_enc_4xx arm arm926ejs cam_enc_4xx ait davinci cam_enc_4xx
hawkboard arm arm926ejs da8xxevm davinci davinci
hawkboard_nand arm arm926ejs da8xxevm davinci davinci hawkboard:NAND_U_BOOT
@@ -130,6 +131,7 @@
davinci_dm355leopard arm arm926ejs dm355leopard davinci davinci
davinci_dm365evm arm arm926ejs dm365evm davinci davinci
davinci_dm6467evm arm arm926ejs dm6467evm davinci davinci
+davinci_dm6467Tevm arm arm926ejs dm6467evm davinci davinci
davinci_dvevm arm arm926ejs dvevm davinci davinci
davinci_schmoogie arm arm926ejs schmoogie davinci davinci
davinci_sffsdr arm arm926ejs sffsdr davinci davinci
@@ -156,13 +158,14 @@
zmx25 arm arm926ejs zmx25 syteco mx25
imx27lite arm arm926ejs imx27lite logicpd mx27
magnesium arm arm926ejs imx27lite logicpd mx27
+m28evk arm arm926ejs - denx mx28
nhk8815 arm arm926ejs nhk8815 st nomadik
nhk8815_onenand arm arm926ejs nhk8815 st nomadik nhk8815:BOOT_ONENAND
omap5912osk arm arm926ejs - ti omap
edminiv2 arm arm926ejs - LaCie orion5x
dkb arm arm926ejs - Marvell pantheon
-integratorap_cm946es arm arm946es integrator armltd - integratorap
-integratorcp_cm946es arm arm946es integrator armltd - integratorcp
+integratorap_cm946es arm arm946es integrator armltd - integratorap:CM946ES
+integratorcp_cm946es arm arm946es integrator armltd - integratorcp:CM946ES
ca9x4_ct_vxp arm armv7 vexpress armltd
highbank arm armv7 highbank - highbank
am335x_evm arm armv7 am335x ti am33xx
@@ -193,6 +196,7 @@
devkit8000 arm armv7 devkit8000 timll omap3
omap4_panda arm armv7 panda ti omap4
omap4_sdp4430 arm armv7 sdp4430 ti omap4
+omap5_evm arm armv7 omap5_evm ti omap5
s5p_goni arm armv7 goni samsung s5pc1xx
smdkc100 arm armv7 smdkc100 samsung s5pc1xx
origen arm armv7 origen samsung s5pc2xx
@@ -213,8 +217,6 @@
cerf250 arm pxa
colibri_pxa270 arm pxa
cradle arm pxa
-csb226 arm pxa
-innokom arm pxa
lubbock arm pxa
palmld arm pxa
palmtc arm pxa
@@ -346,6 +348,7 @@
qi_lb60 mips xburst qi_lb60 qi
nios2-generic nios2 nios2 nios2-generic altera
adp-ag101 nds32 n1213 adp-ag101 AndesTech ag101
+adp-ag101p nds32 n1213 adp-ag101p AndesTech ag101
PCI5441 nios2 nios2 pci5441 psyent
PK1C20 nios2 nios2 pk1c20 psyent
EVB64260 powerpc 74xx_7xx evb64260 - - EVB64260
diff --git a/common/cmd_bedbug.c b/common/cmd_bedbug.c
index 2bd62e2..87b108f 100644
--- a/common/cmd_bedbug.c
+++ b/common/cmd_bedbug.c
@@ -15,7 +15,6 @@
extern void show_regs __P ((struct pt_regs *));
extern int run_command __P ((const char *, int));
-extern char console_buffer[];
ulong dis_last_addr = 0; /* Last address disassembled */
ulong dis_last_len = 20; /* Default disassembler length */
diff --git a/common/cmd_bmp.c b/common/cmd_bmp.c
index 23fc82f..682f395 100644
--- a/common/cmd_bmp.c
+++ b/common/cmd_bmp.c
@@ -237,9 +237,7 @@
}
#if defined(CONFIG_LCD)
- extern int lcd_display_bitmap (ulong, int, int);
-
- ret = lcd_display_bitmap ((unsigned long)bmp, x, y);
+ ret = lcd_display_bitmap((ulong)bmp, x, y);
#elif defined(CONFIG_VIDEO)
extern int video_display_bitmap (ulong, int, int);
diff --git a/common/cmd_dcr.c b/common/cmd_dcr.c
index 45fe66a..568e226 100644
--- a/common/cmd_dcr.c
+++ b/common/cmd_dcr.c
@@ -68,7 +68,6 @@
/* DCR's value */
int nbytes;
- extern char console_buffer[];
/* Validate arguments */
if (argc < 2)
diff --git a/common/cmd_fdc.c b/common/cmd_fdc.c
index 40d12f6..4fe410d 100644
--- a/common/cmd_fdc.c
+++ b/common/cmd_fdc.c
@@ -428,8 +428,8 @@
int fdc_read_data(unsigned char *buffer, unsigned long blocks,FDC_COMMAND_STRUCT *pCMD, FD_GEO_STRUCT *pFG)
{
/* first seek to start address */
- unsigned long len,lastblk,readblk,i,timeout,ii,offset;
- unsigned char pcn,c,retriesrw,retriescal;
+ unsigned long len,readblk,i,timeout,ii,offset;
+ unsigned char c,retriesrw,retriescal;
unsigned char *bufferw; /* working buffer */
int sect_size;
int flags;
@@ -442,18 +442,19 @@
offset=0;
if(fdc_seek(pCMD,pFG)==FALSE) {
stop_fdc_drive(pCMD);
- enable_interrupts();
+ if (flags)
+ enable_interrupts();
return FALSE;
}
if((pCMD->result[STATUS_0]&0x20)!=0x20) {
printf("Seek error Status: %02X\n",pCMD->result[STATUS_0]);
stop_fdc_drive(pCMD);
- enable_interrupts();
+ if (flags)
+ enable_interrupts();
return FALSE;
}
- pcn=pCMD->result[STATUS_PCN]; /* current track */
/* now determine the next seek point */
- lastblk=pCMD->blnr + blocks;
+ /* lastblk=pCMD->blnr + blocks; */
/* readblk=(pFG->head*pFG->sect)-(pCMD->blnr%(pFG->head*pFG->sect)); */
readblk=pFG->sect-(pCMD->blnr%pFG->sect);
PRINTF("1st nr of block possible read %ld start %ld\n",readblk,pCMD->blnr);
@@ -467,7 +468,8 @@
pCMD->cmd[COMMAND]=FDC_CMD_READ;
if(fdc_issue_cmd(pCMD,pFG)==FALSE) {
stop_fdc_drive(pCMD);
- enable_interrupts();
+ if (flags)
+ enable_interrupts();
return FALSE;
}
for (i=0;i<len;i++) {
@@ -488,14 +490,16 @@
if(retriesrw++>FDC_RW_RETRIES) {
if (retriescal++>FDC_CAL_RETRIES) {
stop_fdc_drive(pCMD);
- enable_interrupts();
+ if (flags)
+ enable_interrupts();
return FALSE;
}
else {
PRINTF(" trying to recalibrate Try %d\n",retriescal);
if(fdc_recalibrate(pCMD,pFG)==FALSE) {
stop_fdc_drive(pCMD);
- enable_interrupts();
+ if (flags)
+ enable_interrupts();
return FALSE;
}
retriesrw=0;
@@ -528,7 +532,8 @@
/* a seek is necessary */
if(fdc_seek(pCMD,pFG)==FALSE) {
stop_fdc_drive(pCMD);
- enable_interrupts();
+ if (flags)
+ enable_interrupts();
return FALSE;
}
if((pCMD->result[STATUS_0]&0x20)!=0x20) {
@@ -536,10 +541,10 @@
stop_fdc_drive(pCMD);
return FALSE;
}
- pcn=pCMD->result[STATUS_PCN]; /* current track */
}while(TRUE); /* start over */
stop_fdc_drive(pCMD); /* switch off drive */
- enable_interrupts();
+ if (flags)
+ enable_interrupts();
return TRUE;
}
diff --git a/common/cmd_i2c.c b/common/cmd_i2c.c
index a0c5291..e795139 100644
--- a/common/cmd_i2c.c
+++ b/common/cmd_i2c.c
@@ -449,7 +449,6 @@
ulong data;
int size = 1;
int nbytes;
- extern char console_buffer[];
if (argc != 3)
return cmd_usage(cmdtp);
diff --git a/common/cmd_mem.c b/common/cmd_mem.c
index 461ee19..f7e76d6 100644
--- a/common/cmd_mem.c
+++ b/common/cmd_mem.c
@@ -33,7 +33,6 @@
#include <dataflash.h>
#endif
#include <watchdog.h>
-#include <asm/io.h>
#ifdef CMD_MEM_DEBUG
#define PRINTF(fmt,args...) printf (fmt ,##args)
@@ -142,13 +141,9 @@
# endif
{
- ulong bytes = size * length;
- void *buf = map_physmem(addr, bytes, MAP_WRBACK);
-
/* Print the lines. */
- print_buffer(addr, buf, size, length, DISP_LINE_LEN / size);
- addr += bytes;
- unmap_physmem(buf, bytes);
+ print_buffer(addr, (void*)addr, size, length, DISP_LINE_LEN/size);
+ addr += size*length;
}
#endif
@@ -982,7 +977,6 @@
{
ulong addr, i;
int nbytes, size;
- extern char console_buffer[];
if (argc != 2)
return cmd_usage(cmdtp);
diff --git a/common/cmd_nvedit.c b/common/cmd_nvedit.c
index 396a171..7409a36 100644
--- a/common/cmd_nvedit.c
+++ b/common/cmd_nvedit.c
@@ -125,7 +125,7 @@
}
/* print whole list */
- len = hexport_r(&env_htab, '\n', &res, 0);
+ len = hexport_r(&env_htab, '\n', &res, 0, 0, NULL);
if (len > 0) {
puts(res);
@@ -165,7 +165,8 @@
}
#ifdef CONFIG_CMD_GREPENV
-static int do_env_grep (cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
+static int do_env_grep(cmd_tbl_t *cmdtp, int flag,
+ int argc, char * const argv[])
{
ENTRY *match;
unsigned char matched[env_htab.size / 8];
@@ -178,7 +179,7 @@
while (arg <= argc) {
idx = 0;
- while ((idx = hstrstr_r(argv[arg], idx, &match, &env_htab))) {
+ while (idx = hstrstr_r(argv[arg], idx, &match, &env_htab)) {
if (!(matched[idx / 8] & (1 << (idx & 7)))) {
puts(match->key);
puts("=");
@@ -199,8 +200,7 @@
* Set a new environment variable,
* or replace or delete an existing one.
*/
-
-int _do_env_set (int flag, int argc, char * const argv[])
+int _do_env_set(int flag, int argc, char * const argv[])
{
bd_t *bd = gd->bd;
int i, len;
@@ -211,7 +211,8 @@
name = argv[1];
if (strchr(name, '=')) {
- printf("## Error: illegal character '=' in variable name \"%s\"\n", name);
+ printf("## Error: illegal character '=' in variable name"
+ "\"%s\"\n", name);
return 1;
}
@@ -259,12 +260,12 @@
*/
if (ep) { /* variable exists */
#ifndef CONFIG_ENV_OVERWRITE
- if ((strcmp(name, "serial#") == 0) ||
- ((strcmp(name, "ethaddr") == 0)
+ if (strcmp(name, "serial#") == 0 ||
+ (strcmp(name, "ethaddr") == 0
#if defined(CONFIG_OVERWRITE_ETHADDR_ONCE) && defined(CONFIG_ETHADDR)
- && (strcmp(ep->data, MK_STR(CONFIG_ETHADDR)) != 0)
+ && strcmp(ep->data, MK_STR(CONFIG_ETHADDR)) != 0
#endif /* CONFIG_OVERWRITE_ETHADDR_ONCE && CONFIG_ETHADDR */
- ) ) {
+ )) {
printf("Can't overwrite \"%s\"\n", name);
return 1;
}
@@ -284,8 +285,8 @@
baudrate);
return 1;
}
- printf ("## Switch baudrate to %d bps and press ENTER ...\n",
- baudrate);
+ printf("## Switch baudrate to %d bps and"
+ "press ENTER ...\n", baudrate);
udelay(50000);
gd->baudrate = baudrate;
#if defined(CONFIG_PPC) || defined(CONFIG_MCF52x2)
@@ -294,15 +295,13 @@
serial_setbrg();
udelay(50000);
- for (;;) {
- if (getc() == '\r')
- break;
- }
+ while (getc() != '\r')
+ ;
}
}
/* Delete only ? */
- if ((argc < 3) || argv[2] == NULL) {
+ if (argc < 3 || argv[2] == NULL) {
int rc = hdelete_r(name, &env_htab);
return !rc;
}
@@ -323,13 +322,13 @@
while ((*s++ = *v++) != '\0')
;
- *(s-1) = ' ';
+ *(s - 1) = ' ';
}
if (s != value)
*--s = '\0';
- e.key = name;
- e.data = value;
+ e.key = name;
+ e.data = value;
hsearch_r(e, ENTER, &ep, &env_htab);
free(value);
if (!ep) {
@@ -342,7 +341,6 @@
* Some variables should be updated when the corresponding
* entry in the environment is changed
*/
-
if (strcmp(name, "ipaddr") == 0) {
char *s = argv[2]; /* always use only one arg */
char *e;
@@ -351,8 +349,9 @@
for (addr = 0, i = 0; i < 4; ++i) {
ulong val = s ? simple_strtoul(s, &e, 10) : 0;
addr <<= 8;
- addr |= (val & 0xFF);
- if (s) s = (*e) ? e+1 : e;
+ addr |= val & 0xFF;
+ if (s)
+ s = *e ? e + 1 : e;
}
bd->bi_ip_addr = htonl(addr);
return 0;
@@ -373,7 +372,7 @@
{
const char * const argv[4] = { "setenv", varname, varvalue, NULL };
- if ((varvalue == NULL) || (varvalue[0] == '\0'))
+ if (varvalue == NULL || varvalue[0] == '\0')
return _do_env_set(0, 2, (char * const *)argv);
else
return _do_env_set(0, 3, (char * const *)argv);
@@ -405,7 +404,7 @@
{
char str[17];
- sprintf(str, "%x", (uintptr_t)addr);
+ sprintf(str, "%lx", (uintptr_t)addr);
return setenv(varname, str);
}
@@ -423,7 +422,6 @@
#if defined(CONFIG_CMD_ASKENV)
int do_env_ask(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
{
- extern char console_buffer[CONFIG_SYS_CBSIZE];
char message[CONFIG_SYS_CBSIZE];
int size = CONFIG_SYS_CBSIZE - 1;
int i, len, pos;
@@ -453,9 +451,10 @@
if (pos)
message[pos++] = ' ';
- strcpy(message+pos, argv[i]);
+ strcpy(message + pos, argv[i]);
pos += strlen(argv[i]);
}
+
message[pos] = '\0';
size = simple_strtoul(argv[argc - 1], NULL, 10);
break;
@@ -516,20 +515,19 @@
*/
char *getenv(const char *name)
{
- if (gd->flags & GD_FLG_ENV_READY) { /* after import into hashtable */
+ if (gd->flags & GD_FLG_ENV_READY) { /* after import into hashtable */
ENTRY e, *ep;
WATCHDOG_RESET();
- e.key = name;
- e.data = NULL;
+ e.key = name;
+ e.data = NULL;
hsearch_r(e, FIND, &ep, &env_htab);
return ep ? ep->data : NULL;
}
/* restricted capabilities before import */
-
if (getenv_f(name, (char *)(gd->env_buf), sizeof(gd->env_buf)) > 0)
return (char *)(gd->env_buf);
@@ -543,7 +541,7 @@
{
int i, nxt;
- for (i = 0; env_get_char(i) != '\0'; i = nxt+1) {
+ for (i = 0; env_get_char(i) != '\0'; i = nxt + 1) {
int val, n;
for (nxt = i; env_get_char(nxt) != '\0'; ++nxt) {
@@ -557,7 +555,8 @@
/* found; copy out */
for (n = 0; n < len; ++n, ++buf) {
- if ((*buf = env_get_char(val++)) == '\0')
+ *buf = env_get_char(val++);
+ if (*buf == '\0')
return n;
}
@@ -569,6 +568,7 @@
return n;
}
+
return -1;
}
@@ -593,11 +593,8 @@
}
#if defined(CONFIG_CMD_SAVEENV) && !defined(CONFIG_ENV_IS_NOWHERE)
-
int do_env_save(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
{
- extern char *env_name_spec;
-
printf("Saving Environment to %s...\n", env_name_spec);
return saveenv() ? 1 : 0;
@@ -608,7 +605,6 @@
"save environment variables to persistent storage",
""
);
-
#endif
@@ -617,29 +613,32 @@
*
* s1 is either a simple 'name', or a 'name=value' pair.
* i2 is the environment index for a 'name2=value2' pair.
- * If the names match, return the index for the value2, else NULL.
+ * If the names match, return the index for the value2, else -1.
*/
-
int envmatch(uchar *s1, int i2)
{
while (*s1 == env_get_char(i2++))
if (*s1++ == '=')
return i2;
+
if (*s1 == '\0' && env_get_char(i2-1) == '=')
return i2;
+
return -1;
}
-static int do_env_default(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
+static int do_env_default(cmd_tbl_t *cmdtp, int flag,
+ int argc, char * const argv[])
{
- if ((argc != 2) || (strcmp(argv[1], "-f") != 0))
+ if (argc != 2 || strcmp(argv[1], "-f") != 0)
return cmd_usage(cmdtp);
set_default_env("## Resetting to default environment\n");
return 0;
}
-static int do_env_delete(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
+static int do_env_delete(cmd_tbl_t *cmdtp, int flag,
+ int argc, char * const argv[])
{
printf("Not implemented yet\n");
return 0;
@@ -647,7 +646,7 @@
#ifdef CONFIG_CMD_EXPORTENV
/*
- * env export [-t | -b | -c] addr [size]
+ * env export [-t | -b | -c] [-s size] addr [var ...]
* -t: export as text format; if size is given, data will be
* padded with '\0' bytes; if not, one terminating '\0'
* will be added (which is included in the "filesize"
@@ -657,8 +656,12 @@
* '\0', list end marked by double "\0\0")
* -c: export as checksum protected environment format as
* used for example by "saveenv" command
+ * -s size:
+ * size of output buffer
* addr: memory address where environment gets stored
- * size: size of output buffer
+ * var... List of variable names that get included into the
+ * export. Without arguments, the whole environment gets
+ * exported.
*
* With "-c" and size is NOT given, then the export command will
* format the data as currently used for the persistent storage,
@@ -687,11 +690,12 @@
*
* => env import -d -t ${backup_addr}
*/
-static int do_env_export(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
+static int do_env_export(cmd_tbl_t *cmdtp, int flag,
+ int argc, char * const argv[])
{
char buf[32];
char *addr, *cmd, *res;
- size_t size;
+ size_t size = 0;
ssize_t len;
env_t *envp;
char sep = '\n';
@@ -715,6 +719,11 @@
sep = '\0';
chk = 1;
break;
+ case 's': /* size given */
+ if (--argc <= 0)
+ return cmd_usage(cmdtp);
+ size = simple_strtoul(*++argv, NULL, 16);
+ goto NXTARG;
case 't': /* text format */
if (fmt++)
goto sep_err;
@@ -724,6 +733,7 @@
return cmd_usage(cmdtp);
}
}
+NXTARG: ;
}
if (argc < 1)
@@ -731,18 +741,16 @@
addr = (char *)simple_strtoul(argv[0], NULL, 16);
- if (argc == 2) {
- size = simple_strtoul(argv[1], NULL, 16);
+ if (size)
memset(addr, '\0', size);
- } else {
- size = 0;
- }
+
+ argc--;
+ argv++;
if (sep) { /* export as text file */
- len = hexport_r(&env_htab, sep, &addr, size);
+ len = hexport_r(&env_htab, sep, &addr, size, argc, argv);
if (len < 0) {
- error("Cannot export environment: errno = %d\n",
- errno);
+ error("Cannot export environment: errno = %d\n", errno);
return 1;
}
sprintf(buf, "%zX", (size_t)len);
@@ -758,15 +766,14 @@
else /* export as raw binary data */
res = addr;
- len = hexport_r(&env_htab, '\0', &res, ENV_SIZE);
+ len = hexport_r(&env_htab, '\0', &res, ENV_SIZE, argc, argv);
if (len < 0) {
- error("Cannot export environment: errno = %d\n",
- errno);
+ error("Cannot export environment: errno = %d\n", errno);
return 1;
}
if (chk) {
- envp->crc = crc32(0, envp->data, ENV_SIZE);
+ envp->crc = crc32(0, envp->data, ENV_SIZE);
#ifdef CONFIG_ENV_ADDR_REDUND
envp->flags = ACTIVE_FLAG;
#endif
@@ -777,8 +784,7 @@
return 0;
sep_err:
- printf("## %s: only one of \"-b\", \"-c\" or \"-t\" allowed\n",
- cmd);
+ printf("## %s: only one of \"-b\", \"-c\" or \"-t\" allowed\n", cmd);
return 1;
}
#endif
@@ -796,7 +802,8 @@
* size: length of input data; if missing, proper '\0'
* termination is mandatory
*/
-static int do_env_import(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
+static int do_env_import(cmd_tbl_t *cmdtp, int flag,
+ int argc, char * const argv[])
{
char *cmd, *addr;
char sep = '\n';
@@ -862,7 +869,7 @@
" - truncated\n", MAX_ENV_SIZE);
}
++size;
- printf("## Info: input data size = %zd = 0x%zX\n", size, size);
+ printf("## Info: input data size = %zu = 0x%zX\n", size, size);
}
if (chk) {
@@ -894,10 +901,6 @@
}
#endif
-#if defined(CONFIG_CMD_RUN)
-extern int do_run(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]);
-#endif
-
/*
* New command line interface: "env" command with subcommands
*/
@@ -965,7 +968,7 @@
#if defined(CONFIG_CMD_EDITENV)
"env edit name - edit environment variable\n"
#endif
- "env export [-t | -b | -c] addr [size] - export environment\n"
+ "env export [-t | -b | -c] [-s size] addr [var ...] - export environment\n"
#if defined(CONFIG_CMD_GREPENV)
"env grep string [...] - search environment\n"
#endif
diff --git a/common/cmd_pci.c b/common/cmd_pci.c
index 92631ea..1e477bc 100644
--- a/common/cmd_pci.c
+++ b/common/cmd_pci.c
@@ -341,7 +341,6 @@
{
ulong i;
int nbytes;
- extern char console_buffer[];
uint val4;
ushort val2;
u_char val1;
diff --git a/common/cmd_tsi148.c b/common/cmd_tsi148.c
index 6dc9dab..7f48ea2 100644
--- a/common/cmd_tsi148.c
+++ b/common/cmd_tsi148.c
@@ -53,7 +53,7 @@
int tsi148_init(void)
{
- int j, result, lastError = 0;
+ int j, result;
pci_dev_t busdevfn;
unsigned int val;
@@ -69,8 +69,7 @@
dev = malloc(sizeof(*dev));
if (NULL == dev) {
puts("Tsi148: No memory!\n");
- result = -1;
- goto break_20;
+ return -1;
}
memset(dev, 0, sizeof(*dev));
@@ -139,8 +138,6 @@
break_30:
free(dev);
dev = NULL;
- break_20:
- lastError = result;
return result;
}
diff --git a/common/cmd_universe.c b/common/cmd_universe.c
index a86a574..58384f3 100644
--- a/common/cmd_universe.c
+++ b/common/cmd_universe.c
@@ -46,7 +46,7 @@
int universe_init(void)
{
- int j, result, lastError = 0;
+ int j, result;
pci_dev_t busdevfn;
unsigned int val;
@@ -126,8 +126,6 @@
break_30:
free(dev);
break_20:
- lastError = result;
-
return result;
}
diff --git a/common/env_common.c b/common/env_common.c
index c7e9bea..8a71096 100644
--- a/common/env_common.c
+++ b/common/env_common.c
@@ -34,13 +34,6 @@
DECLARE_GLOBAL_DATA_PTR;
-extern env_t *env_ptr;
-
-extern void env_relocate_spec (void);
-extern uchar env_get_char_spec(int);
-
-static uchar env_get_char_init (int index);
-
/************************************************************************
* Default settings to be used when no valid environment is found
*/
@@ -94,7 +87,7 @@
"serverip=" MK_STR(CONFIG_SERVERIP) "\0"
#endif
#ifdef CONFIG_SYS_AUTOLOAD
- "autoload=" CONFIG_SYS_AUTOLOAD "\0"
+ "autoload=" CONFIG_SYS_AUTOLOAD "\0"
#endif
#ifdef CONFIG_PREBOOT
"preboot=" CONFIG_PREBOOT "\0"
@@ -117,13 +110,13 @@
#ifdef CONFIG_LOADADDR
"loadaddr=" MK_STR(CONFIG_LOADADDR) "\0"
#endif
-#ifdef CONFIG_CLOCKS_IN_MHZ
+#ifdef CONFIG_CLOCKS_IN_MHZ
"clocks_in_mhz=1\0"
#endif
#if defined(CONFIG_PCI_BOOTDELAY) && (CONFIG_PCI_BOOTDELAY > 0)
"pcidelay=" MK_STR(CONFIG_PCI_BOOTDELAY) "\0"
#endif
-#ifdef CONFIG_EXTRA_ENV_SETTINGS
+#ifdef CONFIG_EXTRA_ENV_SETTINGS
CONFIG_EXTRA_ENV_SETTINGS
#endif
"\0"
@@ -131,38 +124,30 @@
struct hsearch_data env_htab;
-static uchar env_get_char_init (int index)
+static uchar env_get_char_init(int index)
{
- uchar c;
-
/* if crc was bad, use the default environment */
if (gd->env_valid)
- c = env_get_char_spec(index);
+ return env_get_char_spec(index);
else
- c = default_environment[index];
-
- return (c);
+ return default_environment[index];
}
-uchar env_get_char_memory (int index)
+uchar env_get_char_memory(int index)
{
return *env_get_addr(index);
}
-uchar env_get_char (int index)
+uchar env_get_char(int index)
{
- uchar c;
-
/* if relocated to RAM */
if (gd->flags & GD_FLG_RELOC)
- c = env_get_char_memory(index);
+ return env_get_char_memory(index);
else
- c = env_get_char_init(index);
-
- return (c);
+ return env_get_char_init(index);
}
-const uchar *env_get_addr (int index)
+const uchar *env_get_addr(int index)
{
if (gd->env_valid)
return (uchar *)(gd->env_addr + index);
@@ -181,7 +166,7 @@
if (*s == '!') {
printf("*** Warning - %s, "
"using default environment\n\n",
- s+1);
+ s + 1);
} else {
puts(s);
}
@@ -190,9 +175,9 @@
}
if (himport_r(&env_htab, (char *)default_environment,
- sizeof(default_environment), '\0', 0) == 0) {
+ sizeof(default_environment), '\0', 0) == 0)
error("Environment import failed: errno = %d\n", errno);
- }
+
gd->flags |= GD_FLG_ENV_READY;
}
@@ -227,22 +212,20 @@
return 0;
}
-void env_relocate (void)
+void env_relocate(void)
{
#if defined(CONFIG_NEEDS_MANUAL_RELOC)
- extern void env_reloc(void);
-
env_reloc();
#endif
if (gd->env_valid == 0) {
#if defined(CONFIG_ENV_IS_NOWHERE) /* Environment not changable */
set_default_env(NULL);
#else
- show_boot_progress (-60);
+ show_boot_progress(-60);
set_default_env("!bad CRC");
#endif
} else {
- env_relocate_spec ();
+ env_relocate_spec();
}
}
@@ -272,6 +255,7 @@
if (idx)
cmdv[found++] = "...";
+
cmdv[found] = NULL;
return found;
}
diff --git a/common/env_dataflash.c b/common/env_dataflash.c
index 1d57079..3c5af37 100644
--- a/common/env_dataflash.c
+++ b/common/env_dataflash.c
@@ -27,25 +27,17 @@
DECLARE_GLOBAL_DATA_PTR;
-env_t *env_ptr = NULL;
+env_t *env_ptr;
-char * env_name_spec = "dataflash";
-
-extern int read_dataflash(unsigned long addr, unsigned long size,
- char *result);
-extern int write_dataflash(unsigned long addr_dest,
- unsigned long addr_src, unsigned long size);
-extern int AT91F_DataflashInit(void);
-
-extern uchar default_environment[];
+char *env_name_spec = "dataflash";
uchar env_get_char_spec(int index)
{
uchar c;
- read_dataflash(CONFIG_ENV_ADDR + index + offsetof(env_t,data),
+ read_dataflash(CONFIG_ENV_ADDR + index + offsetof(env_t, data),
1, (char *)&c);
- return (c);
+ return c;
}
void env_relocate_spec(void)
@@ -68,12 +60,12 @@
char *res;
res = (char *)&env_new.data;
- len = hexport_r(&env_htab, '\0', &res, ENV_SIZE);
+ len = hexport_r(&env_htab, '\0', &res, ENV_SIZE, 0, NULL);
if (len < 0) {
error("Cannot export environment: errno = %d\n", errno);
return 1;
}
- env_new.crc = crc32(0, env_new.data, ENV_SIZE);
+ env_new.crc = crc32(0, env_new.data, ENV_SIZE);
return write_dataflash(CONFIG_ENV_ADDR,
(unsigned long)&env_new,
@@ -88,7 +80,7 @@
*/
int env_init(void)
{
- ulong crc, len, new;
+ ulong crc, len = ENV_SIZE, new = 0;
unsigned off;
uchar buf[64];
@@ -101,25 +93,23 @@
read_dataflash(CONFIG_ENV_ADDR + offsetof(env_t, crc),
sizeof(ulong), (char *)&crc);
- new = 0;
- len = ENV_SIZE;
- off = offsetof(env_t,data);
+ off = offsetof(env_t, data);
while (len > 0) {
int n = (len > sizeof(buf)) ? sizeof(buf) : len;
read_dataflash(CONFIG_ENV_ADDR + off, n, (char *)buf);
- new = crc32 (new, buf, n);
+ new = crc32(new, buf, n);
len -= n;
off += n;
}
if (crc == new) {
- gd->env_addr = offsetof(env_t,data);
- gd->env_valid = 1;
+ gd->env_addr = offsetof(env_t, data);
+ gd->env_valid = 1;
} else {
- gd->env_addr = (ulong)&default_environment[0];
- gd->env_valid = 0;
+ gd->env_addr = (ulong)&default_environment[0];
+ gd->env_valid = 0;
}
return 0;
diff --git a/common/env_eeprom.c b/common/env_eeprom.c
index 0a179ad..b66bba2 100644
--- a/common/env_eeprom.c
+++ b/common/env_eeprom.c
@@ -37,13 +37,13 @@
DECLARE_GLOBAL_DATA_PTR;
-env_t *env_ptr = NULL;
+env_t *env_ptr;
char *env_name_spec = "EEPROM";
int env_eeprom_bus = -1;
static int eeprom_bus_read(unsigned dev_addr, unsigned offset,
- uchar *buffer, unsigned cnt)
+ uchar *buffer, unsigned cnt)
{
int rcode;
#if defined(CONFIG_I2C_ENV_EEPROM_BUS)
@@ -57,7 +57,7 @@
if (dev != NULL)
env_eeprom_bus = dev->busid;
else
- printf ("error adding env eeprom bus.\n");
+ printf("error adding env eeprom bus.\n");
}
if (old_bus != env_eeprom_bus) {
i2c_set_bus_num(env_eeprom_bus);
@@ -69,7 +69,7 @@
}
#endif
- rcode = eeprom_read (dev_addr, offset, buffer, cnt);
+ rcode = eeprom_read(dev_addr, offset, buffer, cnt);
#if defined(CONFIG_I2C_ENV_EEPROM_BUS)
if (old_bus != env_eeprom_bus)
@@ -79,7 +79,7 @@
}
static int eeprom_bus_write(unsigned dev_addr, unsigned offset,
- uchar *buffer, unsigned cnt)
+ uchar *buffer, unsigned cnt)
{
int rcode;
#if defined(CONFIG_I2C_ENV_EEPROM_BUS)
@@ -94,24 +94,22 @@
return rcode;
}
-uchar env_get_char_spec (int index)
+uchar env_get_char_spec(int index)
{
uchar c;
- unsigned int off;
- off = CONFIG_ENV_OFFSET;
+ unsigned int off = CONFIG_ENV_OFFSET;
#ifdef CONFIG_ENV_OFFSET_REDUND
if (gd->env_valid == 2)
off = CONFIG_ENV_OFFSET_REDUND;
#endif
eeprom_bus_read(CONFIG_SYS_DEF_EEPROM_ADDR,
- off + index + offsetof(env_t,data),
- &c, 1);
+ off + index + offsetof(env_t, data), &c, 1);
- return (c);
+ return c;
}
-void env_relocate_spec (void)
+void env_relocate_spec(void)
{
char buf[CONFIG_ENV_SIZE];
unsigned int off = CONFIG_ENV_OFFSET;
@@ -121,9 +119,7 @@
off = CONFIG_ENV_OFFSET_REDUND;
#endif
eeprom_bus_read(CONFIG_SYS_DEF_EEPROM_ADDR,
- off,
- (uchar *)buf,
- CONFIG_ENV_SIZE);
+ off, (uchar *)buf, CONFIG_ENV_SIZE);
env_import(buf, 1);
}
@@ -133,17 +129,17 @@
env_t env_new;
ssize_t len;
char *res;
- int rc;
- unsigned int off = CONFIG_ENV_OFFSET;
+ int rc;
+ unsigned int off = CONFIG_ENV_OFFSET;
#ifdef CONFIG_ENV_OFFSET_REDUND
- unsigned int off_red = CONFIG_ENV_OFFSET_REDUND;
- char flag_obsolete = OBSOLETE_FLAG;
+ unsigned int off_red = CONFIG_ENV_OFFSET_REDUND;
+ char flag_obsolete = OBSOLETE_FLAG;
#endif
BUG_ON(env_ptr != NULL);
res = (char *)&env_new.data;
- len = hexport_r(&env_htab, '\0', &res, ENV_SIZE);
+ len = hexport_r(&env_htab, '\0', &res, ENV_SIZE, 0, NULL);
if (len < 0) {
error("Cannot export environment: errno = %d\n", errno);
return 1;
@@ -152,32 +148,28 @@
#ifdef CONFIG_ENV_OFFSET_REDUND
if (gd->env_valid == 1) {
- off = CONFIG_ENV_OFFSET_REDUND;
- off_red = CONFIG_ENV_OFFSET;
+ off = CONFIG_ENV_OFFSET_REDUND;
+ off_red = CONFIG_ENV_OFFSET;
}
env_new.flags = ACTIVE_FLAG;
#endif
rc = eeprom_bus_write(CONFIG_SYS_DEF_EEPROM_ADDR,
- off,
- (uchar *)&env_new,
- CONFIG_ENV_SIZE);
+ off, (uchar *)&env_new, CONFIG_ENV_SIZE);
#ifdef CONFIG_ENV_OFFSET_REDUND
if (rc == 0) {
eeprom_bus_write(CONFIG_SYS_DEF_EEPROM_ADDR,
- off_red + offsetof(env_t,flags),
- (uchar *)&flag_obsolete,
- 1);
+ off_red + offsetof(env_t, flags),
+ (uchar *)&flag_obsolete, 1);
+
if (gd->env_valid == 1)
gd->env_valid = 2;
else
gd->env_valid = 1;
-
}
#endif
-
return rc;
}
@@ -187,17 +179,13 @@
* We are still running from ROM, so data use is limited.
* Use a (moderately small) buffer on the stack
*/
-
#ifdef CONFIG_ENV_OFFSET_REDUND
int env_init(void)
{
- ulong len;
- ulong crc[2], crc_tmp;
+ ulong len, crc[2], crc_tmp;
unsigned int off, off_env[2];
- uchar buf[64];
- int crc_ok[2] = {0,0};
- unsigned char flags[2];
- int i;
+ uchar buf[64], flags[2];
+ int i, crc_ok[2] = {0, 0};
eeprom_init(); /* prepare for EEPROM read/write */
@@ -207,39 +195,39 @@
for (i = 0; i < 2; i++) {
/* read CRC */
eeprom_bus_read(CONFIG_SYS_DEF_EEPROM_ADDR,
- off_env[i] + offsetof(env_t,crc),
- (uchar *)&crc[i], sizeof(ulong));
+ off_env[i] + offsetof(env_t, crc),
+ (uchar *)&crc[i], sizeof(ulong));
/* read FLAGS */
eeprom_bus_read(CONFIG_SYS_DEF_EEPROM_ADDR,
- off_env[i] + offsetof(env_t,flags),
- (uchar *)&flags[i], sizeof(uchar));
+ off_env[i] + offsetof(env_t, flags),
+ (uchar *)&flags[i], sizeof(uchar));
crc_tmp = 0;
len = ENV_SIZE;
- off = off_env[i] + offsetof(env_t,data);
+ off = off_env[i] + offsetof(env_t, data);
while (len > 0) {
int n = (len > sizeof(buf)) ? sizeof(buf) : len;
eeprom_bus_read(CONFIG_SYS_DEF_EEPROM_ADDR, off,
- buf, n);
+ buf, n);
crc_tmp = crc32(crc_tmp, buf, n);
len -= n;
off += n;
}
+
if (crc_tmp == crc[i])
crc_ok[i] = 1;
}
if (!crc_ok[0] && !crc_ok[1]) {
- gd->env_addr = 0;
- gd->env_valid = 0;
+ gd->env_addr = 0;
+ gd->env_valid = 0;
return 0;
} else if (crc_ok[0] && !crc_ok[1]) {
gd->env_valid = 1;
- }
- else if (!crc_ok[0] && crc_ok[1]) {
+ } else if (!crc_ok[0] && crc_ok[1]) {
gd->env_valid = 2;
} else {
/* both ok - check serial */
@@ -249,18 +237,18 @@
gd->env_valid = 2;
else if (flags[0] == 0xFF && flags[1] == 0)
gd->env_valid = 2;
- else if(flags[1] == 0xFF && flags[0] == 0)
+ else if (flags[1] == 0xFF && flags[0] == 0)
gd->env_valid = 1;
else /* flags are equal - almost impossible */
gd->env_valid = 1;
}
if (gd->env_valid == 2)
- gd->env_addr = off_env[1] + offsetof(env_t,data);
+ gd->env_addr = off_env[1] + offsetof(env_t, data);
else if (gd->env_valid == 1)
- gd->env_addr = off_env[0] + offsetof(env_t,data);
+ gd->env_addr = off_env[0] + offsetof(env_t, data);
- return (0);
+ return 0;
}
#else
int env_init(void)
@@ -273,12 +261,12 @@
/* read old CRC */
eeprom_bus_read(CONFIG_SYS_DEF_EEPROM_ADDR,
- CONFIG_ENV_OFFSET+offsetof(env_t,crc),
- (uchar *)&crc, sizeof(ulong));
+ CONFIG_ENV_OFFSET + offsetof(env_t, crc),
+ (uchar *)&crc, sizeof(ulong));
new = 0;
len = ENV_SIZE;
- off = offsetof(env_t,data);
+ off = offsetof(env_t, data);
while (len > 0) {
int n = (len > sizeof(buf)) ? sizeof(buf) : len;
@@ -291,13 +279,13 @@
}
if (crc == new) {
- gd->env_addr = offsetof(env_t,data);
- gd->env_valid = 1;
+ gd->env_addr = offsetof(env_t, data);
+ gd->env_valid = 1;
} else {
- gd->env_addr = 0;
- gd->env_valid = 0;
+ gd->env_addr = 0;
+ gd->env_valid = 0;
}
- return (0);
+ return 0;
}
#endif
diff --git a/common/env_embedded.c b/common/env_embedded.c
index 6ce1307..80fb29d 100644
--- a/common/env_embedded.c
+++ b/common/env_embedded.c
@@ -22,17 +22,14 @@
*/
#ifndef __ASSEMBLY__
-#define __ASSEMBLY__ /* Dirty trick to get only #defines */
+#define __ASSEMBLY__ /* Dirty trick to get only #defines */
#endif
-#define __ASM_STUB_PROCESSOR_H__ /* don't include asm/processor. */
+#define __ASM_STUB_PROCESSOR_H__ /* don't include asm/processor. */
#include <config.h>
#undef __ASSEMBLY__
#include <environment.h>
-/*
- * Handle HOSTS that have prepended
- * crap on symbol names, not TARGETS.
- */
+/* Handle HOSTS that have prepended crap on symbol names, not TARGETS. */
#if defined(__APPLE__)
/* Leading underscore on symbols */
# define SYM_CHAR "_"
@@ -52,34 +49,36 @@
* U-Boot itself.
*/
#if (defined(CONFIG_SYS_USE_PPCENV) || defined(CONFIG_NAND_U_BOOT)) && \
- defined(ENV_CRC) /* Environment embedded in U-Boot .ppcenv section */
+ defined(ENV_CRC) /* Environment embedded in U-Boot .ppcenv section */
/* XXX - This only works with GNU C */
-# define __PPCENV__ __attribute__ ((section(".ppcenv")))
-# define __PPCTEXT__ __attribute__ ((section(".text")))
+# define __PPCENV__ __attribute__ ((section(".ppcenv")))
+# define __PPCTEXT__ __attribute__ ((section(".text")))
#elif defined(USE_HOSTCC) /* Native for 'tools/envcrc' */
-# define __PPCENV__ /*XXX DO_NOT_DEL_THIS_COMMENT*/
-# define __PPCTEXT__ /*XXX DO_NOT_DEL_THIS_COMMENT*/
+# define __PPCENV__ /*XXX DO_NOT_DEL_THIS_COMMENT*/
+# define __PPCTEXT__ /*XXX DO_NOT_DEL_THIS_COMMENT*/
#else /* Environment is embedded in U-Boot's .text section */
/* XXX - This only works with GNU C */
-# define __PPCENV__ __attribute__ ((section(".text")))
-# define __PPCTEXT__ __attribute__ ((section(".text")))
+# define __PPCENV__ __attribute__ ((section(".text")))
+# define __PPCTEXT__ __attribute__ ((section(".text")))
#endif
/*
* Macros to generate global absolutes.
*/
#if defined(__bfin__)
-# define GEN_SET_VALUE(name, value) asm (".set " GEN_SYMNAME(name) ", " GEN_VALUE(value))
+# define GEN_SET_VALUE(name, value) \
+ asm(".set " GEN_SYMNAME(name) ", " GEN_VALUE(value))
#else
-# define GEN_SET_VALUE(name, value) asm (GEN_SYMNAME(name) " = " GEN_VALUE(value))
+# define GEN_SET_VALUE(name, value) \
+ asm(GEN_SYMNAME(name) " = " GEN_VALUE(value))
#endif
-#define GEN_SYMNAME(str) SYM_CHAR #str
-#define GEN_VALUE(str) #str
-#define GEN_ABS(name, value) \
- asm (".globl " GEN_SYMNAME(name)); \
- GEN_SET_VALUE(name, value)
+#define GEN_SYMNAME(str) SYM_CHAR #str
+#define GEN_VALUE(str) #str
+#define GEN_ABS(name, value) \
+ asm(".globl " GEN_SYMNAME(name)); \
+ GEN_SET_VALUE(name, value)
/*
* Macros to transform values
@@ -93,7 +92,7 @@
* computed CRC. Otherwise define it as ~0.
*/
#if !defined(ENV_CRC)
-# define ENV_CRC ~0
+# define ENV_CRC (~0)
#endif
env_t environment __PPCENV__ = {
@@ -151,7 +150,7 @@
"serverip=" MK_STR(CONFIG_SERVERIP) "\0"
#endif
#ifdef CONFIG_SYS_AUTOLOAD
- "autoload=" CONFIG_SYS_AUTOLOAD "\0"
+ "autoload=" CONFIG_SYS_AUTOLOAD "\0"
#endif
#ifdef CONFIG_ROOTPATH
"rootpath=" CONFIG_ROOTPATH "\0"
@@ -180,7 +179,7 @@
#if defined(CONFIG_PCI_BOOTDELAY) && (CONFIG_PCI_BOOTDELAY > 0)
"pcidelay=" MK_STR(CONFIG_PCI_BOOTDELAY) "\0"
#endif
-#ifdef CONFIG_EXTRA_ENV_SETTINGS
+#ifdef CONFIG_EXTRA_ENV_SETTINGS
CONFIG_EXTRA_ENV_SETTINGS
#endif
"\0" /* Term. env_t.data with 2 NULs */
diff --git a/common/env_flash.c b/common/env_flash.c
index 50ca4ffa..a99f850 100644
--- a/common/env_flash.c
+++ b/common/env_flash.c
@@ -39,19 +39,18 @@
#if defined(CONFIG_CMD_SAVEENV) && defined(CONFIG_CMD_FLASH)
#define CMD_SAVEENV
#elif defined(CONFIG_ENV_ADDR_REDUND)
-#error Cannot use CONFIG_ENV_ADDR_REDUND without CONFIG_CMD_SAVEENV & CONFIG_CMD_FLASH
+#error CONFIG_ENV_ADDR_REDUND must have CONFIG_CMD_SAVEENV & CONFIG_CMD_FLASH
#endif
-#if defined(CONFIG_ENV_SIZE_REDUND) && (CONFIG_ENV_SIZE_REDUND < CONFIG_ENV_SIZE)
+#if defined(CONFIG_ENV_SIZE_REDUND) && \
+ (CONFIG_ENV_SIZE_REDUND < CONFIG_ENV_SIZE)
#error CONFIG_ENV_SIZE_REDUND should not be less then CONFIG_ENV_SIZE
#endif
-char * env_name_spec = "Flash";
+char *env_name_spec = "Flash";
#ifdef ENV_IS_EMBEDDED
-
-extern uchar environment[];
-env_t *env_ptr = (env_t *)(&environment[0]);
+env_t *env_ptr = &environment;
static env_t *flash_addr = (env_t *)CONFIG_ENV_ADDR;
@@ -59,7 +58,6 @@
env_t *env_ptr = (env_t *)CONFIG_ENV_ADDR;
static env_t *flash_addr = (env_t *)CONFIG_ENV_ADDR;
-
#endif /* ENV_IS_EMBEDDED */
#if defined(CMD_SAVEENV) || defined(CONFIG_ENV_ADDR_REDUND)
@@ -74,17 +72,14 @@
static ulong end_addr_new = CONFIG_ENV_ADDR_REDUND + CONFIG_ENV_SECT_SIZE - 1;
#endif /* CONFIG_ENV_ADDR_REDUND */
-extern const uchar default_environment[];
-
uchar env_get_char_spec(int index)
{
- return (*((uchar *)(gd->env_addr + index)));
+ return *((uchar *)(gd->env_addr + index));
}
#ifdef CONFIG_ENV_ADDR_REDUND
-
-int env_init(void)
+int env_init(void)
{
int crc1_ok = 0, crc2_ok = 0;
@@ -95,33 +90,34 @@
ulong addr1 = (ulong)&(flash_addr->data);
ulong addr2 = (ulong)&(flash_addr_new->data);
- crc1_ok = (crc32(0, flash_addr->data, ENV_SIZE) == flash_addr->crc);
- crc2_ok = (crc32(0, flash_addr_new->data, ENV_SIZE) == flash_addr_new->crc);
+ crc1_ok = crc32(0, flash_addr->data, ENV_SIZE) == flash_addr->crc;
+ crc2_ok =
+ crc32(0, flash_addr_new->data, ENV_SIZE) == flash_addr_new->crc;
- if (crc1_ok && ! crc2_ok) {
- gd->env_addr = addr1;
- gd->env_valid = 1;
- } else if (! crc1_ok && crc2_ok) {
- gd->env_addr = addr2;
- gd->env_valid = 1;
- } else if (! crc1_ok && ! crc2_ok) {
- gd->env_addr = addr_default;
- gd->env_valid = 0;
+ if (crc1_ok && !crc2_ok) {
+ gd->env_addr = addr1;
+ gd->env_valid = 1;
+ } else if (!crc1_ok && crc2_ok) {
+ gd->env_addr = addr2;
+ gd->env_valid = 1;
+ } else if (!crc1_ok && !crc2_ok) {
+ gd->env_addr = addr_default;
+ gd->env_valid = 0;
} else if (flag1 == ACTIVE_FLAG && flag2 == OBSOLETE_FLAG) {
- gd->env_addr = addr1;
- gd->env_valid = 1;
+ gd->env_addr = addr1;
+ gd->env_valid = 1;
} else if (flag1 == OBSOLETE_FLAG && flag2 == ACTIVE_FLAG) {
- gd->env_addr = addr2;
- gd->env_valid = 1;
+ gd->env_addr = addr2;
+ gd->env_valid = 1;
} else if (flag1 == flag2) {
- gd->env_addr = addr1;
- gd->env_valid = 2;
+ gd->env_addr = addr1;
+ gd->env_valid = 2;
} else if (flag1 == 0xFF) {
- gd->env_addr = addr1;
- gd->env_valid = 2;
+ gd->env_addr = addr1;
+ gd->env_valid = 2;
} else if (flag2 == 0xFF) {
- gd->env_addr = addr2;
- gd->env_valid = 2;
+ gd->env_addr = addr2;
+ gd->env_valid = 2;
}
return 0;
@@ -132,74 +128,70 @@
{
env_t env_new;
ssize_t len;
- char *saved_data = NULL;
- char *res;
- int rc = 1;
+ char *res, *saved_data = NULL;
char flag = OBSOLETE_FLAG, new_flag = ACTIVE_FLAG;
+ int rc = 1;
#if CONFIG_ENV_SECT_SIZE > CONFIG_ENV_SIZE
ulong up_data = 0;
#endif
- debug("Protect off %08lX ... %08lX\n",
- (ulong)flash_addr, end_addr);
+ debug("Protect off %08lX ... %08lX\n", (ulong)flash_addr, end_addr);
- if (flash_sect_protect(0, (ulong)flash_addr, end_addr)) {
+ if (flash_sect_protect(0, (ulong)flash_addr, end_addr))
goto done;
- }
debug("Protect off %08lX ... %08lX\n",
(ulong)flash_addr_new, end_addr_new);
- if (flash_sect_protect(0, (ulong)flash_addr_new, end_addr_new)) {
+ if (flash_sect_protect(0, (ulong)flash_addr_new, end_addr_new))
goto done;
- }
res = (char *)&env_new.data;
- len = hexport_r(&env_htab, '\0', &res, ENV_SIZE);
+ len = hexport_r(&env_htab, '\0', &res, ENV_SIZE, 0, NULL);
if (len < 0) {
error("Cannot export environment: errno = %d\n", errno);
goto done;
}
- env_new.crc = crc32(0, env_new.data, ENV_SIZE);
- env_new.flags = new_flag;
+ env_new.crc = crc32(0, env_new.data, ENV_SIZE);
+ env_new.flags = new_flag;
#if CONFIG_ENV_SECT_SIZE > CONFIG_ENV_SIZE
- up_data = (end_addr_new + 1 - ((long)flash_addr_new + CONFIG_ENV_SIZE));
+ up_data = end_addr_new + 1 - ((long)flash_addr_new + CONFIG_ENV_SIZE);
debug("Data to save 0x%lX\n", up_data);
if (up_data) {
- if ((saved_data = malloc(up_data)) == NULL) {
+ saved_data = malloc(up_data);
+ if (saved_data == NULL) {
printf("Unable to save the rest of sector (%ld)\n",
up_data);
goto done;
}
memcpy(saved_data,
- (void *)((long)flash_addr_new + CONFIG_ENV_SIZE), up_data);
+ (void *)((long)flash_addr_new + CONFIG_ENV_SIZE),
+ up_data);
debug("Data (start 0x%lX, len 0x%lX) saved at 0x%p\n",
(long)flash_addr_new + CONFIG_ENV_SIZE,
up_data, saved_data);
}
#endif
puts("Erasing Flash...");
- debug(" %08lX ... %08lX ...",
- (ulong)flash_addr_new, end_addr_new);
+ debug(" %08lX ... %08lX ...", (ulong)flash_addr_new, end_addr_new);
- if (flash_sect_erase((ulong)flash_addr_new, end_addr_new)) {
+ if (flash_sect_erase((ulong)flash_addr_new, end_addr_new))
goto done;
- }
puts("Writing to Flash... ");
debug(" %08lX ... %08lX ...",
(ulong)&(flash_addr_new->data),
- sizeof(env_ptr->data)+(ulong)&(flash_addr_new->data));
- if ((rc = flash_write((char *)&env_new,
- (ulong)flash_addr_new,
- sizeof(env_new))) ||
- (rc = flash_write(&flag,
- (ulong)&(flash_addr->flags),
- sizeof(flash_addr->flags))) ) {
- flash_perror(rc);
- goto done;
- }
+ sizeof(env_ptr->data) + (ulong)&(flash_addr_new->data));
+ rc = flash_write((char *)&env_new, (ulong)flash_addr_new,
+ sizeof(env_new));
+ if (rc)
+ goto perror;
+
+ rc = flash_write(&flag, (ulong)&(flash_addr->flags),
+ sizeof(flash_addr->flags));
+ if (rc)
+ goto perror;
#if CONFIG_ENV_SECT_SIZE > CONFIG_ENV_SIZE
if (up_data) { /* restore the rest of sector */
@@ -207,16 +199,14 @@
(long)flash_addr_new + CONFIG_ENV_SIZE, up_data);
if (flash_write(saved_data,
(long)flash_addr_new + CONFIG_ENV_SIZE,
- up_data)) {
- flash_perror(rc);
- goto done;
- }
+ up_data))
+ goto perror;
}
#endif
puts("done\n");
{
- env_t * etmp = flash_addr;
+ env_t *etmp = flash_addr;
ulong ltmp = end_addr;
flash_addr = flash_addr_new;
@@ -227,12 +217,15 @@
}
rc = 0;
+ goto done;
+perror:
+ flash_perror(rc);
done:
if (saved_data)
free(saved_data);
/* try to re-protect */
- (void) flash_sect_protect(1, (ulong)flash_addr, end_addr);
- (void) flash_sect_protect(1, (ulong)flash_addr_new, end_addr_new);
+ flash_sect_protect(1, (ulong)flash_addr, end_addr);
+ flash_sect_protect(1, (ulong)flash_addr_new, end_addr_new);
return rc;
}
@@ -240,35 +233,34 @@
#else /* ! CONFIG_ENV_ADDR_REDUND */
-int env_init(void)
+int env_init(void)
{
if (crc32(0, env_ptr->data, ENV_SIZE) == env_ptr->crc) {
- gd->env_addr = (ulong)&(env_ptr->data);
- gd->env_valid = 1;
- return(0);
+ gd->env_addr = (ulong)&(env_ptr->data);
+ gd->env_valid = 1;
+ return 0;
}
- gd->env_addr = (ulong)&default_environment[0];
- gd->env_valid = 0;
+ gd->env_addr = (ulong)&default_environment[0];
+ gd->env_valid = 0;
return 0;
}
#ifdef CMD_SAVEENV
-
int saveenv(void)
{
env_t env_new;
ssize_t len;
int rc = 1;
- char *res;
- char *saved_data = NULL;
+ char *res, *saved_data = NULL;
#if CONFIG_ENV_SECT_SIZE > CONFIG_ENV_SIZE
ulong up_data = 0;
- up_data = (end_addr + 1 - ((long)flash_addr + CONFIG_ENV_SIZE));
+ up_data = end_addr + 1 - ((long)flash_addr + CONFIG_ENV_SIZE);
debug("Data to save 0x%lx\n", up_data);
if (up_data) {
- if ((saved_data = malloc(up_data)) == NULL) {
+ saved_data = malloc(up_data);
+ if (saved_data == NULL) {
printf("Unable to save the rest of sector (%ld)\n",
up_data);
goto done;
@@ -282,14 +274,13 @@
}
#endif /* CONFIG_ENV_SECT_SIZE */
- debug("Protect off %08lX ... %08lX\n",
- (ulong)flash_addr, end_addr);
+ debug("Protect off %08lX ... %08lX\n", (ulong)flash_addr, end_addr);
if (flash_sect_protect(0, (long)flash_addr, end_addr))
goto done;
res = (char *)&env_new.data;
- len = hexport_r(&env_htab, '\0', &res, ENV_SIZE);
+ len = hexport_r(&env_htab, '\0', &res, ENV_SIZE, 0, NULL);
if (len < 0) {
error("Cannot export environment: errno = %d\n", errno);
goto done;
@@ -302,32 +293,31 @@
puts("Writing to Flash... ");
rc = flash_write((char *)&env_new, (long)flash_addr, CONFIG_ENV_SIZE);
- if (rc != 0) {
- flash_perror(rc);
- goto done;
- }
+ if (rc != 0)
+ goto perror;
+
#if CONFIG_ENV_SECT_SIZE > CONFIG_ENV_SIZE
if (up_data) { /* restore the rest of sector */
debug("Restoring the rest of data to 0x%lx len 0x%lx\n",
(ulong)flash_addr + CONFIG_ENV_SIZE, up_data);
if (flash_write(saved_data,
(long)flash_addr + CONFIG_ENV_SIZE,
- up_data)) {
- flash_perror(rc);
- goto done;
- }
+ up_data))
+ goto perror;
}
#endif
puts("done\n");
rc = 0;
+ goto done;
+perror:
+ flash_perror(rc);
done:
if (saved_data)
free(saved_data);
/* try to re-protect */
- (void) flash_sect_protect(1, (long)flash_addr, end_addr);
+ flash_sect_protect(1, (long)flash_addr, end_addr);
return rc;
}
-
#endif /* CMD_SAVEENV */
#endif /* CONFIG_ENV_ADDR_REDUND */
@@ -347,8 +337,7 @@
}
if (flash_addr_new->flags != OBSOLETE_FLAG &&
- crc32(0, flash_addr_new->data, ENV_SIZE) ==
- flash_addr_new->crc) {
+ crc32(0, flash_addr_new->data, ENV_SIZE) == flash_addr_new->crc) {
char flag = OBSOLETE_FLAG;
gd->env_valid = 2;
@@ -372,8 +361,8 @@
}
if (gd->env_valid == 2)
- puts ("*** Warning - some problems detected "
- "reading environment; recovered successfully\n\n");
+ puts("*** Warning - some problems detected "
+ "reading environment; recovered successfully\n\n");
#endif /* CONFIG_ENV_ADDR_REDUND */
env_import((char *)flash_addr, 1);
diff --git a/common/env_mgdisk.c b/common/env_mgdisk.c
index a69923b..5dd92e7 100644
--- a/common/env_mgdisk.c
+++ b/common/env_mgdisk.c
@@ -27,18 +27,15 @@
#include <linux/stddef.h>
#include <mg_disk.h>
-/* references to names in env_common.c */
-extern uchar default_environment[];
-
char *env_name_spec = "MG_DISK";
-env_t *env_ptr = 0;
+env_t *env_ptr;
DECLARE_GLOBAL_DATA_PTR;
uchar env_get_char_spec(int index)
{
- return (*((uchar *)(gd->env_addr + index)));
+ return *((uchar *)(gd->env_addr + index));
}
void env_relocate_spec(void)
diff --git a/common/env_mmc.c b/common/env_mmc.c
index 83f40f4..8441c77 100644
--- a/common/env_mmc.c
+++ b/common/env_mmc.c
@@ -32,23 +32,14 @@
#include <search.h>
#include <errno.h>
-/* references to names in env_common.c */
-extern uchar default_environment[];
-
char *env_name_spec = "MMC";
#ifdef ENV_IS_EMBEDDED
-extern uchar environment[];
-env_t *env_ptr = (env_t *)(&environment[0]);
+env_t *env_ptr = &environment;
#else /* ! ENV_IS_EMBEDDED */
-env_t *env_ptr = NULL;
+env_t *env_ptr;
#endif /* ENV_IS_EMBEDDED */
-/* local functions */
-#if !defined(ENV_IS_EMBEDDED)
-static void use_default(void);
-#endif
-
DECLARE_GLOBAL_DATA_PTR;
#if !defined(CONFIG_ENV_OFFSET)
@@ -60,9 +51,8 @@
*env_addr = CONFIG_ENV_OFFSET;
return 0;
}
-__attribute__((weak, alias("__mmc_get_env_addr")))
-int mmc_get_env_addr(struct mmc *mmc, u32 *env_addr);
-
+int mmc_get_env_addr(struct mmc *mmc, u32 *env_addr)
+ __attribute__((weak, alias("__mmc_get_env_addr")));
uchar env_get_char_spec(int index)
{
@@ -72,13 +62,13 @@
int env_init(void)
{
/* use default */
- gd->env_addr = (ulong)&default_environment[0];
- gd->env_valid = 1;
+ gd->env_addr = (ulong)&default_environment[0];
+ gd->env_valid = 1;
return 0;
}
-int init_mmc_for_env(struct mmc *mmc)
+static int init_mmc_for_env(struct mmc *mmc)
{
if (!mmc) {
puts("No MMC card found\n");
@@ -87,21 +77,20 @@
if (mmc_init(mmc)) {
puts("MMC init failed\n");
- return -1;
+ return -1;
}
return 0;
}
#ifdef CONFIG_CMD_SAVEENV
-
-inline int write_env(struct mmc *mmc, unsigned long size,
- unsigned long offset, const void *buffer)
+static inline int write_env(struct mmc *mmc, unsigned long size,
+ unsigned long offset, const void *buffer)
{
uint blk_start, blk_cnt, n;
- blk_start = ALIGN(offset, mmc->write_bl_len) / mmc->write_bl_len;
- blk_cnt = ALIGN(size, mmc->write_bl_len) / mmc->write_bl_len;
+ blk_start = ALIGN(offset, mmc->write_bl_len) / mmc->write_bl_len;
+ blk_cnt = ALIGN(size, mmc->write_bl_len) / mmc->write_bl_len;
n = mmc->block_dev.block_write(CONFIG_SYS_MMC_ENV_DEV, blk_start,
blk_cnt, (u_char *)buffer);
@@ -115,21 +104,19 @@
ssize_t len;
char *res;
struct mmc *mmc = find_mmc_device(CONFIG_SYS_MMC_ENV_DEV);
- u32 offset;
+ u32 offset;
- if (init_mmc_for_env(mmc))
- return 1;
-
- if(mmc_get_env_addr(mmc, &offset))
+ if (init_mmc_for_env(mmc) || mmc_get_env_addr(mmc, &offset))
return 1;
res = (char *)&env_new.data;
- len = hexport_r(&env_htab, '\0', &res, ENV_SIZE);
+ len = hexport_r(&env_htab, '\0', &res, ENV_SIZE, 0, NULL);
if (len < 0) {
error("Cannot export environment: errno = %d\n", errno);
return 1;
}
- env_new.crc = crc32(0, env_new.data, ENV_SIZE);
+
+ env_new.crc = crc32(0, env_new.data, ENV_SIZE);
printf("Writing to MMC(%d)... ", CONFIG_SYS_MMC_ENV_DEV);
if (write_env(mmc, CONFIG_ENV_SIZE, offset, (u_char *)&env_new)) {
puts("failed\n");
@@ -141,13 +128,13 @@
}
#endif /* CONFIG_CMD_SAVEENV */
-inline int read_env(struct mmc *mmc, unsigned long size,
- unsigned long offset, const void *buffer)
+static inline int read_env(struct mmc *mmc, unsigned long size,
+ unsigned long offset, const void *buffer)
{
uint blk_start, blk_cnt, n;
- blk_start = ALIGN(offset, mmc->read_bl_len) / mmc->read_bl_len;
- blk_cnt = ALIGN(size, mmc->read_bl_len) / mmc->read_bl_len;
+ blk_start = ALIGN(offset, mmc->read_bl_len) / mmc->read_bl_len;
+ blk_cnt = ALIGN(size, mmc->read_bl_len) / mmc->read_bl_len;
n = mmc->block_dev.block_read(CONFIG_SYS_MMC_ENV_DEV, blk_start,
blk_cnt, (uchar *)buffer);
@@ -159,32 +146,15 @@
{
#if !defined(ENV_IS_EMBEDDED)
char buf[CONFIG_ENV_SIZE];
-
struct mmc *mmc = find_mmc_device(CONFIG_SYS_MMC_ENV_DEV);
u32 offset;
- if (init_mmc_for_env(mmc)) {
- use_default();
- return;
- }
+ if (init_mmc_for_env(mmc) || mmc_get_env_addr(mmc, &offset))
+ return set_default_env(NULL);
- if(mmc_get_env_addr(mmc, &offset)) {
- use_default();
- return ;
- }
-
- if (read_env(mmc, CONFIG_ENV_SIZE, offset, buf)) {
- use_default();
- return;
- }
+ if (read_env(mmc, CONFIG_ENV_SIZE, offset, buf))
+ return set_default_env(NULL);
env_import(buf, 1);
#endif
}
-
-#if !defined(ENV_IS_EMBEDDED)
-static void use_default()
-{
- set_default_env(NULL);
-}
-#endif
diff --git a/common/env_nand.c b/common/env_nand.c
index 14446a6..ce13def 100644
--- a/common/env_nand.c
+++ b/common/env_nand.c
@@ -44,10 +44,11 @@
#if defined(CONFIG_CMD_SAVEENV) && defined(CONFIG_CMD_NAND)
#define CMD_SAVEENV
#elif defined(CONFIG_ENV_OFFSET_REDUND)
-#error Cannot use CONFIG_ENV_OFFSET_REDUND without CONFIG_CMD_SAVEENV & CONFIG_CMD_NAND
+#error CONFIG_ENV_OFFSET_REDUND must have CONFIG_CMD_SAVEENV & CONFIG_CMD_NAND
#endif
-#if defined(CONFIG_ENV_SIZE_REDUND) && (CONFIG_ENV_SIZE_REDUND != CONFIG_ENV_SIZE)
+#if defined(CONFIG_ENV_SIZE_REDUND) && \
+ (CONFIG_ENV_SIZE_REDUND != CONFIG_ENV_SIZE)
#error CONFIG_ENV_SIZE_REDUND should be the same as CONFIG_ENV_SIZE
#endif
@@ -55,26 +56,21 @@
#define CONFIG_ENV_RANGE CONFIG_ENV_SIZE
#endif
-/* references to names in env_common.c */
-extern uchar default_environment[];
-
char *env_name_spec = "NAND";
-
#if defined(ENV_IS_EMBEDDED)
-extern uchar environment[];
-env_t *env_ptr = (env_t *)(&environment[0]);
+env_t *env_ptr = &environment;
#elif defined(CONFIG_NAND_ENV_DST)
env_t *env_ptr = (env_t *)CONFIG_NAND_ENV_DST;
#else /* ! ENV_IS_EMBEDDED */
-env_t *env_ptr = 0;
+env_t *env_ptr;
#endif /* ENV_IS_EMBEDDED */
DECLARE_GLOBAL_DATA_PTR;
-uchar env_get_char_spec (int index)
+uchar env_get_char_spec(int index)
{
- return ( *((uchar *)(gd->env_addr + index)) );
+ return *((uchar *)(gd->env_addr + index));
}
/*
@@ -99,16 +95,14 @@
env_t *tmp_env2;
tmp_env2 = (env_t *)((ulong)env_ptr + CONFIG_ENV_SIZE);
- crc2_ok = (crc32(0, tmp_env2->data, ENV_SIZE) == tmp_env2->crc);
+ crc2_ok = crc32(0, tmp_env2->data, ENV_SIZE) == tmp_env2->crc;
#endif
-
tmp_env1 = env_ptr;
-
- crc1_ok = (crc32(0, tmp_env1->data, ENV_SIZE) == tmp_env1->crc);
+ crc1_ok = crc32(0, tmp_env1->data, ENV_SIZE) == tmp_env1->crc;
if (!crc1_ok && !crc2_ok) {
- gd->env_addr = 0;
- gd->env_valid = 0;
+ gd->env_addr = 0;
+ gd->env_valid = 0;
return 0;
} else if (crc1_ok && !crc2_ok) {
@@ -119,13 +113,13 @@
gd->env_valid = 2;
} else {
/* both ok - check serial */
- if(tmp_env1->flags == 255 && tmp_env2->flags == 0)
+ if (tmp_env1->flags == 255 && tmp_env2->flags == 0)
gd->env_valid = 2;
- else if(tmp_env2->flags == 255 && tmp_env1->flags == 0)
+ else if (tmp_env2->flags == 255 && tmp_env1->flags == 0)
gd->env_valid = 1;
- else if(tmp_env1->flags > tmp_env2->flags)
+ else if (tmp_env1->flags > tmp_env2->flags)
gd->env_valid = 1;
- else if(tmp_env2->flags > tmp_env1->flags)
+ else if (tmp_env2->flags > tmp_env1->flags)
gd->env_valid = 2;
else /* flags are equal - almost impossible */
gd->env_valid = 1;
@@ -141,11 +135,11 @@
gd->env_addr = (ulong)env_ptr->data;
#else /* ENV_IS_EMBEDDED || CONFIG_NAND_ENV_DST */
- gd->env_addr = (ulong)&default_environment[0];
- gd->env_valid = 1;
+ gd->env_addr = (ulong)&default_environment[0];
+ gd->env_valid = 1;
#endif /* ENV_IS_EMBEDDED || CONFIG_NAND_ENV_DST */
- return (0);
+ return 0;
}
#ifdef CMD_SAVEENV
@@ -158,7 +152,6 @@
size_t end = offset + CONFIG_ENV_RANGE;
size_t amount_saved = 0;
size_t blocksize, len;
-
u_char *char_ptr;
blocksize = nand_info[0].erasesize;
@@ -169,9 +162,9 @@
offset += blocksize;
} else {
char_ptr = &buf[amount_saved];
- if (nand_write(&nand_info[0], offset, &len,
- char_ptr))
+ if (nand_write(&nand_info[0], offset, &len, char_ptr))
return 1;
+
offset += blocksize;
amount_saved += len;
}
@@ -200,23 +193,22 @@
return 1;
res = (char *)&env_new.data;
- len = hexport_r(&env_htab, '\0', &res, ENV_SIZE);
+ len = hexport_r(&env_htab, '\0', &res, ENV_SIZE, 0, NULL);
if (len < 0) {
error("Cannot export environment: errno = %d\n", errno);
return 1;
}
- env_new.crc = crc32(0, env_new.data, ENV_SIZE);
- env_new.flags = ++env_flags; /* increase the serial */
+ env_new.crc = crc32(0, env_new.data, ENV_SIZE);
+ env_new.flags = ++env_flags; /* increase the serial */
- if(gd->env_valid == 1) {
+ if (gd->env_valid == 1) {
puts("Erasing redundant NAND...\n");
nand_erase_options.offset = CONFIG_ENV_OFFSET_REDUND;
if (nand_erase_opts(&nand_info[0], &nand_erase_options))
return 1;
puts("Writing to redundant NAND... ");
- ret = writeenv(CONFIG_ENV_OFFSET_REDUND,
- (u_char *)&env_new);
+ ret = writeenv(CONFIG_ENV_OFFSET_REDUND, (u_char *)&env_new);
} else {
puts("Erasing NAND...\n");
nand_erase_options.offset = CONFIG_ENV_OFFSET;
@@ -224,8 +216,7 @@
return 1;
puts("Writing to NAND... ");
- ret = writeenv(CONFIG_ENV_OFFSET,
- (u_char *)&env_new);
+ ret = writeenv(CONFIG_ENV_OFFSET, (u_char *)&env_new);
}
if (ret) {
puts("FAILED!\n");
@@ -234,14 +225,14 @@
puts("done\n");
- gd->env_valid = (gd->env_valid == 2 ? 1 : 2);
+ gd->env_valid = gd->env_valid == 2 ? 1 : 2;
return ret;
}
#else /* ! CONFIG_ENV_OFFSET_REDUND */
int saveenv(void)
{
- int ret = 0;
+ int ret = 0;
env_t env_new;
ssize_t len;
char *res;
@@ -255,12 +246,12 @@
return 1;
res = (char *)&env_new.data;
- len = hexport_r(&env_htab, '\0', &res, ENV_SIZE);
+ len = hexport_r(&env_htab, '\0', &res, ENV_SIZE, 0, NULL);
if (len < 0) {
error("Cannot export environment: errno = %d\n", errno);
return 1;
}
- env_new.crc = crc32(0, env_new.data, ENV_SIZE);
+ env_new.crc = crc32(0, env_new.data, ENV_SIZE);
puts("Erasing Nand...\n");
if (nand_erase_opts(&nand_info[0], &nand_erase_options))
@@ -278,17 +269,17 @@
#endif /* CONFIG_ENV_OFFSET_REDUND */
#endif /* CMD_SAVEENV */
-int readenv(size_t offset, u_char * buf)
+int readenv(size_t offset, u_char *buf)
{
size_t end = offset + CONFIG_ENV_RANGE;
size_t amount_loaded = 0;
size_t blocksize, len;
-
u_char *char_ptr;
blocksize = nand_info[0].erasesize;
if (!blocksize)
return 1;
+
len = min(blocksize, CONFIG_ENV_SIZE);
while (amount_loaded < CONFIG_ENV_SIZE && offset < end) {
@@ -296,12 +287,15 @@
offset += blocksize;
} else {
char_ptr = &buf[amount_loaded];
- if (nand_read_skip_bad(&nand_info[0], offset, &len, char_ptr))
+ if (nand_read_skip_bad(&nand_info[0], offset,
+ &len, char_ptr))
return 1;
+
offset += blocksize;
amount_loaded += len;
}
}
+
if (amount_loaded != CONFIG_ENV_SIZE)
return 1;
@@ -312,14 +306,14 @@
int get_nand_env_oob(nand_info_t *nand, unsigned long *result)
{
struct mtd_oob_ops ops;
- uint32_t oob_buf[ENV_OFFSET_SIZE/sizeof(uint32_t)];
+ uint32_t oob_buf[ENV_OFFSET_SIZE / sizeof(uint32_t)];
int ret;
- ops.datbuf = NULL;
- ops.mode = MTD_OOB_AUTO;
- ops.ooboffs = 0;
- ops.ooblen = ENV_OFFSET_SIZE;
- ops.oobbuf = (void *) oob_buf;
+ ops.datbuf = NULL;
+ ops.mode = MTD_OOB_AUTO;
+ ops.ooboffs = 0;
+ ops.ooblen = ENV_OFFSET_SIZE;
+ ops.oobbuf = (void *)oob_buf;
ret = nand->read_oob(nand, ENV_OFFSET_SIZE, &ops);
if (ret) {
@@ -349,13 +343,10 @@
tmp_env1 = (env_t *)malloc(CONFIG_ENV_SIZE);
tmp_env2 = (env_t *)malloc(CONFIG_ENV_SIZE);
-
- if ((tmp_env1 == NULL) || (tmp_env2 == NULL)) {
+ if (tmp_env1 == NULL || tmp_env2 == NULL) {
puts("Can't allocate buffers for environment\n");
- free(tmp_env1);
- free(tmp_env2);
set_default_env("!malloc() failed");
- return;
+ goto done;
}
if (readenv(CONFIG_ENV_OFFSET, (u_char *) tmp_env1))
@@ -364,14 +355,12 @@
if (readenv(CONFIG_ENV_OFFSET_REDUND, (u_char *) tmp_env2))
puts("No Valid Redundant Environment Area found\n");
- crc1_ok = (crc32(0, tmp_env1->data, ENV_SIZE) == tmp_env1->crc);
- crc2_ok = (crc32(0, tmp_env2->data, ENV_SIZE) == tmp_env2->crc);
+ crc1_ok = crc32(0, tmp_env1->data, ENV_SIZE) == tmp_env1->crc;
+ crc2_ok = crc32(0, tmp_env2->data, ENV_SIZE) == tmp_env2->crc;
if (!crc1_ok && !crc2_ok) {
- free(tmp_env1);
- free(tmp_env2);
set_default_env("!bad CRC");
- return;
+ goto done;
} else if (crc1_ok && !crc2_ok) {
gd->env_valid = 1;
} else if (!crc1_ok && crc2_ok) {
@@ -388,7 +377,6 @@
gd->env_valid = 2;
else /* flags are equal - almost impossible */
gd->env_valid = 1;
-
}
free(env_ptr);
@@ -401,6 +389,7 @@
env_flags = ep->flags;
env_import((char *)ep, 0);
+done:
free(tmp_env1);
free(tmp_env2);
@@ -412,7 +401,7 @@
* device i.e., nand_dev_desc + 0. This is also the behaviour using
* the new NAND code.
*/
-void env_relocate_spec (void)
+void env_relocate_spec(void)
{
#if !defined(ENV_IS_EMBEDDED)
int ret;
diff --git a/common/env_nowhere.c b/common/env_nowhere.c
index 75ef78d..8a3ca19 100644
--- a/common/env_nowhere.c
+++ b/common/env_nowhere.c
@@ -31,9 +31,7 @@
DECLARE_GLOBAL_DATA_PTR;
-env_t *env_ptr = NULL;
-
-extern uchar default_environment[];
+env_t *env_ptr;
void env_relocate_spec(void)
{
@@ -41,7 +39,7 @@
uchar env_get_char_spec(int index)
{
- return ( *((uchar *)(gd->env_addr + index)) );
+ return *((uchar *)(gd->env_addr + index));
}
/*
@@ -51,8 +49,8 @@
*/
int env_init(void)
{
- gd->env_addr = (ulong)&default_environment[0];
- gd->env_valid = 0;
+ gd->env_addr = (ulong)&default_environment[0];
+ gd->env_valid = 0;
- return (0);
+ return 0;
}
diff --git a/common/env_nvram.c b/common/env_nvram.c
index 544ce47..726eaac 100644
--- a/common/env_nvram.c
+++ b/common/env_nvram.c
@@ -52,21 +52,19 @@
#ifdef CONFIG_SYS_NVRAM_ACCESS_ROUTINE
extern void *nvram_read(void *dest, const long src, size_t count);
extern void nvram_write(long dest, const void *src, size_t count);
-env_t *env_ptr = NULL;
+env_t *env_ptr;
#else
env_t *env_ptr = (env_t *)CONFIG_ENV_ADDR;
#endif
-char * env_name_spec = "NVRAM";
-
-extern uchar default_environment[];
+char *env_name_spec = "NVRAM";
uchar env_get_char_spec(int index)
{
#ifdef CONFIG_SYS_NVRAM_ACCESS_ROUTINE
uchar c;
- nvram_read(&c, CONFIG_ENV_ADDR+index, 1);
+ nvram_read(&c, CONFIG_ENV_ADDR + index, 1);
return c;
#else
@@ -81,7 +79,7 @@
#if defined(CONFIG_SYS_NVRAM_ACCESS_ROUTINE)
nvram_read(buf, CONFIG_ENV_ADDR, CONFIG_ENV_SIZE);
#else
- memcpy(buf, (void*)CONFIG_ENV_ADDR, CONFIG_ENV_SIZE);
+ memcpy(buf, (void *)CONFIG_ENV_ADDR, CONFIG_ENV_SIZE);
#endif
env_import(buf, 1);
}
@@ -94,7 +92,7 @@
int rcode = 0;
res = (char *)&env_new.data;
- len = hexport_r(&env_htab, '\0', &res, ENV_SIZE);
+ len = hexport_r(&env_htab, '\0', &res, ENV_SIZE, 0, NULL);
if (len < 0) {
error("Cannot export environment: errno = %d\n", errno);
return 1;
@@ -110,7 +108,6 @@
return rcode;
}
-
/*
* Initialize Environment use
*
@@ -123,18 +120,19 @@
uchar data[ENV_SIZE];
nvram_read(&crc, CONFIG_ENV_ADDR, sizeof(ulong));
- nvram_read(data, CONFIG_ENV_ADDR+sizeof(ulong), ENV_SIZE);
+ nvram_read(data, CONFIG_ENV_ADDR + sizeof(ulong), ENV_SIZE);
if (crc32(0, data, ENV_SIZE) == crc) {
- gd->env_addr = (ulong)CONFIG_ENV_ADDR + sizeof(long);
+ gd->env_addr = (ulong)CONFIG_ENV_ADDR + sizeof(long);
#else
if (crc32(0, env_ptr->data, ENV_SIZE) == env_ptr->crc) {
- gd->env_addr = (ulong)&(env_ptr->data);
+ gd->env_addr = (ulong)&env_ptr->data;
#endif
- gd->env_valid = 1;
+ gd->env_valid = 1;
} else {
- gd->env_addr = (ulong)&default_environment[0];
- gd->env_valid = 0;
+ gd->env_addr = (ulong)&default_environment[0];
+ gd->env_valid = 0;
}
- return (0);
+
+ return 0;
}
diff --git a/common/env_onenand.c b/common/env_onenand.c
index 5e04a06..0ad2fc7 100644
--- a/common/env_onenand.c
+++ b/common/env_onenand.c
@@ -31,31 +31,22 @@
#include <malloc.h>
#include <search.h>
#include <errno.h>
+#include <onenand_uboot.h>
#include <linux/mtd/compat.h>
#include <linux/mtd/mtd.h>
#include <linux/mtd/onenand.h>
-extern struct mtd_info onenand_mtd;
-extern struct onenand_chip onenand_chip;
-
-/* References to names in env_common.c */
-extern uchar default_environment[];
-
char *env_name_spec = "OneNAND";
#define ONENAND_MAX_ENV_SIZE 4096
#define ONENAND_ENV_SIZE(mtd) (ONENAND_MAX_ENV_SIZE - ENV_HEADER_SIZE)
-#ifdef ENV_IS_EMBEDDED
-extern uchar environment[];
-#endif /* ENV_IS_EMBEDDED */
-
DECLARE_GLOBAL_DATA_PTR;
uchar env_get_char_spec(int index)
{
- return (*((uchar *)(gd->env_addr + index)));
+ return *((uchar *)(gd->env_addr + index));
}
void env_relocate_spec(void)
@@ -67,7 +58,7 @@
int rc;
size_t retlen;
#ifdef ENV_IS_EMBEDDED
- char *buf = (char *)&environment[0];
+ char *buf = (char *)&environment;
#else
loff_t env_addr = CONFIG_ENV_ADDR;
char onenand_env[ONENAND_MAX_ENV_SIZE];
@@ -83,7 +74,7 @@
if (mtd->writesize)
/* Ignore read fail */
mtd->read(mtd, env_addr, ONENAND_MAX_ENV_SIZE,
- &retlen, (u_char *)buf);
+ &retlen, (u_char *)buf);
else
mtd->writesize = MAX_ONENAND_PAGESIZE;
#endif /* !ENV_IS_EMBEDDED */
@@ -109,7 +100,7 @@
};
res = (char *)&env_new.data;
- len = hexport_r(&env_htab, '\0', &res, ENV_SIZE);
+ len = hexport_r(&env_htab, '\0', &res, ENV_SIZE, 0, NULL);
if (len < 0) {
error("Cannot export environment: errno = %d\n", errno);
return 1;
@@ -133,7 +124,7 @@
}
if (mtd->write(mtd, env_addr, ONENAND_MAX_ENV_SIZE, &retlen,
- (u_char *)&env_new)) {
+ (u_char *)&env_new)) {
printf("OneNAND: write failed at 0x%llx\n", instr.addr);
return 2;
}
@@ -144,7 +135,7 @@
int env_init(void)
{
/* use default */
- gd->env_addr = (ulong) & default_environment[0];
+ gd->env_addr = (ulong)&default_environment[0];
gd->env_valid = 1;
return 0;
diff --git a/common/env_sf.c b/common/env_sf.c
index d3b36d0..592b870 100644
--- a/common/env_sf.c
+++ b/common/env_sf.c
@@ -36,7 +36,7 @@
# define CONFIG_ENV_SPI_BUS 0
#endif
#ifndef CONFIG_ENV_SPI_CS
-# define CONFIG_ENV_SPI_CS 0
+# define CONFIG_ENV_SPI_CS 0
#endif
#ifndef CONFIG_ENV_SPI_MAX_HZ
# define CONFIG_ENV_SPI_MAX_HZ 1000000
@@ -46,19 +46,16 @@
#endif
#ifdef CONFIG_ENV_OFFSET_REDUND
-static ulong env_offset = CONFIG_ENV_OFFSET;
-static ulong env_new_offset = CONFIG_ENV_OFFSET_REDUND;
+static ulong env_offset = CONFIG_ENV_OFFSET;
+static ulong env_new_offset = CONFIG_ENV_OFFSET_REDUND;
-#define ACTIVE_FLAG 1
-#define OBSOLETE_FLAG 0
+#define ACTIVE_FLAG 1
+#define OBSOLETE_FLAG 0
#endif /* CONFIG_ENV_OFFSET_REDUND */
DECLARE_GLOBAL_DATA_PTR;
-/* references to names in env_common.c */
-extern uchar default_environment[];
-
-char * env_name_spec = "SPI Flash";
+char *env_name_spec = "SPI Flash";
static struct spi_flash *env_flash;
@@ -68,17 +65,13 @@
}
#if defined(CONFIG_ENV_OFFSET_REDUND)
-
int saveenv(void)
{
env_t env_new;
ssize_t len;
- char *res;
- u32 saved_size, saved_offset;
- char *saved_buffer = NULL;
- u32 sector = 1;
+ char *res, *saved_buffer = NULL, flag = OBSOLETE_FLAG;
+ u32 saved_size, saved_offset, sector = 1;
int ret;
- char flag = OBSOLETE_FLAG;
if (!env_flash) {
env_flash = spi_flash_probe(CONFIG_ENV_SPI_BUS,
@@ -91,13 +84,13 @@
}
res = (char *)&env_new.data;
- len = hexport_r(&env_htab, '\0', &res, ENV_SIZE);
+ len = hexport_r(&env_htab, '\0', &res, ENV_SIZE, 0, NULL);
if (len < 0) {
error("Cannot export environment: errno = %d\n", errno);
return 1;
}
- env_new.crc = crc32(0, env_new.data, ENV_SIZE);
- env_new.flags = ACTIVE_FLAG;
+ env_new.crc = crc32(0, env_new.data, ENV_SIZE);
+ env_new.flags = ACTIVE_FLAG;
if (gd->env_valid == 1) {
env_new_offset = CONFIG_ENV_OFFSET_REDUND;
@@ -148,21 +141,21 @@
goto done;
}
- ret = spi_flash_write(env_flash,
- env_offset + offsetof(env_t, flags),
- sizeof(env_new.flags), &flag);
+ ret = spi_flash_write(env_flash, env_offset + offsetof(env_t, flags),
+ sizeof(env_new.flags), &flag);
if (ret)
goto done;
puts("done\n");
- gd->env_valid = (gd->env_valid == 2 ? 1 : 2);
+ gd->env_valid = gd->env_valid == 2 ? 1 : 2;
printf("Valid environment: %d\n", (int)gd->env_valid);
done:
if (saved_buffer)
free(saved_buffer);
+
return ret;
}
@@ -248,18 +241,14 @@
out:
free(tmp_env1);
free(tmp_env2);
-
- return;
}
#else
int saveenv(void)
{
- u32 saved_size, saved_offset;
- char *saved_buffer = NULL;
- u32 sector = 1;
- int ret = 1;
+ u32 saved_size, saved_offset, sector = 1;
+ char *res, *saved_buffer = NULL;
+ int ret = 1;
env_t env_new;
- char *res;
ssize_t len;
if (!env_flash) {
@@ -277,9 +266,9 @@
saved_size = CONFIG_ENV_SECT_SIZE - CONFIG_ENV_SIZE;
saved_offset = CONFIG_ENV_OFFSET + CONFIG_ENV_SIZE;
saved_buffer = malloc(saved_size);
- if (!saved_buffer) {
+ if (!saved_buffer)
goto done;
- }
+
ret = spi_flash_read(env_flash, saved_offset,
saved_size, saved_buffer);
if (ret)
@@ -293,7 +282,7 @@
}
res = (char *)&env_new.data;
- len = hexport_r(&env_htab, '\0', &res, ENV_SIZE);
+ len = hexport_r(&env_htab, '\0', &res, ENV_SIZE, 0, NULL);
if (len < 0) {
error("Cannot export environment: errno = %d\n", errno);
goto done;
@@ -325,6 +314,7 @@
done:
if (saved_buffer)
free(saved_buffer);
+
return ret;
}
@@ -348,7 +338,6 @@
}
ret = env_import(buf, 1);
-
if (ret)
gd->env_valid = 1;
out:
diff --git a/common/fdt_support.c b/common/fdt_support.c
index bdda64d..593f16c 100644
--- a/common/fdt_support.c
+++ b/common/fdt_support.c
@@ -49,8 +49,8 @@
* Convenience function to find a node and return it's property or a
* default value if it doesn't exist.
*/
-u32 fdt_getprop_u32_default(void *fdt, const char *path, const char *prop,
- const u32 dflt)
+u32 fdt_getprop_u32_default(const void *fdt, const char *path,
+ const char *prop, const u32 dflt)
{
const u32 *val;
int off;
@@ -61,7 +61,7 @@
val = fdt_getprop(fdt, off, prop, NULL);
if (val)
- return *val;
+ return fdt32_to_cpu(*val);
else
return dflt;
}
@@ -372,7 +372,7 @@
const u32 *cell;
cell = fdt_getprop(blob, 0, nr_cells_name, NULL);
- if (cell && *cell == 2)
+ if (cell && fdt32_to_cpu(*cell) == 2)
return 8;
return 4;
diff --git a/common/hush.c b/common/hush.c
index 2495a6d..e8e24d7 100644
--- a/common/hush.c
+++ b/common/hush.c
@@ -1000,7 +1000,6 @@
fflush(stdout);
i->p = the_command;
#else
- extern char console_buffer[];
int n;
static char the_command[CONFIG_SYS_CBSIZE];
diff --git a/common/lcd.c b/common/lcd.c
index d9cb8ca..6313ec0 100644
--- a/common/lcd.c
+++ b/common/lcd.c
@@ -57,12 +57,14 @@
/* ** FONT DATA */
/************************************************************************/
#include <video_font.h> /* Get font data, width and height */
+#include <video_font_data.h>
/************************************************************************/
/* ** LOGO DATA */
/************************************************************************/
#ifdef CONFIG_LCD_LOGO
# include <bmp_logo.h> /* Get logo data, width and height */
+# include <bmp_logo_data.h>
# if (CONSOLE_COLOR_WHITE >= BMP_LOGO_OFFSET) && (LCD_BPP != LCD_COLOR16)
# error Default Color Map overlaps with Logo Color Map
# endif
@@ -78,7 +80,6 @@
static int lcd_init (void *lcdbase);
-static int lcd_clear (cmd_tbl_t * cmdtp, int flag, int argc, char * const argv[]);
static void *lcd_logo (void);
static int lcd_getbgcolor (void);
@@ -353,7 +354,14 @@
}
/*----------------------------------------------------------------------*/
-static int lcd_clear (cmd_tbl_t * cmdtp, int flag, int argc, char * const argv[])
+static
+int do_lcd_clear(cmd_tbl_t *cmdtp, int flag, int argc, char *const argv[])
+{
+ lcd_clear();
+ return 0;
+}
+
+void lcd_clear(void)
{
#if LCD_BPP == LCD_MONOCHROME
/* Setting the palette */
@@ -394,12 +402,10 @@
console_col = 0;
console_row = 0;
-
- return (0);
}
U_BOOT_CMD(
- cls, 1, 1, lcd_clear,
+ cls, 1, 1, do_lcd_clear,
"clear screen",
""
);
@@ -413,7 +419,7 @@
lcd_ctrl_init (lcdbase);
lcd_is_enabled = 1;
- lcd_clear (NULL, 1, 1, NULL); /* dummy args */
+ lcd_clear();
lcd_enable ();
/* Initialize the console */
diff --git a/common/modem.c b/common/modem.c
index a017b29..e37e1ea 100644
--- a/common/modem.c
+++ b/common/modem.c
@@ -62,7 +62,6 @@
char env_str[16];
char *init_str;
int i;
- extern char console_buffer[];
extern void enable_putc(void);
extern int hwflow_onoff(int);
diff --git a/common/usb.c b/common/usb.c
index bed5116..4418c70 100644
--- a/common/usb.c
+++ b/common/usb.c
@@ -263,18 +263,24 @@
return dev->epmaxpacketin[((pipe>>15) & 0xf)];
}
-/* The routine usb_set_maxpacket_ep() is extracted from the loop of routine
+/*
+ * The routine usb_set_maxpacket_ep() is extracted from the loop of routine
* usb_set_maxpacket(), because the optimizer of GCC 4.x chokes on this routine
* when it is inlined in 1 single routine. What happens is that the register r3
* is used as loop-count 'i', but gets overwritten later on.
* This is clearly a compiler bug, but it is easier to workaround it here than
* to update the compiler (Occurs with at least several GCC 4.{1,2},x
* CodeSourcery compilers like e.g. 2007q3, 2008q1, 2008q3 lite editions on ARM)
+ *
+ * NOTE: Similar behaviour was observed with GCC4.6 on ARMv5.
*/
static void __attribute__((noinline))
-usb_set_maxpacket_ep(struct usb_device *dev, struct usb_endpoint_descriptor *ep)
+usb_set_maxpacket_ep(struct usb_device *dev, int if_idx, int ep_idx)
{
int b;
+ struct usb_endpoint_descriptor *ep;
+
+ ep = &dev->config.if_desc[if_idx].ep_desc[ep_idx];
b = ep->bEndpointAddress & USB_ENDPOINT_NUMBER_MASK;
@@ -313,8 +319,7 @@
for (i = 0; i < dev->config.desc.bNumInterfaces; i++)
for (ii = 0; ii < dev->config.if_desc[i].desc.bNumEndpoints; ii++)
- usb_set_maxpacket_ep(dev,
- &dev->config.if_desc[i].ep_desc[ii]);
+ usb_set_maxpacket_ep(dev, i, ii);
return 0;
}
diff --git a/doc/README.m28 b/doc/README.m28
new file mode 100644
index 0000000..b749ce0
--- /dev/null
+++ b/doc/README.m28
@@ -0,0 +1,223 @@
+DENX M28EVK
+===========
+
+This document describes the DENX M28/M28EVK U-Boot port. This document mostly
+covers topics related to making the module/board bootable.
+
+Terminology
+-----------
+
+The dollar symbol ($) introduces a snipped of shell code. This shall be typed
+into the unix command prompt in U-Boot source code root directory.
+
+The (=>) introduces a snipped of code that should by typed into U-Boot command
+prompt.
+
+Contents
+--------
+
+0) Files of the M28/M28EVK port
+1) Prerequisites
+2) Compiling U-Boot for M28
+3) Installation of U-Boot for M28EVK to SD card
+4) Installation of U-Boot for M28 to NAND flash
+
+0) Files of the M28/M28EVK port
+-------------------------------
+
+arch/arm/cpu/arm926ejs/mx28/ - The CPU support code for the Freescale i.MX28
+arch/arm/include/asm/arch-mx28/ - Header files for the Freescale i.MX28
+board/denx/m28evk/ - M28EVK board specific files
+include/configs/m28evk.h - M28EVK configuration file
+
+1) Prerequisites
+----------------
+
+To make the M28 module or the M28 module or M28EVK board bootable, some tools
+are necessary. The first one is the "elftosb" tool distributed by Freescale
+Semiconductor. The other tool is the "mxsboot" tool found in U-Boot source tree.
+
+Firstly, obtain the elftosb archive from the following location:
+
+ http://foss.doredevelopment.dk/mirrors/imx/elftosb-10.12.01.tar.gz
+
+We use a $VER variable here to denote the current version. At the time of
+writing of this document, that is "10.12.01". To obtain the file from command
+line, use:
+
+ $ VER="10.12.01"
+ $ wget http://foss.doredevelopment.dk/mirrors/imx/elftosb-${VER}.tar.gz
+
+Extract the file:
+
+ $ tar xzf elftosb-${VER}.tar.gz
+
+Compile the file. We need to manually tell the linker to use also libm:
+
+ $ cd elftosb-${VER}/
+ $ make LIBS="-lstdc++ -lm" elftosb
+
+Optionally, remove debugging symbols from elftosb:
+
+ $ strip bld/linux/elftosb
+
+Finally, install the "elftosb" binary. The "install" target is missing, so just
+copy the binary by hand:
+
+ $ sudo cp bld/linux/elftosb /usr/local/bin/
+
+Make sure the "elftosb" binary can be found in your $PATH, in this case this
+means "/usr/local/bin/" has to be in your $PATH.
+
+2) Compiling U-Boot for M28
+---------------------------
+
+Compiling the U-Boot for M28 is straightforward and done as compiling U-Boot
+for any other ARM device. For cross-compiler setup, please refer to ELDK5.0
+documentation. First, clean up the source code:
+
+ $ make mrproper
+
+Next, configure U-Boot for M28EVK:
+
+ $ make m28evk_config
+
+Lastly, compile U-Boot and prepare a "BootStream". The "BootStream" is a special
+type of file, which the i.MX28 CPU can boot. This is handled by the following
+command:
+
+ $ make u-boot.sb
+
+HINT: To speed-up the build process, you can add -j<N>, where N is number of
+ compiler instances that'll run in parallel.
+
+The code produces "u-boot.sb" file. This file needs to be augmented with a
+proper header to allow successful boot from SD or NAND. Adding the header is
+discussed in the following chapters.
+
+3) Installation of U-Boot for M28EVK to SD card
+-----------------------------------------------
+
+To boot an M28 from SD, set the boot mode DIP switches according to i.MX28
+manual chapter 12.2.1 (Table 12-2), PORT=SSP0, SD/MMC master on SSP0, 3.3V.
+
+An SD card the i.MX28 CPU can use to boot U-Boot must contain a DOS partition
+table, which in turn carries a partition of special type and which contains a
+special header. The rest of partitions in the DOS partition table can be used
+by the user.
+
+To prepare such partition, use your favourite partitioning tool. The partition
+must have the following parameters:
+
+ * Start sector .......... sector 2048
+ * Partition size ........ at least 1024 kb
+ * Partition type ........ 0x53 (sometimes "OnTrack DM6 Aux3")
+
+For example in Linux fdisk, the sequence for a clear card is the following:
+
+ * o ..................... create a clear partition table
+ * n ..................... create new partition
+ * p ............. primary partition
+ * 1 ............. first partition
+ * 2048 .......... first sector is 2048
+ * +1M ........... make the partition 1Mb big
+ * t 1 ................... change first partition ID
+ * 53 ............ change the ID to 0x53 (OnTrack DM6 Aux3)
+ * <create other partitions>
+ * w ..................... write partition table to disk
+
+The partition layout is ready, next the special partition must be filled with
+proper contents. The contents is generated by running the following command (see
+chapter 2)):
+
+ $ ./tools/mxsboot sd u-boot.sb u-boot.sd
+
+The resulting file, "u-boot.sd", shall then be written to the partition. In this
+case, we assume the first partition of the SD card is /dev/mmcblk0p1:
+
+ $ dd if=u-boot.sd of=/dev/mmcblk0p1
+
+Last step is to insert the card into M28EVK and boot.
+
+NOTE: If the user needs to adjust the start sector, the "mxsboot" tool contains
+ a "-p" switch for that purpose. The "-p" switch takes the sector number as
+ an argument.
+
+4) Installation of U-Boot for M28 to NAND flash
+-----------------------------------------------
+
+To boot an M28 from NAND, set the boot mode DIP switches according to i.MX28
+manual chapter 12.2.1 (Table 12-2), PORT=GPMI, NAND 1.8 V.
+
+There are two possibilities when preparing an image writable to NAND flash.
+
+ I) The NAND wasn't written at all yet or the BCB is broken
+ ----------------------------------------------------------
+ In this case, both BCB (FCB and DBBT) and firmware needs to be
+ written to NAND. To generate NAND image containing all these,
+ there is a tool called "mxsboot" in the "tools/" directory. The tool
+ is invoked on "u-boot.sb" file from chapter 2):
+
+ $ ./tools/mxsboot nand u-boot.sb u-boot.nand
+
+ NOTE: The above invokation works for NAND flash with geometry of
+ 2048b per page, 64b OOB data, 128kb erase size. If your chip
+ has a different geometry, please use:
+
+ -w <size> change page size (default 2048 b)
+ -o <size> change oob size (default 64 b)
+ -e <size> change erase size (default 131072 b)
+
+ The geometry information can be obtained from running U-Boot
+ on M28 by issuing the "nand info" command.
+
+ The resulting file, "u-boot.nand" can be written directly to NAND
+ from the U-Boot prompt. To simplify the process, the U-Boot default
+ environment contains script "update_nand_full" to update the system.
+
+ This script expects a working TFTP server containing the file
+ "u-boot.nand" in it's root directory. This can be changed by
+ adjusting the "update_nand_full_filename" varible.
+
+ To update the system, run the following in U-Boot prompt:
+
+ => run update_nand_full
+
+ In case you would only need to update the bootloader in future,
+ see II) below.
+
+ II) The NAND was already written with a good BCB
+ ------------------------------------------------
+ This part applies after the part I) above was done at least once.
+
+ If part I) above was done correctly already, there is no need to
+ write the FCB and DBBT parts of NAND again. It's possible to upgrade
+ only the bootloader image.
+
+ To simplify the process of firmware update, the U-Boot default
+ environment contains script "update_nand_firmware" to update only
+ the firmware, without rewriting FCB and DBBT.
+
+ This script expects a working TFTP server containing the file
+ "u-boot.sb" in it's root directory. This can be changed by
+ adjusting the "update_nand_firmware_filename" varible.
+
+ To update the system, run the following in U-Boot prompt:
+
+ => run update_nand_firmware
+
+ III) Special settings for the update scripts
+ --------------------------------------------
+ There is a slight possibility of the user wanting to adjust the
+ STRIDE and COUNT options of the NAND boot. For description of these,
+ see i.MX28 manual section 12.12.1.2 and 12.12.1.3.
+
+ The update scripts take this possibility into account. In case the
+ user changes STRIDE by blowing fuses, the user also has to change
+ "update_nand_stride" variable. In case the user changes COUNT by
+ blowing fuses, the user also has to change "update_nand_count"
+ variable for the update scripts to work correctly.
+
+ In case the user needs to boot a firmware image bigger than 1Mb, the
+ user has to adjust the "update_nand_firmware_maxsz" variable for the
+ update scripts to work properly.
diff --git a/drivers/bios_emulator/x86emu/ops.c b/drivers/bios_emulator/x86emu/ops.c
index c836a20..f8e093d 100644
--- a/drivers/bios_emulator/x86emu/ops.c
+++ b/drivers/bios_emulator/x86emu/ops.c
@@ -3518,11 +3518,9 @@
****************************************************************************/
void x86emuOp_int3(u8 X86EMU_UNUSED(op1))
{
- u16 tmp;
-
START_OF_INSTR();
DECODE_PRINTF("INT 3\n");
- tmp = (u16) mem_access_word(3 * 4 + 2);
+ (void)mem_access_word(3 * 4 + 2);
/* access the segment register */
TRACE_AND_STEP();
if (_X86EMU_intrTab[3]) {
@@ -3546,14 +3544,13 @@
****************************************************************************/
void x86emuOp_int_IMM(u8 X86EMU_UNUSED(op1))
{
- u16 tmp;
u8 intnum;
START_OF_INSTR();
DECODE_PRINTF("INT\t");
intnum = fetch_byte_imm();
DECODE_PRINTF2("%x\n", intnum);
- tmp = mem_access_word(intnum * 4 + 2);
+ (void)mem_access_word(intnum * 4 + 2);
TRACE_AND_STEP();
if (_X86EMU_intrTab[intnum]) {
(*_X86EMU_intrTab[intnum])(intnum);
@@ -3576,13 +3573,11 @@
****************************************************************************/
void x86emuOp_into(u8 X86EMU_UNUSED(op1))
{
- u16 tmp;
-
START_OF_INSTR();
DECODE_PRINTF("INTO\n");
TRACE_AND_STEP();
if (ACCESS_FLAG(F_OF)) {
- tmp = mem_access_word(4 * 4 + 2);
+ (void)mem_access_word(4 * 4 + 2);
if (_X86EMU_intrTab[4]) {
(*_X86EMU_intrTab[4])(4);
} else {
@@ -3990,11 +3985,9 @@
****************************************************************************/
void x86emuOp_aad(u8 X86EMU_UNUSED(op1))
{
- u8 a;
-
START_OF_INSTR();
DECODE_PRINTF("AAD\n");
- a = fetch_byte_imm();
+ (void)fetch_byte_imm();
TRACE_AND_STEP();
M.x86.R_AX = aad_word(M.x86.R_AX);
DECODE_CLEAR_SEGOVR();
diff --git a/drivers/block/ahci.c b/drivers/block/ahci.c
index 015b341..7b2ec50 100644
--- a/drivers/block/ahci.c
+++ b/drivers/block/ahci.c
@@ -561,12 +561,9 @@
*/
static int ata_scsiop_read10(ccb * pccb)
{
- u64 lba = 0;
u32 len = 0;
u8 fis[20];
- lba = (((u64) pccb->cmd[2]) << 24) | (((u64) pccb->cmd[3]) << 16)
- | (((u64) pccb->cmd[4]) << 8) | ((u64) pccb->cmd[5]);
len = (((u32) pccb->cmd[7]) << 8) | ((u32) pccb->cmd[8]);
/* For 10-byte and 16-byte SCSI R/W commands, transfer
diff --git a/drivers/block/ftide020.c b/drivers/block/ftide020.c
index 4a7a07f..ad8fdad 100644
--- a/drivers/block/ftide020.c
+++ b/drivers/block/ftide020.c
@@ -316,10 +316,9 @@
/* auto-detect IDE controller */
if (ftide_controller_probe()) {
- printf("Faraday %s driver version %s\n", FTIDE_IP_NAME,
- FTIDE_DRIVER_VERSION);
+ printf("FTIDE020_S\n");
} else {
- printf("Faraday ATA controller not found.\n");
+ printf("FTIDE020_S ATA controller not found.\n");
return API_ENODEV;
}
diff --git a/drivers/block/sata_dwc.c b/drivers/block/sata_dwc.c
index b2b3804..69ec5fd 100644
--- a/drivers/block/sata_dwc.c
+++ b/drivers/block/sata_dwc.c
@@ -440,11 +440,9 @@
{
u8 nsect,lbal = 0;
u8 tmp = 0;
- u32 serror = 0;
- u8 status = 0;
struct ata_ioports *ioaddr = &ap->ioaddr;
- serror = in_le32((void *)ap->ioaddr.scr_addr + (SCR_ERROR * 4));
+ in_le32((void *)ap->ioaddr.scr_addr + (SCR_ERROR * 4));
writeb(0x55, ioaddr->nsect_addr);
writeb(0xaa, ioaddr->lbal_addr);
@@ -476,7 +474,7 @@
writeb(ap->ctl, ioaddr->ctl_addr);
msleep(150);
- status = ata_check_status(ap);
+ ata_check_status(ap);
msleep(50);
ata_check_status(ap);
@@ -535,7 +533,6 @@
const u16 *id;
struct ata_device *ata_dev = &ata_device;
unsigned long pio_mask, mwdma_mask, udma_mask;
- unsigned long xfer_mask;
char revbuf[7];
u16 iobuf[ATA_SECTOR_WORDS];
@@ -629,10 +626,6 @@
if (id[ATA_ID_FIELD_VALID] & (1 << 2))
udma_mask = id[ATA_ID_UDMA_MODES] & 0xff;
- xfer_mask = ((pio_mask << ATA_SHIFT_PIO) & ATA_MASK_PIO) |
- ((mwdma_mask << ATA_SHIFT_MWDMA) & ATA_MASK_MWDMA) |
- ((udma_mask << ATA_SHIFT_UDMA) & ATA_MASK_UDMA);
-
if (ata_dev->class == ATA_DEV_ATA) {
if (ata_id_is_cfa(id)) {
if (id[162] & 1)
@@ -651,14 +644,11 @@
ata_dev->multi_count = ata_dev->id[59] & 0xff;
if (ata_id_has_lba(id)) {
- const char *lba_desc;
char ncq_desc[20];
- lba_desc = "LBA";
ata_dev->flags |= ATA_DFLAG_LBA;
if (ata_id_has_lba48(id)) {
ata_dev->flags |= ATA_DFLAG_LBA48;
- lba_desc = "LBA48";
if (ata_dev->n_sectors >= (1UL << 28) &&
ata_id_has_flush_ext(id))
@@ -890,6 +880,7 @@
return 0;
err_out:
+ printf("failed to READ ID (%s, err_mask=0x%x)\n", reason, err_mask);
return rc;
}
@@ -1807,7 +1798,6 @@
unsigned int err_mask = 0;
const char *reason;
int may_fallback = 1;
- int rc;
if (dev_state == SATA_ERROR)
return FALSE;
@@ -1904,19 +1894,10 @@
return -ENOENT;
}
- rc = -EIO;
reason = "I/O error";
goto err_out;
}
- /* Falling back doesn't make sense if ID data was read
- * successfully at least once.
- */
- may_fallback = 0;
-
- rc = -EINVAL;
- reason = "device reports invalid type";
-
return TRUE;
err_out:
@@ -1991,7 +1972,6 @@
unsigned int err_mask = 0;
const char *reason;
int may_fallback = 1;
- int rc;
if (dev_state == SATA_ERROR)
return FALSE;
@@ -2089,19 +2069,10 @@
return -ENOENT;
}
- rc = -EIO;
reason = "I/O error";
goto err_out;
}
- /* Falling back doesn't make sense if ID data was read
- * successfully at least once.
- */
- may_fallback = 0;
-
- rc = -EINVAL;
- reason = "device reports invalid type";
-
return TRUE;
err_out:
diff --git a/drivers/block/sata_sil3114.c b/drivers/block/sata_sil3114.c
index 1e60636..34fe038 100644
--- a/drivers/block/sata_sil3114.c
+++ b/drivers/block/sata_sil3114.c
@@ -782,6 +782,7 @@
(iobase[5] + VND_TF2_CH0) | ATA_PCI_CTL_OFS;
port[0].ioaddr.bmdma_addr = iobase[5] + VND_BMDMA_CH0;
break;
+#if (CONFIG_SYS_SATA_MAX_DEVICE >= 1)
case 1:
port[1].port_no = 0;
port[1].ioaddr.cmd_addr = iobase[5] + VND_TF0_CH1;
@@ -789,6 +790,7 @@
(iobase[5] + VND_TF2_CH1) | ATA_PCI_CTL_OFS;
port[1].ioaddr.bmdma_addr = iobase[5] + VND_BMDMA_CH1;
break;
+#elif (CONFIG_SYS_SATA_MAX_DEVICE >= 2)
case 2:
port[2].port_no = 0;
port[2].ioaddr.cmd_addr = iobase[5] + VND_TF0_CH2;
@@ -796,6 +798,7 @@
(iobase[5] + VND_TF2_CH2) | ATA_PCI_CTL_OFS;
port[2].ioaddr.bmdma_addr = iobase[5] + VND_BMDMA_CH2;
break;
+#elif (CONFIG_SYS_SATA_MAX_DEVICE >= 3)
case 3:
port[3].port_no = 0;
port[3].ioaddr.cmd_addr = iobase[5] + VND_TF0_CH3;
@@ -803,6 +806,7 @@
(iobase[5] + VND_TF2_CH3) | ATA_PCI_CTL_OFS;
port[3].ioaddr.bmdma_addr = iobase[5] + VND_BMDMA_CH3;
break;
+#endif
default:
printf ("Tried to scan unknown port: ata%d\n", dev);
return 1;
diff --git a/drivers/block/sym53c8xx.c b/drivers/block/sym53c8xx.c
index 8094b41..564aa98 100644
--- a/drivers/block/sym53c8xx.c
+++ b/drivers/block/sym53c8xx.c
@@ -453,11 +453,9 @@
void scsi_write_dsp(unsigned long start)
{
- unsigned long val;
#ifdef SCSI_SINGLE_STEP
unsigned char t;
#endif
- val = start;
out32r(scsi_mem_addr + DSP,start);
#ifdef SCSI_SINGLE_STEP
t=scsi_read_byte(DCNTL);
diff --git a/drivers/dma/Makefile b/drivers/dma/Makefile
index 3d9c9f1..5d864b5 100644
--- a/drivers/dma/Makefile
+++ b/drivers/dma/Makefile
@@ -26,6 +26,7 @@
LIB := $(obj)libdma.o
COBJS-$(CONFIG_FSLDMAFEC) += MCD_tasksInit.o MCD_dmaApi.o MCD_tasks.o
+COBJS-$(CONFIG_APBH_DMA) += apbh_dma.o
COBJS-$(CONFIG_FSL_DMA) += fsl_dma.o
COBJS-$(CONFIG_OMAP3_DMA) += omap3_dma.o
diff --git a/drivers/dma/apbh_dma.c b/drivers/dma/apbh_dma.c
new file mode 100644
index 0000000..69a1042
--- /dev/null
+++ b/drivers/dma/apbh_dma.c
@@ -0,0 +1,691 @@
+/*
+ * Freescale i.MX28 APBH DMA driver
+ *
+ * Copyright (C) 2011 Marek Vasut <marek.vasut@gmail.com>
+ * on behalf of DENX Software Engineering GmbH
+ *
+ * Based on code from LTIB:
+ * Copyright (C) 2010 Freescale Semiconductor, Inc. All Rights Reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License along
+ * with this program; if not, write to the Free Software Foundation, Inc.,
+ * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
+ */
+
+#include <linux/list.h>
+
+#include <common.h>
+#include <malloc.h>
+#include <asm/errno.h>
+#include <asm/io.h>
+#include <asm/arch/clock.h>
+#include <asm/arch/imx-regs.h>
+#include <asm/arch/sys_proto.h>
+#include <asm/arch/dma.h>
+
+static struct mxs_dma_chan mxs_dma_channels[MXS_MAX_DMA_CHANNELS];
+
+/*
+ * Test is the DMA channel is valid channel
+ */
+int mxs_dma_validate_chan(int channel)
+{
+ struct mxs_dma_chan *pchan;
+
+ if ((channel < 0) || (channel >= MXS_MAX_DMA_CHANNELS))
+ return -EINVAL;
+
+ pchan = mxs_dma_channels + channel;
+ if (!(pchan->flags & MXS_DMA_FLAGS_ALLOCATED))
+ return -EINVAL;
+
+ return 0;
+}
+
+/*
+ * Enable a DMA channel.
+ *
+ * If the given channel has any DMA descriptors on its active list, this
+ * function causes the DMA hardware to begin processing them.
+ *
+ * This function marks the DMA channel as "busy," whether or not there are any
+ * descriptors to process.
+ */
+int mxs_dma_enable(int channel)
+{
+ struct mx28_apbh_regs *apbh_regs =
+ (struct mx28_apbh_regs *)MXS_APBH_BASE;
+ unsigned int sem;
+ struct mxs_dma_chan *pchan;
+ struct mxs_dma_desc *pdesc;
+ int ret;
+
+ ret = mxs_dma_validate_chan(channel);
+ if (ret)
+ return ret;
+
+ pchan = mxs_dma_channels + channel;
+
+ if (pchan->pending_num == 0) {
+ pchan->flags |= MXS_DMA_FLAGS_BUSY;
+ return 0;
+ }
+
+ pdesc = list_first_entry(&pchan->active, struct mxs_dma_desc, node);
+ if (pdesc == NULL)
+ return -EFAULT;
+
+ if (pchan->flags & MXS_DMA_FLAGS_BUSY) {
+ if (!(pdesc->cmd.data & MXS_DMA_DESC_CHAIN))
+ return 0;
+
+ sem = mxs_dma_read_semaphore(channel);
+ if (sem == 0)
+ return 0;
+
+ if (sem == 1) {
+ pdesc = list_entry(pdesc->node.next,
+ struct mxs_dma_desc, node);
+ writel(mxs_dma_cmd_address(pdesc),
+ &apbh_regs->ch[channel].hw_apbh_ch_nxtcmdar);
+ }
+ writel(pchan->pending_num,
+ &apbh_regs->ch[channel].hw_apbh_ch_sema);
+ pchan->active_num += pchan->pending_num;
+ pchan->pending_num = 0;
+ } else {
+ pchan->active_num += pchan->pending_num;
+ pchan->pending_num = 0;
+ writel(mxs_dma_cmd_address(pdesc),
+ &apbh_regs->ch[channel].hw_apbh_ch_nxtcmdar);
+ writel(pchan->active_num,
+ &apbh_regs->ch[channel].hw_apbh_ch_sema);
+ writel(1 << (channel + APBH_CTRL0_CLKGATE_CHANNEL_OFFSET),
+ &apbh_regs->hw_apbh_ctrl0_clr);
+ }
+
+ pchan->flags |= MXS_DMA_FLAGS_BUSY;
+ return 0;
+}
+
+/*
+ * Disable a DMA channel.
+ *
+ * This function shuts down a DMA channel and marks it as "not busy." Any
+ * descriptors on the active list are immediately moved to the head of the
+ * "done" list, whether or not they have actually been processed by the
+ * hardware. The "ready" flags of these descriptors are NOT cleared, so they
+ * still appear to be active.
+ *
+ * This function immediately shuts down a DMA channel's hardware, aborting any
+ * I/O that may be in progress, potentially leaving I/O hardware in an undefined
+ * state. It is unwise to call this function if there is ANY chance the hardware
+ * is still processing a command.
+ */
+int mxs_dma_disable(int channel)
+{
+ struct mxs_dma_chan *pchan;
+ struct mx28_apbh_regs *apbh_regs =
+ (struct mx28_apbh_regs *)MXS_APBH_BASE;
+ int ret;
+
+ ret = mxs_dma_validate_chan(channel);
+ if (ret)
+ return ret;
+
+ pchan = mxs_dma_channels + channel;
+
+ if (!(pchan->flags & MXS_DMA_FLAGS_BUSY))
+ return -EINVAL;
+
+ writel(1 << (channel + APBH_CTRL0_CLKGATE_CHANNEL_OFFSET),
+ &apbh_regs->hw_apbh_ctrl0_set);
+
+ pchan->flags &= ~MXS_DMA_FLAGS_BUSY;
+ pchan->active_num = 0;
+ pchan->pending_num = 0;
+ list_splice_init(&pchan->active, &pchan->done);
+
+ return 0;
+}
+
+/*
+ * Resets the DMA channel hardware.
+ */
+int mxs_dma_reset(int channel)
+{
+ struct mx28_apbh_regs *apbh_regs =
+ (struct mx28_apbh_regs *)MXS_APBH_BASE;
+ int ret;
+
+ ret = mxs_dma_validate_chan(channel);
+ if (ret)
+ return ret;
+
+ writel(1 << (channel + APBH_CHANNEL_CTRL_RESET_CHANNEL_OFFSET),
+ &apbh_regs->hw_apbh_channel_ctrl_set);
+
+ return 0;
+}
+
+/*
+ * Freeze a DMA channel.
+ *
+ * This function causes the channel to continuously fail arbitration for bus
+ * access, which halts all forward progress without losing any state. A call to
+ * mxs_dma_unfreeze() will cause the channel to continue its current operation
+ * with no ill effect.
+ */
+int mxs_dma_freeze(int channel)
+{
+ struct mx28_apbh_regs *apbh_regs =
+ (struct mx28_apbh_regs *)MXS_APBH_BASE;
+ int ret;
+
+ ret = mxs_dma_validate_chan(channel);
+ if (ret)
+ return ret;
+
+ writel(1 << (channel + APBH_CHANNEL_CTRL_FREEZE_CHANNEL_OFFSET),
+ &apbh_regs->hw_apbh_channel_ctrl_set);
+
+ return 0;
+}
+
+/*
+ * Unfreeze a DMA channel.
+ *
+ * This function reverses the effect of mxs_dma_freeze(), enabling the DMA
+ * channel to continue from where it was frozen.
+ */
+int mxs_dma_unfreeze(int channel)
+{
+ struct mx28_apbh_regs *apbh_regs =
+ (struct mx28_apbh_regs *)MXS_APBH_BASE;
+ int ret;
+
+ ret = mxs_dma_validate_chan(channel);
+ if (ret)
+ return ret;
+
+ writel(1 << (channel + APBH_CHANNEL_CTRL_FREEZE_CHANNEL_OFFSET),
+ &apbh_regs->hw_apbh_channel_ctrl_clr);
+
+ return 0;
+}
+
+/*
+ * Read a DMA channel's hardware semaphore.
+ *
+ * As used by the MXS platform's DMA software, the DMA channel's hardware
+ * semaphore reflects the number of DMA commands the hardware will process, but
+ * has not yet finished. This is a volatile value read directly from hardware,
+ * so it must be be viewed as immediately stale.
+ *
+ * If the channel is not marked busy, or has finished processing all its
+ * commands, this value should be zero.
+ *
+ * See mxs_dma_append() for details on how DMA command blocks must be configured
+ * to maintain the expected behavior of the semaphore's value.
+ */
+int mxs_dma_read_semaphore(int channel)
+{
+ struct mx28_apbh_regs *apbh_regs =
+ (struct mx28_apbh_regs *)MXS_APBH_BASE;
+ uint32_t tmp;
+ int ret;
+
+ ret = mxs_dma_validate_chan(channel);
+ if (ret)
+ return ret;
+
+ tmp = readl(&apbh_regs->ch[channel].hw_apbh_ch_sema);
+
+ tmp &= APBH_CHn_SEMA_PHORE_MASK;
+ tmp >>= APBH_CHn_SEMA_PHORE_OFFSET;
+
+ return tmp;
+}
+
+/*
+ * Enable or disable DMA interrupt.
+ *
+ * This function enables the given DMA channel to interrupt the CPU.
+ */
+int mxs_dma_enable_irq(int channel, int enable)
+{
+ struct mx28_apbh_regs *apbh_regs =
+ (struct mx28_apbh_regs *)MXS_APBH_BASE;
+ int ret;
+
+ ret = mxs_dma_validate_chan(channel);
+ if (ret)
+ return ret;
+
+ if (enable)
+ writel(1 << (channel + APBH_CTRL1_CH_CMDCMPLT_IRQ_EN_OFFSET),
+ &apbh_regs->hw_apbh_ctrl1_set);
+ else
+ writel(1 << (channel + APBH_CTRL1_CH_CMDCMPLT_IRQ_EN_OFFSET),
+ &apbh_regs->hw_apbh_ctrl1_clr);
+
+ return 0;
+}
+
+/*
+ * Check if a DMA interrupt is pending.
+ */
+int mxs_dma_irq_is_pending(int channel)
+{
+ struct mx28_apbh_regs *apbh_regs =
+ (struct mx28_apbh_regs *)MXS_APBH_BASE;
+ uint32_t tmp;
+ int ret;
+
+ ret = mxs_dma_validate_chan(channel);
+ if (ret)
+ return ret;
+
+ tmp = readl(&apbh_regs->hw_apbh_ctrl1);
+ tmp |= readl(&apbh_regs->hw_apbh_ctrl2);
+
+ return (tmp >> channel) & 1;
+}
+
+/*
+ * Clear DMA interrupt.
+ *
+ * The software that is using the DMA channel must register to receive its
+ * interrupts and, when they arrive, must call this function to clear them.
+ */
+int mxs_dma_ack_irq(int channel)
+{
+ struct mx28_apbh_regs *apbh_regs =
+ (struct mx28_apbh_regs *)MXS_APBH_BASE;
+ int ret;
+
+ ret = mxs_dma_validate_chan(channel);
+ if (ret)
+ return ret;
+
+ writel(1 << channel, &apbh_regs->hw_apbh_ctrl1_clr);
+ writel(1 << channel, &apbh_regs->hw_apbh_ctrl2_clr);
+
+ return 0;
+}
+
+/*
+ * Request to reserve a DMA channel
+ */
+int mxs_dma_request(int channel)
+{
+ struct mxs_dma_chan *pchan;
+
+ if ((channel < 0) || (channel >= MXS_MAX_DMA_CHANNELS))
+ return -EINVAL;
+
+ pchan = mxs_dma_channels + channel;
+ if ((pchan->flags & MXS_DMA_FLAGS_VALID) != MXS_DMA_FLAGS_VALID)
+ return -ENODEV;
+
+ if (pchan->flags & MXS_DMA_FLAGS_ALLOCATED)
+ return -EBUSY;
+
+ pchan->flags |= MXS_DMA_FLAGS_ALLOCATED;
+ pchan->active_num = 0;
+ pchan->pending_num = 0;
+
+ INIT_LIST_HEAD(&pchan->active);
+ INIT_LIST_HEAD(&pchan->done);
+
+ return 0;
+}
+
+/*
+ * Release a DMA channel.
+ *
+ * This function releases a DMA channel from its current owner.
+ *
+ * The channel will NOT be released if it's marked "busy" (see
+ * mxs_dma_enable()).
+ */
+int mxs_dma_release(int channel)
+{
+ struct mxs_dma_chan *pchan;
+ int ret;
+
+ ret = mxs_dma_validate_chan(channel);
+ if (ret)
+ return ret;
+
+ pchan = mxs_dma_channels + channel;
+
+ if (pchan->flags & MXS_DMA_FLAGS_BUSY)
+ return -EBUSY;
+
+ pchan->dev = 0;
+ pchan->active_num = 0;
+ pchan->pending_num = 0;
+ pchan->flags &= ~MXS_DMA_FLAGS_ALLOCATED;
+
+ return 0;
+}
+
+/*
+ * Allocate DMA descriptor
+ */
+struct mxs_dma_desc *mxs_dma_desc_alloc(void)
+{
+ struct mxs_dma_desc *pdesc;
+
+ pdesc = memalign(MXS_DMA_ALIGNMENT, sizeof(struct mxs_dma_desc));
+
+ if (pdesc == NULL)
+ return NULL;
+
+ memset(pdesc, 0, sizeof(*pdesc));
+ pdesc->address = (dma_addr_t)pdesc;
+
+ return pdesc;
+};
+
+/*
+ * Free DMA descriptor
+ */
+void mxs_dma_desc_free(struct mxs_dma_desc *pdesc)
+{
+ if (pdesc == NULL)
+ return;
+
+ free(pdesc);
+}
+
+/*
+ * Return the address of the command within a descriptor.
+ */
+unsigned int mxs_dma_cmd_address(struct mxs_dma_desc *desc)
+{
+ return desc->address + offsetof(struct mxs_dma_desc, cmd);
+}
+
+/*
+ * Check if descriptor is on a channel's active list.
+ *
+ * This function returns the state of a descriptor's "ready" flag. This flag is
+ * usually set only if the descriptor appears on a channel's active list. The
+ * descriptor may or may not have already been processed by the hardware.
+ *
+ * The "ready" flag is set when the descriptor is submitted to a channel by a
+ * call to mxs_dma_append() or mxs_dma_append_list(). The "ready" flag is
+ * cleared when a processed descriptor is moved off the active list by a call
+ * to mxs_dma_finish(). The "ready" flag is NOT cleared if the descriptor is
+ * aborted by a call to mxs_dma_disable().
+ */
+int mxs_dma_desc_pending(struct mxs_dma_desc *pdesc)
+{
+ return pdesc->flags & MXS_DMA_DESC_READY;
+}
+
+/*
+ * Add a DMA descriptor to a channel.
+ *
+ * If the descriptor list for this channel is not empty, this function sets the
+ * CHAIN bit and the NEXTCMD_ADDR fields in the last descriptor's DMA command so
+ * it will chain to the new descriptor's command.
+ *
+ * Then, this function marks the new descriptor as "ready," adds it to the end
+ * of the active descriptor list, and increments the count of pending
+ * descriptors.
+ *
+ * The MXS platform DMA software imposes some rules on DMA commands to maintain
+ * important invariants. These rules are NOT checked, but they must be carefully
+ * applied by software that uses MXS DMA channels.
+ *
+ * Invariant:
+ * The DMA channel's hardware semaphore must reflect the number of DMA
+ * commands the hardware will process, but has not yet finished.
+ *
+ * Explanation:
+ * A DMA channel begins processing commands when its hardware semaphore is
+ * written with a value greater than zero, and it stops processing commands
+ * when the semaphore returns to zero.
+ *
+ * When a channel finishes a DMA command, it will decrement its semaphore if
+ * the DECREMENT_SEMAPHORE bit is set in that command's flags bits.
+ *
+ * In principle, it's not necessary for the DECREMENT_SEMAPHORE to be set,
+ * unless it suits the purposes of the software. For example, one could
+ * construct a series of five DMA commands, with the DECREMENT_SEMAPHORE
+ * bit set only in the last one. Then, setting the DMA channel's hardware
+ * semaphore to one would cause the entire series of five commands to be
+ * processed. However, this example would violate the invariant given above.
+ *
+ * Rule:
+ * ALL DMA commands MUST have the DECREMENT_SEMAPHORE bit set so that the DMA
+ * channel's hardware semaphore will be decremented EVERY time a command is
+ * processed.
+ */
+int mxs_dma_desc_append(int channel, struct mxs_dma_desc *pdesc)
+{
+ struct mxs_dma_chan *pchan;
+ struct mxs_dma_desc *last;
+ int ret;
+
+ ret = mxs_dma_validate_chan(channel);
+ if (ret)
+ return ret;
+
+ pchan = mxs_dma_channels + channel;
+
+ pdesc->cmd.next = mxs_dma_cmd_address(pdesc);
+ pdesc->flags |= MXS_DMA_DESC_FIRST | MXS_DMA_DESC_LAST;
+
+ if (!list_empty(&pchan->active)) {
+ last = list_entry(pchan->active.prev, struct mxs_dma_desc,
+ node);
+
+ pdesc->flags &= ~MXS_DMA_DESC_FIRST;
+ last->flags &= ~MXS_DMA_DESC_LAST;
+
+ last->cmd.next = mxs_dma_cmd_address(pdesc);
+ last->cmd.data |= MXS_DMA_DESC_CHAIN;
+ }
+ pdesc->flags |= MXS_DMA_DESC_READY;
+ if (pdesc->flags & MXS_DMA_DESC_FIRST)
+ pchan->pending_num++;
+ list_add_tail(&pdesc->node, &pchan->active);
+
+ return ret;
+}
+
+/*
+ * Retrieve processed DMA descriptors.
+ *
+ * This function moves all the descriptors from the DMA channel's "done" list to
+ * the head of the given list.
+ */
+int mxs_dma_get_finished(int channel, struct list_head *head)
+{
+ struct mxs_dma_chan *pchan;
+ int ret;
+
+ ret = mxs_dma_validate_chan(channel);
+ if (ret)
+ return ret;
+
+ if (head == NULL)
+ return 0;
+
+ pchan = mxs_dma_channels + channel;
+
+ list_splice(&pchan->done, head);
+
+ return 0;
+}
+
+/*
+ * Clean up processed DMA descriptors.
+ *
+ * This function removes processed DMA descriptors from the "active" list. Pass
+ * in a non-NULL list head to get the descriptors moved to your list. Pass NULL
+ * to get the descriptors moved to the channel's "done" list. Descriptors on
+ * the "done" list can be retrieved with mxs_dma_get_finished().
+ *
+ * This function marks the DMA channel as "not busy" if no unprocessed
+ * descriptors remain on the "active" list.
+ */
+int mxs_dma_finish(int channel, struct list_head *head)
+{
+ int sem;
+ struct mxs_dma_chan *pchan;
+ struct list_head *p, *q;
+ struct mxs_dma_desc *pdesc;
+ int ret;
+
+ ret = mxs_dma_validate_chan(channel);
+ if (ret)
+ return ret;
+
+ pchan = mxs_dma_channels + channel;
+
+ sem = mxs_dma_read_semaphore(channel);
+ if (sem < 0)
+ return sem;
+
+ if (sem == pchan->active_num)
+ return 0;
+
+ list_for_each_safe(p, q, &pchan->active) {
+ if ((pchan->active_num) <= sem)
+ break;
+
+ pdesc = list_entry(p, struct mxs_dma_desc, node);
+ pdesc->flags &= ~MXS_DMA_DESC_READY;
+
+ if (head)
+ list_move_tail(p, head);
+ else
+ list_move_tail(p, &pchan->done);
+
+ if (pdesc->flags & MXS_DMA_DESC_LAST)
+ pchan->active_num--;
+ }
+
+ if (sem == 0)
+ pchan->flags &= ~MXS_DMA_FLAGS_BUSY;
+
+ return 0;
+}
+
+/*
+ * Wait for DMA channel to complete
+ */
+int mxs_dma_wait_complete(uint32_t timeout, unsigned int chan)
+{
+ struct mx28_apbh_regs *apbh_regs =
+ (struct mx28_apbh_regs *)MXS_APBH_BASE;
+ int ret;
+
+ ret = mxs_dma_validate_chan(chan);
+ if (ret)
+ return ret;
+
+ if (mx28_wait_mask_set(&apbh_regs->hw_apbh_ctrl1_reg,
+ 1 << chan, timeout)) {
+ ret = -ETIMEDOUT;
+ mxs_dma_reset(chan);
+ }
+
+ return 0;
+}
+
+/*
+ * Execute the DMA channel
+ */
+int mxs_dma_go(int chan)
+{
+ uint32_t timeout = 10000;
+ int ret;
+
+ LIST_HEAD(tmp_desc_list);
+
+ mxs_dma_enable_irq(chan, 1);
+ mxs_dma_enable(chan);
+
+ /* Wait for DMA to finish. */
+ ret = mxs_dma_wait_complete(timeout, chan);
+
+ /* Clear out the descriptors we just ran. */
+ mxs_dma_finish(chan, &tmp_desc_list);
+
+ /* Shut the DMA channel down. */
+ mxs_dma_ack_irq(chan);
+ mxs_dma_reset(chan);
+ mxs_dma_enable_irq(chan, 0);
+ mxs_dma_disable(chan);
+
+ return ret;
+}
+
+/*
+ * Initialize the DMA hardware
+ */
+int mxs_dma_init(void)
+{
+ struct mx28_apbh_regs *apbh_regs =
+ (struct mx28_apbh_regs *)MXS_APBH_BASE;
+ struct mxs_dma_chan *pchan;
+ int ret, channel;
+
+ mx28_reset_block(&apbh_regs->hw_apbh_ctrl0_reg);
+
+#ifdef CONFIG_APBH_DMA_BURST8
+ writel(APBH_CTRL0_AHB_BURST8_EN,
+ &apbh_regs->hw_apbh_ctrl0_set);
+#else
+ writel(APBH_CTRL0_AHB_BURST8_EN,
+ &apbh_regs->hw_apbh_ctrl0_clr);
+#endif
+
+#ifdef CONFIG_APBH_DMA_BURST
+ writel(APBH_CTRL0_APB_BURST_EN,
+ &apbh_regs->hw_apbh_ctrl0_set);
+#else
+ writel(APBH_CTRL0_APB_BURST_EN,
+ &apbh_regs->hw_apbh_ctrl0_clr);
+#endif
+
+ for (channel = 0; channel < MXS_MAX_DMA_CHANNELS; channel++) {
+ pchan = mxs_dma_channels + channel;
+ pchan->flags = MXS_DMA_FLAGS_VALID;
+
+ ret = mxs_dma_request(channel);
+
+ if (ret) {
+ printf("MXS DMA: Can't acquire DMA channel %i\n",
+ channel);
+
+ goto err;
+ }
+
+ mxs_dma_reset(channel);
+ mxs_dma_ack_irq(channel);
+ }
+
+ return 0;
+
+err:
+ while (--channel >= 0)
+ mxs_dma_release(channel);
+ return ret;
+}
diff --git a/drivers/fpga/ivm_core.c b/drivers/fpga/ivm_core.c
index 2b5a485..b5a47d1 100755
--- a/drivers/fpga/ivm_core.c
+++ b/drivers/fpga/ivm_core.c
@@ -2102,7 +2102,6 @@
unsigned char ucState = 0;
unsigned short usDelay = 0;
unsigned short usToggle = 0;
- unsigned char usByte = 0;
g_usIntelBufferSize = (unsigned short)ispVMDataSize();
@@ -2171,7 +2170,6 @@
ucState = 0;
usDelay = 0;
usToggle = 0;
- usByte = 0;
usContinue = 1;
/*
diff --git a/drivers/gpio/Makefile b/drivers/gpio/Makefile
index f505813..e22c096 100644
--- a/drivers/gpio/Makefile
+++ b/drivers/gpio/Makefile
@@ -30,11 +30,13 @@
COBJS-$(CONFIG_MARVELL_GPIO) += mvgpio.o
COBJS-$(CONFIG_MARVELL_MFP) += mvmfp.o
COBJS-$(CONFIG_MXC_GPIO) += mxc_gpio.o
+COBJS-$(CONFIG_MXS_GPIO) += mxs_gpio.o
COBJS-$(CONFIG_PCA953X) += pca953x.o
COBJS-$(CONFIG_PCA9698) += pca9698.o
COBJS-$(CONFIG_S5P) += s5p_gpio.o
COBJS-$(CONFIG_TEGRA2_GPIO) += tegra2_gpio.o
COBJS-$(CONFIG_DA8XX_GPIO) += da8xx_gpio.o
+COBJS-$(CONFIG_ALTERA_PIO) += altera_pio.o
COBJS := $(COBJS-y)
SRCS := $(COBJS:.o=.c)
diff --git a/drivers/gpio/altera_pio.c b/drivers/gpio/altera_pio.c
new file mode 100644
index 0000000..fb03760
--- /dev/null
+++ b/drivers/gpio/altera_pio.c
@@ -0,0 +1,299 @@
+/*
+ * Driver for Altera's PIO ip core
+ *
+ * Copyright (C) 2011 Missing Link Electronics
+ * Joachim Foerster <joachim@missinglinkelectronics.com>
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ *
+ * To use this driver, in your board's config. header:
+ * #define CONFIG_ALTERA_PIO
+ * #define CONFIG_SYS_ALTERA_PIO_NUM <number-of-pio-cores>
+ * #define CONFIG_SYS_ALTERA_PIO_GPIO_NUM <total-number-of-gpios>
+ * And in your board's early setup routine:
+ * altera_pio_init(<baseaddr>, <width>, 'i'|'o'|'t',
+ * <reset-value>, <neg-mask>, "label");
+ * - 'i'|'o'|'t': PIO is input-only/output-only/tri-state
+ * - <reset-value>: for correct initial status display, output-only
+ * - <neg-mask> is meant to be used to in cases of active-low
+ * GPIOs, such as LEDs and buttons (on/pressed == 0). Each bit
+ * which is 1 in <neg-mask> inverts the corresponding GPIO's value
+ * before set/after get. So: gpio_set_value(gpio, 1) => LED on .
+ *
+ * Do NOT define CONFIG_SYS_GPIO_BASE !
+ *
+ * Optionally, in your board's config. header:
+ * - To force a GPIO numbering scheme like in Linux ...
+ * #define CONFIG_GPIO_DOWNTO_NUMBERING
+ * ... starting with 255 (default)
+ * #define CONFIG_GPIO_DOWNTO_MAX 255
+ */
+#include <common.h>
+#include <asm/io.h>
+#include <asm/gpio.h>
+
+#ifdef CONFIG_GPIO_DOWNTO_NUMBERING
+#ifndef CONFIG_GPIO_DOWNTO_MAX
+#define CONFIG_GPIO_DOWNTO_MAX 255
+#endif
+#endif
+
+#define ALTERA_PIO_DATA 0x0
+#define ALTERA_PIO_DIR 0x4
+
+#define GPIO_LABEL_SIZE 9
+
+
+static struct altera_pio {
+ u32 base;
+ u8 width;
+ char iot;
+ u32 negmask;
+ u32 sh_data;
+ u32 sh_dir;
+ int gidx;
+ char label[GPIO_LABEL_SIZE];
+} pios[CONFIG_SYS_ALTERA_PIO_NUM];
+
+static int pio_num;
+
+static struct altera_pio_gpio {
+ unsigned num;
+ struct altera_pio *pio;
+ char reqlabel[GPIO_LABEL_SIZE];
+} gpios[CONFIG_SYS_ALTERA_PIO_GPIO_NUM];
+
+static int pio_gpio_num;
+
+
+static int altera_pio_gidx(unsigned gpio)
+{
+ int i;
+
+ for (i = 0; i < pio_gpio_num; ++i) {
+ if (gpio == gpios[i].num)
+ break;
+ }
+ if (i >= pio_gpio_num)
+ return -1;
+ return i;
+}
+
+static struct altera_pio *altera_pio_get_and_mask(unsigned gpio, u32 *mask)
+{
+ int gidx = altera_pio_gidx(gpio);
+ if (gidx < 0)
+ return NULL;
+ if (mask)
+ *mask = 1 << (gidx - gpios[gidx].pio->gidx);
+ return gpios[gidx].pio;
+}
+
+#define altera_pio_use_gidx(_gidx, _reqlabel) \
+ { strncpy(gpios[_gidx].reqlabel, _reqlabel, GPIO_LABEL_SIZE); }
+#define altera_pio_unuse_gidx(_gidx) { gpios[_gidx].reqlabel[0] = '\0'; }
+#define altera_pio_is_gidx_used(_gidx) (gpios[_gidx].reqlabel[0] != '\0')
+
+static int altera_pio_gpio_init(struct altera_pio *pio, u8 width)
+{
+ u8 gidx = pio_gpio_num;
+ int i;
+
+ if (!width)
+ return -1;
+ if ((pio_gpio_num + width) > CONFIG_SYS_ALTERA_PIO_GPIO_NUM)
+ return -1;
+
+ for (i = 0; i < width; ++i) {
+#ifdef CONFIG_GPIO_DOWNTO_NUMBERING
+ gpios[pio_gpio_num + i].num = \
+ CONFIG_GPIO_DOWNTO_MAX + 1 - gidx - width + i;
+#else
+ gpios[pio_gpio_num + i].num = pio_gpio_num + i;
+#endif
+ gpios[pio_gpio_num + i].pio = pio;
+ altera_pio_unuse_gidx(pio_gpio_num + i);
+ }
+ pio_gpio_num += width;
+ return gidx;
+}
+
+int altera_pio_init(u32 base, u8 width, char iot, u32 rstval, u32 negmask,
+ const char *label)
+{
+ if (pio_num >= CONFIG_SYS_ALTERA_PIO_NUM)
+ return -1;
+
+ pios[pio_num].base = base;
+ pios[pio_num].width = width;
+ pios[pio_num].iot = iot;
+ switch (iot) {
+ case 'i':
+ /* input only */
+ pios[pio_num].sh_dir = 0;
+ pios[pio_num].sh_data = readl(base + ALTERA_PIO_DATA);
+ break;
+ case 'o':
+ /* output only */
+ pios[pio_num].sh_dir = 0xffffffff & ((1 << width) - 1);
+ pios[pio_num].sh_data = rstval;
+ break;
+ case 't':
+ /* bidir, tri-state */
+ pios[pio_num].sh_dir = readl(base + ALTERA_PIO_DIR);
+ pios[pio_num].sh_data = readl(base + ALTERA_PIO_DATA);
+ break;
+ default:
+ return -1;
+ }
+ pios[pio_num].negmask = negmask & ((1 << width) - 1);
+ pios[pio_num].gidx = altera_pio_gpio_init(&pios[pio_num], width);
+ if (pios[pio_num].gidx < 0)
+ return -1;
+ strncpy(pios[pio_num].label, label, GPIO_LABEL_SIZE);
+ return pio_num++;
+}
+
+void altera_pio_info(void)
+{
+ int i;
+ int j;
+ int gidx;
+ u32 mask;
+
+ for (i = 0; i < pio_num; ++i) {
+ printf("Altera PIO % 2d, @0x%08x, "
+ "width: %u, label: %s\n",
+ i, pios[i].base, pios[i].width, pios[i].label);
+ gidx = pios[i].gidx;
+ for (j = gidx; j < (gidx + pios[i].width); ++j) {
+ mask = 1 << (j - gidx);
+ printf("\tGPIO % 4d: %s %s [%c] %s\n",
+ gpios[j].num,
+ gpios[j].pio->sh_dir & mask ? "out" : " in",
+ gpio_get_value(gpios[j].num) ? "set" : "clr",
+ altera_pio_is_gidx_used(j) ? 'x' : ' ',
+ gpios[j].reqlabel);
+ }
+ }
+}
+
+
+int gpio_request(unsigned gpio, const char *label)
+{
+ int gidx = altera_pio_gidx(gpio);
+ if (gidx < 0)
+ return gidx;
+ if (altera_pio_is_gidx_used(gidx))
+ return -1;
+
+ altera_pio_use_gidx(gidx, label);
+ return 0;
+}
+
+int gpio_free(unsigned gpio)
+{
+ int gidx = altera_pio_gidx(gpio);
+ if (gidx < 0)
+ return gidx;
+ if (!altera_pio_is_gidx_used(gidx))
+ return -1;
+
+ altera_pio_unuse_gidx(gidx);
+ return 0;
+}
+
+int gpio_direction_input(unsigned gpio)
+{
+ u32 mask;
+ struct altera_pio *pio;
+
+ pio = altera_pio_get_and_mask(gpio, &mask);
+ if (!pio)
+ return -1;
+ if (pio->iot == 'o')
+ return -1;
+
+ writel(pio->sh_dir &= ~mask, pio->base + ALTERA_PIO_DIR);
+ return 0;
+}
+
+int gpio_direction_output(unsigned gpio, int value)
+{
+ u32 mask;
+ struct altera_pio *pio;
+
+ pio = altera_pio_get_and_mask(gpio, &mask);
+ if (!pio)
+ return -1;
+ if (pio->iot == 'i')
+ return -1;
+
+ value = (pio->negmask & mask) ? !value : value;
+ if (value)
+ pio->sh_data |= mask;
+ else
+ pio->sh_data &= ~mask;
+ writel(pio->sh_data, pio->base + ALTERA_PIO_DATA);
+ writel(pio->sh_dir |= mask, pio->base + ALTERA_PIO_DIR);
+ return 0;
+}
+
+int gpio_get_value(unsigned gpio)
+{
+ u32 mask;
+ struct altera_pio *pio;
+ u32 val;
+
+ pio = altera_pio_get_and_mask(gpio, &mask);
+ if (!pio)
+ return -1;
+
+ if ((pio->sh_dir & mask) || (pio->iot == 'o'))
+ val = pio->sh_data & mask;
+ else
+ val = readl(pio->base + ALTERA_PIO_DATA) & mask;
+ return (pio->negmask & mask) ? !val : val;
+}
+
+void gpio_set_value(unsigned gpio, int value)
+{
+ u32 mask;
+ struct altera_pio *pio;
+
+ pio = altera_pio_get_and_mask(gpio, &mask);
+ if (!pio)
+ return;
+ if (pio->iot == 'i')
+ return;
+
+ value = (pio->negmask & mask) ? !value : value;
+ if (value)
+ pio->sh_data |= mask;
+ else
+ pio->sh_data &= ~mask;
+ writel(pio->sh_data, pio->base + ALTERA_PIO_DATA);
+ return;
+}
+
+int gpio_is_valid(int number)
+{
+ int gidx = altera_pio_gidx(number);
+
+ if (gidx < 0)
+ return 1;
+ return 0;
+}
diff --git a/drivers/gpio/mxs_gpio.c b/drivers/gpio/mxs_gpio.c
new file mode 100644
index 0000000..b7e9591
--- /dev/null
+++ b/drivers/gpio/mxs_gpio.c
@@ -0,0 +1,136 @@
+/*
+ * Freescale i.MX28 GPIO control code
+ *
+ * Copyright (C) 2011 Marek Vasut <marek.vasut@gmail.com>
+ * on behalf of DENX Software Engineering GmbH
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <netdev.h>
+#include <asm/errno.h>
+#include <asm/io.h>
+#include <asm/arch/iomux.h>
+#include <asm/arch/imx-regs.h>
+
+#if defined(CONFIG_MX23)
+#define PINCTRL_BANKS 3
+#define PINCTRL_DOUT(n) (0x0500 + ((n) * 0x10))
+#define PINCTRL_DIN(n) (0x0600 + ((n) * 0x10))
+#define PINCTRL_DOE(n) (0x0700 + ((n) * 0x10))
+#define PINCTRL_PIN2IRQ(n) (0x0800 + ((n) * 0x10))
+#define PINCTRL_IRQEN(n) (0x0900 + ((n) * 0x10))
+#define PINCTRL_IRQSTAT(n) (0x0c00 + ((n) * 0x10))
+#elif defined(CONFIG_MX28)
+#define PINCTRL_BANKS 5
+#define PINCTRL_DOUT(n) (0x0700 + ((n) * 0x10))
+#define PINCTRL_DIN(n) (0x0900 + ((n) * 0x10))
+#define PINCTRL_DOE(n) (0x0b00 + ((n) * 0x10))
+#define PINCTRL_PIN2IRQ(n) (0x1000 + ((n) * 0x10))
+#define PINCTRL_IRQEN(n) (0x1100 + ((n) * 0x10))
+#define PINCTRL_IRQSTAT(n) (0x1400 + ((n) * 0x10))
+#else
+#error "Please select CONFIG_MX23 or CONFIG_MX28"
+#endif
+
+#define GPIO_INT_FALL_EDGE 0x0
+#define GPIO_INT_LOW_LEV 0x1
+#define GPIO_INT_RISE_EDGE 0x2
+#define GPIO_INT_HIGH_LEV 0x3
+#define GPIO_INT_LEV_MASK (1 << 0)
+#define GPIO_INT_POL_MASK (1 << 1)
+
+void mxs_gpio_init(void)
+{
+ int i;
+
+ for (i = 0; i < PINCTRL_BANKS; i++) {
+ writel(0, MXS_PINCTRL_BASE + PINCTRL_PIN2IRQ(i));
+ writel(0, MXS_PINCTRL_BASE + PINCTRL_IRQEN(i));
+ /* Use SCT address here to clear the IRQSTAT bits */
+ writel(0xffffffff, MXS_PINCTRL_BASE + PINCTRL_IRQSTAT(i) + 8);
+ }
+}
+
+int gpio_get_value(int gp)
+{
+ uint32_t bank = PAD_BANK(gp);
+ uint32_t offset = PINCTRL_DIN(bank);
+ struct mx28_register *reg =
+ (struct mx28_register *)(MXS_PINCTRL_BASE + offset);
+
+ return (readl(®->reg) >> PAD_PIN(gp)) & 1;
+}
+
+void gpio_set_value(int gp, int value)
+{
+ uint32_t bank = PAD_BANK(gp);
+ uint32_t offset = PINCTRL_DOUT(bank);
+ struct mx28_register *reg =
+ (struct mx28_register *)(MXS_PINCTRL_BASE + offset);
+
+ if (value)
+ writel(1 << PAD_PIN(gp), ®->reg_set);
+ else
+ writel(1 << PAD_PIN(gp), ®->reg_clr);
+}
+
+int gpio_direction_input(int gp)
+{
+ uint32_t bank = PAD_BANK(gp);
+ uint32_t offset = PINCTRL_DOE(bank);
+ struct mx28_register *reg =
+ (struct mx28_register *)(MXS_PINCTRL_BASE + offset);
+
+ writel(1 << PAD_PIN(gp), ®->reg_clr);
+
+ return 0;
+}
+
+int gpio_direction_output(int gp, int value)
+{
+ uint32_t bank = PAD_BANK(gp);
+ uint32_t offset = PINCTRL_DOE(bank);
+ struct mx28_register *reg =
+ (struct mx28_register *)(MXS_PINCTRL_BASE + offset);
+
+ writel(1 << PAD_PIN(gp), ®->reg_set);
+
+ gpio_set_value(gp, value);
+
+ return 0;
+}
+
+int gpio_request(int gp, const char *label)
+{
+ if (PAD_BANK(gp) > PINCTRL_BANKS)
+ return -EINVAL;
+
+ return 0;
+}
+
+void gpio_free(int gp)
+{
+}
+
+void gpio_toggle_value(int gp)
+{
+ gpio_set_value(gp, !gpio_get_value(gp));
+}
diff --git a/drivers/gpio/pca9698.c b/drivers/gpio/pca9698.c
index b946efa..fe6d2c6 100644
--- a/drivers/gpio/pca9698.c
+++ b/drivers/gpio/pca9698.c
@@ -27,6 +27,7 @@
#include <common.h>
#include <i2c.h>
+#include <asm/errno.h>
#include <pca9698.h>
/*
@@ -39,19 +40,20 @@
#define PCA9698_REG_CONFIG 0x18
#define PCA9698_BUFFER_SIZE 5
+#define PCA9698_GPIO_COUNT 40
-static int pca9698_read40(u8 chip, u8 offset, u8 *buffer)
+static int pca9698_read40(u8 addr, u8 offset, u8 *buffer)
{
u8 command = offset | 0x80; /* autoincrement */
- return i2c_read(chip, command, 1, buffer, PCA9698_BUFFER_SIZE);
+ return i2c_read(addr, command, 1, buffer, PCA9698_BUFFER_SIZE);
}
-static int pca9698_write40(u8 chip, u8 offset, u8 *buffer)
+static int pca9698_write40(u8 addr, u8 offset, u8 *buffer)
{
u8 command = offset | 0x80; /* autoincrement */
- return i2c_write(chip, command, 1, buffer, PCA9698_BUFFER_SIZE);
+ return i2c_write(addr, command, 1, buffer, PCA9698_BUFFER_SIZE);
}
static void pca9698_set_bit(unsigned gpio, u8 *buffer, unsigned value)
@@ -65,41 +67,59 @@
buffer[byte] &= ~(1 << bit);
}
-int pca9698_direction_input(u8 chip, unsigned offset)
+int pca9698_request(unsigned gpio, const char *label)
+{
+ if (gpio >= PCA9698_GPIO_COUNT)
+ return -EINVAL;
+
+ return 0;
+}
+
+void pca9698_free(unsigned gpio)
+{
+}
+
+int pca9698_direction_input(u8 addr, unsigned gpio)
{
u8 data[PCA9698_BUFFER_SIZE];
int res;
- res = pca9698_read40(chip, PCA9698_REG_CONFIG, data);
+ res = pca9698_read40(addr, PCA9698_REG_CONFIG, data);
if (res)
return res;
- pca9698_set_bit(offset, data, 1);
- return pca9698_write40(chip, PCA9698_REG_CONFIG, data);
+ pca9698_set_bit(gpio, data, 1);
+
+ return pca9698_write40(addr, PCA9698_REG_CONFIG, data);
}
-int pca9698_direction_output(u8 chip, unsigned offset)
+int pca9698_direction_output(u8 addr, unsigned gpio, int value)
{
u8 data[PCA9698_BUFFER_SIZE];
int res;
- res = pca9698_read40(chip, PCA9698_REG_CONFIG, data);
+ res = pca9698_set_value(addr, gpio, value);
if (res)
return res;
- pca9698_set_bit(offset, data, 0);
- return pca9698_write40(chip, PCA9698_REG_CONFIG, data);
+ res = pca9698_read40(addr, PCA9698_REG_CONFIG, data);
+ if (res)
+ return res;
+
+ pca9698_set_bit(gpio, data, 0);
+
+ return pca9698_write40(addr, PCA9698_REG_CONFIG, data);
}
-int pca9698_get_input(u8 chip, unsigned offset)
+int pca9698_get_value(u8 addr, unsigned gpio)
{
- unsigned config_byte = offset / 8;
- unsigned config_bit = offset % 8;
+ unsigned config_byte = gpio / 8;
+ unsigned config_bit = gpio % 8;
unsigned value;
u8 data[PCA9698_BUFFER_SIZE];
int res;
- res = pca9698_read40(chip, PCA9698_REG_INPUT, data);
+ res = pca9698_read40(addr, PCA9698_REG_INPUT, data);
if (res)
return -1;
@@ -108,16 +128,16 @@
return !!value;
}
-int pca9698_set_output(u8 chip, unsigned offset, int value)
+int pca9698_set_value(u8 addr, unsigned gpio, int value)
{
u8 data[PCA9698_BUFFER_SIZE];
int res;
- res = pca9698_read40(chip, PCA9698_REG_OUTPUT, data);
+ res = pca9698_read40(addr, PCA9698_REG_OUTPUT, data);
if (res)
return res;
- memset(data, sizeof(data), 0);
- pca9698_set_bit(offset, data, value);
- return pca9698_write40(chip, PCA9698_REG_OUTPUT, data);
+ pca9698_set_bit(gpio, data, value);
+
+ return pca9698_write40(addr, PCA9698_REG_OUTPUT, data);
}
diff --git a/drivers/i2c/Makefile b/drivers/i2c/Makefile
index a48047a..504db03 100644
--- a/drivers/i2c/Makefile
+++ b/drivers/i2c/Makefile
@@ -31,6 +31,7 @@
COBJS-$(CONFIG_I2C_MVTWSI) += mvtwsi.o
COBJS-$(CONFIG_I2C_MV) += mv_i2c.o
COBJS-$(CONFIG_I2C_MXC) += mxc_i2c.o
+COBJS-$(CONFIG_I2C_MXS) += mxs_i2c.o
COBJS-$(CONFIG_DRIVER_OMAP1510_I2C) += omap1510_i2c.o
COBJS-$(CONFIG_DRIVER_OMAP24XX_I2C) += omap24xx_i2c.o
COBJS-$(CONFIG_DRIVER_OMAP34XX_I2C) += omap24xx_i2c.o
@@ -42,6 +43,7 @@
COBJS-$(CONFIG_SPEAR_I2C) += spr_i2c.o
COBJS-$(CONFIG_TSI108_I2C) += tsi108_i2c.o
COBJS-$(CONFIG_U8500_I2C) += u8500_i2c.o
+COBJS-$(CONFIG_SH_I2C) += sh_i2c.o
COBJS := $(COBJS-y)
SRCS := $(COBJS:.o=.c)
diff --git a/drivers/i2c/davinci_i2c.c b/drivers/i2c/davinci_i2c.c
index 5e3406d..2abddfb 100644
--- a/drivers/i2c/davinci_i2c.c
+++ b/drivers/i2c/davinci_i2c.c
@@ -78,13 +78,11 @@
void flush_rx(void)
{
- int dummy;
-
while (1) {
if (!(REG(I2C_STAT) & I2C_STAT_RRDY))
break;
- dummy = REG(I2C_DRR);
+ REG(I2C_DRR);
REG(I2C_STAT) = I2C_STAT_RRDY;
udelay(1000);
}
diff --git a/drivers/i2c/fsl_i2c.c b/drivers/i2c/fsl_i2c.c
index 258be0a..5b017a9 100644
--- a/drivers/i2c/fsl_i2c.c
+++ b/drivers/i2c/fsl_i2c.c
@@ -225,7 +225,7 @@
void
i2c_init(int speed, int slaveadd)
{
- struct fsl_i2c *dev;
+ const struct fsl_i2c *dev;
unsigned int temp;
int bus_num, i;
diff --git a/drivers/i2c/mxs_i2c.c b/drivers/i2c/mxs_i2c.c
new file mode 100644
index 0000000..c8fea32
--- /dev/null
+++ b/drivers/i2c/mxs_i2c.c
@@ -0,0 +1,246 @@
+/*
+ * Freescale i.MX28 I2C Driver
+ *
+ * Copyright (C) 2011 Marek Vasut <marek.vasut@gmail.com>
+ * on behalf of DENX Software Engineering GmbH
+ *
+ * Partly based on Linux kernel i2c-mxs.c driver:
+ * Copyright (C) 2011 Wolfram Sang, Pengutronix e.K.
+ *
+ * Which was based on a (non-working) driver which was:
+ * Copyright (C) 2009-2010 Freescale Semiconductor, Inc. All Rights Reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
+ *
+ */
+
+#include <common.h>
+#include <malloc.h>
+#include <asm/errno.h>
+#include <asm/io.h>
+#include <asm/arch/clock.h>
+#include <asm/arch/imx-regs.h>
+#include <asm/arch/sys_proto.h>
+
+#define MXS_I2C_MAX_TIMEOUT 1000000
+
+void mxs_i2c_reset(void)
+{
+ struct mx28_i2c_regs *i2c_regs = (struct mx28_i2c_regs *)MXS_I2C0_BASE;
+ int ret;
+
+ ret = mx28_reset_block(&i2c_regs->hw_i2c_ctrl0_reg);
+ if (ret) {
+ debug("MXS I2C: Block reset timeout\n");
+ return;
+ }
+
+ writel(I2C_CTRL1_DATA_ENGINE_CMPLT_IRQ | I2C_CTRL1_NO_SLAVE_ACK_IRQ |
+ I2C_CTRL1_EARLY_TERM_IRQ | I2C_CTRL1_MASTER_LOSS_IRQ |
+ I2C_CTRL1_SLAVE_STOP_IRQ | I2C_CTRL1_SLAVE_IRQ,
+ &i2c_regs->hw_i2c_ctrl1_clr);
+
+ writel(I2C_QUEUECTRL_PIO_QUEUE_MODE, &i2c_regs->hw_i2c_queuectrl_set);
+}
+
+void mxs_i2c_setup_read(uint8_t chip, int len)
+{
+ struct mx28_i2c_regs *i2c_regs = (struct mx28_i2c_regs *)MXS_I2C0_BASE;
+
+ writel(I2C_QUEUECMD_RETAIN_CLOCK | I2C_QUEUECMD_PRE_SEND_START |
+ I2C_QUEUECMD_MASTER_MODE | I2C_QUEUECMD_DIRECTION |
+ (1 << I2C_QUEUECMD_XFER_COUNT_OFFSET),
+ &i2c_regs->hw_i2c_queuecmd);
+
+ writel((chip << 1) | 1, &i2c_regs->hw_i2c_data);
+
+ writel(I2C_QUEUECMD_SEND_NAK_ON_LAST | I2C_QUEUECMD_MASTER_MODE |
+ (len << I2C_QUEUECMD_XFER_COUNT_OFFSET) |
+ I2C_QUEUECMD_POST_SEND_STOP, &i2c_regs->hw_i2c_queuecmd);
+
+ writel(I2C_QUEUECTRL_QUEUE_RUN, &i2c_regs->hw_i2c_queuectrl_set);
+}
+
+void mxs_i2c_write(uchar chip, uint addr, int alen,
+ uchar *buf, int blen, int stop)
+{
+ struct mx28_i2c_regs *i2c_regs = (struct mx28_i2c_regs *)MXS_I2C0_BASE;
+ uint32_t data;
+ int i, remain, off;
+
+ if ((alen > 4) || (alen == 0)) {
+ debug("MXS I2C: Invalid address length\n");
+ return;
+ }
+
+ if (stop)
+ stop = I2C_QUEUECMD_POST_SEND_STOP;
+
+ writel(I2C_QUEUECMD_PRE_SEND_START |
+ I2C_QUEUECMD_MASTER_MODE | I2C_QUEUECMD_DIRECTION |
+ ((blen + alen + 1) << I2C_QUEUECMD_XFER_COUNT_OFFSET) | stop,
+ &i2c_regs->hw_i2c_queuecmd);
+
+ data = (chip << 1) << 24;
+
+ for (i = 0; i < alen; i++) {
+ data >>= 8;
+ data |= ((char *)&addr)[i] << 24;
+ if ((i & 3) == 2)
+ writel(data, &i2c_regs->hw_i2c_data);
+ }
+
+ off = i;
+ for (; i < off + blen; i++) {
+ data >>= 8;
+ data |= buf[i - off] << 24;
+ if ((i & 3) == 2)
+ writel(data, &i2c_regs->hw_i2c_data);
+ }
+
+ remain = 24 - ((i & 3) * 8);
+ if (remain)
+ writel(data >> remain, &i2c_regs->hw_i2c_data);
+
+ writel(I2C_QUEUECTRL_QUEUE_RUN, &i2c_regs->hw_i2c_queuectrl_set);
+}
+
+int mxs_i2c_wait_for_ack(void)
+{
+ struct mx28_i2c_regs *i2c_regs = (struct mx28_i2c_regs *)MXS_I2C0_BASE;
+ uint32_t tmp;
+ int timeout = MXS_I2C_MAX_TIMEOUT;
+
+ for (;;) {
+ tmp = readl(&i2c_regs->hw_i2c_ctrl1);
+ if (tmp & I2C_CTRL1_NO_SLAVE_ACK_IRQ) {
+ debug("MXS I2C: No slave ACK\n");
+ goto err;
+ }
+
+ if (tmp & (
+ I2C_CTRL1_EARLY_TERM_IRQ | I2C_CTRL1_MASTER_LOSS_IRQ |
+ I2C_CTRL1_SLAVE_STOP_IRQ | I2C_CTRL1_SLAVE_IRQ)) {
+ debug("MXS I2C: Error (CTRL1 = %08x)\n", tmp);
+ goto err;
+ }
+
+ if (tmp & I2C_CTRL1_DATA_ENGINE_CMPLT_IRQ)
+ break;
+
+ if (!timeout--) {
+ debug("MXS I2C: Operation timed out\n");
+ goto err;
+ }
+
+ udelay(1);
+ }
+
+ return 0;
+
+err:
+ mxs_i2c_reset();
+ return 1;
+}
+
+int i2c_read(uchar chip, uint addr, int alen, uchar *buffer, int len)
+{
+ struct mx28_i2c_regs *i2c_regs = (struct mx28_i2c_regs *)MXS_I2C0_BASE;
+ uint32_t tmp = 0;
+ int ret;
+ int i;
+
+ mxs_i2c_write(chip, addr, alen, NULL, 0, 0);
+ ret = mxs_i2c_wait_for_ack();
+ if (ret) {
+ debug("MXS I2C: Failed writing address\n");
+ return ret;
+ }
+
+ mxs_i2c_setup_read(chip, len);
+ ret = mxs_i2c_wait_for_ack();
+ if (ret) {
+ debug("MXS I2C: Failed reading address\n");
+ return ret;
+ }
+
+ for (i = 0; i < len; i++) {
+ if (!(i & 3)) {
+ while (readl(&i2c_regs->hw_i2c_queuestat) &
+ I2C_QUEUESTAT_RD_QUEUE_EMPTY)
+ ;
+ tmp = readl(&i2c_regs->hw_i2c_queuedata);
+ }
+ buffer[i] = tmp & 0xff;
+ tmp >>= 8;
+ }
+
+ return 0;
+}
+
+int i2c_write(uchar chip, uint addr, int alen, uchar *buffer, int len)
+{
+ int ret;
+ mxs_i2c_write(chip, addr, alen, buffer, len, 1);
+ ret = mxs_i2c_wait_for_ack();
+ if (ret)
+ debug("MXS I2C: Failed writing address\n");
+
+ return ret;
+}
+
+int i2c_probe(uchar chip)
+{
+ int ret;
+ mxs_i2c_write(chip, 0, 1, NULL, 0, 1);
+ ret = mxs_i2c_wait_for_ack();
+ mxs_i2c_reset();
+ return ret;
+}
+
+void i2c_init(int speed, int slaveadd)
+{
+ struct mx28_i2c_regs *i2c_regs = (struct mx28_i2c_regs *)MXS_I2C0_BASE;
+
+ mxs_i2c_reset();
+
+ switch (speed) {
+ case 100000:
+ writel((0x0078 << I2C_TIMING0_HIGH_COUNT_OFFSET) |
+ (0x0030 << I2C_TIMING0_RCV_COUNT_OFFSET),
+ &i2c_regs->hw_i2c_timing0);
+ writel((0x0080 << I2C_TIMING1_LOW_COUNT_OFFSET) |
+ (0x0030 << I2C_TIMING1_XMIT_COUNT_OFFSET),
+ &i2c_regs->hw_i2c_timing1);
+ break;
+ case 400000:
+ writel((0x000f << I2C_TIMING0_HIGH_COUNT_OFFSET) |
+ (0x0007 << I2C_TIMING0_RCV_COUNT_OFFSET),
+ &i2c_regs->hw_i2c_timing0);
+ writel((0x001f << I2C_TIMING1_LOW_COUNT_OFFSET) |
+ (0x000f << I2C_TIMING1_XMIT_COUNT_OFFSET),
+ &i2c_regs->hw_i2c_timing1);
+ break;
+ default:
+ printf("MXS I2C: Invalid speed selected (%d Hz)\n", speed);
+ return;
+ }
+
+ writel((0x0015 << I2C_TIMING2_BUS_FREE_OFFSET) |
+ (0x000d << I2C_TIMING2_LEADIN_COUNT_OFFSET),
+ &i2c_regs->hw_i2c_timing2);
+
+ return;
+}
diff --git a/drivers/i2c/sh_i2c.c b/drivers/i2c/sh_i2c.c
new file mode 100644
index 0000000..fd8cb92
--- /dev/null
+++ b/drivers/i2c/sh_i2c.c
@@ -0,0 +1,292 @@
+/*
+ * Copyright (C) 2011 Renesas Solutions Corp.
+ * Copyright (C) 2011 Nobuhiro Iwamatsu <nobuhiro.iwamatsu.yj@renesas.com>
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <asm/io.h>
+
+/* Every register is 32bit aligned, but only 8bits in size */
+#define ureg(name) u8 name; u8 __pad_##name##0; u16 __pad_##name##1;
+struct sh_i2c {
+ ureg(icdr);
+ ureg(iccr);
+ ureg(icsr);
+ ureg(icic);
+ ureg(iccl);
+ ureg(icch);
+};
+#undef ureg
+
+static struct sh_i2c *base;
+
+/* ICCR */
+#define SH_I2C_ICCR_ICE (1 << 7)
+#define SH_I2C_ICCR_RACK (1 << 6)
+#define SH_I2C_ICCR_RTS (1 << 4)
+#define SH_I2C_ICCR_BUSY (1 << 2)
+#define SH_I2C_ICCR_SCP (1 << 0)
+
+/* ICSR / ICIC */
+#define SH_IC_BUSY (1 << 3)
+#define SH_IC_TACK (1 << 2)
+#define SH_IC_WAIT (1 << 1)
+#define SH_IC_DTE (1 << 0)
+
+static u8 iccl, icch;
+
+#define IRQ_WAIT 1000
+
+static void irq_wait(struct sh_i2c *base)
+{
+ int i;
+ u8 status;
+
+ for (i = 0 ; i < IRQ_WAIT ; i++) {
+ status = readb(&base->icsr);
+ if (SH_IC_WAIT & status)
+ break;
+
+ udelay(10);
+ }
+
+ writeb(status & ~SH_IC_WAIT, &base->icsr);
+}
+
+static void irq_dte(struct sh_i2c *base)
+{
+ int i;
+
+ for (i = 0 ; i < IRQ_WAIT ; i++) {
+ if (SH_IC_DTE & readb(&base->icsr))
+ break;
+ udelay(10);
+ }
+}
+
+static void irq_busy(struct sh_i2c *base)
+{
+ int i;
+
+ for (i = 0 ; i < IRQ_WAIT ; i++) {
+ if (!(SH_IC_BUSY & readb(&base->icsr)))
+ break;
+ udelay(10);
+ }
+}
+
+static void i2c_set_addr(struct sh_i2c *base, u8 id, u8 reg, int stop)
+{
+ writeb(readb(&base->iccr) & ~SH_I2C_ICCR_ICE, &base->iccr);
+ writeb(readb(&base->iccr) | SH_I2C_ICCR_ICE, &base->iccr);
+
+ writeb(iccl, &base->iccl);
+ writeb(icch, &base->icch);
+ writeb(0, &base->icic);
+
+ writeb((SH_I2C_ICCR_ICE|SH_I2C_ICCR_RTS|SH_I2C_ICCR_BUSY), &base->iccr);
+ irq_dte(base);
+
+ writeb(id << 1, &base->icdr);
+ irq_dte(base);
+
+ writeb(reg, &base->icdr);
+ if (stop)
+ writeb((SH_I2C_ICCR_ICE|SH_I2C_ICCR_RTS), &base->iccr);
+
+ irq_dte(base);
+}
+
+static void i2c_finish(struct sh_i2c *base)
+{
+ writeb(0, &base->icsr);
+ writeb(readb(&base->iccr) & ~SH_I2C_ICCR_ICE, &base->iccr);
+}
+
+static void i2c_raw_write(struct sh_i2c *base, u8 id, u8 reg, u8 val)
+{
+ i2c_set_addr(base, id, reg, 0);
+ udelay(10);
+
+ writeb(val, &base->icdr);
+ irq_dte(base);
+
+ writeb((SH_I2C_ICCR_ICE | SH_I2C_ICCR_RTS), &base->iccr);
+ irq_dte(base);
+ irq_busy(base);
+
+ i2c_finish(base);
+}
+
+static u8 i2c_raw_read(struct sh_i2c *base, u8 id, u8 reg)
+{
+ u8 ret;
+
+ i2c_set_addr(base, id, reg, 1);
+ udelay(100);
+
+ writeb((SH_I2C_ICCR_ICE|SH_I2C_ICCR_RTS|SH_I2C_ICCR_BUSY), &base->iccr);
+ irq_dte(base);
+
+ writeb(id << 1 | 0x01, &base->icdr);
+ irq_dte(base);
+
+ writeb((SH_I2C_ICCR_ICE|SH_I2C_ICCR_SCP), &base->iccr);
+ irq_dte(base);
+
+ ret = readb(&base->icdr);
+
+ writeb((SH_I2C_ICCR_ICE|SH_I2C_ICCR_RACK), &base->iccr);
+ readb(&base->icdr); /* Dummy read */
+ irq_busy(base);
+
+ i2c_finish(base);
+
+ return ret;
+}
+
+#ifdef CONFIG_I2C_MULTI_BUS
+static unsigned int current_bus;
+
+/**
+ * i2c_set_bus_num - change active I2C bus
+ * @bus: bus index, zero based
+ * @returns: 0 on success, non-0 on failure
+ */
+int i2c_set_bus_num(unsigned int bus)
+{
+ if ((bus < 0) || (bus >= CONFIG_SYS_MAX_I2C_BUS)) {
+ printf("Bad bus: %d\n", bus);
+ return -1;
+ }
+
+ switch (bus) {
+ case 0:
+ base = (void *)CONFIG_SH_I2C_BASE0;
+ break;
+ case 1:
+ base = (void *)CONFIG_SH_I2C_BASE1;
+ break;
+ default:
+ return -1;
+ }
+ current_bus = bus;
+
+ return 0;
+}
+
+/**
+ * i2c_get_bus_num - returns index of active I2C bus
+ */
+unsigned int i2c_get_bus_num(void)
+{
+ return current_bus;
+}
+#endif
+
+#define SH_I2C_ICCL_CALC(clk, date, t_low, t_high) \
+ ((clk / rate) * (t_low / t_low + t_high))
+#define SH_I2C_ICCH_CALC(clk, date, t_low, t_high) \
+ ((clk / rate) * (t_high / t_low + t_high))
+
+void i2c_init(int speed, int slaveaddr)
+{
+ int num, denom, tmp;
+
+#ifdef CONFIG_I2C_MULTI_BUS
+ current_bus = 0;
+#endif
+ base = (struct sh_i2c *)CONFIG_SH_I2C_BASE0;
+
+ /*
+ * Calculate the value for iccl. From the data sheet:
+ * iccl = (p-clock / transfer-rate) * (L / (L + H))
+ * where L and H are the SCL low and high ratio.
+ */
+ num = CONFIG_SH_I2C_CLOCK * CONFIG_SH_I2C_DATA_LOW;
+ denom = speed * (CONFIG_SH_I2C_DATA_HIGH + CONFIG_SH_I2C_DATA_LOW);
+ tmp = num * 10 / denom;
+ if (tmp % 10 >= 5)
+ iccl = (u8)((num/denom) + 1);
+ else
+ iccl = (u8)(num/denom);
+
+ /* Calculate the value for icch. From the data sheet:
+ icch = (p clock / transfer rate) * (H / (L + H)) */
+ num = CONFIG_SH_I2C_CLOCK * CONFIG_SH_I2C_DATA_HIGH;
+ tmp = num * 10 / denom;
+ if (tmp % 10 >= 5)
+ icch = (u8)((num/denom) + 1);
+ else
+ icch = (u8)(num/denom);
+}
+
+/*
+ * i2c_read: - Read multiple bytes from an i2c device
+ *
+ * The higher level routines take into account that this function is only
+ * called with len < page length of the device (see configuration file)
+ *
+ * @chip: address of the chip which is to be read
+ * @addr: i2c data address within the chip
+ * @alen: length of the i2c data address (1..2 bytes)
+ * @buffer: where to write the data
+ * @len: how much byte do we want to read
+ * @return: 0 in case of success
+ */
+int i2c_read(u8 chip, u32 addr, int alen, u8 *buffer, int len)
+{
+ int i = 0;
+ for (i = 0 ; i < len ; i++)
+ buffer[i] = i2c_raw_read(base, chip, addr + i);
+
+ return 0;
+}
+
+/*
+ * i2c_write: - Write multiple bytes to an i2c device
+ *
+ * The higher level routines take into account that this function is only
+ * called with len < page length of the device (see configuration file)
+ *
+ * @chip: address of the chip which is to be written
+ * @addr: i2c data address within the chip
+ * @alen: length of the i2c data address (1..2 bytes)
+ * @buffer: where to find the data to be written
+ * @len: how much byte do we want to read
+ * @return: 0 in case of success
+ */
+int i2c_write(u8 chip, u32 addr, int alen, u8 *buffer, int len)
+{
+ int i = 0;
+ for (i = 0; i < len ; i++)
+ i2c_raw_write(base, chip, addr + i, buffer[i]);
+
+ return 0;
+}
+
+/*
+ * i2c_probe: - Test if a chip answers for a given i2c address
+ *
+ * @chip: address of the chip which is searched for
+ * @return: 0 if a chip was found, -1 otherwhise
+ */
+int i2c_probe(u8 chip)
+{
+ return 0;
+}
diff --git a/drivers/mmc/Makefile b/drivers/mmc/Makefile
index 9f9db75..506f1d6 100644
--- a/drivers/mmc/Makefile
+++ b/drivers/mmc/Makefile
@@ -36,6 +36,7 @@
COBJS-$(CONFIG_ARM_PL180_MMCI) += arm_pl180_mmci.o
COBJS-$(CONFIG_MV_SDHCI) += mv_sdhci.o
COBJS-$(CONFIG_MXC_MMC) += mxcmmc.o
+COBJS-$(CONFIG_MXS_MMC) += mxsmmc.o
COBJS-$(CONFIG_OMAP_HSMMC) += omap_hsmmc.o
COBJS-$(CONFIG_PXA_MMC) += pxa_mmc.o
COBJS-$(CONFIG_PXA_MMC_GENERIC) += pxa_mmc_gen.o
diff --git a/drivers/mmc/arm_pl180_mmci.c b/drivers/mmc/arm_pl180_mmci.c
index ed296ee..e6467a2 100644
--- a/drivers/mmc/arm_pl180_mmci.c
+++ b/drivers/mmc/arm_pl180_mmci.c
@@ -111,7 +111,6 @@
static int read_bytes(struct mmc *dev, u32 *dest, u32 blkcount, u32 blksize)
{
u32 *tempbuff = dest;
- int i;
u64 xfercount = blkcount * blksize;
struct mmc_host *host = dev->priv;
u32 status, status_err;
@@ -121,31 +120,6 @@
status = readl(&host->base->status);
status_err = status & (SDI_STA_DCRCFAIL | SDI_STA_DTIMEOUT |
SDI_STA_RXOVERR);
- while (!status_err &&
- (xfercount >= SDI_FIFO_BURST_SIZE * sizeof(u32))) {
- if (status & SDI_STA_RXFIFOBR) {
- for (i = 0; i < SDI_FIFO_BURST_SIZE; i++)
- *(tempbuff + i) = readl(&host->base->fifo);
- tempbuff += SDI_FIFO_BURST_SIZE;
- xfercount -= SDI_FIFO_BURST_SIZE * sizeof(u32);
- }
- status = readl(&host->base->status);
- status_err = status &
- (SDI_STA_DCRCFAIL | SDI_STA_DTIMEOUT | SDI_STA_RXOVERR);
- }
-
- if (status & SDI_STA_DTIMEOUT) {
- printf("Read data timed out, xfercount: %llu, status: 0x%08X\n",
- xfercount, status);
- return -ETIMEDOUT;
- } else if (status & SDI_STA_DCRCFAIL) {
- printf("Read data blk CRC error: 0x%x\n", status);
- return -EILSEQ;
- } else if (status & SDI_STA_RXOVERR) {
- printf("Read data RX overflow error\n");
- return -EIO;
- }
-
while ((!status_err) && (xfercount >= sizeof(u32))) {
if (status & SDI_STA_RXDAVL) {
*(tempbuff) = readl(&host->base->fifo);
diff --git a/drivers/mmc/davinci_mmc.c b/drivers/mmc/davinci_mmc.c
index 5d918e6..ce96736 100644
--- a/drivers/mmc/davinci_mmc.c
+++ b/drivers/mmc/davinci_mmc.c
@@ -69,8 +69,8 @@
static int
dmmc_wait_fifo_status(volatile struct davinci_mmc_regs *regs, uint status)
{
- uint mmcstatus1, wdog = WATCHDOG_COUNT;
- mmcstatus1 = get_val(®s->mmcst1);
+ uint wdog = WATCHDOG_COUNT;
+
while (--wdog && ((get_val(®s->mmcst1) & status) != status))
udelay(10);
@@ -86,9 +86,8 @@
/* Busy bit wait loop for MMCST1 */
static int dmmc_busy_wait(volatile struct davinci_mmc_regs *regs)
{
- uint mmcstatus1, wdog = WATCHDOG_COUNT;
+ uint wdog = WATCHDOG_COUNT;
- mmcstatus1 = get_val(®s->mmcst1);
while (--wdog && (get_val(®s->mmcst1) & MMCST1_BUSY))
udelay(10);
diff --git a/drivers/mmc/mxsmmc.c b/drivers/mmc/mxsmmc.c
new file mode 100644
index 0000000..2a9949e
--- /dev/null
+++ b/drivers/mmc/mxsmmc.c
@@ -0,0 +1,351 @@
+/*
+ * Freescale i.MX28 SSP MMC driver
+ *
+ * Copyright (C) 2011 Marek Vasut <marek.vasut@gmail.com>
+ * on behalf of DENX Software Engineering GmbH
+ *
+ * Based on code from LTIB:
+ * (C) Copyright 2008-2010 Freescale Semiconductor, Inc.
+ * Terry Lv
+ *
+ * Copyright 2007, Freescale Semiconductor, Inc
+ * Andy Fleming
+ *
+ * Based vaguely on the pxa mmc code:
+ * (C) Copyright 2003
+ * Kyle Harris, Nexus Technologies, Inc. kharris@nexus-tech.net
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+#include <common.h>
+#include <malloc.h>
+#include <mmc.h>
+#include <asm/errno.h>
+#include <asm/io.h>
+#include <asm/arch/clock.h>
+#include <asm/arch/imx-regs.h>
+#include <asm/arch/sys_proto.h>
+
+struct mxsmmc_priv {
+ int id;
+ struct mx28_ssp_regs *regs;
+ uint32_t clkseq_bypass;
+ uint32_t *clkctrl_ssp;
+ uint32_t buswidth;
+ int (*mmc_is_wp)(int);
+};
+
+#define MXSMMC_MAX_TIMEOUT 10000
+
+/*
+ * Sends a command out on the bus. Takes the mmc pointer,
+ * a command pointer, and an optional data pointer.
+ */
+static int
+mxsmmc_send_cmd(struct mmc *mmc, struct mmc_cmd *cmd, struct mmc_data *data)
+{
+ struct mxsmmc_priv *priv = (struct mxsmmc_priv *)mmc->priv;
+ struct mx28_ssp_regs *ssp_regs = priv->regs;
+ uint32_t reg;
+ int timeout;
+ uint32_t data_count;
+ uint32_t *data_ptr;
+ uint32_t ctrl0;
+
+ debug("MMC%d: CMD%d\n", mmc->block_dev.dev, cmd->cmdidx);
+
+ /* Check bus busy */
+ timeout = MXSMMC_MAX_TIMEOUT;
+ while (--timeout) {
+ udelay(1000);
+ reg = readl(&ssp_regs->hw_ssp_status);
+ if (!(reg &
+ (SSP_STATUS_BUSY | SSP_STATUS_DATA_BUSY |
+ SSP_STATUS_CMD_BUSY))) {
+ break;
+ }
+ }
+
+ if (!timeout) {
+ printf("MMC%d: Bus busy timeout!\n", mmc->block_dev.dev);
+ return TIMEOUT;
+ }
+
+ /* See if card is present */
+ if (readl(&ssp_regs->hw_ssp_status) & SSP_STATUS_CARD_DETECT) {
+ printf("MMC%d: No card detected!\n", mmc->block_dev.dev);
+ return NO_CARD_ERR;
+ }
+
+ /* Start building CTRL0 contents */
+ ctrl0 = priv->buswidth;
+
+ /* Set up command */
+ if (!(cmd->resp_type & MMC_RSP_CRC))
+ ctrl0 |= SSP_CTRL0_IGNORE_CRC;
+ if (cmd->resp_type & MMC_RSP_PRESENT) /* Need to get response */
+ ctrl0 |= SSP_CTRL0_GET_RESP;
+ if (cmd->resp_type & MMC_RSP_136) /* It's a 136 bits response */
+ ctrl0 |= SSP_CTRL0_LONG_RESP;
+
+ /* Command index */
+ reg = readl(&ssp_regs->hw_ssp_cmd0);
+ reg &= ~(SSP_CMD0_CMD_MASK | SSP_CMD0_APPEND_8CYC);
+ reg |= cmd->cmdidx << SSP_CMD0_CMD_OFFSET;
+ if (cmd->cmdidx == MMC_CMD_STOP_TRANSMISSION)
+ reg |= SSP_CMD0_APPEND_8CYC;
+ writel(reg, &ssp_regs->hw_ssp_cmd0);
+
+ /* Command argument */
+ writel(cmd->cmdarg, &ssp_regs->hw_ssp_cmd1);
+
+ /* Set up data */
+ if (data) {
+ /* READ or WRITE */
+ if (data->flags & MMC_DATA_READ) {
+ ctrl0 |= SSP_CTRL0_READ;
+ } else if (priv->mmc_is_wp(mmc->block_dev.dev)) {
+ printf("MMC%d: Can not write a locked card!\n",
+ mmc->block_dev.dev);
+ return UNUSABLE_ERR;
+ }
+
+ ctrl0 |= SSP_CTRL0_DATA_XFER;
+ reg = ((data->blocks - 1) <<
+ SSP_BLOCK_SIZE_BLOCK_COUNT_OFFSET) |
+ ((ffs(data->blocksize) - 1) <<
+ SSP_BLOCK_SIZE_BLOCK_SIZE_OFFSET);
+ writel(reg, &ssp_regs->hw_ssp_block_size);
+
+ reg = data->blocksize * data->blocks;
+ writel(reg, &ssp_regs->hw_ssp_xfer_size);
+ }
+
+ /* Kick off the command */
+ ctrl0 |= SSP_CTRL0_WAIT_FOR_IRQ | SSP_CTRL0_ENABLE | SSP_CTRL0_RUN;
+ writel(ctrl0, &ssp_regs->hw_ssp_ctrl0);
+
+ /* Wait for the command to complete */
+ timeout = MXSMMC_MAX_TIMEOUT;
+ while (--timeout) {
+ udelay(1000);
+ reg = readl(&ssp_regs->hw_ssp_status);
+ if (!(reg & SSP_STATUS_CMD_BUSY))
+ break;
+ }
+
+ if (!timeout) {
+ printf("MMC%d: Command %d busy\n",
+ mmc->block_dev.dev, cmd->cmdidx);
+ return TIMEOUT;
+ }
+
+ /* Check command timeout */
+ if (reg & SSP_STATUS_RESP_TIMEOUT) {
+ printf("MMC%d: Command %d timeout (status 0x%08x)\n",
+ mmc->block_dev.dev, cmd->cmdidx, reg);
+ return TIMEOUT;
+ }
+
+ /* Check command errors */
+ if (reg & (SSP_STATUS_RESP_CRC_ERR | SSP_STATUS_RESP_ERR)) {
+ printf("MMC%d: Command %d error (status 0x%08x)!\n",
+ mmc->block_dev.dev, cmd->cmdidx, reg);
+ return COMM_ERR;
+ }
+
+ /* Copy response to response buffer */
+ if (cmd->resp_type & MMC_RSP_136) {
+ cmd->response[3] = readl(&ssp_regs->hw_ssp_sdresp0);
+ cmd->response[2] = readl(&ssp_regs->hw_ssp_sdresp1);
+ cmd->response[1] = readl(&ssp_regs->hw_ssp_sdresp2);
+ cmd->response[0] = readl(&ssp_regs->hw_ssp_sdresp3);
+ } else
+ cmd->response[0] = readl(&ssp_regs->hw_ssp_sdresp0);
+
+ /* Return if no data to process */
+ if (!data)
+ return 0;
+
+ /* Process the data */
+ data_count = data->blocksize * data->blocks;
+ timeout = MXSMMC_MAX_TIMEOUT;
+ if (data->flags & MMC_DATA_READ) {
+ data_ptr = (uint32_t *)data->dest;
+ while (data_count && --timeout) {
+ reg = readl(&ssp_regs->hw_ssp_status);
+ if (!(reg & SSP_STATUS_FIFO_EMPTY)) {
+ *data_ptr++ = readl(&ssp_regs->hw_ssp_data);
+ data_count -= 4;
+ timeout = MXSMMC_MAX_TIMEOUT;
+ } else
+ udelay(1000);
+ }
+ } else {
+ data_ptr = (uint32_t *)data->src;
+ timeout *= 100;
+ while (data_count && --timeout) {
+ reg = readl(&ssp_regs->hw_ssp_status);
+ if (!(reg & SSP_STATUS_FIFO_FULL)) {
+ writel(*data_ptr++, &ssp_regs->hw_ssp_data);
+ data_count -= 4;
+ timeout = MXSMMC_MAX_TIMEOUT;
+ } else
+ udelay(1000);
+ }
+ }
+
+ if (!timeout) {
+ printf("MMC%d: Data timeout with command %d (status 0x%08x)!\n",
+ mmc->block_dev.dev, cmd->cmdidx, reg);
+ return COMM_ERR;
+ }
+
+ /* Check data errors */
+ reg = readl(&ssp_regs->hw_ssp_status);
+ if (reg &
+ (SSP_STATUS_TIMEOUT | SSP_STATUS_DATA_CRC_ERR |
+ SSP_STATUS_FIFO_OVRFLW | SSP_STATUS_FIFO_UNDRFLW)) {
+ printf("MMC%d: Data error with command %d (status 0x%08x)!\n",
+ mmc->block_dev.dev, cmd->cmdidx, reg);
+ return COMM_ERR;
+ }
+
+ return 0;
+}
+
+static void mxsmmc_set_ios(struct mmc *mmc)
+{
+ struct mxsmmc_priv *priv = (struct mxsmmc_priv *)mmc->priv;
+ struct mx28_ssp_regs *ssp_regs = priv->regs;
+
+ /* Set the clock speed */
+ if (mmc->clock)
+ mx28_set_ssp_busclock(priv->id, mmc->clock / 1000);
+
+ switch (mmc->bus_width) {
+ case 1:
+ priv->buswidth = SSP_CTRL0_BUS_WIDTH_ONE_BIT;
+ break;
+ case 4:
+ priv->buswidth = SSP_CTRL0_BUS_WIDTH_FOUR_BIT;
+ break;
+ case 8:
+ priv->buswidth = SSP_CTRL0_BUS_WIDTH_EIGHT_BIT;
+ break;
+ }
+
+ /* Set the bus width */
+ clrsetbits_le32(&ssp_regs->hw_ssp_ctrl0,
+ SSP_CTRL0_BUS_WIDTH_MASK, priv->buswidth);
+
+ debug("MMC%d: Set %d bits bus width\n",
+ mmc->block_dev.dev, mmc->bus_width);
+}
+
+static int mxsmmc_init(struct mmc *mmc)
+{
+ struct mxsmmc_priv *priv = (struct mxsmmc_priv *)mmc->priv;
+ struct mx28_ssp_regs *ssp_regs = priv->regs;
+
+ /* Reset SSP */
+ mx28_reset_block(&ssp_regs->hw_ssp_ctrl0_reg);
+
+ /* 8 bits word length in MMC mode */
+ clrsetbits_le32(&ssp_regs->hw_ssp_ctrl1,
+ SSP_CTRL1_SSP_MODE_MASK | SSP_CTRL1_WORD_LENGTH_MASK,
+ SSP_CTRL1_SSP_MODE_SD_MMC | SSP_CTRL1_WORD_LENGTH_EIGHT_BITS);
+
+ /* Set initial bit clock 400 KHz */
+ mx28_set_ssp_busclock(priv->id, 400);
+
+ /* Send initial 74 clock cycles (185 us @ 400 KHz)*/
+ writel(SSP_CMD0_CONT_CLKING_EN, &ssp_regs->hw_ssp_cmd0_set);
+ udelay(200);
+ writel(SSP_CMD0_CONT_CLKING_EN, &ssp_regs->hw_ssp_cmd0_clr);
+
+ return 0;
+}
+
+int mxsmmc_initialize(bd_t *bis, int id, int (*wp)(int))
+{
+ struct mx28_clkctrl_regs *clkctrl_regs =
+ (struct mx28_clkctrl_regs *)MXS_CLKCTRL_BASE;
+ struct mmc *mmc = NULL;
+ struct mxsmmc_priv *priv = NULL;
+
+ mmc = malloc(sizeof(struct mmc));
+ if (!mmc)
+ return -ENOMEM;
+
+ priv = malloc(sizeof(struct mxsmmc_priv));
+ if (!priv) {
+ free(mmc);
+ return -ENOMEM;
+ }
+
+ priv->mmc_is_wp = wp;
+ priv->id = id;
+ switch (id) {
+ case 0:
+ priv->regs = (struct mx28_ssp_regs *)MXS_SSP0_BASE;
+ priv->clkseq_bypass = CLKCTRL_CLKSEQ_BYPASS_SSP0;
+ priv->clkctrl_ssp = &clkctrl_regs->hw_clkctrl_ssp0;
+ break;
+ case 1:
+ priv->regs = (struct mx28_ssp_regs *)MXS_SSP1_BASE;
+ priv->clkseq_bypass = CLKCTRL_CLKSEQ_BYPASS_SSP1;
+ priv->clkctrl_ssp = &clkctrl_regs->hw_clkctrl_ssp1;
+ break;
+ case 2:
+ priv->regs = (struct mx28_ssp_regs *)MXS_SSP2_BASE;
+ priv->clkseq_bypass = CLKCTRL_CLKSEQ_BYPASS_SSP2;
+ priv->clkctrl_ssp = &clkctrl_regs->hw_clkctrl_ssp2;
+ break;
+ case 3:
+ priv->regs = (struct mx28_ssp_regs *)MXS_SSP3_BASE;
+ priv->clkseq_bypass = CLKCTRL_CLKSEQ_BYPASS_SSP3;
+ priv->clkctrl_ssp = &clkctrl_regs->hw_clkctrl_ssp3;
+ break;
+ }
+
+ sprintf(mmc->name, "MXS MMC");
+ mmc->send_cmd = mxsmmc_send_cmd;
+ mmc->set_ios = mxsmmc_set_ios;
+ mmc->init = mxsmmc_init;
+ mmc->priv = priv;
+
+ mmc->voltages = MMC_VDD_32_33 | MMC_VDD_33_34;
+
+ mmc->host_caps = MMC_MODE_4BIT | MMC_MODE_8BIT |
+ MMC_MODE_HS_52MHz | MMC_MODE_HS;
+
+ /*
+ * SSPCLK = 480 * 18 / 29 / 1 = 297.731 MHz
+ * SSP bit rate = SSPCLK / (CLOCK_DIVIDE * (1 + CLOCK_RATE)),
+ * CLOCK_DIVIDE has to be an even value from 2 to 254, and
+ * CLOCK_RATE could be any integer from 0 to 255.
+ */
+ mmc->f_min = 400000;
+ mmc->f_max = mxc_get_clock(MXC_SSP0_CLK + id) * 1000 / 2;
+ mmc->b_max = 0;
+
+ mmc_register(mmc);
+ return 0;
+}
diff --git a/drivers/mmc/omap_hsmmc.c b/drivers/mmc/omap_hsmmc.c
index ebda980..c38b9e6 100644
--- a/drivers/mmc/omap_hsmmc.c
+++ b/drivers/mmc/omap_hsmmc.c
@@ -36,8 +36,9 @@
/* If we fail after 1 second wait, something is really bad */
#define MAX_RETRY_MS 1000
-static int mmc_read_data(hsmmc_t *mmc_base, char *buf, unsigned int size);
-static int mmc_write_data(hsmmc_t *mmc_base, const char *buf, unsigned int siz);
+static int mmc_read_data(struct hsmmc *mmc_base, char *buf, unsigned int size);
+static int mmc_write_data(struct hsmmc *mmc_base, const char *buf,
+ unsigned int siz);
static struct mmc hsmmc_dev[2];
#if defined(CONFIG_OMAP44XX) && defined(CONFIG_TWL6030_POWER)
@@ -97,7 +98,7 @@
return 0;
}
-void mmc_init_stream(hsmmc_t *mmc_base)
+void mmc_init_stream(struct hsmmc *mmc_base)
{
ulong start;
@@ -128,7 +129,7 @@
static int mmc_init_setup(struct mmc *mmc)
{
- hsmmc_t *mmc_base = (hsmmc_t *)mmc->priv;
+ struct hsmmc *mmc_base = (struct hsmmc *)mmc->priv;
unsigned int reg_val;
unsigned int dsor;
ulong start;
@@ -192,7 +193,7 @@
static int mmc_send_cmd(struct mmc *mmc, struct mmc_cmd *cmd,
struct mmc_data *data)
{
- hsmmc_t *mmc_base = (hsmmc_t *)mmc->priv;
+ struct hsmmc *mmc_base = (struct hsmmc *)mmc->priv;
unsigned int flags, mmc_stat;
ulong start;
@@ -305,7 +306,7 @@
return 0;
}
-static int mmc_read_data(hsmmc_t *mmc_base, char *buf, unsigned int size)
+static int mmc_read_data(struct hsmmc *mmc_base, char *buf, unsigned int size)
{
unsigned int *output_buf = (unsigned int *)buf;
unsigned int mmc_stat;
@@ -356,7 +357,8 @@
return 0;
}
-static int mmc_write_data(hsmmc_t *mmc_base, const char *buf, unsigned int size)
+static int mmc_write_data(struct hsmmc *mmc_base, const char *buf,
+ unsigned int size)
{
unsigned int *input_buf = (unsigned int *)buf;
unsigned int mmc_stat;
@@ -409,7 +411,7 @@
static void mmc_set_ios(struct mmc *mmc)
{
- hsmmc_t *mmc_base = (hsmmc_t *)mmc->priv;
+ struct hsmmc *mmc_base = (struct hsmmc *)mmc->priv;
unsigned int dsor = 0;
ulong start;
@@ -473,20 +475,20 @@
switch (dev_index) {
case 0:
- mmc->priv = (hsmmc_t *)OMAP_HSMMC1_BASE;
+ mmc->priv = (struct hsmmc *)OMAP_HSMMC1_BASE;
break;
#ifdef OMAP_HSMMC2_BASE
case 1:
- mmc->priv = (hsmmc_t *)OMAP_HSMMC2_BASE;
+ mmc->priv = (struct hsmmc *)OMAP_HSMMC2_BASE;
break;
#endif
#ifdef OMAP_HSMMC3_BASE
case 2:
- mmc->priv = (hsmmc_t *)OMAP_HSMMC3_BASE;
+ mmc->priv = (struct hsmmc *)OMAP_HSMMC3_BASE;
break;
#endif
default:
- mmc->priv = (hsmmc_t *)OMAP_HSMMC1_BASE;
+ mmc->priv = (struct hsmmc *)OMAP_HSMMC1_BASE;
return 1;
}
mmc->voltages = MMC_VDD_32_33 | MMC_VDD_33_34 | MMC_VDD_165_195;
diff --git a/drivers/mmc/tegra2_mmc.c b/drivers/mmc/tegra2_mmc.c
index 78b1190..ccf48bb 100644
--- a/drivers/mmc/tegra2_mmc.c
+++ b/drivers/mmc/tegra2_mmc.c
@@ -81,7 +81,8 @@
* 11 = Selects 64-bit Address ADMA2
*/
ctrl = readb(&host->reg->hostctl);
- ctrl &= ~(3 << 3); /* SDMA */
+ ctrl &= ~TEGRA_MMC_HOSTCTL_DMASEL_MASK;
+ ctrl |= TEGRA_MMC_HOSTCTL_DMASEL_SDMA;
writeb(ctrl, &host->reg->hostctl);
/* We do not handle DMA boundaries, so set it to max (512 KiB) */
@@ -103,43 +104,36 @@
* ENBLKCNT[1] : Block Count Enable
* ENDMA[0] : DMA Enable
*/
- mode = (1 << 1) | (1 << 0);
+ mode = (TEGRA_MMC_TRNMOD_DMA_ENABLE |
+ TEGRA_MMC_TRNMOD_BLOCK_COUNT_ENABLE);
+
if (data->blocks > 1)
- mode |= (1 << 5);
+ mode |= TEGRA_MMC_TRNMOD_MULTI_BLOCK_SELECT;
+
if (data->flags & MMC_DATA_READ)
- mode |= (1 << 4);
+ mode |= TEGRA_MMC_TRNMOD_DATA_XFER_DIR_SEL_READ;
writew(mode, &host->reg->trnmod);
}
-static int mmc_send_cmd(struct mmc *mmc, struct mmc_cmd *cmd,
- struct mmc_data *data)
+static int mmc_wait_inhibit(struct mmc_host *host,
+ struct mmc_cmd *cmd,
+ struct mmc_data *data,
+ unsigned int timeout)
{
- struct mmc_host *host = (struct mmc_host *)mmc->priv;
- int flags, i;
- unsigned int timeout;
- unsigned int mask;
- unsigned int retry = 0x100000;
- debug(" mmc_send_cmd called\n");
-
- /* Wait max 10 ms */
- timeout = 10;
-
/*
* PRNSTS
- * CMDINHDAT[1] : Command Inhibit (DAT)
- * CMDINHCMD[0] : Command Inhibit (CMD)
+ * CMDINHDAT[1] : Command Inhibit (DAT)
+ * CMDINHCMD[0] : Command Inhibit (CMD)
*/
- mask = (1 << 0);
- if ((data != NULL) || (cmd->resp_type & MMC_RSP_BUSY))
- mask |= (1 << 1);
+ unsigned int mask = TEGRA_MMC_PRNSTS_CMD_INHIBIT_CMD;
/*
* We shouldn't wait for data inhibit for stop commands, even
* though they might use busy signaling
*/
- if (data)
- mask &= ~(1 << 1);
+ if ((data == NULL) && (cmd->resp_type & MMC_RSP_BUSY))
+ mask |= TEGRA_MMC_PRNSTS_CMD_INHIBIT_DAT;
while (readl(&host->reg->prnsts) & mask) {
if (timeout == 0) {
@@ -150,6 +144,24 @@
udelay(1000);
}
+ return 0;
+}
+
+static int mmc_send_cmd(struct mmc *mmc, struct mmc_cmd *cmd,
+ struct mmc_data *data)
+{
+ struct mmc_host *host = (struct mmc_host *)mmc->priv;
+ int flags, i;
+ int result;
+ unsigned int mask;
+ unsigned int retry = 0x100000;
+ debug(" mmc_send_cmd called\n");
+
+ result = mmc_wait_inhibit(host, cmd, data, 10 /* ms */);
+
+ if (result < 0)
+ return result;
+
if (data)
mmc_prepare_data(host, data);
@@ -175,20 +187,20 @@
* 11 = Length 48 Check busy after response
*/
if (!(cmd->resp_type & MMC_RSP_PRESENT))
- flags = 0;
+ flags = TEGRA_MMC_CMDREG_RESP_TYPE_SELECT_NO_RESPONSE;
else if (cmd->resp_type & MMC_RSP_136)
- flags = (1 << 0);
+ flags = TEGRA_MMC_CMDREG_RESP_TYPE_SELECT_LENGTH_136;
else if (cmd->resp_type & MMC_RSP_BUSY)
- flags = (3 << 0);
+ flags = TEGRA_MMC_CMDREG_RESP_TYPE_SELECT_LENGTH_48_BUSY;
else
- flags = (2 << 0);
+ flags = TEGRA_MMC_CMDREG_RESP_TYPE_SELECT_LENGTH_48;
if (cmd->resp_type & MMC_RSP_CRC)
- flags |= (1 << 3);
+ flags |= TEGRA_MMC_TRNMOD_CMD_CRC_CHECK;
if (cmd->resp_type & MMC_RSP_OPCODE)
- flags |= (1 << 4);
+ flags |= TEGRA_MMC_TRNMOD_CMD_INDEX_CHECK;
if (data)
- flags |= (1 << 5);
+ flags |= TEGRA_MMC_TRNMOD_DATA_PRESENT_SELECT_DATA_TRANSFER;
debug("cmd: %d\n", cmd->cmdidx);
@@ -197,7 +209,7 @@
for (i = 0; i < retry; i++) {
mask = readl(&host->reg->norintsts);
/* Command Complete */
- if (mask & (1 << 0)) {
+ if (mask & TEGRA_MMC_NORINTSTS_CMD_COMPLETE) {
if (!data)
writel(mask, &host->reg->norintsts);
break;
@@ -209,11 +221,11 @@
return TIMEOUT;
}
- if (mask & (1 << 16)) {
+ if (mask & TEGRA_MMC_NORINTSTS_CMD_TIMEOUT) {
/* Timeout Error */
debug("timeout: %08x cmd %d\n", mask, cmd->cmdidx);
return TIMEOUT;
- } else if (mask & (1 << 15)) {
+ } else if (mask & TEGRA_MMC_NORINTSTS_ERR_INTERRUPT) {
/* Error Interrupt */
debug("error: %08x cmd %d\n", mask, cmd->cmdidx);
return -1;
@@ -256,23 +268,44 @@
}
if (data) {
+ unsigned long start = get_timer(0);
+
while (1) {
mask = readl(&host->reg->norintsts);
- if (mask & (1 << 15)) {
+ if (mask & TEGRA_MMC_NORINTSTS_ERR_INTERRUPT) {
/* Error Interrupt */
writel(mask, &host->reg->norintsts);
printf("%s: error during transfer: 0x%08x\n",
__func__, mask);
return -1;
- } else if (mask & (1 << 3)) {
- /* DMA Interrupt */
+ } else if (mask & TEGRA_MMC_NORINTSTS_DMA_INTERRUPT) {
+ /*
+ * DMA Interrupt, restart the transfer where
+ * it was interrupted.
+ */
+ unsigned int address = readl(&host->reg->sysad);
+
debug("DMA end\n");
- break;
- } else if (mask & (1 << 1)) {
+ writel(TEGRA_MMC_NORINTSTS_DMA_INTERRUPT,
+ &host->reg->norintsts);
+ writel(address, &host->reg->sysad);
+ } else if (mask & TEGRA_MMC_NORINTSTS_XFER_COMPLETE) {
/* Transfer Complete */
debug("r/w is done\n");
break;
+ } else if (get_timer(start) > 2000UL) {
+ writel(mask, &host->reg->norintsts);
+ printf("%s: MMC Timeout\n"
+ " Interrupt status 0x%08x\n"
+ " Interrupt status enable 0x%08x\n"
+ " Interrupt signal enable 0x%08x\n"
+ " Present status 0x%08x\n",
+ __func__, mask,
+ readl(&host->reg->norintstsen),
+ readl(&host->reg->norintsigen),
+ readl(&host->reg->prnsts));
+ return -1;
}
}
writel(mask, &host->reg->norintsts);
@@ -310,12 +343,14 @@
* ENINTCLK[0] : Internal Clock Enable
*/
div >>= 1;
- clk = (div << 8) | (1 << 0);
+ clk = ((div << TEGRA_MMC_CLKCON_SDCLK_FREQ_SEL_SHIFT) |
+ TEGRA_MMC_CLKCON_INTERNAL_CLOCK_ENABLE);
writew(clk, &host->reg->clkcon);
/* Wait max 10 ms */
timeout = 10;
- while (!(readw(&host->reg->clkcon) & (1 << 1))) {
+ while (!(readw(&host->reg->clkcon) &
+ TEGRA_MMC_CLKCON_INTERNAL_CLOCK_STABLE)) {
if (timeout == 0) {
printf("%s: timeout error\n", __func__);
return;
@@ -324,7 +359,7 @@
udelay(1000);
}
- clk |= (1 << 2);
+ clk |= TEGRA_MMC_CLKCON_SD_CLOCK_ENABLE;
writew(clk, &host->reg->clkcon);
debug("mmc_change_clock: clkcon = %08X\n", clk);
@@ -375,7 +410,7 @@
* 1 = reset
* 0 = work
*/
- writeb((1 << 0), &host->reg->swrst);
+ writeb(TEGRA_MMC_SWRST_SW_RESET_FOR_ALL, &host->reg->swrst);
host->clock = 0;
@@ -383,7 +418,7 @@
timeout = 100;
/* hw clears the bit when it's done */
- while (readb(&host->reg->swrst) & (1 << 0)) {
+ while (readb(&host->reg->swrst) & TEGRA_MMC_SWRST_SW_RESET_FOR_ALL) {
if (timeout == 0) {
printf("%s: timeout error\n", __func__);
return;
@@ -413,12 +448,17 @@
* NORMAL Interrupt Status Enable Register init
* [5] ENSTABUFRDRDY : Buffer Read Ready Status Enable
* [4] ENSTABUFWTRDY : Buffer write Ready Status Enable
+ * [3] ENSTADMAINT : DMA boundary interrupt
* [1] ENSTASTANSCMPLT : Transfre Complete Status Enable
* [0] ENSTACMDCMPLT : Command Complete Status Enable
*/
mask = readl(&host->reg->norintstsen);
mask &= ~(0xffff);
- mask |= (1 << 5) | (1 << 4) | (1 << 1) | (1 << 0);
+ mask |= (TEGRA_MMC_NORINTSTSEN_CMD_COMPLETE |
+ TEGRA_MMC_NORINTSTSEN_XFER_COMPLETE |
+ TEGRA_MMC_NORINTSTSEN_DMA_INTERRUPT |
+ TEGRA_MMC_NORINTSTSEN_BUFFER_WRITE_READY |
+ TEGRA_MMC_NORINTSTSEN_BUFFER_READ_READY);
writel(mask, &host->reg->norintstsen);
/*
@@ -427,7 +467,7 @@
*/
mask = readl(&host->reg->norintsigen);
mask &= ~(0xffff);
- mask |= (1 << 1);
+ mask |= TEGRA_MMC_NORINTSIGEN_XFER_COMPLETE;
writel(mask, &host->reg->norintsigen);
return 0;
diff --git a/drivers/mmc/tegra2_mmc.h b/drivers/mmc/tegra2_mmc.h
index 28698e0..671583c 100644
--- a/drivers/mmc/tegra2_mmc.h
+++ b/drivers/mmc/tegra2_mmc.h
@@ -68,6 +68,55 @@
unsigned char res6[0x100]; /* RESERVED, offset 100h-1FFh */
};
+#define TEGRA_MMC_HOSTCTL_DMASEL_MASK (3 << 3)
+#define TEGRA_MMC_HOSTCTL_DMASEL_SDMA (0 << 3)
+#define TEGRA_MMC_HOSTCTL_DMASEL_ADMA2_32BIT (2 << 3)
+#define TEGRA_MMC_HOSTCTL_DMASEL_ADMA2_64BIT (3 << 3)
+
+#define TEGRA_MMC_TRNMOD_DMA_ENABLE (1 << 0)
+#define TEGRA_MMC_TRNMOD_BLOCK_COUNT_ENABLE (1 << 1)
+#define TEGRA_MMC_TRNMOD_DATA_XFER_DIR_SEL_WRITE (0 << 4)
+#define TEGRA_MMC_TRNMOD_DATA_XFER_DIR_SEL_READ (1 << 4)
+#define TEGRA_MMC_TRNMOD_MULTI_BLOCK_SELECT (1 << 5)
+
+#define TEGRA_MMC_CMDREG_RESP_TYPE_SELECT_MASK (3 << 0)
+#define TEGRA_MMC_CMDREG_RESP_TYPE_SELECT_NO_RESPONSE (0 << 0)
+#define TEGRA_MMC_CMDREG_RESP_TYPE_SELECT_LENGTH_136 (1 << 0)
+#define TEGRA_MMC_CMDREG_RESP_TYPE_SELECT_LENGTH_48 (2 << 0)
+#define TEGRA_MMC_CMDREG_RESP_TYPE_SELECT_LENGTH_48_BUSY (3 << 0)
+
+#define TEGRA_MMC_TRNMOD_CMD_CRC_CHECK (1 << 3)
+#define TEGRA_MMC_TRNMOD_CMD_INDEX_CHECK (1 << 4)
+#define TEGRA_MMC_TRNMOD_DATA_PRESENT_SELECT_DATA_TRANSFER (1 << 5)
+
+#define TEGRA_MMC_PRNSTS_CMD_INHIBIT_CMD (1 << 0)
+#define TEGRA_MMC_PRNSTS_CMD_INHIBIT_DAT (1 << 1)
+
+#define TEGRA_MMC_CLKCON_INTERNAL_CLOCK_ENABLE (1 << 0)
+#define TEGRA_MMC_CLKCON_INTERNAL_CLOCK_STABLE (1 << 1)
+#define TEGRA_MMC_CLKCON_SD_CLOCK_ENABLE (1 << 2)
+
+#define TEGRA_MMC_CLKCON_SDCLK_FREQ_SEL_SHIFT 8
+#define TEGRA_MMC_CLKCON_SDCLK_FREQ_SEL_MASK (0xff << 8)
+
+#define TEGRA_MMC_SWRST_SW_RESET_FOR_ALL (1 << 0)
+#define TEGRA_MMC_SWRST_SW_RESET_FOR_CMD_LINE (1 << 1)
+#define TEGRA_MMC_SWRST_SW_RESET_FOR_DAT_LINE (1 << 2)
+
+#define TEGRA_MMC_NORINTSTS_CMD_COMPLETE (1 << 0)
+#define TEGRA_MMC_NORINTSTS_XFER_COMPLETE (1 << 1)
+#define TEGRA_MMC_NORINTSTS_DMA_INTERRUPT (1 << 3)
+#define TEGRA_MMC_NORINTSTS_ERR_INTERRUPT (1 << 15)
+#define TEGRA_MMC_NORINTSTS_CMD_TIMEOUT (1 << 16)
+
+#define TEGRA_MMC_NORINTSTSEN_CMD_COMPLETE (1 << 0)
+#define TEGRA_MMC_NORINTSTSEN_XFER_COMPLETE (1 << 1)
+#define TEGRA_MMC_NORINTSTSEN_DMA_INTERRUPT (1 << 3)
+#define TEGRA_MMC_NORINTSTSEN_BUFFER_WRITE_READY (1 << 4)
+#define TEGRA_MMC_NORINTSTSEN_BUFFER_READ_READY (1 << 5)
+
+#define TEGRA_MMC_NORINTSIGEN_XFER_COMPLETE (1 << 1)
+
struct mmc_host {
struct tegra2_mmc *reg;
unsigned int version; /* SDHCI spec. version */
diff --git a/drivers/mtd/dataflash.c b/drivers/mtd/dataflash.c
index 96cd395..981ccd5 100644
--- a/drivers/mtd/dataflash.c
+++ b/drivers/mtd/dataflash.c
@@ -39,7 +39,6 @@
int i, j;
int dfcode;
int part;
- int last_part;
int found[CONFIG_SYS_MAX_DATAFLASH_BANKS];
unsigned char protected;
@@ -136,7 +135,6 @@
dataflash_info[i].Device.pages_size) - 1;
part = 0;
- last_part = 0;
/* set the area addresses */
for(j = 0; j < NB_DATAFLASH_AREA; j++) {
if(found[i]!=0) {
@@ -147,7 +145,6 @@
dataflash_info[i].Device.area_list[j].end =
dataflash_info[i].end_address +
dataflash_info[i].logical_address;
- last_part = 1;
} else {
dataflash_info[i].Device.area_list[j].end =
area_list[part].end +
diff --git a/drivers/mtd/nand/Makefile b/drivers/mtd/nand/Makefile
index 28bd350..36ee454 100644
--- a/drivers/mtd/nand/Makefile
+++ b/drivers/mtd/nand/Makefile
@@ -54,6 +54,7 @@
COBJS-$(CONFIG_NAND_KMETER1) += kmeter1_nand.o
COBJS-$(CONFIG_NAND_MPC5121_NFC) += mpc5121_nfc.o
COBJS-$(CONFIG_NAND_MXC) += mxc_nand.o
+COBJS-$(CONFIG_NAND_MXS) += mxs_nand.o
COBJS-$(CONFIG_NAND_NDFC) += ndfc.o
COBJS-$(CONFIG_NAND_NOMADIK) += nomadik.o
COBJS-$(CONFIG_NAND_S3C2410) += s3c2410_nand.o
diff --git a/drivers/mtd/nand/mxs_nand.c b/drivers/mtd/nand/mxs_nand.c
new file mode 100644
index 0000000..ce2a326
--- /dev/null
+++ b/drivers/mtd/nand/mxs_nand.c
@@ -0,0 +1,1118 @@
+/*
+ * Freescale i.MX28 NAND flash driver
+ *
+ * Copyright (C) 2011 Marek Vasut <marek.vasut@gmail.com>
+ * on behalf of DENX Software Engineering GmbH
+ *
+ * Based on code from LTIB:
+ * Freescale GPMI NFC NAND Flash Driver
+ *
+ * Copyright (C) 2010 Freescale Semiconductor, Inc.
+ * Copyright (C) 2008 Embedded Alley Solutions, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License along
+ * with this program; if not, write to the Free Software Foundation, Inc.,
+ * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
+ */
+
+#include <linux/mtd/mtd.h>
+#include <linux/mtd/nand.h>
+#include <linux/types.h>
+#include <common.h>
+#include <malloc.h>
+#include <asm/errno.h>
+#include <asm/io.h>
+#include <asm/arch/clock.h>
+#include <asm/arch/imx-regs.h>
+#include <asm/arch/sys_proto.h>
+#include <asm/arch/dma.h>
+
+#define MXS_NAND_DMA_DESCRIPTOR_COUNT 4
+
+#define MXS_NAND_CHUNK_DATA_CHUNK_SIZE 512
+#define MXS_NAND_METADATA_SIZE 10
+
+#define MXS_NAND_COMMAND_BUFFER_SIZE 32
+
+#define MXS_NAND_BCH_TIMEOUT 10000
+
+struct mxs_nand_info {
+ int cur_chip;
+
+ uint32_t cmd_queue_len;
+
+ uint8_t *cmd_buf;
+ uint8_t *data_buf;
+ uint8_t *oob_buf;
+
+ uint8_t marking_block_bad;
+ uint8_t raw_oob_mode;
+
+ /* Functions with altered behaviour */
+ int (*hooked_read_oob)(struct mtd_info *mtd,
+ loff_t from, struct mtd_oob_ops *ops);
+ int (*hooked_write_oob)(struct mtd_info *mtd,
+ loff_t to, struct mtd_oob_ops *ops);
+ int (*hooked_block_markbad)(struct mtd_info *mtd,
+ loff_t ofs);
+
+ /* DMA descriptors */
+ struct mxs_dma_desc **desc;
+ uint32_t desc_index;
+};
+
+struct nand_ecclayout fake_ecc_layout;
+
+static struct mxs_dma_desc *mxs_nand_get_dma_desc(struct mxs_nand_info *info)
+{
+ struct mxs_dma_desc *desc;
+
+ if (info->desc_index >= MXS_NAND_DMA_DESCRIPTOR_COUNT) {
+ printf("MXS NAND: Too many DMA descriptors requested\n");
+ return NULL;
+ }
+
+ desc = info->desc[info->desc_index];
+ info->desc_index++;
+
+ return desc;
+}
+
+static void mxs_nand_return_dma_descs(struct mxs_nand_info *info)
+{
+ int i;
+ struct mxs_dma_desc *desc;
+
+ for (i = 0; i < info->desc_index; i++) {
+ desc = info->desc[i];
+ memset(desc, 0, sizeof(struct mxs_dma_desc));
+ desc->address = (dma_addr_t)desc;
+ }
+
+ info->desc_index = 0;
+}
+
+static uint32_t mxs_nand_ecc_chunk_cnt(uint32_t page_data_size)
+{
+ return page_data_size / MXS_NAND_CHUNK_DATA_CHUNK_SIZE;
+}
+
+static uint32_t mxs_nand_ecc_size_in_bits(uint32_t ecc_strength)
+{
+ return ecc_strength * 13;
+}
+
+static uint32_t mxs_nand_aux_status_offset(void)
+{
+ return (MXS_NAND_METADATA_SIZE + 0x3) & ~0x3;
+}
+
+static inline uint32_t mxs_nand_get_ecc_strength(uint32_t page_data_size,
+ uint32_t page_oob_size)
+{
+ if (page_data_size == 2048)
+ return 8;
+
+ if (page_data_size == 4096) {
+ if (page_oob_size == 128)
+ return 8;
+
+ if (page_oob_size == 218)
+ return 16;
+ }
+
+ return 0;
+}
+
+static inline uint32_t mxs_nand_get_mark_offset(uint32_t page_data_size,
+ uint32_t ecc_strength)
+{
+ uint32_t chunk_data_size_in_bits;
+ uint32_t chunk_ecc_size_in_bits;
+ uint32_t chunk_total_size_in_bits;
+ uint32_t block_mark_chunk_number;
+ uint32_t block_mark_chunk_bit_offset;
+ uint32_t block_mark_bit_offset;
+
+ chunk_data_size_in_bits = MXS_NAND_CHUNK_DATA_CHUNK_SIZE * 8;
+ chunk_ecc_size_in_bits = mxs_nand_ecc_size_in_bits(ecc_strength);
+
+ chunk_total_size_in_bits =
+ chunk_data_size_in_bits + chunk_ecc_size_in_bits;
+
+ /* Compute the bit offset of the block mark within the physical page. */
+ block_mark_bit_offset = page_data_size * 8;
+
+ /* Subtract the metadata bits. */
+ block_mark_bit_offset -= MXS_NAND_METADATA_SIZE * 8;
+
+ /*
+ * Compute the chunk number (starting at zero) in which the block mark
+ * appears.
+ */
+ block_mark_chunk_number =
+ block_mark_bit_offset / chunk_total_size_in_bits;
+
+ /*
+ * Compute the bit offset of the block mark within its chunk, and
+ * validate it.
+ */
+ block_mark_chunk_bit_offset = block_mark_bit_offset -
+ (block_mark_chunk_number * chunk_total_size_in_bits);
+
+ if (block_mark_chunk_bit_offset > chunk_data_size_in_bits)
+ return 1;
+
+ /*
+ * Now that we know the chunk number in which the block mark appears,
+ * we can subtract all the ECC bits that appear before it.
+ */
+ block_mark_bit_offset -=
+ block_mark_chunk_number * chunk_ecc_size_in_bits;
+
+ return block_mark_bit_offset;
+}
+
+static uint32_t mxs_nand_mark_byte_offset(struct mtd_info *mtd)
+{
+ uint32_t ecc_strength;
+ ecc_strength = mxs_nand_get_ecc_strength(mtd->writesize, mtd->oobsize);
+ return mxs_nand_get_mark_offset(mtd->writesize, ecc_strength) >> 3;
+}
+
+static uint32_t mxs_nand_mark_bit_offset(struct mtd_info *mtd)
+{
+ uint32_t ecc_strength;
+ ecc_strength = mxs_nand_get_ecc_strength(mtd->writesize, mtd->oobsize);
+ return mxs_nand_get_mark_offset(mtd->writesize, ecc_strength) & 0x7;
+}
+
+/*
+ * Wait for BCH complete IRQ and clear the IRQ
+ */
+static int mxs_nand_wait_for_bch_complete(void)
+{
+ struct mx28_bch_regs *bch_regs = (struct mx28_bch_regs *)MXS_BCH_BASE;
+ int timeout = MXS_NAND_BCH_TIMEOUT;
+ int ret;
+
+ ret = mx28_wait_mask_set(&bch_regs->hw_bch_ctrl_reg,
+ BCH_CTRL_COMPLETE_IRQ, timeout);
+
+ writel(BCH_CTRL_COMPLETE_IRQ, &bch_regs->hw_bch_ctrl_clr);
+
+ return ret;
+}
+
+/*
+ * This is the function that we install in the cmd_ctrl function pointer of the
+ * owning struct nand_chip. The only functions in the reference implementation
+ * that use these functions pointers are cmdfunc and select_chip.
+ *
+ * In this driver, we implement our own select_chip, so this function will only
+ * be called by the reference implementation's cmdfunc. For this reason, we can
+ * ignore the chip enable bit and concentrate only on sending bytes to the NAND
+ * Flash.
+ */
+static void mxs_nand_cmd_ctrl(struct mtd_info *mtd, int data, unsigned int ctrl)
+{
+ struct nand_chip *nand = mtd->priv;
+ struct mxs_nand_info *nand_info = nand->priv;
+ struct mxs_dma_desc *d;
+ uint32_t channel = MXS_DMA_CHANNEL_AHB_APBH_GPMI0 + nand_info->cur_chip;
+ int ret;
+
+ /*
+ * If this condition is true, something is _VERY_ wrong in MTD
+ * subsystem!
+ */
+ if (nand_info->cmd_queue_len == MXS_NAND_COMMAND_BUFFER_SIZE) {
+ printf("MXS NAND: Command queue too long\n");
+ return;
+ }
+
+ /*
+ * Every operation begins with a command byte and a series of zero or
+ * more address bytes. These are distinguished by either the Address
+ * Latch Enable (ALE) or Command Latch Enable (CLE) signals being
+ * asserted. When MTD is ready to execute the command, it will
+ * deasert both latch enables.
+ *
+ * Rather than run a separate DMA operation for every single byte, we
+ * queue them up and run a single DMA operation for the entire series
+ * of command and data bytes.
+ */
+ if (ctrl & (NAND_ALE | NAND_CLE)) {
+ if (data != NAND_CMD_NONE)
+ nand_info->cmd_buf[nand_info->cmd_queue_len++] = data;
+ return;
+ }
+
+ /*
+ * If control arrives here, MTD has deasserted both the ALE and CLE,
+ * which means it's ready to run an operation. Check if we have any
+ * bytes to send.
+ */
+ if (nand_info->cmd_queue_len == 0)
+ return;
+
+ /* Compile the DMA descriptor -- a descriptor that sends command. */
+ d = mxs_nand_get_dma_desc(nand_info);
+ d->cmd.data =
+ MXS_DMA_DESC_COMMAND_DMA_READ | MXS_DMA_DESC_IRQ |
+ MXS_DMA_DESC_CHAIN | MXS_DMA_DESC_DEC_SEM |
+ MXS_DMA_DESC_WAIT4END | (3 << MXS_DMA_DESC_PIO_WORDS_OFFSET) |
+ (nand_info->cmd_queue_len << MXS_DMA_DESC_BYTES_OFFSET);
+
+ d->cmd.address = (dma_addr_t)nand_info->cmd_buf;
+
+ d->cmd.pio_words[0] =
+ GPMI_CTRL0_COMMAND_MODE_WRITE |
+ GPMI_CTRL0_WORD_LENGTH |
+ (nand_info->cur_chip << GPMI_CTRL0_CS_OFFSET) |
+ GPMI_CTRL0_ADDRESS_NAND_CLE |
+ GPMI_CTRL0_ADDRESS_INCREMENT |
+ nand_info->cmd_queue_len;
+
+ mxs_dma_desc_append(channel, d);
+
+ /* Execute the DMA chain. */
+ ret = mxs_dma_go(channel);
+ if (ret)
+ printf("MXS NAND: Error sending command\n");
+
+ mxs_nand_return_dma_descs(nand_info);
+
+ /* Reset the command queue. */
+ nand_info->cmd_queue_len = 0;
+}
+
+/*
+ * Test if the NAND flash is ready.
+ */
+static int mxs_nand_device_ready(struct mtd_info *mtd)
+{
+ struct nand_chip *chip = mtd->priv;
+ struct mxs_nand_info *nand_info = chip->priv;
+ struct mx28_gpmi_regs *gpmi_regs =
+ (struct mx28_gpmi_regs *)MXS_GPMI_BASE;
+ uint32_t tmp;
+
+ tmp = readl(&gpmi_regs->hw_gpmi_stat);
+ tmp >>= (GPMI_STAT_READY_BUSY_OFFSET + nand_info->cur_chip);
+
+ return tmp & 1;
+}
+
+/*
+ * Select the NAND chip.
+ */
+static void mxs_nand_select_chip(struct mtd_info *mtd, int chip)
+{
+ struct nand_chip *nand = mtd->priv;
+ struct mxs_nand_info *nand_info = nand->priv;
+
+ nand_info->cur_chip = chip;
+}
+
+/*
+ * Handle block mark swapping.
+ *
+ * Note that, when this function is called, it doesn't know whether it's
+ * swapping the block mark, or swapping it *back* -- but it doesn't matter
+ * because the the operation is the same.
+ */
+static void mxs_nand_swap_block_mark(struct mtd_info *mtd,
+ uint8_t *data_buf, uint8_t *oob_buf)
+{
+ uint32_t bit_offset;
+ uint32_t buf_offset;
+
+ uint32_t src;
+ uint32_t dst;
+
+ bit_offset = mxs_nand_mark_bit_offset(mtd);
+ buf_offset = mxs_nand_mark_byte_offset(mtd);
+
+ /*
+ * Get the byte from the data area that overlays the block mark. Since
+ * the ECC engine applies its own view to the bits in the page, the
+ * physical block mark won't (in general) appear on a byte boundary in
+ * the data.
+ */
+ src = data_buf[buf_offset] >> bit_offset;
+ src |= data_buf[buf_offset + 1] << (8 - bit_offset);
+
+ dst = oob_buf[0];
+
+ oob_buf[0] = src;
+
+ data_buf[buf_offset] &= ~(0xff << bit_offset);
+ data_buf[buf_offset + 1] &= 0xff << bit_offset;
+
+ data_buf[buf_offset] |= dst << bit_offset;
+ data_buf[buf_offset + 1] |= dst >> (8 - bit_offset);
+}
+
+/*
+ * Read data from NAND.
+ */
+static void mxs_nand_read_buf(struct mtd_info *mtd, uint8_t *buf, int length)
+{
+ struct nand_chip *nand = mtd->priv;
+ struct mxs_nand_info *nand_info = nand->priv;
+ struct mxs_dma_desc *d;
+ uint32_t channel = MXS_DMA_CHANNEL_AHB_APBH_GPMI0 + nand_info->cur_chip;
+ int ret;
+
+ if (length > NAND_MAX_PAGESIZE) {
+ printf("MXS NAND: DMA buffer too big\n");
+ return;
+ }
+
+ if (!buf) {
+ printf("MXS NAND: DMA buffer is NULL\n");
+ return;
+ }
+
+ /* Compile the DMA descriptor - a descriptor that reads data. */
+ d = mxs_nand_get_dma_desc(nand_info);
+ d->cmd.data =
+ MXS_DMA_DESC_COMMAND_DMA_WRITE | MXS_DMA_DESC_IRQ |
+ MXS_DMA_DESC_DEC_SEM | MXS_DMA_DESC_WAIT4END |
+ (1 << MXS_DMA_DESC_PIO_WORDS_OFFSET) |
+ (length << MXS_DMA_DESC_BYTES_OFFSET);
+
+ d->cmd.address = (dma_addr_t)nand_info->data_buf;
+
+ d->cmd.pio_words[0] =
+ GPMI_CTRL0_COMMAND_MODE_READ |
+ GPMI_CTRL0_WORD_LENGTH |
+ (nand_info->cur_chip << GPMI_CTRL0_CS_OFFSET) |
+ GPMI_CTRL0_ADDRESS_NAND_DATA |
+ length;
+
+ mxs_dma_desc_append(channel, d);
+
+ /*
+ * A DMA descriptor that waits for the command to end and the chip to
+ * become ready.
+ *
+ * I think we actually should *not* be waiting for the chip to become
+ * ready because, after all, we don't care. I think the original code
+ * did that and no one has re-thought it yet.
+ */
+ d = mxs_nand_get_dma_desc(nand_info);
+ d->cmd.data =
+ MXS_DMA_DESC_COMMAND_NO_DMAXFER | MXS_DMA_DESC_IRQ |
+ MXS_DMA_DESC_NAND_WAIT_4_READY | MXS_DMA_DESC_DEC_SEM |
+ MXS_DMA_DESC_WAIT4END | (4 << MXS_DMA_DESC_PIO_WORDS_OFFSET);
+
+ d->cmd.address = 0;
+
+ d->cmd.pio_words[0] =
+ GPMI_CTRL0_COMMAND_MODE_WAIT_FOR_READY |
+ GPMI_CTRL0_WORD_LENGTH |
+ (nand_info->cur_chip << GPMI_CTRL0_CS_OFFSET) |
+ GPMI_CTRL0_ADDRESS_NAND_DATA;
+
+ mxs_dma_desc_append(channel, d);
+
+ /* Execute the DMA chain. */
+ ret = mxs_dma_go(channel);
+ if (ret) {
+ printf("MXS NAND: DMA read error\n");
+ goto rtn;
+ }
+
+ memcpy(buf, nand_info->data_buf, length);
+
+rtn:
+ mxs_nand_return_dma_descs(nand_info);
+}
+
+/*
+ * Write data to NAND.
+ */
+static void mxs_nand_write_buf(struct mtd_info *mtd, const uint8_t *buf,
+ int length)
+{
+ struct nand_chip *nand = mtd->priv;
+ struct mxs_nand_info *nand_info = nand->priv;
+ struct mxs_dma_desc *d;
+ uint32_t channel = MXS_DMA_CHANNEL_AHB_APBH_GPMI0 + nand_info->cur_chip;
+ int ret;
+
+ if (length > NAND_MAX_PAGESIZE) {
+ printf("MXS NAND: DMA buffer too big\n");
+ return;
+ }
+
+ if (!buf) {
+ printf("MXS NAND: DMA buffer is NULL\n");
+ return;
+ }
+
+ memcpy(nand_info->data_buf, buf, length);
+
+ /* Compile the DMA descriptor - a descriptor that writes data. */
+ d = mxs_nand_get_dma_desc(nand_info);
+ d->cmd.data =
+ MXS_DMA_DESC_COMMAND_DMA_READ | MXS_DMA_DESC_IRQ |
+ MXS_DMA_DESC_DEC_SEM | MXS_DMA_DESC_WAIT4END |
+ (4 << MXS_DMA_DESC_PIO_WORDS_OFFSET) |
+ (length << MXS_DMA_DESC_BYTES_OFFSET);
+
+ d->cmd.address = (dma_addr_t)nand_info->data_buf;
+
+ d->cmd.pio_words[0] =
+ GPMI_CTRL0_COMMAND_MODE_WRITE |
+ GPMI_CTRL0_WORD_LENGTH |
+ (nand_info->cur_chip << GPMI_CTRL0_CS_OFFSET) |
+ GPMI_CTRL0_ADDRESS_NAND_DATA |
+ length;
+
+ mxs_dma_desc_append(channel, d);
+
+ /* Execute the DMA chain. */
+ ret = mxs_dma_go(channel);
+ if (ret)
+ printf("MXS NAND: DMA write error\n");
+
+ mxs_nand_return_dma_descs(nand_info);
+}
+
+/*
+ * Read a single byte from NAND.
+ */
+static uint8_t mxs_nand_read_byte(struct mtd_info *mtd)
+{
+ uint8_t buf;
+ mxs_nand_read_buf(mtd, &buf, 1);
+ return buf;
+}
+
+/*
+ * Read a page from NAND.
+ */
+static int mxs_nand_ecc_read_page(struct mtd_info *mtd, struct nand_chip *nand,
+ uint8_t *buf, int page)
+{
+ struct mxs_nand_info *nand_info = nand->priv;
+ struct mxs_dma_desc *d;
+ uint32_t channel = MXS_DMA_CHANNEL_AHB_APBH_GPMI0 + nand_info->cur_chip;
+ uint32_t corrected = 0, failed = 0;
+ uint8_t *status;
+ int i, ret;
+
+ /* Compile the DMA descriptor - wait for ready. */
+ d = mxs_nand_get_dma_desc(nand_info);
+ d->cmd.data =
+ MXS_DMA_DESC_COMMAND_NO_DMAXFER | MXS_DMA_DESC_CHAIN |
+ MXS_DMA_DESC_NAND_WAIT_4_READY | MXS_DMA_DESC_WAIT4END |
+ (1 << MXS_DMA_DESC_PIO_WORDS_OFFSET);
+
+ d->cmd.address = 0;
+
+ d->cmd.pio_words[0] =
+ GPMI_CTRL0_COMMAND_MODE_WAIT_FOR_READY |
+ GPMI_CTRL0_WORD_LENGTH |
+ (nand_info->cur_chip << GPMI_CTRL0_CS_OFFSET) |
+ GPMI_CTRL0_ADDRESS_NAND_DATA;
+
+ mxs_dma_desc_append(channel, d);
+
+ /* Compile the DMA descriptor - enable the BCH block and read. */
+ d = mxs_nand_get_dma_desc(nand_info);
+ d->cmd.data =
+ MXS_DMA_DESC_COMMAND_NO_DMAXFER | MXS_DMA_DESC_CHAIN |
+ MXS_DMA_DESC_WAIT4END | (6 << MXS_DMA_DESC_PIO_WORDS_OFFSET);
+
+ d->cmd.address = 0;
+
+ d->cmd.pio_words[0] =
+ GPMI_CTRL0_COMMAND_MODE_READ |
+ GPMI_CTRL0_WORD_LENGTH |
+ (nand_info->cur_chip << GPMI_CTRL0_CS_OFFSET) |
+ GPMI_CTRL0_ADDRESS_NAND_DATA |
+ (mtd->writesize + mtd->oobsize);
+ d->cmd.pio_words[1] = 0;
+ d->cmd.pio_words[2] =
+ GPMI_ECCCTRL_ENABLE_ECC |
+ GPMI_ECCCTRL_ECC_CMD_DECODE |
+ GPMI_ECCCTRL_BUFFER_MASK_BCH_PAGE;
+ d->cmd.pio_words[3] = mtd->writesize + mtd->oobsize;
+ d->cmd.pio_words[4] = (dma_addr_t)nand_info->data_buf;
+ d->cmd.pio_words[5] = (dma_addr_t)nand_info->oob_buf;
+
+ mxs_dma_desc_append(channel, d);
+
+ /* Compile the DMA descriptor - disable the BCH block. */
+ d = mxs_nand_get_dma_desc(nand_info);
+ d->cmd.data =
+ MXS_DMA_DESC_COMMAND_NO_DMAXFER | MXS_DMA_DESC_CHAIN |
+ MXS_DMA_DESC_NAND_WAIT_4_READY | MXS_DMA_DESC_WAIT4END |
+ (3 << MXS_DMA_DESC_PIO_WORDS_OFFSET);
+
+ d->cmd.address = 0;
+
+ d->cmd.pio_words[0] =
+ GPMI_CTRL0_COMMAND_MODE_WAIT_FOR_READY |
+ GPMI_CTRL0_WORD_LENGTH |
+ (nand_info->cur_chip << GPMI_CTRL0_CS_OFFSET) |
+ GPMI_CTRL0_ADDRESS_NAND_DATA |
+ (mtd->writesize + mtd->oobsize);
+ d->cmd.pio_words[1] = 0;
+ d->cmd.pio_words[2] = 0;
+
+ mxs_dma_desc_append(channel, d);
+
+ /* Compile the DMA descriptor - deassert the NAND lock and interrupt. */
+ d = mxs_nand_get_dma_desc(nand_info);
+ d->cmd.data =
+ MXS_DMA_DESC_COMMAND_NO_DMAXFER | MXS_DMA_DESC_IRQ |
+ MXS_DMA_DESC_DEC_SEM;
+
+ d->cmd.address = 0;
+
+ mxs_dma_desc_append(channel, d);
+
+ /* Execute the DMA chain. */
+ ret = mxs_dma_go(channel);
+ if (ret) {
+ printf("MXS NAND: DMA read error\n");
+ goto rtn;
+ }
+
+ ret = mxs_nand_wait_for_bch_complete();
+ if (ret) {
+ printf("MXS NAND: BCH read timeout\n");
+ goto rtn;
+ }
+
+ /* Read DMA completed, now do the mark swapping. */
+ mxs_nand_swap_block_mark(mtd, nand_info->data_buf, nand_info->oob_buf);
+
+ /* Loop over status bytes, accumulating ECC status. */
+ status = nand_info->oob_buf + mxs_nand_aux_status_offset();
+ for (i = 0; i < mxs_nand_ecc_chunk_cnt(mtd->writesize); i++) {
+ if (status[i] == 0x00)
+ continue;
+
+ if (status[i] == 0xff)
+ continue;
+
+ if (status[i] == 0xfe) {
+ failed++;
+ continue;
+ }
+
+ corrected += status[i];
+ }
+
+ /* Propagate ECC status to the owning MTD. */
+ mtd->ecc_stats.failed += failed;
+ mtd->ecc_stats.corrected += corrected;
+
+ /*
+ * It's time to deliver the OOB bytes. See mxs_nand_ecc_read_oob() for
+ * details about our policy for delivering the OOB.
+ *
+ * We fill the caller's buffer with set bits, and then copy the block
+ * mark to the caller's buffer. Note that, if block mark swapping was
+ * necessary, it has already been done, so we can rely on the first
+ * byte of the auxiliary buffer to contain the block mark.
+ */
+ memset(nand->oob_poi, 0xff, mtd->oobsize);
+
+ nand->oob_poi[0] = nand_info->oob_buf[0];
+
+ memcpy(buf, nand_info->data_buf, mtd->writesize);
+
+rtn:
+ mxs_nand_return_dma_descs(nand_info);
+
+ return ret;
+}
+
+/*
+ * Write a page to NAND.
+ */
+static void mxs_nand_ecc_write_page(struct mtd_info *mtd,
+ struct nand_chip *nand, const uint8_t *buf)
+{
+ struct mxs_nand_info *nand_info = nand->priv;
+ struct mxs_dma_desc *d;
+ uint32_t channel = MXS_DMA_CHANNEL_AHB_APBH_GPMI0 + nand_info->cur_chip;
+ int ret;
+
+ memcpy(nand_info->data_buf, buf, mtd->writesize);
+ memcpy(nand_info->oob_buf, nand->oob_poi, mtd->oobsize);
+
+ /* Handle block mark swapping. */
+ mxs_nand_swap_block_mark(mtd, nand_info->data_buf, nand_info->oob_buf);
+
+ /* Compile the DMA descriptor - write data. */
+ d = mxs_nand_get_dma_desc(nand_info);
+ d->cmd.data =
+ MXS_DMA_DESC_COMMAND_NO_DMAXFER | MXS_DMA_DESC_IRQ |
+ MXS_DMA_DESC_DEC_SEM | MXS_DMA_DESC_WAIT4END |
+ (6 << MXS_DMA_DESC_PIO_WORDS_OFFSET);
+
+ d->cmd.address = 0;
+
+ d->cmd.pio_words[0] =
+ GPMI_CTRL0_COMMAND_MODE_WRITE |
+ GPMI_CTRL0_WORD_LENGTH |
+ (nand_info->cur_chip << GPMI_CTRL0_CS_OFFSET) |
+ GPMI_CTRL0_ADDRESS_NAND_DATA;
+ d->cmd.pio_words[1] = 0;
+ d->cmd.pio_words[2] =
+ GPMI_ECCCTRL_ENABLE_ECC |
+ GPMI_ECCCTRL_ECC_CMD_ENCODE |
+ GPMI_ECCCTRL_BUFFER_MASK_BCH_PAGE;
+ d->cmd.pio_words[3] = (mtd->writesize + mtd->oobsize);
+ d->cmd.pio_words[4] = (dma_addr_t)nand_info->data_buf;
+ d->cmd.pio_words[5] = (dma_addr_t)nand_info->oob_buf;
+
+ mxs_dma_desc_append(channel, d);
+
+ /* Execute the DMA chain. */
+ ret = mxs_dma_go(channel);
+ if (ret) {
+ printf("MXS NAND: DMA write error\n");
+ goto rtn;
+ }
+
+ ret = mxs_nand_wait_for_bch_complete();
+ if (ret) {
+ printf("MXS NAND: BCH write timeout\n");
+ goto rtn;
+ }
+
+rtn:
+ mxs_nand_return_dma_descs(nand_info);
+}
+
+/*
+ * Read OOB from NAND.
+ *
+ * This function is a veneer that replaces the function originally installed by
+ * the NAND Flash MTD code.
+ */
+static int mxs_nand_hook_read_oob(struct mtd_info *mtd, loff_t from,
+ struct mtd_oob_ops *ops)
+{
+ struct nand_chip *chip = mtd->priv;
+ struct mxs_nand_info *nand_info = chip->priv;
+ int ret;
+
+ if (ops->mode == MTD_OOB_RAW)
+ nand_info->raw_oob_mode = 1;
+ else
+ nand_info->raw_oob_mode = 0;
+
+ ret = nand_info->hooked_read_oob(mtd, from, ops);
+
+ nand_info->raw_oob_mode = 0;
+
+ return ret;
+}
+
+/*
+ * Write OOB to NAND.
+ *
+ * This function is a veneer that replaces the function originally installed by
+ * the NAND Flash MTD code.
+ */
+static int mxs_nand_hook_write_oob(struct mtd_info *mtd, loff_t to,
+ struct mtd_oob_ops *ops)
+{
+ struct nand_chip *chip = mtd->priv;
+ struct mxs_nand_info *nand_info = chip->priv;
+ int ret;
+
+ if (ops->mode == MTD_OOB_RAW)
+ nand_info->raw_oob_mode = 1;
+ else
+ nand_info->raw_oob_mode = 0;
+
+ ret = nand_info->hooked_write_oob(mtd, to, ops);
+
+ nand_info->raw_oob_mode = 0;
+
+ return ret;
+}
+
+/*
+ * Mark a block bad in NAND.
+ *
+ * This function is a veneer that replaces the function originally installed by
+ * the NAND Flash MTD code.
+ */
+static int mxs_nand_hook_block_markbad(struct mtd_info *mtd, loff_t ofs)
+{
+ struct nand_chip *chip = mtd->priv;
+ struct mxs_nand_info *nand_info = chip->priv;
+ int ret;
+
+ nand_info->marking_block_bad = 1;
+
+ ret = nand_info->hooked_block_markbad(mtd, ofs);
+
+ nand_info->marking_block_bad = 0;
+
+ return ret;
+}
+
+/*
+ * There are several places in this driver where we have to handle the OOB and
+ * block marks. This is the function where things are the most complicated, so
+ * this is where we try to explain it all. All the other places refer back to
+ * here.
+ *
+ * These are the rules, in order of decreasing importance:
+ *
+ * 1) Nothing the caller does can be allowed to imperil the block mark, so all
+ * write operations take measures to protect it.
+ *
+ * 2) In read operations, the first byte of the OOB we return must reflect the
+ * true state of the block mark, no matter where that block mark appears in
+ * the physical page.
+ *
+ * 3) ECC-based read operations return an OOB full of set bits (since we never
+ * allow ECC-based writes to the OOB, it doesn't matter what ECC-based reads
+ * return).
+ *
+ * 4) "Raw" read operations return a direct view of the physical bytes in the
+ * page, using the conventional definition of which bytes are data and which
+ * are OOB. This gives the caller a way to see the actual, physical bytes
+ * in the page, without the distortions applied by our ECC engine.
+ *
+ * What we do for this specific read operation depends on whether we're doing
+ * "raw" read, or an ECC-based read.
+ *
+ * It turns out that knowing whether we want an "ECC-based" or "raw" read is not
+ * easy. When reading a page, for example, the NAND Flash MTD code calls our
+ * ecc.read_page or ecc.read_page_raw function. Thus, the fact that MTD wants an
+ * ECC-based or raw view of the page is implicit in which function it calls
+ * (there is a similar pair of ECC-based/raw functions for writing).
+ *
+ * Since MTD assumes the OOB is not covered by ECC, there is no pair of
+ * ECC-based/raw functions for reading or or writing the OOB. The fact that the
+ * caller wants an ECC-based or raw view of the page is not propagated down to
+ * this driver.
+ *
+ * Since our OOB *is* covered by ECC, we need this information. So, we hook the
+ * ecc.read_oob and ecc.write_oob function pointers in the owning
+ * struct mtd_info with our own functions. These hook functions set the
+ * raw_oob_mode field so that, when control finally arrives here, we'll know
+ * what to do.
+ */
+static int mxs_nand_ecc_read_oob(struct mtd_info *mtd, struct nand_chip *nand,
+ int page, int cmd)
+{
+ struct mxs_nand_info *nand_info = nand->priv;
+
+ /*
+ * First, fill in the OOB buffer. If we're doing a raw read, we need to
+ * get the bytes from the physical page. If we're not doing a raw read,
+ * we need to fill the buffer with set bits.
+ */
+ if (nand_info->raw_oob_mode) {
+ /*
+ * If control arrives here, we're doing a "raw" read. Send the
+ * command to read the conventional OOB and read it.
+ */
+ nand->cmdfunc(mtd, NAND_CMD_READ0, mtd->writesize, page);
+ nand->read_buf(mtd, nand->oob_poi, mtd->oobsize);
+ } else {
+ /*
+ * If control arrives here, we're not doing a "raw" read. Fill
+ * the OOB buffer with set bits and correct the block mark.
+ */
+ memset(nand->oob_poi, 0xff, mtd->oobsize);
+
+ nand->cmdfunc(mtd, NAND_CMD_READ0, mtd->writesize, page);
+ mxs_nand_read_buf(mtd, nand->oob_poi, 1);
+ }
+
+ return 0;
+
+}
+
+/*
+ * Write OOB data to NAND.
+ */
+static int mxs_nand_ecc_write_oob(struct mtd_info *mtd, struct nand_chip *nand,
+ int page)
+{
+ struct mxs_nand_info *nand_info = nand->priv;
+ uint8_t block_mark = 0;
+
+ /*
+ * There are fundamental incompatibilities between the i.MX GPMI NFC and
+ * the NAND Flash MTD model that make it essentially impossible to write
+ * the out-of-band bytes.
+ *
+ * We permit *ONE* exception. If the *intent* of writing the OOB is to
+ * mark a block bad, we can do that.
+ */
+
+ if (!nand_info->marking_block_bad) {
+ printf("NXS NAND: Writing OOB isn't supported\n");
+ return -EIO;
+ }
+
+ /* Write the block mark. */
+ nand->cmdfunc(mtd, NAND_CMD_SEQIN, mtd->writesize, page);
+ nand->write_buf(mtd, &block_mark, 1);
+ nand->cmdfunc(mtd, NAND_CMD_PAGEPROG, -1, -1);
+
+ /* Check if it worked. */
+ if (nand->waitfunc(mtd, nand) & NAND_STATUS_FAIL)
+ return -EIO;
+
+ return 0;
+}
+
+/*
+ * Claims all blocks are good.
+ *
+ * In principle, this function is *only* called when the NAND Flash MTD system
+ * isn't allowed to keep an in-memory bad block table, so it is forced to ask
+ * the driver for bad block information.
+ *
+ * In fact, we permit the NAND Flash MTD system to have an in-memory BBT, so
+ * this function is *only* called when we take it away.
+ *
+ * Thus, this function is only called when we want *all* blocks to look good,
+ * so it *always* return success.
+ */
+static int mxs_nand_block_bad(struct mtd_info *mtd, loff_t ofs, int getchip)
+{
+ return 0;
+}
+
+/*
+ * Nominally, the purpose of this function is to look for or create the bad
+ * block table. In fact, since the we call this function at the very end of
+ * the initialization process started by nand_scan(), and we doesn't have a
+ * more formal mechanism, we "hook" this function to continue init process.
+ *
+ * At this point, the physical NAND Flash chips have been identified and
+ * counted, so we know the physical geometry. This enables us to make some
+ * important configuration decisions.
+ *
+ * The return value of this function propogates directly back to this driver's
+ * call to nand_scan(). Anything other than zero will cause this driver to
+ * tear everything down and declare failure.
+ */
+static int mxs_nand_scan_bbt(struct mtd_info *mtd)
+{
+ struct nand_chip *nand = mtd->priv;
+ struct mxs_nand_info *nand_info = nand->priv;
+ struct mx28_bch_regs *bch_regs = (struct mx28_bch_regs *)MXS_BCH_BASE;
+ uint32_t tmp;
+
+ /* Configure BCH and set NFC geometry */
+ mx28_reset_block(&bch_regs->hw_bch_ctrl_reg);
+
+ /* Configure layout 0 */
+ tmp = (mxs_nand_ecc_chunk_cnt(mtd->writesize) - 1)
+ << BCH_FLASHLAYOUT0_NBLOCKS_OFFSET;
+ tmp |= MXS_NAND_METADATA_SIZE << BCH_FLASHLAYOUT0_META_SIZE_OFFSET;
+ tmp |= (mxs_nand_get_ecc_strength(mtd->writesize, mtd->oobsize) >> 1)
+ << BCH_FLASHLAYOUT0_ECC0_OFFSET;
+ tmp |= MXS_NAND_CHUNK_DATA_CHUNK_SIZE;
+ writel(tmp, &bch_regs->hw_bch_flash0layout0);
+
+ tmp = (mtd->writesize + mtd->oobsize)
+ << BCH_FLASHLAYOUT1_PAGE_SIZE_OFFSET;
+ tmp |= (mxs_nand_get_ecc_strength(mtd->writesize, mtd->oobsize) >> 1)
+ << BCH_FLASHLAYOUT1_ECCN_OFFSET;
+ tmp |= MXS_NAND_CHUNK_DATA_CHUNK_SIZE;
+ writel(tmp, &bch_regs->hw_bch_flash0layout1);
+
+ /* Set *all* chip selects to use layout 0 */
+ writel(0, &bch_regs->hw_bch_layoutselect);
+
+ /* Enable BCH complete interrupt */
+ writel(BCH_CTRL_COMPLETE_IRQ_EN, &bch_regs->hw_bch_ctrl_set);
+
+ /* Hook some operations at the MTD level. */
+ if (mtd->read_oob != mxs_nand_hook_read_oob) {
+ nand_info->hooked_read_oob = mtd->read_oob;
+ mtd->read_oob = mxs_nand_hook_read_oob;
+ }
+
+ if (mtd->write_oob != mxs_nand_hook_write_oob) {
+ nand_info->hooked_write_oob = mtd->write_oob;
+ mtd->write_oob = mxs_nand_hook_write_oob;
+ }
+
+ if (mtd->block_markbad != mxs_nand_hook_block_markbad) {
+ nand_info->hooked_block_markbad = mtd->block_markbad;
+ mtd->block_markbad = mxs_nand_hook_block_markbad;
+ }
+
+ /* We use the reference implementation for bad block management. */
+ return nand_default_bbt(mtd);
+}
+
+/*
+ * Allocate DMA buffers
+ */
+int mxs_nand_alloc_buffers(struct mxs_nand_info *nand_info)
+{
+ uint8_t *buf;
+ const int size = NAND_MAX_PAGESIZE + NAND_MAX_OOBSIZE;
+
+ /* DMA buffers */
+ buf = memalign(MXS_DMA_ALIGNMENT, size);
+ if (!buf) {
+ printf("MXS NAND: Error allocating DMA buffers\n");
+ return -ENOMEM;
+ }
+
+ memset(buf, 0, size);
+
+ nand_info->data_buf = buf;
+ nand_info->oob_buf = buf + NAND_MAX_PAGESIZE;
+
+ /* Command buffers */
+ nand_info->cmd_buf = memalign(MXS_DMA_ALIGNMENT,
+ MXS_NAND_COMMAND_BUFFER_SIZE);
+ if (!nand_info->cmd_buf) {
+ free(buf);
+ printf("MXS NAND: Error allocating command buffers\n");
+ return -ENOMEM;
+ }
+ memset(nand_info->cmd_buf, 0, MXS_NAND_COMMAND_BUFFER_SIZE);
+ nand_info->cmd_queue_len = 0;
+
+ return 0;
+}
+
+/*
+ * Initializes the NFC hardware.
+ */
+int mxs_nand_init(struct mxs_nand_info *info)
+{
+ struct mx28_gpmi_regs *gpmi_regs =
+ (struct mx28_gpmi_regs *)MXS_GPMI_BASE;
+ int i = 0;
+
+ info->desc = malloc(sizeof(struct mxs_dma_desc *) *
+ MXS_NAND_DMA_DESCRIPTOR_COUNT);
+ if (!info->desc)
+ goto err1;
+
+ /* Allocate the DMA descriptors. */
+ for (i = 0; i < MXS_NAND_DMA_DESCRIPTOR_COUNT; i++) {
+ info->desc[i] = mxs_dma_desc_alloc();
+ if (!info->desc[i])
+ goto err2;
+ }
+
+ /* Init the DMA controller. */
+ mxs_dma_init();
+
+ /* Reset the GPMI block. */
+ mx28_reset_block(&gpmi_regs->hw_gpmi_ctrl0_reg);
+
+ /*
+ * Choose NAND mode, set IRQ polarity, disable write protection and
+ * select BCH ECC.
+ */
+ clrsetbits_le32(&gpmi_regs->hw_gpmi_ctrl1,
+ GPMI_CTRL1_GPMI_MODE,
+ GPMI_CTRL1_ATA_IRQRDY_POLARITY | GPMI_CTRL1_DEV_RESET |
+ GPMI_CTRL1_BCH_MODE);
+
+ return 0;
+
+err2:
+ free(info->desc);
+err1:
+ for (--i; i >= 0; i--)
+ mxs_dma_desc_free(info->desc[i]);
+ printf("MXS NAND: Unable to allocate DMA descriptors\n");
+ return -ENOMEM;
+}
+
+/*!
+ * This function is called during the driver binding process.
+ *
+ * @param pdev the device structure used to store device specific
+ * information that is used by the suspend, resume and
+ * remove functions
+ *
+ * @return The function always returns 0.
+ */
+int board_nand_init(struct nand_chip *nand)
+{
+ struct mxs_nand_info *nand_info;
+ int err;
+
+ nand_info = malloc(sizeof(struct mxs_nand_info));
+ if (!nand_info) {
+ printf("MXS NAND: Failed to allocate private data\n");
+ return -ENOMEM;
+ }
+ memset(nand_info, 0, sizeof(struct mxs_nand_info));
+
+ err = mxs_nand_alloc_buffers(nand_info);
+ if (err)
+ goto err1;
+
+ err = mxs_nand_init(nand_info);
+ if (err)
+ goto err2;
+
+ memset(&fake_ecc_layout, 0, sizeof(fake_ecc_layout));
+
+ nand->priv = nand_info;
+ nand->options |= NAND_NO_SUBPAGE_WRITE;
+
+ nand->cmd_ctrl = mxs_nand_cmd_ctrl;
+
+ nand->dev_ready = mxs_nand_device_ready;
+ nand->select_chip = mxs_nand_select_chip;
+ nand->block_bad = mxs_nand_block_bad;
+ nand->scan_bbt = mxs_nand_scan_bbt;
+
+ nand->read_byte = mxs_nand_read_byte;
+
+ nand->read_buf = mxs_nand_read_buf;
+ nand->write_buf = mxs_nand_write_buf;
+
+ nand->ecc.read_page = mxs_nand_ecc_read_page;
+ nand->ecc.write_page = mxs_nand_ecc_write_page;
+ nand->ecc.read_oob = mxs_nand_ecc_read_oob;
+ nand->ecc.write_oob = mxs_nand_ecc_write_oob;
+
+ nand->ecc.layout = &fake_ecc_layout;
+ nand->ecc.mode = NAND_ECC_HW;
+ nand->ecc.bytes = 9;
+ nand->ecc.size = 512;
+
+ return 0;
+
+err2:
+ free(nand_info->data_buf);
+ free(nand_info->cmd_buf);
+err1:
+ free(nand_info);
+ return err;
+}
diff --git a/drivers/mtd/onenand/Makefile b/drivers/mtd/onenand/Makefile
index b984bd4..b090d40 100644
--- a/drivers/mtd/onenand/Makefile
+++ b/drivers/mtd/onenand/Makefile
@@ -25,8 +25,12 @@
LIB := $(obj)libonenand.o
+ifndef CONFIG_SPL_BUILD
COBJS-$(CONFIG_CMD_ONENAND) := onenand_uboot.o onenand_base.o onenand_bbt.o
COBJS-$(CONFIG_SAMSUNG_ONENAND) += samsung.o
+else
+COBJS-y := onenand_spl.o
+endif
COBJS := $(COBJS-y)
SRCS := $(COBJS:.o=.c)
diff --git a/drivers/mtd/onenand/onenand_base.c b/drivers/mtd/onenand/onenand_base.c
index 24e02c2..06f187f 100644
--- a/drivers/mtd/onenand/onenand_base.c
+++ b/drivers/mtd/onenand/onenand_base.c
@@ -1943,16 +1943,10 @@
{
struct onenand_chip *this = mtd->priv;
int start, end, block, value, status;
- int wp_status_mask;
start = onenand_block(this, ofs);
end = onenand_block(this, ofs + len);
- if (cmd == ONENAND_CMD_LOCK)
- wp_status_mask = ONENAND_WP_LS;
- else
- wp_status_mask = ONENAND_WP_US;
-
/* Continuous lock scheme */
if (this->options & ONENAND_HAS_CONT_LOCK) {
/* Set start block address */
@@ -2226,19 +2220,21 @@
static int onenand_check_maf(int manuf)
{
int size = ARRAY_SIZE(onenand_manuf_ids);
- char *name;
int i;
+#ifdef ONENAND_DEBUG
+ char *name;
+#endif
for (i = 0; i < size; i++)
if (manuf == onenand_manuf_ids[i].id)
break;
+#ifdef ONENAND_DEBUG
if (i < size)
name = onenand_manuf_ids[i].name;
else
name = "Unknown";
-#ifdef ONENAND_DEBUG
printk(KERN_DEBUG "OneNAND Manufacturer: %s (0x%0x)\n", name, manuf);
#endif
@@ -2255,7 +2251,7 @@
{
struct onenand_chip *this = mtd->priv;
unsigned int die, bdry;
- int ret, syscfg, locked;
+ int syscfg, locked;
/* Disable ECC */
syscfg = this->read_word(this->base + ONENAND_REG_SYS_CFG1);
@@ -2266,7 +2262,7 @@
this->wait(mtd, FL_SYNCING);
this->command(mtd, FLEXONENAND_CMD_READ_PI, die, 0);
- ret = this->wait(mtd, FL_READING);
+ this->wait(mtd, FL_READING);
bdry = this->read_word(this->base + ONENAND_DATARAM);
if ((bdry >> FLEXONENAND_PI_UNLOCK_SHIFT) == 3)
@@ -2276,7 +2272,7 @@
this->boundary[die] = bdry & FLEXONENAND_PI_MASK;
this->command(mtd, ONENAND_CMD_RESET, 0, 0);
- ret = this->wait(mtd, FL_RESETING);
+ this->wait(mtd, FL_RESETING);
printk(KERN_INFO "Die %d boundary: %d%s\n", die,
this->boundary[die], locked ? "(Locked)" : "(Unlocked)");
diff --git a/drivers/mtd/onenand/onenand_spl.c b/drivers/mtd/onenand/onenand_spl.c
new file mode 100644
index 0000000..50eaa71
--- /dev/null
+++ b/drivers/mtd/onenand/onenand_spl.c
@@ -0,0 +1,146 @@
+/*
+ * Copyright (C) 2011 Marek Vasut <marek.vasut@gmail.com>
+ *
+ * Based on code:
+ * Copyright (C) 2005-2009 Samsung Electronics
+ * Kyungmin Park <kyungmin.park@samsung.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <asm/io.h>
+#include <linux/mtd/onenand_regs.h>
+#include <onenand_uboot.h>
+
+/*
+ * Device geometry:
+ * - 2048b page, 128k erase block.
+ * - 4096b page, 256k erase block.
+ */
+enum onenand_spl_pagesize {
+ PAGE_2K = 2048,
+ PAGE_4K = 4096,
+};
+
+#define ONENAND_PAGES_PER_BLOCK 64
+#define onenand_block_address(block) (block)
+#define onenand_sector_address(page) (page << 2)
+#define onenand_buffer_address() ((1 << 3) << 8)
+#define onenand_bufferram_address(block) (0)
+
+static inline uint16_t onenand_readw(uint32_t addr)
+{
+ return readw(CONFIG_SYS_ONENAND_BASE + addr);
+}
+
+static inline void onenand_writew(uint16_t value, uint32_t addr)
+{
+ writew(value, CONFIG_SYS_ONENAND_BASE + addr);
+}
+
+static enum onenand_spl_pagesize onenand_spl_get_geometry(void)
+{
+ uint32_t dev_id, density;
+
+ if (!onenand_readw(ONENAND_REG_TECHNOLOGY)) {
+ dev_id = onenand_readw(ONENAND_REG_DEVICE_ID);
+ density = dev_id >> ONENAND_DEVICE_DENSITY_SHIFT;
+ density &= ONENAND_DEVICE_DENSITY_MASK;
+
+ if (density < ONENAND_DEVICE_DENSITY_4Gb)
+ return PAGE_2K;
+
+ if (dev_id & ONENAND_DEVICE_IS_DDP)
+ return PAGE_2K;
+ }
+
+ return PAGE_4K;
+}
+
+static int onenand_spl_read_page(uint32_t block, uint32_t page, uint32_t *buf,
+ enum onenand_spl_pagesize pagesize)
+{
+ const uint32_t addr = CONFIG_SYS_ONENAND_BASE + ONENAND_DATARAM;
+ uint32_t offset;
+
+ onenand_writew(onenand_block_address(block),
+ ONENAND_REG_START_ADDRESS1);
+
+ onenand_writew(onenand_bufferram_address(block),
+ ONENAND_REG_START_ADDRESS2);
+
+ onenand_writew(onenand_sector_address(page),
+ ONENAND_REG_START_ADDRESS8);
+
+ onenand_writew(onenand_buffer_address(),
+ ONENAND_REG_START_BUFFER);
+
+ onenand_writew(ONENAND_INT_CLEAR, ONENAND_REG_INTERRUPT);
+
+ onenand_writew(ONENAND_CMD_READ, ONENAND_REG_COMMAND);
+
+ while (!(onenand_readw(ONENAND_REG_INTERRUPT) & ONENAND_INT_READ))
+ continue;
+
+ /* Check for invalid block mark */
+ if (page < 2 && (onenand_readw(ONENAND_SPARERAM) != 0xffff))
+ return 1;
+
+ for (offset = 0; offset < pagesize; offset += 4)
+ buf[offset / 4] = readl(addr + offset);
+
+ return 0;
+}
+
+void onenand_spl_load_image(uint32_t offs, uint32_t size, void *dst)
+{
+ uint32_t *addr = (uint32_t *)dst;
+ uint32_t total_pages;
+ uint32_t block;
+ uint32_t page, rpage;
+ enum onenand_spl_pagesize pagesize;
+ int ret;
+
+ pagesize = onenand_spl_get_geometry();
+
+ /*
+ * The page can be either 2k or 4k, avoid using DIV_ROUND_UP to avoid
+ * pulling further unwanted functions into the SPL.
+ */
+ if (pagesize == 2048) {
+ total_pages = DIV_ROUND_UP(size, 2048);
+ page = offs / 2048;
+ } else {
+ total_pages = DIV_ROUND_UP(size, 4096);
+ page = offs / 4096;
+ }
+
+ for (; page <= total_pages; page++) {
+ block = page / ONENAND_PAGES_PER_BLOCK;
+ rpage = page & (ONENAND_PAGES_PER_BLOCK - 1);
+ ret = onenand_spl_read_page(block, rpage, addr, pagesize);
+ if (ret) {
+ total_pages += ONENAND_PAGES_PER_BLOCK;
+ page += ONENAND_PAGES_PER_BLOCK - 1;
+ } else {
+ addr += pagesize / 4;
+ }
+ }
+}
diff --git a/drivers/net/4xx_enet.c b/drivers/net/4xx_enet.c
index a771139..73700dd 100644
--- a/drivers/net/4xx_enet.c
+++ b/drivers/net/4xx_enet.c
@@ -92,6 +92,7 @@
#include <asm/ppc4xx-mal.h>
#include <miiphy.h>
#include <malloc.h>
+#include <linux/compiler.h>
#if !(defined(CONFIG_MII) || defined(CONFIG_CMD_MII))
#error "CONFIG_MII has to be defined!"
@@ -872,7 +873,7 @@
defined(CONFIG_440EPX) || defined(CONFIG_440GRX) || \
defined(CONFIG_460EX) || defined(CONFIG_460GT) || \
defined(CONFIG_405EX)
- int ethgroup = -1;
+ __maybe_unused int ethgroup = -1;
#endif
#endif
u32 bd_cached;
diff --git a/drivers/net/Makefile b/drivers/net/Makefile
index 15eee8d..d3df82e 100644
--- a/drivers/net/Makefile
+++ b/drivers/net/Makefile
@@ -63,7 +63,6 @@
COBJS-$(CONFIG_NS8382X) += ns8382x.o
COBJS-$(CONFIG_PCNET) += pcnet.o
COBJS-$(CONFIG_PLB2800_ETHER) += plb2800_eth.o
-COBJS-$(CONFIG_DRIVER_RTL8019) += rtl8019.o
COBJS-$(CONFIG_RTL8139) += rtl8139.o
COBJS-$(CONFIG_RTL8169) += rtl8169.o
COBJS-$(CONFIG_SH_ETHER) += sh_eth.o
diff --git a/drivers/net/at91_emac.c b/drivers/net/at91_emac.c
index 97d2739..9bda1fc 100644
--- a/drivers/net/at91_emac.c
+++ b/drivers/net/at91_emac.c
@@ -474,11 +474,9 @@
static int at91emac_write_hwaddr(struct eth_device *netdev)
{
- emac_device *dev;
at91_emac_t *emac;
at91_pmc_t *pmc = (at91_pmc_t *) ATMEL_BASE_PMC;
emac = (at91_emac_t *) netdev->iobase;
- dev = (emac_device *) netdev->priv;
writel(1 << ATMEL_ID_EMAC, &pmc->pcer);
DEBUG_AT91EMAC("init MAC-ADDR %02x:%02x:%02x:%02x:%02x:%02x\n",
diff --git a/drivers/net/davinci_emac.c b/drivers/net/davinci_emac.c
index fa31159..36c33af 100644
--- a/drivers/net/davinci_emac.c
+++ b/drivers/net/davinci_emac.c
@@ -85,15 +85,17 @@
/* Receive packet buffers */
static unsigned char emac_rx_buffers[EMAC_MAX_RX_BUFFERS * (EMAC_MAX_ETHERNET_PKT_SIZE + EMAC_PKT_ALIGN)];
-#define MAX_PHY 3
+#ifndef CONFIG_SYS_DAVINCI_EMAC_PHY_COUNT
+#define CONFIG_SYS_DAVINCI_EMAC_PHY_COUNT 3
+#endif
/* PHY address for a discovered PHY (0xff - not found) */
-static u_int8_t active_phy_addr[MAX_PHY] = { 0xff, 0xff, 0xff };
+static u_int8_t active_phy_addr[CONFIG_SYS_DAVINCI_EMAC_PHY_COUNT];
/* number of PHY found active */
static u_int8_t num_phy;
-phy_t phy[MAX_PHY];
+phy_t phy[CONFIG_SYS_DAVINCI_EMAC_PHY_COUNT];
static int davinci_eth_set_mac_addr(struct eth_device *dev)
{
@@ -160,9 +162,8 @@
int j;
unsigned int count = 0;
- active_phy_addr[0] = 0xff;
- active_phy_addr[1] = 0xff;
- active_phy_addr[2] = 0xff;
+ for (i = 0; i < CONFIG_SYS_DAVINCI_EMAC_PHY_COUNT; i++)
+ active_phy_addr[i] = 0xff;
udelay(1000);
phy_act_state = readl(&adap_mdio->ALIVE);
@@ -175,7 +176,14 @@
for (i = 0, j = 0; i < 32; i++)
if (phy_act_state & (1 << i)) {
count++;
- active_phy_addr[j++] = i;
+ if (count < CONFIG_SYS_DAVINCI_EMAC_PHY_COUNT) {
+ active_phy_addr[j++] = i;
+ } else {
+ printf("%s: to many PHYs detected.\n",
+ __func__);
+ count = 0;
+ break;
+ }
}
num_phy = count;
@@ -752,7 +760,7 @@
if (!ret)
return(0);
else
- printf(" %d ETH PHY detected\n", ret);
+ debug_emac(" %d ETH PHY detected\n", ret);
/* Get PHY ID and initialize phy_ops for a detected PHY */
for (i = 0; i < num_phy; i++) {
diff --git a/drivers/net/e1000.c b/drivers/net/e1000.c
index 6eab7b2..6b71bd9 100644
--- a/drivers/net/e1000.c
+++ b/drivers/net/e1000.c
@@ -1370,7 +1370,6 @@
{
uint32_t ctrl;
uint32_t ctrl_ext;
- uint32_t icr;
uint32_t manc;
uint32_t pba = 0;
@@ -1443,7 +1442,7 @@
E1000_WRITE_REG(hw, IMC, 0xffffffff);
/* Clear any pending interrupt events. */
- icr = E1000_READ_REG(hw, ICR);
+ E1000_READ_REG(hw, ICR);
/* If MWI was previously enabled, reenable it. */
if (hw->mac_type == e1000_82542_rev2_0) {
@@ -4447,7 +4446,8 @@
mdelay(20);
/* Now enable the transmitter */
- e1000_write_phy_reg(hw, 0x2F5B, phy_saved_data);
+ if (!ret_val)
+ e1000_write_phy_reg(hw, 0x2F5B, phy_saved_data);
if (hw->mac_type == e1000_82547) {
uint16_t fused, fine, coarse;
diff --git a/drivers/net/e1000.h b/drivers/net/e1000.h
index d8400d4..fd1d8f8 100644
--- a/drivers/net/e1000.h
+++ b/drivers/net/e1000.h
@@ -1678,14 +1678,6 @@
#define EEPROM_EWEN_OPCODE 0x13 /* EERPOM erase/write enable */
#define EEPROM_EWDS_OPCODE 0x10 /* EERPOM erast/write disable */
-/* EEPROM Word Offsets */
-#define EEPROM_COMPAT 0x0003
-#define EEPROM_ID_LED_SETTINGS 0x0004
-#define EEPROM_INIT_CONTROL1_REG 0x000A
-#define EEPROM_INIT_CONTROL2_REG 0x000F
-#define EEPROM_FLASH_VERSION 0x0032
-#define EEPROM_CHECKSUM_REG 0x003F
-
/* Word definitions for ID LED Settings */
#define ID_LED_RESERVED_0000 0x0000
#define ID_LED_RESERVED_FFFF 0xFFFF
@@ -2479,7 +2471,6 @@
#define ADVERTISE_100_FULL 0x0008
#define ADVERTISE_1000_HALF 0x0010
#define ADVERTISE_1000_FULL 0x0020
-#define AUTONEG_ADVERTISE_SPEED_DEFAULT 0x002F /* Everything but 1000-Half */
#define ICH_FLASH_GFPREG 0x0000
#define ICH_FLASH_HSFSTS 0x0004
@@ -2504,7 +2495,6 @@
#define ICH_GFPREG_BASE_MASK 0x1FFF
#define ICH_FLASH_LINEAR_ADDR_MASK 0x00FFFFFF
-#define E1000_EEWR 0x0102C /* EEPROM Write Register - RW */
#define E1000_SW_FW_SYNC 0x05B5C /* Software-Firmware Synchronization - RW */
/* SPI EEPROM Status Register */
@@ -2599,7 +2589,6 @@
#define PHY_CFG_TIMEOUT 100
#define DEFAULT_80003ES2LAN_TIPG_IPGT_10_100 0x00000009
#define DEFAULT_80003ES2LAN_TIPG_IPGT_1000 0x00000008
-#define E1000_TXDMAC_DPP 0x00000001
#define AUTO_ALL_MODES 0
#ifndef E1000_MASTER_SLAVE
diff --git a/drivers/net/enc28j60.c b/drivers/net/enc28j60.c
index d55cacd..e2011ae 100644
--- a/drivers/net/enc28j60.c
+++ b/drivers/net/enc28j60.c
@@ -432,7 +432,6 @@
u16 pkt_len;
u16 copy_len;
u16 status;
- u8 eir_reg;
u8 pkt_cnt = 0;
u16 rxbuf_rdpt;
u8 hbuf[6];
@@ -476,7 +475,7 @@
/* read pktcnt */
pkt_cnt = enc_r8(enc, CTL_REG_EPKTCNT);
if (copy_len == 0) {
- eir_reg = enc_r8(enc, CTL_REG_EIR);
+ (void)enc_r8(enc, CTL_REG_EIR);
enc_reset_rx(enc);
printf("%s: receive copy_len=0\n", enc->dev->name);
continue;
@@ -489,7 +488,7 @@
NetReceive(packet, pkt_len);
if (enc_claim_bus(enc))
return;
- eir_reg = enc_r8(enc, CTL_REG_EIR);
+ (void)enc_r8(enc, CTL_REG_EIR);
} while (pkt_cnt);
/* Use EPKTCNT not EIR.PKTIF flag, see errata pt. 6 */
}
@@ -500,14 +499,13 @@
static void enc_poll(enc_dev_t *enc)
{
u8 eir_reg;
- u8 estat_reg;
u8 pkt_cnt;
#ifdef CONFIG_USE_IRQ
/* clear global interrupt enable bit in enc28j60 */
enc_bclr(enc, CTL_REG_EIE, ENC_EIE_INTIE);
#endif
- estat_reg = enc_r8(enc, CTL_REG_ESTAT);
+ (void)enc_r8(enc, CTL_REG_ESTAT);
eir_reg = enc_r8(enc, CTL_REG_EIR);
if (eir_reg & ENC_EIR_TXIF) {
/* clear TXIF bit in EIR */
diff --git a/drivers/net/fec_mxc.c b/drivers/net/fec_mxc.c
index 0c0c7cd..b05a4c0 100644
--- a/drivers/net/fec_mxc.c
+++ b/drivers/net/fec_mxc.c
@@ -42,6 +42,14 @@
#define CONFIG_FEC_XCV_TYPE MII100
#endif
+/*
+ * The i.MX28 operates with packets in big endian. We need to swap them before
+ * sending and after receiving.
+ */
+#ifdef CONFIG_MX28
+#define CONFIG_FEC_MXC_SWAP_PACKET
+#endif
+
#undef DEBUG
struct nbuf {
@@ -51,6 +59,32 @@
uint8_t head[16]; /**< MAC header(6 + 6 + 2) + 2(aligned) */
};
+#ifdef CONFIG_FEC_MXC_SWAP_PACKET
+static void swap_packet(uint32_t *packet, int length)
+{
+ int i;
+
+ for (i = 0; i < DIV_ROUND_UP(length, 4); i++)
+ packet[i] = __swab32(packet[i]);
+}
+#endif
+
+/*
+ * The i.MX28 has two ethernet interfaces, but they are not equal.
+ * Only the first one can access the MDIO bus.
+ */
+#ifdef CONFIG_MX28
+static inline struct ethernet_regs *fec_miiphy_fec_to_eth(struct fec_priv *fec)
+{
+ return (struct ethernet_regs *)MXS_ENET0_BASE;
+}
+#else
+static inline struct ethernet_regs *fec_miiphy_fec_to_eth(struct fec_priv *fec)
+{
+ return fec->eth;
+}
+#endif
+
/*
* MII-interface related functions
*/
@@ -59,7 +93,7 @@
{
struct eth_device *edev = eth_get_dev_by_name(dev);
struct fec_priv *fec = (struct fec_priv *)edev->priv;
- struct ethernet_regs *eth = fec->eth;
+ struct ethernet_regs *eth = fec_miiphy_fec_to_eth(fec);
uint32_t reg; /* convenient holder for the PHY register */
uint32_t phy; /* convenient holder for the PHY */
@@ -117,7 +151,7 @@
{
struct eth_device *edev = eth_get_dev_by_name(dev);
struct fec_priv *fec = (struct fec_priv *)edev->priv;
- struct ethernet_regs *eth = fec->eth;
+ struct ethernet_regs *eth = fec_miiphy_fec_to_eth(fec);
uint32_t reg; /* convenient holder for the PHY register */
uint32_t phy; /* convenient holder for the PHY */
@@ -572,6 +606,9 @@
* Note: We are always using the first buffer for transmission,
* the second will be empty and only used to stop the DMA engine
*/
+#ifdef CONFIG_FEC_MXC_SWAP_PACKET
+ swap_packet((uint32_t *)packet, length);
+#endif
writew(length, &fec->tbd_base[fec->tbd_index].data_length);
writel((uint32_t)packet, &fec->tbd_base[fec->tbd_index].data_pointer);
/*
@@ -668,6 +705,9 @@
/*
* Fill the buffer and pass it to upper layers
*/
+#ifdef CONFIG_FEC_MXC_SWAP_PACKET
+ swap_packet((uint32_t *)frame->data, frame_length);
+#endif
memcpy(buff, frame->data, frame_length);
NetReceive(buff, frame_length);
len = frame_length;
diff --git a/drivers/net/fm/fm.c b/drivers/net/fm/fm.c
index 23ef14b..846c372 100644
--- a/drivers/net/fm/fm.c
+++ b/drivers/net/fm/fm.c
@@ -395,7 +395,6 @@
int dev = CONFIG_SYS_MMC_ENV_DEV;
void *addr = malloc(CONFIG_SYS_FMAN_FW_LENGTH);
u32 cnt = CONFIG_SYS_FMAN_FW_LENGTH / 512;
- u32 n;
u32 blk = CONFIG_SYS_QE_FW_IN_MMC / 512;
struct mmc *mmc = find_mmc_device(CONFIG_SYS_MMC_ENV_DEV);
@@ -405,7 +404,7 @@
printf("\nMMC read: dev # %u, block # %u, count %u ...\n",
dev, blk, cnt);
mmc_init(mmc);
- n = mmc->block_dev.block_read(dev, blk, cnt, addr);
+ (void)mmc->block_dev.block_read(dev, blk, cnt, addr);
/* flush cache after read */
flush_cache((ulong)addr, cnt * 512);
}
diff --git a/drivers/net/rtl8019.c b/drivers/net/rtl8019.c
deleted file mode 100644
index f516afe..0000000
--- a/drivers/net/rtl8019.c
+++ /dev/null
@@ -1,271 +0,0 @@
-/*
- * Realtek 8019AS Ethernet
- * (C) Copyright 2002-2003
- * Xue Ligong(lgxue@hotmail.com),Wang Kehao, ESLAB, whut.edu.cn
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-/*
- * This code works in 8bit mode.
- * If you need to work in 16bit mode, PLS change it!
- */
-
-#include <common.h>
-#include <command.h>
-#include "rtl8019.h"
-#include <net.h>
-
-/* packet page register access functions */
-
-static unsigned char get_reg (unsigned int regno)
-{
- return (*(unsigned char *) regno);
-}
-
-static void put_reg (unsigned int regno, unsigned char val)
-{
- *(volatile unsigned char *) regno = val;
-}
-
-static void eth_reset (void)
-{
- unsigned char ucTemp;
-
- /* reset NIC */
- ucTemp = get_reg (RTL8019_RESET);
- put_reg (RTL8019_RESET, ucTemp);
- put_reg (RTL8019_INTERRUPTSTATUS, 0xff);
- udelay (2000); /* wait for 2ms */
-}
-
-void rtl8019_get_enetaddr (uchar * addr)
-{
- unsigned char i;
- unsigned char temp;
-
- eth_reset ();
-
- put_reg (RTL8019_COMMAND, RTL8019_REMOTEDMARD);
- put_reg (RTL8019_DATACONFIGURATION, 0x48);
- put_reg (RTL8019_REMOTESTARTADDRESS0, 0x00);
- put_reg (RTL8019_REMOTESTARTADDRESS1, 0x00);
- put_reg (RTL8019_REMOTEBYTECOUNT0, 12);
- put_reg (RTL8019_REMOTEBYTECOUNT1, 0x00);
- put_reg (RTL8019_COMMAND, RTL8019_REMOTEDMARD);
- printf ("MAC: ");
- for (i = 0; i < 6; i++) {
- temp = get_reg (RTL8019_DMA_DATA);
- *addr++ = temp;
- temp = get_reg (RTL8019_DMA_DATA);
- printf ("%x:", temp);
- }
-
- while ((!get_reg (RTL8019_INTERRUPTSTATUS) & 0x40));
- printf ("\b \n");
- put_reg (RTL8019_REMOTEBYTECOUNT0, 0x00);
- put_reg (RTL8019_REMOTEBYTECOUNT1, 0x00);
- put_reg (RTL8019_COMMAND, RTL8019_PAGE0);
-}
-
-void eth_halt (void)
-{
- put_reg (RTL8019_COMMAND, 0x01);
-}
-
-int eth_init (bd_t * bd)
-{
- uchar enetaddr[6];
- eth_reset ();
- put_reg (RTL8019_COMMAND, RTL8019_PAGE0STOP);
- put_reg (RTL8019_DATACONFIGURATION, 0x48);
- put_reg (RTL8019_REMOTEBYTECOUNT0, 0x00);
- put_reg (RTL8019_REMOTEBYTECOUNT1, 0x00);
- put_reg (RTL8019_RECEIVECONFIGURATION, 0x00); /*00; */
- put_reg (RTL8019_TRANSMITPAGE, RTL8019_TPSTART);
- put_reg (RTL8019_TRANSMITCONFIGURATION, 0x02);
- put_reg (RTL8019_PAGESTART, RTL8019_PSTART);
- put_reg (RTL8019_BOUNDARY, RTL8019_PSTART);
- put_reg (RTL8019_PAGESTOP, RTL8019_PSTOP);
- put_reg (RTL8019_INTERRUPTSTATUS, 0xff);
- put_reg (RTL8019_INTERRUPTMASK, 0x11); /*b; */
- put_reg (RTL8019_COMMAND, RTL8019_PAGE1STOP);
- eth_getenv_enetaddr("ethaddr", enetaddr);
- put_reg (RTL8019_PHYSICALADDRESS0, enetaddr[0]);
- put_reg (RTL8019_PHYSICALADDRESS1, enetaddr[1]);
- put_reg (RTL8019_PHYSICALADDRESS2, enetaddr[2]);
- put_reg (RTL8019_PHYSICALADDRESS3, enetaddr[3]);
- put_reg (RTL8019_PHYSICALADDRESS4, enetaddr[4]);
- put_reg (RTL8019_PHYSICALADDRESS5, enetaddr[5]);
- put_reg (RTL8019_MULTIADDRESS0, 0x00);
- put_reg (RTL8019_MULTIADDRESS1, 0x00);
- put_reg (RTL8019_MULTIADDRESS2, 0x00);
- put_reg (RTL8019_MULTIADDRESS3, 0x00);
- put_reg (RTL8019_MULTIADDRESS4, 0x00);
- put_reg (RTL8019_MULTIADDRESS5, 0x00);
- put_reg (RTL8019_MULTIADDRESS6, 0x00);
- put_reg (RTL8019_MULTIADDRESS7, 0x00);
- put_reg (RTL8019_CURRENT, RTL8019_PSTART);
- put_reg (RTL8019_COMMAND, RTL8019_PAGE0);
- put_reg (RTL8019_TRANSMITCONFIGURATION, 0xe0); /*58; */
-
- return 0;
-}
-
-static unsigned char nic_to_pc (void)
-{
- unsigned char rec_head_status;
- unsigned char next_packet_pointer;
- unsigned char packet_length0;
- unsigned char packet_length1;
- unsigned short rxlen = 0;
- unsigned int i = 4;
- unsigned char current_point;
- unsigned char *addr;
-
- /*
- * The RTL8019's first 4B is packet status,page of next packet
- * and packet length(2B).So we receive the fist 4B.
- */
- put_reg (RTL8019_REMOTESTARTADDRESS1, get_reg (RTL8019_BOUNDARY));
- put_reg (RTL8019_REMOTESTARTADDRESS0, 0x00);
- put_reg (RTL8019_REMOTEBYTECOUNT1, 0x00);
- put_reg (RTL8019_REMOTEBYTECOUNT0, 0x04);
-
- put_reg (RTL8019_COMMAND, RTL8019_REMOTEDMARD);
-
- rec_head_status = get_reg (RTL8019_DMA_DATA);
- next_packet_pointer = get_reg (RTL8019_DMA_DATA);
- packet_length0 = get_reg (RTL8019_DMA_DATA);
- packet_length1 = get_reg (RTL8019_DMA_DATA);
-
- put_reg (RTL8019_COMMAND, RTL8019_PAGE0);
- /*Packet length is in two 8bit registers */
- rxlen = packet_length1;
- rxlen = (((rxlen << 8) & 0xff00) + packet_length0);
- rxlen -= 4;
-
- if (rxlen > PKTSIZE_ALIGN + PKTALIGN)
- printf ("packet too big!\n");
-
- /*Receive the packet */
- put_reg (RTL8019_REMOTESTARTADDRESS0, 0x04);
- put_reg (RTL8019_REMOTESTARTADDRESS1, get_reg (RTL8019_BOUNDARY));
-
- put_reg (RTL8019_REMOTEBYTECOUNT0, (rxlen & 0xff));
- put_reg (RTL8019_REMOTEBYTECOUNT1, ((rxlen >> 8) & 0xff));
-
-
- put_reg (RTL8019_COMMAND, RTL8019_REMOTEDMARD);
-
- for (addr = (unsigned char *) NetRxPackets[0], i = rxlen; i > 0; i--)
- *addr++ = get_reg (RTL8019_DMA_DATA);
- /* Pass the packet up to the protocol layers. */
- NetReceive (NetRxPackets[0], rxlen);
-
- while (!(get_reg (RTL8019_INTERRUPTSTATUS)) & 0x40); /* wait for the op. */
-
- /*
- * To test whether the packets are all received,get the
- * location of current point
- */
- put_reg (RTL8019_COMMAND, RTL8019_PAGE1);
- current_point = get_reg (RTL8019_CURRENT);
- put_reg (RTL8019_COMMAND, RTL8019_PAGE0);
- put_reg (RTL8019_BOUNDARY, next_packet_pointer);
- return current_point;
-}
-
-/* Get a data block via Ethernet */
-extern int eth_rx (void)
-{
- unsigned char temp, current_point;
-
- put_reg (RTL8019_COMMAND, RTL8019_PAGE0);
-
- while (1) {
- temp = get_reg (RTL8019_INTERRUPTSTATUS);
-
- if (temp & 0x90) {
- /*overflow */
- put_reg (RTL8019_COMMAND, RTL8019_PAGE0STOP);
- udelay (2000);
- put_reg (RTL8019_REMOTEBYTECOUNT0, 0);
- put_reg (RTL8019_REMOTEBYTECOUNT1, 0);
- put_reg (RTL8019_TRANSMITCONFIGURATION, 2);
- do {
- current_point = nic_to_pc ();
- } while (get_reg (RTL8019_BOUNDARY) != current_point);
-
- put_reg (RTL8019_TRANSMITCONFIGURATION, 0xe0);
- }
-
- if (temp & 0x1) {
- /*packet received */
- do {
- put_reg (RTL8019_INTERRUPTSTATUS, 0x01);
- current_point = nic_to_pc ();
- } while (get_reg (RTL8019_BOUNDARY) != current_point);
- }
-
- if (!(temp & 0x1))
- return 0;
- /* done and exit. */
- }
-}
-
-/* Send a data block via Ethernet. */
-extern int eth_send (volatile void *packet, int length)
-{
- volatile unsigned char *p;
- unsigned int pn;
-
- pn = length;
- p = (volatile unsigned char *) packet;
-
- while (get_reg (RTL8019_COMMAND) == RTL8019_TRANSMIT);
-
- put_reg (RTL8019_REMOTESTARTADDRESS0, 0);
- put_reg (RTL8019_REMOTESTARTADDRESS1, RTL8019_TPSTART);
- put_reg (RTL8019_REMOTEBYTECOUNT0, (pn & 0xff));
- put_reg (RTL8019_REMOTEBYTECOUNT1, ((pn >> 8) & 0xff));
-
- put_reg (RTL8019_COMMAND, RTL8019_REMOTEDMAWR);
- while (pn > 0) {
- put_reg (RTL8019_DMA_DATA, *p++);
- pn--;
- }
-
- pn = length;
-
- while (pn < 60) { /*Padding */
- put_reg (RTL8019_DMA_DATA, 0);
- pn++;
- }
-
- while (!(get_reg (RTL8019_INTERRUPTSTATUS)) & 0x40);
-
- put_reg (RTL8019_INTERRUPTSTATUS, 0x40);
- put_reg (RTL8019_TRANSMITPAGE, RTL8019_TPSTART);
- put_reg (RTL8019_TRANSMITBYTECOUNT0, (pn & 0xff));
- put_reg (RTL8019_TRANSMITBYTECOUNT1, ((pn >> 8 & 0xff)));
- put_reg (RTL8019_COMMAND, RTL8019_TRANSMIT);
-
- return 0;
-}
diff --git a/drivers/net/rtl8019.h b/drivers/net/rtl8019.h
deleted file mode 100644
index ae5163c..0000000
--- a/drivers/net/rtl8019.h
+++ /dev/null
@@ -1,114 +0,0 @@
-/*
- * Realtek 8019AS Ethernet
- * (C) Copyright 2002-2003
- * Xue Ligong(lgxue@hotmail.com),Wang Kehao, ESLAB, whut.edu.cn
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-/*
- * This code works in 8bit mode.
- * If you need to work in 16bit mode, PLS change it!
- */
-
-#include <asm/types.h>
-#include <config.h>
-
-#ifdef CONFIG_DRIVER_RTL8019
-
-#define RTL8019_REG_00 (RTL8019_BASE + 0x00)
-#define RTL8019_REG_01 (RTL8019_BASE + 0x01)
-#define RTL8019_REG_02 (RTL8019_BASE + 0x02)
-#define RTL8019_REG_03 (RTL8019_BASE + 0x03)
-#define RTL8019_REG_04 (RTL8019_BASE + 0x04)
-#define RTL8019_REG_05 (RTL8019_BASE + 0x05)
-#define RTL8019_REG_06 (RTL8019_BASE + 0x06)
-#define RTL8019_REG_07 (RTL8019_BASE + 0x07)
-#define RTL8019_REG_08 (RTL8019_BASE + 0x08)
-#define RTL8019_REG_09 (RTL8019_BASE + 0x09)
-#define RTL8019_REG_0a (RTL8019_BASE + 0x0a)
-#define RTL8019_REG_0b (RTL8019_BASE + 0x0b)
-#define RTL8019_REG_0c (RTL8019_BASE + 0x0c)
-#define RTL8019_REG_0d (RTL8019_BASE + 0x0d)
-#define RTL8019_REG_0e (RTL8019_BASE + 0x0e)
-#define RTL8019_REG_0f (RTL8019_BASE + 0x0f)
-#define RTL8019_REG_10 (RTL8019_BASE + 0x10)
-#define RTL8019_REG_1f (RTL8019_BASE + 0x1f)
-
-#define RTL8019_COMMAND RTL8019_REG_00
-#define RTL8019_PAGESTART RTL8019_REG_01
-#define RTL8019_PAGESTOP RTL8019_REG_02
-#define RTL8019_BOUNDARY RTL8019_REG_03
-#define RTL8019_TRANSMITSTATUS RTL8019_REG_04
-#define RTL8019_TRANSMITPAGE RTL8019_REG_04
-#define RTL8019_TRANSMITBYTECOUNT0 RTL8019_REG_05
-#define RTL8019_NCR RTL8019_REG_05
-#define RTL8019_TRANSMITBYTECOUNT1 RTL8019_REG_06
-#define RTL8019_INTERRUPTSTATUS RTL8019_REG_07
-#define RTL8019_CURRENT RTL8019_REG_07
-#define RTL8019_REMOTESTARTADDRESS0 RTL8019_REG_08
-#define RTL8019_CRDMA0 RTL8019_REG_08
-#define RTL8019_REMOTESTARTADDRESS1 RTL8019_REG_09
-#define RTL8019_CRDMA1 RTL8019_REG_09
-#define RTL8019_REMOTEBYTECOUNT0 RTL8019_REG_0a
-#define RTL8019_REMOTEBYTECOUNT1 RTL8019_REG_0b
-#define RTL8019_RECEIVESTATUS RTL8019_REG_0c
-#define RTL8019_RECEIVECONFIGURATION RTL8019_REG_0c
-#define RTL8019_TRANSMITCONFIGURATION RTL8019_REG_0d
-#define RTL8019_FAE_TALLY RTL8019_REG_0d
-#define RTL8019_DATACONFIGURATION RTL8019_REG_0e
-#define RTL8019_CRC_TALLY RTL8019_REG_0e
-#define RTL8019_INTERRUPTMASK RTL8019_REG_0f
-#define RTL8019_MISS_PKT_TALLY RTL8019_REG_0f
-#define RTL8019_PHYSICALADDRESS0 RTL8019_REG_01
-#define RTL8019_PHYSICALADDRESS1 RTL8019_REG_02
-#define RTL8019_PHYSICALADDRESS2 RTL8019_REG_03
-#define RTL8019_PHYSICALADDRESS3 RTL8019_REG_04
-#define RTL8019_PHYSICALADDRESS4 RTL8019_REG_05
-#define RTL8019_PHYSICALADDRESS5 RTL8019_REG_06
-#define RTL8019_MULTIADDRESS0 RTL8019_REG_08
-#define RTL8019_MULTIADDRESS1 RTL8019_REG_09
-#define RTL8019_MULTIADDRESS2 RTL8019_REG_0a
-#define RTL8019_MULTIADDRESS3 RTL8019_REG_0b
-#define RTL8019_MULTIADDRESS4 RTL8019_REG_0c
-#define RTL8019_MULTIADDRESS5 RTL8019_REG_0d
-#define RTL8019_MULTIADDRESS6 RTL8019_REG_0e
-#define RTL8019_MULTIADDRESS7 RTL8019_REG_0f
-#define RTL8019_DMA_DATA RTL8019_REG_10
-#define RTL8019_RESET RTL8019_REG_1f
-
-#define RTL8019_PAGE0 0x22
-#define RTL8019_PAGE1 0x62
-#define RTL8019_PAGE0DMAWRITE 0x12
-#define RTL8019_PAGE2DMAWRITE 0x92
-#define RTL8019_REMOTEDMAWR 0x12
-#define RTL8019_REMOTEDMARD 0x0A
-#define RTL8019_ABORTDMAWR 0x32
-#define RTL8019_ABORTDMARD 0x2A
-#define RTL8019_PAGE0STOP 0x21
-#define RTL8019_PAGE1STOP 0x61
-#define RTL8019_TRANSMIT 0x26
-#define RTL8019_TXINPROGRESS 0x04
-#define RTL8019_SEND 0x1A
-
-#define RTL8019_PSTART 0x4c
-#define RTL8019_PSTOP 0x80
-#define RTL8019_TPSTART 0x40
-
-#endif /*end of CONFIG_DRIVER_RTL8019*/
diff --git a/drivers/net/smc911x.h b/drivers/net/smc911x.h
index 8ce08a9..a290073 100644
--- a/drivers/net/smc911x.h
+++ b/drivers/net/smc911x.h
@@ -471,8 +471,11 @@
{
int timeout;
- /* Take out of PM setting first */
- if (smc911x_reg_read(dev, PMT_CTRL) & PMT_CTRL_READY) {
+ /*
+ * Take out of PM setting first
+ * Device is already wake up if PMT_CTRL_READY bit is set
+ */
+ if ((smc911x_reg_read(dev, PMT_CTRL) & PMT_CTRL_READY) == 0) {
/* Write to the bytetest will take out of powerdown */
smc911x_reg_write(dev, BYTE_TEST, 0x0);
diff --git a/drivers/net/tsec.c b/drivers/net/tsec.c
index 78ffc95..160bc05 100644
--- a/drivers/net/tsec.c
+++ b/drivers/net/tsec.c
@@ -19,6 +19,7 @@
#include <tsec.h>
#include <fsl_mdio.h>
#include <asm/errno.h>
+#include <asm/processor.h>
DECLARE_GLOBAL_DATA_PTR;
@@ -43,6 +44,9 @@
#error "rtx must be 64-bit aligned"
#endif
+static int tsec_send(struct eth_device *dev,
+ volatile void *packet, int length);
+
/* Default initializations for TSEC controllers. */
static struct tsec_info_struct tsec_info[] = {
@@ -236,6 +240,87 @@
(phydev->port == PORT_FIBRE) ? ", fiber mode" : "");
}
+#ifdef CONFIG_SYS_FSL_ERRATUM_NMG_ETSEC129
+/*
+ * When MACCFG1[Rx_EN] is enabled during system boot as part
+ * of the eTSEC port initialization sequence,
+ * the eTSEC Rx logic may not be properly initialized.
+ */
+void redundant_init(struct eth_device *dev)
+{
+ struct tsec_private *priv = dev->priv;
+ tsec_t *regs = priv->regs;
+ uint t, count = 0;
+ int fail = 1;
+ static const u8 pkt[] = {
+ 0x00, 0x1e, 0x4f, 0x12, 0xcb, 0x2c, 0x00, 0x25,
+ 0x64, 0xbb, 0xd1, 0xab, 0x08, 0x00, 0x45, 0x00,
+ 0x00, 0x5c, 0xdd, 0x22, 0x00, 0x00, 0x80, 0x01,
+ 0x1f, 0x71, 0x0a, 0xc1, 0x14, 0x22, 0x0a, 0xc1,
+ 0x14, 0x6a, 0x08, 0x00, 0xef, 0x7e, 0x02, 0x00,
+ 0x94, 0x05, 0x61, 0x62, 0x63, 0x64, 0x65, 0x66,
+ 0x67, 0x68, 0x69, 0x6a, 0x6b, 0x6c, 0x6d, 0x6e,
+ 0x6f, 0x70, 0x71, 0x72, 0x73, 0x74, 0x75, 0x76,
+ 0x77, 0x61, 0x62, 0x63, 0x64, 0x65, 0x66, 0x67,
+ 0x68, 0x69, 0x6a, 0x6b, 0x6c, 0x6d, 0x6e, 0x6f,
+ 0x70, 0x71, 0x72, 0x73, 0x74, 0x75, 0x76, 0x77,
+ 0x61, 0x62, 0x63, 0x64, 0x65, 0x66, 0x67, 0x68,
+ 0x69, 0x6a, 0x6b, 0x6c, 0x6d, 0x6e, 0x6f, 0x70,
+ 0x71, 0x72};
+
+ /* Enable promiscuous mode */
+ setbits_be32(®s->rctrl, 0x8);
+ /* Enable loopback mode */
+ setbits_be32(®s->maccfg1, MACCFG1_LOOPBACK);
+ /* Enable transmit and receive */
+ setbits_be32(®s->maccfg1, MACCFG1_RX_EN | MACCFG1_TX_EN);
+
+ /* Tell the DMA it is clear to go */
+ setbits_be32(®s->dmactrl, DMACTRL_INIT_SETTINGS);
+ out_be32(®s->tstat, TSTAT_CLEAR_THALT);
+ out_be32(®s->rstat, RSTAT_CLEAR_RHALT);
+ clrbits_be32(®s->dmactrl, DMACTRL_GRS | DMACTRL_GTS);
+
+ do {
+ tsec_send(dev, (void *)pkt, sizeof(pkt));
+
+ /* Wait for buffer to be received */
+ for (t = 0; rtx.rxbd[rxIdx].status & RXBD_EMPTY; t++) {
+ if (t >= 10 * TOUT_LOOP) {
+ printf("%s: tsec: rx error\n", dev->name);
+ break;
+ }
+ }
+
+ if (!memcmp(pkt, (void *)NetRxPackets[rxIdx], sizeof(pkt)))
+ fail = 0;
+
+ rtx.rxbd[rxIdx].length = 0;
+ rtx.rxbd[rxIdx].status =
+ RXBD_EMPTY | (((rxIdx + 1) == PKTBUFSRX) ? RXBD_WRAP : 0);
+ rxIdx = (rxIdx + 1) % PKTBUFSRX;
+
+ if (in_be32(®s->ievent) & IEVENT_BSY) {
+ out_be32(®s->ievent, IEVENT_BSY);
+ out_be32(®s->rstat, RSTAT_CLEAR_RHALT);
+ }
+ if (fail) {
+ printf("loopback recv packet error!\n");
+ clrbits_be32(®s->maccfg1, MACCFG1_RX_EN);
+ udelay(1000);
+ setbits_be32(®s->maccfg1, MACCFG1_RX_EN);
+ }
+ } while ((count++ < 4) && (fail == 1));
+
+ if (fail)
+ panic("eTSEC init fail!\n");
+ /* Disable promiscuous mode */
+ clrbits_be32(®s->rctrl, 0x8);
+ /* Disable loopback mode */
+ clrbits_be32(®s->maccfg1, MACCFG1_LOOPBACK);
+}
+#endif
+
/* Set up the buffers and their descriptors, and bring up the
* interface
*/
@@ -248,6 +333,9 @@
/* reset the indices to zero */
rxIdx = 0;
txIdx = 0;
+#ifdef CONFIG_SYS_FSL_ERRATUM_NMG_ETSEC129
+ uint svr;
+#endif
/* Point to the buffer descriptors */
out_be32(®s->tbase, (unsigned int)(&rtx.txbd[txIdx]));
@@ -269,6 +357,11 @@
}
rtx.txbd[TX_BUF_CNT - 1].status |= TXBD_WRAP;
+#ifdef CONFIG_SYS_FSL_ERRATUM_NMG_ETSEC129
+ svr = get_svr();
+ if ((SVR_MAJ(svr) == 1) || IS_SVR_REV(svr, 2, 0))
+ redundant_init(dev);
+#endif
/* Enable Transmit and Receive */
setbits_be32(®s->maccfg1, MACCFG1_RX_EN | MACCFG1_TX_EN);
diff --git a/drivers/qe/uec.c b/drivers/qe/uec.c
index 1ecb137..3e46e35 100644
--- a/drivers/qe/uec.c
+++ b/drivers/qe/uec.c
@@ -264,13 +264,10 @@
static int uec_stop(uec_private_t *uec, comm_dir_e mode)
{
- ucc_fast_private_t *uccf;
-
if (!uec || !uec->uccf) {
printf("%s: No handle passed.\n", __FUNCTION__);
return -EINVAL;
}
- uccf = uec->uccf;
/* check if the UCC number is in range. */
if (uec->uec_info->uf_info.ucc_num >= UCC_MAX_NUM) {
@@ -325,7 +322,6 @@
phy_interface_t if_mode, int speed)
{
phy_interface_t enet_if_mode;
- uec_info_t *uec_info;
uec_t *uec_regs;
u32 upsmr;
u32 maccfg2;
@@ -335,7 +331,6 @@
return -EINVAL;
}
- uec_info = uec->uec_info;
uec_regs = uec->uec_regs;
enet_if_mode = if_mode;
@@ -516,12 +511,10 @@
static void adjust_link(struct eth_device *dev)
{
uec_private_t *uec = (uec_private_t *)dev->priv;
- uec_t *uec_regs;
struct uec_mii_info *mii_info = uec->mii_info;
extern void change_phy_interface_mode(struct eth_device *dev,
phy_interface_t mode, int speed);
- uec_regs = uec->uec_regs;
if (mii_info->link) {
/* Now we make sure that we can be in full duplex mode.
diff --git a/drivers/rtc/Makefile b/drivers/rtc/Makefile
index a16f590..faf4fcd 100644
--- a/drivers/rtc/Makefile
+++ b/drivers/rtc/Makefile
@@ -57,6 +57,7 @@
COBJS-$(CONFIG_RTC_MPC5200) += mpc5xxx.o
COBJS-$(CONFIG_RTC_MPC8xx) += mpc8xx.o
COBJS-$(CONFIG_RTC_MV) += mvrtc.o
+COBJS-$(CONFIG_RTC_MXS) += mxsrtc.o
COBJS-$(CONFIG_RTC_PCF8563) += pcf8563.o
COBJS-$(CONFIG_RTC_PL031) += pl031.o
COBJS-$(CONFIG_RTC_PT7C4338) += pt7c4338.o
diff --git a/drivers/rtc/mxsrtc.c b/drivers/rtc/mxsrtc.c
new file mode 100644
index 0000000..5beb1a0
--- /dev/null
+++ b/drivers/rtc/mxsrtc.c
@@ -0,0 +1,86 @@
+/*
+ * Freescale i.MX28 RTC Driver
+ *
+ * Copyright (C) 2011 Marek Vasut <marek.vasut@gmail.com>
+ * on behalf of DENX Software Engineering GmbH
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
+ *
+ */
+
+#include <common.h>
+#include <rtc.h>
+#include <asm/io.h>
+#include <asm/arch/imx-regs.h>
+#include <asm/arch/sys_proto.h>
+
+#define MXS_RTC_MAX_TIMEOUT 1000000
+
+/* Set time in seconds since 1970-01-01 */
+int mxs_rtc_set_time(uint32_t secs)
+{
+ struct mx28_rtc_regs *rtc_regs = (struct mx28_rtc_regs *)MXS_RTC_BASE;
+ int ret;
+
+ writel(secs, &rtc_regs->hw_rtc_seconds);
+
+ /*
+ * The 0x80 here means seconds were copied to analog. This information
+ * is taken from the linux kernel driver for the STMP37xx RTC since
+ * documentation doesn't mention it.
+ */
+ ret = mx28_wait_mask_clr(&rtc_regs->hw_rtc_stat_reg,
+ 0x80 << RTC_STAT_STALE_REGS_OFFSET, MXS_RTC_MAX_TIMEOUT);
+
+ if (ret)
+ printf("MXS RTC: Timeout waiting for update\n");
+
+ return ret;
+}
+
+int rtc_get(struct rtc_time *time)
+{
+ struct mx28_rtc_regs *rtc_regs = (struct mx28_rtc_regs *)MXS_RTC_BASE;
+ uint32_t secs;
+
+ secs = readl(&rtc_regs->hw_rtc_seconds);
+ to_tm(secs, time);
+
+ return 0;
+}
+
+int rtc_set(struct rtc_time *time)
+{
+ uint32_t secs;
+
+ secs = mktime(time->tm_year, time->tm_mon, time->tm_mday,
+ time->tm_hour, time->tm_min, time->tm_sec);
+
+ return mxs_rtc_set_time(secs);
+}
+
+void rtc_reset(void)
+{
+ struct mx28_rtc_regs *rtc_regs = (struct mx28_rtc_regs *)MXS_RTC_BASE;
+ int ret;
+
+ /* Set time to 1970-01-01 */
+ mxs_rtc_set_time(0);
+
+ /* Reset the RTC block */
+ ret = mx28_reset_block(&rtc_regs->hw_rtc_ctrl_reg);
+ if (ret)
+ printf("MXS RTC: Block reset timeout\n");
+}
diff --git a/drivers/rtc/s3c24x0_rtc.c b/drivers/rtc/s3c24x0_rtc.c
index 9667939..c16ff2e 100644
--- a/drivers/rtc/s3c24x0_rtc.c
+++ b/drivers/rtc/s3c24x0_rtc.c
@@ -34,8 +34,7 @@
#include <rtc.h>
#include <asm/io.h>
-
-/*#define DEBUG*/
+#include <linux/compiler.h>
typedef enum {
RTC_ENABLE,
@@ -64,7 +63,8 @@
{
struct s3c24x0_rtc *rtc = s3c24x0_get_base_rtc();
uchar sec, min, hour, mday, wday, mon, year;
- uchar a_sec, a_min, a_hour, a_date, a_mon, a_year, a_armed;
+ __maybe_unused uchar a_sec, a_min, a_hour, a_date,
+ a_mon, a_year, a_armed;
/* enable access to RTC registers */
SetRTC_Access(RTC_ENABLE);
diff --git a/drivers/serial/serial_pxa.c b/drivers/serial/serial_pxa.c
index 68469a4..84bb17c 100644
--- a/drivers/serial/serial_pxa.c
+++ b/drivers/serial/serial_pxa.c
@@ -1,4 +1,6 @@
/*
+ * Copyright (C) 2011 Marek Vasut <marek.vasut@gmail.com>
+ *
* (C) Copyright 2002
* Wolfgang Denk, DENX Software Engineering, <wd@denx.de>
*
@@ -32,148 +34,161 @@
#include <watchdog.h>
#include <serial.h>
#include <asm/arch/pxa-regs.h>
+#include <asm/arch/regs-uart.h>
#include <asm/io.h>
DECLARE_GLOBAL_DATA_PTR;
-#define FFUART_INDEX 0
-#define BTUART_INDEX 1
-#define STUART_INDEX 2
+/*
+ * The numbering scheme differs here for PXA25x, PXA27x and PXA3xx so we can
+ * easily handle enabling of clock.
+ */
+#ifdef CONFIG_CPU_MONAHANS
+#define UART_CLK_BASE CKENA_21_BTUART
+#define UART_CLK_REG CKENA
+#define BTUART_INDEX 0
+#define FFUART_INDEX 1
+#define STUART_INDEX 2
+#elif CONFIG_PXA250
+#define UART_CLK_BASE (1 << 4) /* HWUART */
+#define UART_CLK_REG CKEN
+#define HWUART_INDEX 0
+#define STUART_INDEX 1
+#define FFUART_INDEX 2
+#define BTUART_INDEX 3
+#else /* PXA27x */
+#define UART_CLK_BASE CKEN5_STUART
+#define UART_CLK_REG CKEN
+#define STUART_INDEX 0
+#define FFUART_INDEX 1
+#define BTUART_INDEX 2
+#endif
+
+/*
+ * Only PXA250 has HWUART, to avoid poluting the code with more macros,
+ * artificially introduce this.
+ */
+#ifndef CONFIG_PXA250
+#define HWUART_INDEX 0xff
+#endif
#ifndef CONFIG_SERIAL_MULTI
-#if defined (CONFIG_FFUART)
+#if defined(CONFIG_FFUART)
#define UART_INDEX FFUART_INDEX
-#elif defined (CONFIG_BTUART)
+#elif defined(CONFIG_BTUART)
#define UART_INDEX BTUART_INDEX
-#elif defined (CONFIG_STUART)
+#elif defined(CONFIG_STUART)
#define UART_INDEX STUART_INDEX
+#elif defined(CONFIG_HWUART)
+#define UART_INDEX HWUART_INDEX
#else
-#error "Bad: you didn't configure serial ..."
+#error "Please select CONFIG_(FF|BT|ST|HW)UART in board config file."
#endif
#endif
-void pxa_setbrg_dev (unsigned int uart_index)
+uint32_t pxa_uart_get_baud_divider(void)
{
- unsigned int quot = 0;
-
if (gd->baudrate == 1200)
- quot = 768;
+ return 768;
else if (gd->baudrate == 9600)
- quot = 96;
+ return 96;
else if (gd->baudrate == 19200)
- quot = 48;
+ return 48;
else if (gd->baudrate == 38400)
- quot = 24;
+ return 24;
else if (gd->baudrate == 57600)
- quot = 16;
+ return 16;
else if (gd->baudrate == 115200)
- quot = 8;
- else
- hang ();
+ return 8;
+ else /* Unsupported baudrate */
+ return 0;
+}
+struct pxa_uart_regs *pxa_uart_index_to_regs(uint32_t uart_index)
+{
switch (uart_index) {
- case FFUART_INDEX:
-#ifdef CONFIG_CPU_MONAHANS
- writel(readl(CKENA) | CKENA_22_FFUART, CKENA);
-#else
- writel(readl(CKEN) | CKEN6_FFUART, CKEN);
-#endif /* CONFIG_CPU_MONAHANS */
-
- writel(0, FFIER); /* Disable for now */
- writel(0, FFFCR); /* No fifos enabled */
-
- /* set baud rate */
- writel(LCR_WLS0 | LCR_WLS1 | LCR_DLAB, FFLCR);
- writel(quot & 0xff, FFDLL);
- writel(quot >> 8, FFDLH);
- writel(LCR_WLS0 | LCR_WLS1, FFLCR);
-
- writel(IER_UUE, FFIER); /* Enable FFUART */
- break;
-
- case BTUART_INDEX:
-#ifdef CONFIG_CPU_MONAHANS
- writel(readl(CKENA) | CKENA_21_BTUART, CKENA);
-#else
- writel(readl(CKEN) | CKEN7_BTUART, CKEN);
-#endif /* CONFIG_CPU_MONAHANS */
-
- writel(0, BTIER);
- writel(0, BTFCR);
-
- /* set baud rate */
- writel(LCR_DLAB, BTLCR);
- writel(quot & 0xff, BTDLL);
- writel(quot >> 8, BTDLH);
- writel(LCR_WLS0 | LCR_WLS1, BTLCR);
-
- writel(IER_UUE, BTIER); /* Enable BFUART */
-
- break;
-
- case STUART_INDEX:
-#ifdef CONFIG_CPU_MONAHANS
- writel(readl(CKENA) | CKENA_23_STUART, CKENA);
-#else
- writel(readl(CKEN) | CKEN5_STUART, CKEN);
-#endif /* CONFIG_CPU_MONAHANS */
-
- writel(0, STIER);
- writel(0, STFCR);
-
- /* set baud rate */
- writel(LCR_DLAB, STLCR);
- writel(quot & 0xff, STDLL);
- writel(quot >> 8, STDLH);
- writel(LCR_WLS0 | LCR_WLS1, STLCR);
-
- writel(IER_UUE, STIER); /* Enable STUART */
- break;
-
- default:
- hang();
+ case FFUART_INDEX: return (struct pxa_uart_regs *)FFUART_BASE;
+ case BTUART_INDEX: return (struct pxa_uart_regs *)BTUART_BASE;
+ case STUART_INDEX: return (struct pxa_uart_regs *)STUART_BASE;
+ case HWUART_INDEX: return (struct pxa_uart_regs *)HWUART_BASE;
+ default:
+ return NULL;
}
}
+void pxa_uart_toggle_clock(uint32_t uart_index, int enable)
+{
+ uint32_t clk_reg, clk_offset, reg;
+
+ clk_reg = UART_CLK_REG;
+ clk_offset = UART_CLK_BASE << uart_index;
+
+ reg = readl(clk_reg);
+
+ if (enable)
+ reg |= clk_offset;
+ else
+ reg &= ~clk_offset;
+
+ writel(reg, clk_reg);
+}
+
+/*
+ * Enable clock and set baud rate, parity etc.
+ */
+void pxa_setbrg_dev(uint32_t uart_index)
+{
+ uint32_t divider = 0;
+ struct pxa_uart_regs *uart_regs;
+
+ divider = pxa_uart_get_baud_divider();
+ if (!divider)
+ hang();
+
+ uart_regs = pxa_uart_index_to_regs(uart_index);
+ if (!uart_regs)
+ hang();
+
+ pxa_uart_toggle_clock(uart_index, 1);
+
+ /* Disable interrupts and FIFOs */
+ writel(0, &uart_regs->ier);
+ writel(0, &uart_regs->fcr);
+
+ /* Set baud rate */
+ writel(LCR_WLS0 | LCR_WLS1 | LCR_DLAB, &uart_regs->lcr);
+ writel(divider & 0xff, &uart_regs->dll);
+ writel(divider >> 8, &uart_regs->dlh);
+ writel(LCR_WLS0 | LCR_WLS1, &uart_regs->lcr);
+
+ /* Enable UART */
+ writel(IER_UUE, &uart_regs->ier);
+}
/*
* Initialise the serial port with the given baudrate. The settings
* are always 8 data bits, no parity, 1 stop bit, no start bits.
- *
*/
-int pxa_init_dev (unsigned int uart_index)
+int pxa_init_dev(unsigned int uart_index)
{
pxa_setbrg_dev (uart_index);
-
- return (0);
+ return 0;
}
-
/*
* Output a single byte to the serial port.
*/
-void pxa_putc_dev (unsigned int uart_index,const char c)
+void pxa_putc_dev(unsigned int uart_index, const char c)
{
- switch (uart_index) {
- case FFUART_INDEX:
- /* wait for room in the tx FIFO on FFUART */
- while ((readl(FFLSR) & LSR_TEMT) == 0)
- WATCHDOG_RESET (); /* Reset HW Watchdog, if needed */
- writel(c, FFTHR);
- break;
+ struct pxa_uart_regs *uart_regs;
- case BTUART_INDEX:
- while ((readl(BTLSR) & LSR_TEMT) == 0)
- WATCHDOG_RESET (); /* Reset HW Watchdog, if needed */
- writel(c, BTTHR);
- break;
+ uart_regs = pxa_uart_index_to_regs(uart_index);
+ if (!uart_regs)
+ hang();
- case STUART_INDEX:
- while ((readl(STLSR) & LSR_TEMT) == 0)
- WATCHDOG_RESET (); /* Reset HW Watchdog, if needed */
- writel(c, STTHR);
- break;
- }
+ while (!(readl(&uart_regs->lsr) & LSR_TEMT))
+ WATCHDOG_RESET();
+ writel(c, &uart_regs->thr);
/* If \n, also do \r */
if (c == '\n')
@@ -185,17 +200,15 @@
* otherwise. When the function is succesfull, the character read is
* written into its argument c.
*/
-int pxa_tstc_dev (unsigned int uart_index)
+int pxa_tstc_dev(unsigned int uart_index)
{
- switch (uart_index) {
- case FFUART_INDEX:
- return readl(FFLSR) & LSR_DR;
- case BTUART_INDEX:
- return readl(BTLSR) & LSR_DR;
- case STUART_INDEX:
- return readl(STLSR) & LSR_DR;
- }
- return -1;
+ struct pxa_uart_regs *uart_regs;
+
+ uart_regs = pxa_uart_index_to_regs(uart_index);
+ if (!uart_regs)
+ return -1;
+
+ return readl(&uart_regs->lsr) & LSR_DR;
}
/*
@@ -203,187 +216,86 @@
* otherwise. When the function is succesfull, the character read is
* written into its argument c.
*/
-int pxa_getc_dev (unsigned int uart_index)
+int pxa_getc_dev(unsigned int uart_index)
{
- switch (uart_index) {
- case FFUART_INDEX:
- while (!(readl(FFLSR) & LSR_DR))
- /* Reset HW Watchdog, if needed */
- WATCHDOG_RESET();
- return (char) readl(FFRBR) & 0xff;
+ struct pxa_uart_regs *uart_regs;
- case BTUART_INDEX:
- while (!(readl(BTLSR) & LSR_DR))
- /* Reset HW Watchdog, if needed */
- WATCHDOG_RESET();
- return (char) readl(BTRBR) & 0xff;
- case STUART_INDEX:
- while (!(readl(STLSR) & LSR_DR))
- /* Reset HW Watchdog, if needed */
- WATCHDOG_RESET();
- return (char) readl(STRBR) & 0xff;
- }
- return -1;
+ uart_regs = pxa_uart_index_to_regs(uart_index);
+ if (!uart_regs)
+ return -1;
+
+ while (!(readl(&uart_regs->lsr) & LSR_DR))
+ WATCHDOG_RESET();
+ return readl(&uart_regs->rbr) & 0xff;
}
-void
-pxa_puts_dev (unsigned int uart_index,const char *s)
+void pxa_puts_dev(unsigned int uart_index, const char *s)
{
- while (*s) {
- pxa_putc_dev (uart_index,*s++);
- }
+ while (*s)
+ pxa_putc_dev(uart_index, *s++);
}
-#if defined (CONFIG_FFUART)
-static int ffuart_init(void)
-{
- return pxa_init_dev(FFUART_INDEX);
-}
+#define pxa_uart(uart, UART) \
+ int uart##_init(void) \
+ { \
+ return pxa_init_dev(UART##_INDEX); \
+ } \
+ \
+ void uart##_setbrg(void) \
+ { \
+ return pxa_setbrg_dev(UART##_INDEX); \
+ } \
+ \
+ void uart##_putc(const char c) \
+ { \
+ return pxa_putc_dev(UART##_INDEX, c); \
+ } \
+ \
+ void uart##_puts(const char *s) \
+ { \
+ return pxa_puts_dev(UART##_INDEX, s); \
+ } \
+ \
+ int uart##_getc(void) \
+ { \
+ return pxa_getc_dev(UART##_INDEX); \
+ } \
+ \
+ int uart##_tstc(void) \
+ { \
+ return pxa_tstc_dev(UART##_INDEX); \
+ } \
-static void ffuart_setbrg(void)
-{
- return pxa_setbrg_dev(FFUART_INDEX);
-}
+#define pxa_uart_desc(uart) \
+ struct serial_device serial_##uart##_device = \
+ { \
+ "serial_"#uart, \
+ uart##_init, \
+ NULL, \
+ uart##_setbrg, \
+ uart##_getc, \
+ uart##_tstc, \
+ uart##_putc, \
+ uart##_puts, \
+ };
-static void ffuart_putc(const char c)
-{
- return pxa_putc_dev(FFUART_INDEX,c);
-}
+#define pxa_uart_multi(uart, UART) \
+ pxa_uart(uart, UART) \
+ pxa_uart_desc(uart)
-static void ffuart_puts(const char *s)
-{
- return pxa_puts_dev(FFUART_INDEX,s);
-}
-
-static int ffuart_getc(void)
-{
- return pxa_getc_dev(FFUART_INDEX);
-}
-
-static int ffuart_tstc(void)
-{
- return pxa_tstc_dev(FFUART_INDEX);
-}
-
-struct serial_device serial_ffuart_device =
-{
- "serial_ffuart",
- ffuart_init,
- NULL,
- ffuart_setbrg,
- ffuart_getc,
- ffuart_tstc,
- ffuart_putc,
- ffuart_puts,
-};
+#if defined(CONFIG_HWUART)
+ pxa_uart_multi(hwuart, HWUART)
+#endif
+#if defined(CONFIG_STUART)
+ pxa_uart_multi(stuart, STUART)
+#endif
+#if defined(CONFIG_FFUART)
+ pxa_uart_multi(ffuart, FFUART)
+#endif
+#if defined(CONFIG_BTUART)
+ pxa_uart_multi(btuart, BTUART)
#endif
-#if defined (CONFIG_BTUART)
-static int btuart_init(void)
-{
- return pxa_init_dev(BTUART_INDEX);
-}
-
-static void btuart_setbrg(void)
-{
- return pxa_setbrg_dev(BTUART_INDEX);
-}
-
-static void btuart_putc(const char c)
-{
- return pxa_putc_dev(BTUART_INDEX,c);
-}
-
-static void btuart_puts(const char *s)
-{
- return pxa_puts_dev(BTUART_INDEX,s);
-}
-
-static int btuart_getc(void)
-{
- return pxa_getc_dev(BTUART_INDEX);
-}
-
-static int btuart_tstc(void)
-{
- return pxa_tstc_dev(BTUART_INDEX);
-}
-
-struct serial_device serial_btuart_device =
-{
- "serial_btuart",
- btuart_init,
- NULL,
- btuart_setbrg,
- btuart_getc,
- btuart_tstc,
- btuart_putc,
- btuart_puts,
-};
+#ifndef CONFIG_SERIAL_MULTI
+ pxa_uart(serial, UART)
#endif
-
-#if defined (CONFIG_STUART)
-static int stuart_init(void)
-{
- return pxa_init_dev(STUART_INDEX);
-}
-
-static void stuart_setbrg(void)
-{
- return pxa_setbrg_dev(STUART_INDEX);
-}
-
-static void stuart_putc(const char c)
-{
- return pxa_putc_dev(STUART_INDEX,c);
-}
-
-static void stuart_puts(const char *s)
-{
- return pxa_puts_dev(STUART_INDEX,s);
-}
-
-static int stuart_getc(void)
-{
- return pxa_getc_dev(STUART_INDEX);
-}
-
-static int stuart_tstc(void)
-{
- return pxa_tstc_dev(STUART_INDEX);
-}
-
-struct serial_device serial_stuart_device =
-{
- "serial_stuart",
- stuart_init,
- NULL,
- stuart_setbrg,
- stuart_getc,
- stuart_tstc,
- stuart_putc,
- stuart_puts,
-};
-#endif
-
-
-#ifndef CONFIG_SERIAL_MULTI
-inline int serial_init(void) {
- return (pxa_init_dev(UART_INDEX));
-}
-void serial_setbrg(void) {
- pxa_setbrg_dev(UART_INDEX);
-}
-int serial_getc(void) {
- return(pxa_getc_dev(UART_INDEX));
-}
-int serial_tstc(void) {
- return(pxa_tstc_dev(UART_INDEX));
-}
-void serial_putc(const char c) {
- pxa_putc_dev(UART_INDEX,c);
-}
-void serial_puts(const char *s) {
- pxa_puts_dev(UART_INDEX,s);
-}
-#endif /* CONFIG_SERIAL_MULTI */
diff --git a/drivers/spi/Makefile b/drivers/spi/Makefile
index 84ad6fa..6f389f0 100644
--- a/drivers/spi/Makefile
+++ b/drivers/spi/Makefile
@@ -37,6 +37,7 @@
COBJS-$(CONFIG_MPC52XX_SPI) += mpc52xx_spi.o
COBJS-$(CONFIG_MPC8XXX_SPI) += mpc8xxx_spi.o
COBJS-$(CONFIG_MXC_SPI) += mxc_spi.o
+COBJS-$(CONFIG_MXS_SPI) += mxs_spi.o
COBJS-$(CONFIG_OC_TINY_SPI) += oc_tiny_spi.o
COBJS-$(CONFIG_OMAP3_SPI) += omap3_spi.o
COBJS-$(CONFIG_SOFT_SPI) += soft_spi.o
diff --git a/drivers/spi/atmel_spi.c b/drivers/spi/atmel_spi.c
index 33e38b6..83ef8e8 100644
--- a/drivers/spi/atmel_spi.c
+++ b/drivers/spi/atmel_spi.c
@@ -136,13 +136,11 @@
unsigned int len_tx;
unsigned int len_rx;
unsigned int len;
- int ret;
u32 status;
const u8 *txp = dout;
u8 *rxp = din;
u8 value;
- ret = 0;
if (bitlen == 0)
/* Finish any previously submitted transfers */
goto out;
diff --git a/drivers/spi/mxs_spi.c b/drivers/spi/mxs_spi.c
new file mode 100644
index 0000000..4c27fef
--- /dev/null
+++ b/drivers/spi/mxs_spi.c
@@ -0,0 +1,186 @@
+/*
+ * Freescale i.MX28 SPI driver
+ *
+ * Copyright (C) 2011 Marek Vasut <marek.vasut@gmail.com>
+ * on behalf of DENX Software Engineering GmbH
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ *
+ * NOTE: This driver only supports the SPI-controller chipselects,
+ * GPIO driven chipselects are not supported.
+ */
+
+#include <common.h>
+#include <malloc.h>
+#include <spi.h>
+#include <asm/errno.h>
+#include <asm/io.h>
+#include <asm/arch/clock.h>
+#include <asm/arch/imx-regs.h>
+#include <asm/arch/sys_proto.h>
+
+#define MXS_SPI_MAX_TIMEOUT 1000000
+#define MXS_SPI_PORT_OFFSET 0x2000
+
+struct mxs_spi_slave {
+ struct spi_slave slave;
+ uint32_t max_khz;
+ uint32_t mode;
+ struct mx28_ssp_regs *regs;
+};
+
+static inline struct mxs_spi_slave *to_mxs_slave(struct spi_slave *slave)
+{
+ return container_of(slave, struct mxs_spi_slave, slave);
+}
+
+void spi_init(void)
+{
+}
+
+struct spi_slave *spi_setup_slave(unsigned int bus, unsigned int cs,
+ unsigned int max_hz, unsigned int mode)
+{
+ struct mxs_spi_slave *mxs_slave;
+ uint32_t addr;
+
+ if (bus > 3) {
+ printf("MXS SPI: Max bus number is 3\n");
+ return NULL;
+ }
+
+ mxs_slave = malloc(sizeof(struct mxs_spi_slave));
+ if (!mxs_slave)
+ return NULL;
+
+ addr = MXS_SSP0_BASE + (bus * MXS_SPI_PORT_OFFSET);
+
+ mxs_slave->slave.bus = bus;
+ mxs_slave->slave.cs = cs;
+ mxs_slave->max_khz = max_hz / 1000;
+ mxs_slave->mode = mode;
+ mxs_slave->regs = (struct mx28_ssp_regs *)addr;
+
+ return &mxs_slave->slave;
+}
+
+void spi_free_slave(struct spi_slave *slave)
+{
+ struct mxs_spi_slave *mxs_slave = to_mxs_slave(slave);
+ free(mxs_slave);
+}
+
+int spi_claim_bus(struct spi_slave *slave)
+{
+ struct mxs_spi_slave *mxs_slave = to_mxs_slave(slave);
+ struct mx28_ssp_regs *ssp_regs = mxs_slave->regs;
+ uint32_t reg = 0;
+
+ mx28_reset_block(&ssp_regs->hw_ssp_ctrl0_reg);
+
+ writel(SSP_CTRL0_BUS_WIDTH_ONE_BIT, &ssp_regs->hw_ssp_ctrl0);
+
+ reg = SSP_CTRL1_SSP_MODE_SPI | SSP_CTRL1_WORD_LENGTH_EIGHT_BITS;
+ reg |= (mxs_slave->mode & SPI_CPOL) ? SSP_CTRL1_POLARITY : 0;
+ reg |= (mxs_slave->mode & SPI_CPHA) ? SSP_CTRL1_PHASE : 0;
+ writel(reg, &ssp_regs->hw_ssp_ctrl1);
+
+ writel(0, &ssp_regs->hw_ssp_cmd0);
+
+ mx28_set_ssp_busclock(slave->bus, mxs_slave->max_khz);
+
+ return 0;
+}
+
+void spi_release_bus(struct spi_slave *slave)
+{
+}
+
+static void mxs_spi_start_xfer(struct mx28_ssp_regs *ssp_regs)
+{
+ writel(SSP_CTRL0_LOCK_CS, &ssp_regs->hw_ssp_ctrl0_set);
+ writel(SSP_CTRL0_IGNORE_CRC, &ssp_regs->hw_ssp_ctrl0_clr);
+}
+
+static void mxs_spi_end_xfer(struct mx28_ssp_regs *ssp_regs)
+{
+ writel(SSP_CTRL0_LOCK_CS, &ssp_regs->hw_ssp_ctrl0_clr);
+ writel(SSP_CTRL0_IGNORE_CRC, &ssp_regs->hw_ssp_ctrl0_set);
+}
+
+int spi_xfer(struct spi_slave *slave, unsigned int bitlen,
+ const void *dout, void *din, unsigned long flags)
+{
+ struct mxs_spi_slave *mxs_slave = to_mxs_slave(slave);
+ struct mx28_ssp_regs *ssp_regs = mxs_slave->regs;
+ int len = bitlen / 8;
+ const char *tx = dout;
+ char *rx = din;
+
+ if (bitlen == 0)
+ return 0;
+
+ if (!rx && !tx)
+ return 0;
+
+ if (flags & SPI_XFER_BEGIN)
+ mxs_spi_start_xfer(ssp_regs);
+
+ while (len--) {
+ /* We transfer 1 byte */
+ writel(1, &ssp_regs->hw_ssp_xfer_size);
+
+ if ((flags & SPI_XFER_END) && !len)
+ mxs_spi_end_xfer(ssp_regs);
+
+ if (tx)
+ writel(SSP_CTRL0_READ, &ssp_regs->hw_ssp_ctrl0_clr);
+ else
+ writel(SSP_CTRL0_READ, &ssp_regs->hw_ssp_ctrl0_set);
+
+ writel(SSP_CTRL0_RUN, &ssp_regs->hw_ssp_ctrl0_set);
+
+ if (mx28_wait_mask_set(&ssp_regs->hw_ssp_ctrl0_reg,
+ SSP_CTRL0_RUN, MXS_SPI_MAX_TIMEOUT)) {
+ printf("MXS SPI: Timeout waiting for start\n");
+ return -1;
+ }
+
+ if (tx)
+ writel(*tx++, &ssp_regs->hw_ssp_data);
+
+ writel(SSP_CTRL0_DATA_XFER, &ssp_regs->hw_ssp_ctrl0_set);
+
+ if (rx) {
+ if (mx28_wait_mask_clr(&ssp_regs->hw_ssp_status_reg,
+ SSP_STATUS_FIFO_EMPTY, MXS_SPI_MAX_TIMEOUT)) {
+ printf("MXS SPI: Timeout waiting for data\n");
+ return -1;
+ }
+
+ *rx = readl(&ssp_regs->hw_ssp_data);
+ rx++;
+ }
+
+ if (mx28_wait_mask_clr(&ssp_regs->hw_ssp_ctrl0_reg,
+ SSP_CTRL0_RUN, MXS_SPI_MAX_TIMEOUT)) {
+ printf("MXS SPI: Timeout waiting for finish\n");
+ return -1;
+ }
+ }
+
+ return 0;
+}
diff --git a/drivers/usb/eth/smsc95xx.c b/drivers/usb/eth/smsc95xx.c
index 7ee4f87..2f63340 100644
--- a/drivers/usb/eth/smsc95xx.c
+++ b/drivers/usb/eth/smsc95xx.c
@@ -20,6 +20,7 @@
* MA 02111-1307 USA
*/
+#include <asm/unaligned.h>
#include <common.h>
#include <usb.h>
#include <linux/mii.h>
@@ -372,26 +373,21 @@
static int smsc95xx_write_hwaddr(struct eth_device *eth)
{
struct ueth_data *dev = (struct ueth_data *)eth->priv;
- u32 addr_lo, addr_hi;
+ u32 addr_lo = __get_unaligned_le32(ð->enetaddr[0]);
+ u32 addr_hi = __get_unaligned_le16(ð->enetaddr[4]);
int ret;
/* set hardware address */
debug("** %s()\n", __func__);
- addr_lo = cpu_to_le32(*eth->enetaddr);
- addr_hi = cpu_to_le16(*((u16 *)(eth->enetaddr + 4)));
ret = smsc95xx_write_reg(dev, ADDRL, addr_lo);
- if (ret < 0) {
- debug("Failed to write ADDRL: %d\n", ret);
+ if (ret < 0)
return ret;
- }
ret = smsc95xx_write_reg(dev, ADDRH, addr_hi);
if (ret < 0)
return ret;
- debug("MAC %02x:%02x:%02x:%02x:%02x:%02x\n",
- eth->enetaddr[0], eth->enetaddr[1],
- eth->enetaddr[2], eth->enetaddr[3],
- eth->enetaddr[4], eth->enetaddr[5]);
+
+ debug("MAC %pM\n", eth->enetaddr);
dev->have_hwaddr = 1;
return 0;
}
diff --git a/drivers/usb/host/Makefile b/drivers/usb/host/Makefile
index 51b2494..09abb75 100644
--- a/drivers/usb/host/Makefile
+++ b/drivers/usb/host/Makefile
@@ -41,6 +41,7 @@
COBJS-$(CONFIG_USB_EHCI_FSL) += ehci-fsl.o
endif
COBJS-$(CONFIG_USB_EHCI_MXC) += ehci-mxc.o
+COBJS-$(CONFIG_USB_EHCI_MXS) += ehci-mxs.o
COBJS-$(CONFIG_USB_EHCI_PPC4XX) += ehci-ppc4xx.o
COBJS-$(CONFIG_USB_EHCI_IXP4XX) += ehci-ixp.o
COBJS-$(CONFIG_USB_EHCI_KIRKWOOD) += ehci-kirkwood.o
diff --git a/drivers/usb/host/ehci-fsl.c b/drivers/usb/host/ehci-fsl.c
index 5a65d92..b2d294e 100644
--- a/drivers/usb/host/ehci-fsl.c
+++ b/drivers/usb/host/ehci-fsl.c
@@ -40,11 +40,13 @@
int ehci_hcd_init(void)
{
struct usb_ehci *ehci;
- char usb_phy[5];
const char *phy_type = NULL;
size_t len;
+#ifdef CONFIG_SYS_FSL_USB_INTERNAL_UTMI_PHY
+ char usb_phy[5];
usb_phy[0] = '\0';
+#endif
ehci = (struct usb_ehci *)CONFIG_SYS_FSL_USB_ADDR;
hccr = (struct ehci_hccr *)((uint32_t)&ehci->caplength);
diff --git a/drivers/usb/host/ehci-mxs.c b/drivers/usb/host/ehci-mxs.c
new file mode 100644
index 0000000..c795f23
--- /dev/null
+++ b/drivers/usb/host/ehci-mxs.c
@@ -0,0 +1,154 @@
+/*
+ * Freescale i.MX28 USB Host driver
+ *
+ * Copyright (C) 2011 Marek Vasut <marek.vasut@gmail.com>
+ * on behalf of DENX Software Engineering GmbH
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <asm/io.h>
+#include <asm/arch/regs-common.h>
+#include <asm/arch/regs-base.h>
+#include <asm/arch/regs-clkctrl.h>
+#include <asm/arch/regs-usb.h>
+#include <asm/arch/regs-usbphy.h>
+
+#include "ehci-core.h"
+#include "ehci.h"
+
+#if (CONFIG_EHCI_MXS_PORT != 0) && (CONFIG_EHCI_MXS_PORT != 1)
+#error "MXS EHCI: Invalid port selected!"
+#endif
+
+#ifndef CONFIG_EHCI_MXS_PORT
+#error "MXS EHCI: Please define correct port using CONFIG_EHCI_MXS_PORT!"
+#endif
+
+static struct ehci_mxs {
+ struct mx28_usb_regs *usb_regs;
+ struct mx28_usbphy_regs *phy_regs;
+} ehci_mxs;
+
+int mxs_ehci_get_port(struct ehci_mxs *mxs_usb, int port)
+{
+ uint32_t usb_base, phy_base;
+ switch (port) {
+ case 0:
+ usb_base = MXS_USBCTRL0_BASE;
+ phy_base = MXS_USBPHY0_BASE;
+ break;
+ case 1:
+ usb_base = MXS_USBCTRL1_BASE;
+ phy_base = MXS_USBPHY1_BASE;
+ break;
+ default:
+ printf("CONFIG_EHCI_MXS_PORT (port = %d)\n", port);
+ return -1;
+ }
+
+ mxs_usb->usb_regs = (struct mx28_usb_regs *)usb_base;
+ mxs_usb->phy_regs = (struct mx28_usbphy_regs *)phy_base;
+ return 0;
+}
+
+/* This DIGCTL register ungates clock to USB */
+#define HW_DIGCTL_CTRL 0x8001c000
+#define HW_DIGCTL_CTRL_USB0_CLKGATE (1 << 2)
+#define HW_DIGCTL_CTRL_USB1_CLKGATE (1 << 16)
+
+int ehci_hcd_init(void)
+{
+
+ int ret;
+ uint32_t usb_base, cap_base;
+ struct mx28_register *digctl_ctrl =
+ (struct mx28_register *)HW_DIGCTL_CTRL;
+ struct mx28_clkctrl_regs *clkctrl_regs =
+ (struct mx28_clkctrl_regs *)MXS_CLKCTRL_BASE;
+
+ ret = mxs_ehci_get_port(&ehci_mxs, CONFIG_EHCI_MXS_PORT);
+ if (ret)
+ return ret;
+
+ /* Reset the PHY block */
+ writel(USBPHY_CTRL_SFTRST, &ehci_mxs.phy_regs->hw_usbphy_ctrl_set);
+ udelay(10);
+ writel(USBPHY_CTRL_SFTRST | USBPHY_CTRL_CLKGATE,
+ &ehci_mxs.phy_regs->hw_usbphy_ctrl_clr);
+
+ /* Enable USB clock */
+ writel(CLKCTRL_PLL0CTRL0_EN_USB_CLKS | CLKCTRL_PLL0CTRL0_POWER,
+ &clkctrl_regs->hw_clkctrl_pll0ctrl0_set);
+ writel(CLKCTRL_PLL1CTRL0_EN_USB_CLKS | CLKCTRL_PLL1CTRL0_POWER,
+ &clkctrl_regs->hw_clkctrl_pll1ctrl0_set);
+
+ writel(HW_DIGCTL_CTRL_USB0_CLKGATE | HW_DIGCTL_CTRL_USB1_CLKGATE,
+ &digctl_ctrl->reg_clr);
+
+ /* Start USB PHY */
+ writel(0, &ehci_mxs.phy_regs->hw_usbphy_pwd);
+
+ /* Enable UTMI+ Level 2 and Level 3 compatibility */
+ writel(USBPHY_CTRL_ENUTMILEVEL3 | USBPHY_CTRL_ENUTMILEVEL2 | 1,
+ &ehci_mxs.phy_regs->hw_usbphy_ctrl_set);
+
+ usb_base = ((uint32_t)ehci_mxs.usb_regs) + 0x100;
+ hccr = (struct ehci_hccr *)usb_base;
+
+ cap_base = ehci_readl(&hccr->cr_capbase);
+ hcor = (struct ehci_hcor *)(usb_base + HC_LENGTH(cap_base));
+
+ return 0;
+}
+
+int ehci_hcd_stop(void)
+{
+ int ret;
+ uint32_t tmp;
+ struct mx28_register *digctl_ctrl =
+ (struct mx28_register *)HW_DIGCTL_CTRL;
+ struct mx28_clkctrl_regs *clkctrl_regs =
+ (struct mx28_clkctrl_regs *)MXS_CLKCTRL_BASE;
+
+ ret = mxs_ehci_get_port(&ehci_mxs, CONFIG_EHCI_MXS_PORT);
+ if (ret)
+ return ret;
+
+ /* Stop the USB port */
+ tmp = ehci_readl(&hcor->or_usbcmd);
+ tmp &= ~CMD_RUN;
+ ehci_writel(tmp, &hcor->or_usbcmd);
+
+ /* Disable the PHY */
+ tmp = USBPHY_PWD_RXPWDRX | USBPHY_PWD_RXPWDDIFF |
+ USBPHY_PWD_RXPWD1PT1 | USBPHY_PWD_RXPWDENV |
+ USBPHY_PWD_TXPWDV2I | USBPHY_PWD_TXPWDIBIAS |
+ USBPHY_PWD_TXPWDFS;
+ writel(tmp, &ehci_mxs.phy_regs->hw_usbphy_pwd);
+
+ /* Disable USB clock */
+ writel(CLKCTRL_PLL0CTRL0_EN_USB_CLKS,
+ &clkctrl_regs->hw_clkctrl_pll0ctrl0_clr);
+ writel(CLKCTRL_PLL1CTRL0_EN_USB_CLKS,
+ &clkctrl_regs->hw_clkctrl_pll1ctrl0_clr);
+
+ /* Gate off the USB clock */
+ writel(HW_DIGCTL_CTRL_USB0_CLKGATE | HW_DIGCTL_CTRL_USB1_CLKGATE,
+ &digctl_ctrl->reg_set);
+
+ return 0;
+}
diff --git a/drivers/video/bus_vcxk.c b/drivers/video/bus_vcxk.c
index 7aecb92..9c4714d 100644
--- a/drivers/video/bus_vcxk.c
+++ b/drivers/video/bus_vcxk.c
@@ -393,7 +393,6 @@
unsigned long width;
unsigned long height;
unsigned long bpp;
- unsigned long compression;
unsigned long lw;
@@ -404,7 +403,6 @@
bmp = (bmp_image_t *) addr;
if ((bmp->header.signature[0] == 'B') &&
(bmp->header.signature[1] == 'M')) {
- compression = le32_to_cpu(bmp->header.compression);
width = le32_to_cpu(bmp->header.width);
height = le32_to_cpu(bmp->header.height);
bpp = le16_to_cpu(bmp->header.bit_count);
diff --git a/drivers/video/cfb_console.c b/drivers/video/cfb_console.c
index 561883a..32e890c 100644
--- a/drivers/video/cfb_console.c
+++ b/drivers/video/cfb_console.c
@@ -203,6 +203,7 @@
#include <linux/types.h>
#include <stdio_dev.h>
#include <video_font.h>
+#include <video_font_data.h>
#if defined(CONFIG_CMD_DATE)
#include <rtc.h>
@@ -286,6 +287,7 @@
#ifdef CONFIG_VIDEO_LOGO
#ifdef CONFIG_VIDEO_BMP_LOGO
#include <bmp_logo.h>
+#include <bmp_logo_data.h>
#define VIDEO_LOGO_WIDTH BMP_LOGO_WIDTH
#define VIDEO_LOGO_HEIGHT BMP_LOGO_HEIGHT
#define VIDEO_LOGO_LUT_OFFSET BMP_LOGO_OFFSET
diff --git a/drivers/video/ct69000.c b/drivers/video/ct69000.c
index 3db614d..0ed5f41 100644
--- a/drivers/video/ct69000.c
+++ b/drivers/video/ct69000.c
@@ -35,9 +35,11 @@
#undef VGA_DEBUG
#undef VGA_DUMP_REG
#ifdef VGA_DEBUG
-#define PRINTF(fmt,args...) printf (fmt ,##args)
+#undef _DEBUG
+#define _DEBUG 1
#else
-#define PRINTF(fmt,args...)
+#undef _DEBUG
+#define _DEBUG 0
#endif
/* Macros */
@@ -740,7 +742,7 @@
}
m += param->mn_diff;
n += param->mn_diff;
- PRINTF ("VCO %d, pd %d, m %d n %d vld %d \n", fvco, pd, m, n, vld);
+ debug("VCO %d, pd %d, m %d n %d vld %d\n", fvco, pd, m, n, vld);
xr_cb = ((0x7 & PD) << 4) | (vld == param->vld_set ? 0x04 : 0);
/* All four of the registers used for dot clock 2 (XRC8 - XRCB) must be
* written, and in order from XRC8 to XRCB, before the hardware will
@@ -751,7 +753,7 @@
ctWrite_i (CT_XR_O, 0xca, 0); /* because of a hw bug I guess, but we write */
ctWrite_i (CT_XR_O, 0xcb, xr_cb); /* 0 to it for savety */
new_pixclock = ReadPixClckFromXrRegsBack (param);
- PRINTF ("pixelclock.set = %d, pixelclock.real = %d \n",
+ debug("pixelclock.set = %d, pixelclock.real = %d\n",
pixelclock, new_pixclock);
}
@@ -1119,7 +1121,7 @@
pGD->dprBase &= 0xfffff000;
pGD->dprBase += 0x00001000;
}
- PRINTF ("Cursor Start %x Pattern Start %x\n", pGD->dprBase,
+ debug("Cursor Start %x Pattern Start %x\n", pGD->dprBase,
PATTERN_ADR);
pGD->vprBase = pci_mem_base; /* Dummy */
pGD->cprBase = pci_mem_base; /* Dummy */
diff --git a/drivers/video/da8xx-fb.c b/drivers/video/da8xx-fb.c
index bca9fb5..a2981b1 100644
--- a/drivers/video/da8xx-fb.c
+++ b/drivers/video/da8xx-fb.c
@@ -685,7 +685,6 @@
void *video_hw_init(void)
{
struct da8xx_fb_par *par;
- int ret;
u32 size;
char *p;
@@ -738,7 +737,6 @@
if (lcd_init(par, &lcd_cfg, lcd_panel) < 0) {
printf("lcd_init failed\n");
- ret = -EFAULT;
goto err_release_fb;
}
@@ -754,7 +752,6 @@
(unsigned int)par->vram_virt);
if (!par->vram_virt) {
printf("GLCD: malloc for frame buffer failed\n");
- ret = -EINVAL;
goto err_release_fb;
}
diff --git a/drivers/video/fsl_diu_fb.c b/drivers/video/fsl_diu_fb.c
index cb43904..350241e 100644
--- a/drivers/video/fsl_diu_fb.c
+++ b/drivers/video/fsl_diu_fb.c
@@ -252,8 +252,10 @@
break;
case RESOLUTION(800, 600):
fsl_diu_mode_db = &fsl_diu_mode_800_600;
+ break;
case RESOLUTION(1024, 768):
fsl_diu_mode_db = &fsl_diu_mode_1024_768;
+ break;
case RESOLUTION(1280, 1024):
fsl_diu_mode_db = &fsl_diu_mode_1280_1024;
break;
diff --git a/drivers/video/mx3fb.c b/drivers/video/mx3fb.c
index f30deb3..eb75c6a 100644
--- a/drivers/video/mx3fb.c
+++ b/drivers/video/mx3fb.c
@@ -824,7 +824,7 @@
char *penv;
u32 memsize;
unsigned long t1, hsynch, vsynch;
- int bits_per_pixel, i, tmp, vesa_idx = 0, videomode;
+ int bits_per_pixel, i, tmp, videomode;
tmp = 0;
@@ -857,7 +857,6 @@
mode = (struct ctfb_res_modes *)
&res_mode_init[vesa_modes[i].resindex];
bits_per_pixel = vesa_modes[i].bits_per_pixel;
- vesa_idx = vesa_modes[i].resindex;
} else {
mode = (struct ctfb_res_modes *) &var_mode;
bits_per_pixel = video_get_params(mode, penv);
diff --git a/drivers/video/sed156x.c b/drivers/video/sed156x.c
index 707250d..a610b74 100644
--- a/drivers/video/sed156x.c
+++ b/drivers/video/sed156x.c
@@ -41,6 +41,7 @@
/* include the font data */
#include <video_font.h>
+#include <video_font_data.h>
#if VIDEO_FONT_WIDTH != 8 || VIDEO_FONT_HEIGHT != 16
#error Expecting VIDEO_FONT_WIDTH == 8 && VIDEO_FONT_HEIGHT == 16
diff --git a/examples/api/demo.c b/examples/api/demo.c
index 65e7491..19d38f6 100644
--- a/examples/api/demo.c
+++ b/examples/api/demo.c
@@ -48,6 +48,7 @@
ulong start, now;
struct device_info *di;
lbasize_t rlen;
+ struct display_info disinfo;
if (!api_search_sig(&sig))
return -1;
@@ -176,6 +177,36 @@
while ((env = ub_env_enum(env)) != NULL)
printf("%s = %s\n", env, ub_env_get(env));
+ printf("\n*** Display ***\n");
+
+ if (ub_display_get_info(DISPLAY_TYPE_LCD, &disinfo)) {
+ printf("LCD info: failed\n");
+ } else {
+ printf("LCD info:\n");
+ printf(" pixel width: %d\n", disinfo.pixel_width);
+ printf(" pixel height: %d\n", disinfo.pixel_height);
+ printf(" screen rows: %d\n", disinfo.screen_rows);
+ printf(" screen cols: %d\n", disinfo.screen_cols);
+ }
+ if (ub_display_get_info(DISPLAY_TYPE_VIDEO, &disinfo)) {
+ printf("video info: failed\n");
+ } else {
+ printf("video info:\n");
+ printf(" pixel width: %d\n", disinfo.pixel_width);
+ printf(" pixel height: %d\n", disinfo.pixel_height);
+ printf(" screen rows: %d\n", disinfo.screen_rows);
+ printf(" screen cols: %d\n", disinfo.screen_cols);
+ }
+
+ printf("*** Press any key to continue ***\n");
+ printf("got char 0x%x\n", ub_getc());
+
+ /*
+ * This only clears messages on screen, not on serial port. It is
+ * equivalent to a no-op if no display is available.
+ */
+ ub_display_clear();
+
/* reset */
printf("\n*** Resetting board ***\n");
ub_reset();
diff --git a/examples/api/glue.c b/examples/api/glue.c
index eff6a7e..d907e3f 100644
--- a/examples/api/glue.c
+++ b/examples/api/glue.c
@@ -402,3 +402,34 @@
return env_name;
}
+
+/****************************************
+ *
+ * display
+ *
+ ****************************************/
+
+int ub_display_get_info(int type, struct display_info *di)
+{
+ int err = 0;
+
+ if (!syscall(API_DISPLAY_GET_INFO, &err, (uint32_t)type, (uint32_t)di))
+ return API_ESYSC;
+
+ return err;
+}
+
+int ub_display_draw_bitmap(ulong bitmap, int x, int y)
+{
+ int err = 0;
+
+ if (!syscall(API_DISPLAY_DRAW_BITMAP, &err, bitmap, x, y))
+ return API_ESYSC;
+
+ return err;
+}
+
+void ub_display_clear(void)
+{
+ syscall(API_DISPLAY_CLEAR, NULL);
+}
diff --git a/examples/api/glue.h b/examples/api/glue.h
index 6bf47d0..e43f7d9 100644
--- a/examples/api/glue.h
+++ b/examples/api/glue.h
@@ -77,4 +77,9 @@
int ub_dev_recv(int handle, void *buf, int len, int *rlen);
struct device_info * ub_dev_get(int);
+/* display */
+int ub_display_get_info(int type, struct display_info *di);
+int ub_display_draw_bitmap(ulong bitmap, int x, int y);
+void ub_display_clear(void);
+
#endif /* _API_GLUE_H_ */
diff --git a/fs/yaffs2/yaffs_guts.c b/fs/yaffs2/yaffs_guts.c
index c4329af..f0ef8db 100644
--- a/fs/yaffs2/yaffs_guts.c
+++ b/fs/yaffs2/yaffs_guts.c
@@ -851,9 +851,8 @@
int retval = YAFFS_OK;
__u8 *data = yaffs_GetTempBuffer(dev, __LINE__);
yaffs_ExtendedTags tags;
- int result;
- result = yaffs_ReadChunkWithTagsFromNAND(dev, chunkInNAND, data, &tags);
+ yaffs_ReadChunkWithTagsFromNAND(dev, chunkInNAND, data, &tags);
if(tags.eccResult > YAFFS_ECC_RESULT_NO_ERROR)
retval = YAFFS_FAIL;
@@ -3460,7 +3459,6 @@
int prevChunkId;
int retVal = 0;
- int result = 0;
int newChunkId;
yaffs_ExtendedTags newTags;
@@ -3484,7 +3482,7 @@
prevChunkId = in->chunkId;
if (prevChunkId >= 0) {
- result = yaffs_ReadChunkWithTagsFromNAND(dev, prevChunkId,
+ yaffs_ReadChunkWithTagsFromNAND(dev, prevChunkId,
buffer, &oldTags);
yaffs_VerifyObjectHeader(in,oh,&oldTags,0);
@@ -3771,7 +3769,6 @@
yaffs_Object *theObj;
int usage;
int i;
- int pushout;
if (dev->nShortOpCaches > 0) {
/* Try find a non-dirty one... */
@@ -3790,7 +3787,6 @@
theObj = NULL;
usage = -1;
cache = NULL;
- pushout = -1;
for (i = 0; i < dev->nShortOpCaches; i++) {
if (dev->srCache[i].object &&
@@ -3800,7 +3796,6 @@
usage = dev->srCache[i].lastUse;
theObj = dev->srCache[i].object;
cache = &dev->srCache[i];
- pushout = i;
}
}
@@ -5234,7 +5229,6 @@
int startIterator;
int endIterator;
int nBlocksToScan = 0;
- int result;
int chunk;
int c;
@@ -5377,7 +5371,7 @@
/* Read the tags and decide what to do */
chunk = blk * dev->nChunksPerBlock + c;
- result = yaffs_ReadChunkWithTagsFromNAND(dev, chunk, NULL,
+ yaffs_ReadChunkWithTagsFromNAND(dev, chunk, NULL,
&tags);
/* Let's have a good look at this chunk... */
@@ -5474,7 +5468,7 @@
yaffs_SetChunkBit(dev, blk, c);
bi->pagesInUse++;
- result = yaffs_ReadChunkWithTagsFromNAND(dev, chunk,
+ yaffs_ReadChunkWithTagsFromNAND(dev, chunk,
chunkData,
NULL);
@@ -5744,8 +5738,6 @@
yaffs_ObjectHeader *oh;
yaffs_Device *dev = in->myDev;
yaffs_ExtendedTags tags;
- int result;
- int alloc_failed = 0;
if(!in)
return;
@@ -5760,7 +5752,8 @@
in->lazyLoaded = 0;
chunkData = yaffs_GetTempBuffer(dev, __LINE__);
- result = yaffs_ReadChunkWithTagsFromNAND(dev,in->chunkId,chunkData,&tags);
+ yaffs_ReadChunkWithTagsFromNAND(dev, in->chunkId,
+ chunkData, &tags);
oh = (yaffs_ObjectHeader *) chunkData;
in->yst_mode = oh->yst_mode;
@@ -5785,8 +5778,6 @@
if(in->variantType == YAFFS_OBJECT_TYPE_SYMLINK){
in->variant.symLinkVariant.alias =
yaffs_CloneString(oh->alias);
- if(!in->variant.symLinkVariant.alias)
- alloc_failed = 1; /* Not returned to caller */
}
yaffs_ReleaseTempBuffer(dev,chunkData, __LINE__);
@@ -5803,9 +5794,7 @@
int nBlocksToScan = 0;
int chunk;
- int result;
int c;
- int deleted;
yaffs_BlockState state;
yaffs_Object *hardList = NULL;
yaffs_BlockInfo *bi;
@@ -5971,8 +5960,6 @@
state = bi->blockState;
- deleted = 0;
-
/* For each chunk in each block that needs scanning.... */
foundChunksInBlock = 0;
for (c = dev->nChunksPerBlock - 1;
@@ -5985,7 +5972,7 @@
chunk = blk * dev->nChunksPerBlock + c;
- result = yaffs_ReadChunkWithTagsFromNAND(dev, chunk, NULL,
+ yaffs_ReadChunkWithTagsFromNAND(dev, chunk, NULL,
&tags);
/* Let's have a good look at this chunk... */
@@ -6132,7 +6119,7 @@
* living with invalid data until needed.
*/
- result = yaffs_ReadChunkWithTagsFromNAND(dev,
+ yaffs_ReadChunkWithTagsFromNAND(dev,
chunk,
chunkData,
NULL);
@@ -6654,7 +6641,6 @@
}
#endif
else {
- int result;
__u8 *buffer = yaffs_GetTempBuffer(obj->myDev, __LINE__);
yaffs_ObjectHeader *oh = (yaffs_ObjectHeader *) buffer;
@@ -6662,7 +6648,7 @@
memset(buffer, 0, obj->myDev->nDataBytesPerChunk);
if (obj->chunkId >= 0) {
- result = yaffs_ReadChunkWithTagsFromNAND(obj->myDev,
+ yaffs_ReadChunkWithTagsFromNAND(obj->myDev,
obj->chunkId, buffer,
NULL);
}
diff --git a/fs/yaffs2/yaffs_tagscompat.c b/fs/yaffs2/yaffs_tagscompat.c
index 70a8a8c..e872323 100644
--- a/fs/yaffs2/yaffs_tagscompat.c
+++ b/fs/yaffs2/yaffs_tagscompat.c
@@ -136,9 +136,8 @@
}
static void yaffs_GetTagsFromSpare(yaffs_Device * dev, yaffs_Spare * sparePtr,
- yaffs_Tags * tagsPtr)
+ yaffs_TagsUnion *tu)
{
- yaffs_TagsUnion *tu = (yaffs_TagsUnion *) tagsPtr;
int result;
tu->asBytes[0] = sparePtr->tagByte0;
@@ -150,7 +149,7 @@
tu->asBytes[6] = sparePtr->tagByte6;
tu->asBytes[7] = sparePtr->tagByte7;
- result = yaffs_CheckECCOnTags(tagsPtr);
+ result = yaffs_CheckECCOnTags(&tu->asTags);
if (result > 0) {
dev->tagsEccFixed++;
} else if (result < 0) {
@@ -437,7 +436,7 @@
{
yaffs_Spare spare;
- yaffs_Tags tags;
+ yaffs_TagsUnion tags;
yaffs_ECCResult eccResult;
static yaffs_Spare spareFF;
@@ -467,10 +466,10 @@
if (eTags->chunkUsed) {
yaffs_GetTagsFromSpare(dev, &spare, &tags);
- eTags->objectId = tags.objectId;
- eTags->chunkId = tags.chunkId;
- eTags->byteCount = tags.byteCount;
- eTags->serialNumber = tags.serialNumber;
+ eTags->objectId = tags.asTags.objectId;
+ eTags->chunkId = tags.asTags.chunkId;
+ eTags->byteCount = tags.asTags.byteCount;
+ eTags->serialNumber = tags.asTags.serialNumber;
}
}
diff --git a/include/.gitignore b/include/.gitignore
index ec224c5..7cd3e90 100644
--- a/include/.gitignore
+++ b/include/.gitignore
@@ -1,5 +1,6 @@
/autoconf.mk*
/asm
/bmp_logo.h
+/bmp_logo_data.h
/config.h
/config.mk
diff --git a/include/andestech/andes_pcu.h b/include/andestech/andes_pcu.h
new file mode 100644
index 0000000..b4dbd71
--- /dev/null
+++ b/include/andestech/andes_pcu.h
@@ -0,0 +1,367 @@
+/*
+ * (C) Copyright 2011 Andes Technology Corp
+ * Macpaul Lin <macpaul@andestech.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
+ */
+
+/*
+ * Andes Power Control Unit
+ */
+#ifndef __ANDES_PCU_H
+#define __ANDES_PCU_H
+
+#ifndef __ASSEMBLY__
+
+struct pcs {
+ unsigned int cr; /* PCSx Configuration (clock scaling) */
+ unsigned int parm; /* PCSx Parameter*/
+ unsigned int stat1; /* PCSx Status 1 */
+ unsigned int stat2; /* PCSx Stusts 2 */
+ unsigned int pdd; /* PCSx PDD */
+};
+
+struct andes_pcu {
+ unsigned int rev; /* 0x00 - PCU Revision */
+ unsigned int spinfo; /* 0x04 - Scratch Pad Info */
+ unsigned int rsvd1[2]; /* 0x08-0x0C: Reserved */
+ unsigned int soc_id; /* 0x10 - SoC ID */
+ unsigned int soc_ahb; /* 0x14 - SoC AHB configuration */
+ unsigned int soc_apb; /* 0x18 - SoC APB configuration */
+ unsigned int rsvd2; /* 0x1C */
+ unsigned int dcsrcr0; /* 0x20 - Driving Capability
+ and Slew Rate Control 0 */
+ unsigned int dcsrcr1; /* 0x24 - Driving Capability
+ and Slew Rate Control 1 */
+ unsigned int dcsrcr2; /* 0x28 - Driving Capability
+ and Slew Rate Control 2 */
+ unsigned int rsvd3; /* 0x2C */
+ unsigned int mfpsr0; /* 0x30 - Multi-Func Port Setting 0 */
+ unsigned int mfpsr1; /* 0x34 - Multi-Func Port Setting 1 */
+ unsigned int dmaes; /* 0x38 - DMA Engine Selection */
+ unsigned int rsvd4; /* 0x3C */
+ unsigned int oscc; /* 0x40 - OSC Control */
+ unsigned int pwmcd; /* 0x44 - PWM Clock divider */
+ unsigned int socmisc; /* 0x48 - SoC Misc. */
+ unsigned int rsvd5[13]; /* 0x4C-0x7C: Reserved */
+ unsigned int bsmcr; /* 0x80 - BSM Controrl */
+ unsigned int bsmst; /* 0x84 - BSM Status */
+ unsigned int wes; /* 0x88 - Wakeup Event Sensitivity*/
+ unsigned int west; /* 0x8C - Wakeup Event Status */
+ unsigned int rsttiming; /* 0x90 - Reset Timing */
+ unsigned int intr_st; /* 0x94 - PCU Interrupt Status */
+ unsigned int rsvd6[2]; /* 0x98-0x9C: Reserved */
+ struct pcs pcs1; /* 0xA0-0xB0: PCS1 (clock scaling) */
+ unsigned int pcsrsvd1[3]; /* 0xB4-0xBC: Reserved */
+ struct pcs pcs2; /* 0xC0-0xD0: PCS2 (AHB clock gating) */
+ unsigned int pcsrsvd2[3]; /* 0xD4-0xDC: Reserved */
+ struct pcs pcs3; /* 0xE0-0xF0: PCS3 (APB clock gating) */
+ unsigned int pcsrsvd3[3]; /* 0xF4-0xFC: Reserved */
+ struct pcs pcs4; /* 0x100-0x110: PCS4 main PLL scaling */
+ unsigned int pcsrsvd4[3]; /* 0x114-0x11C: Reserved */
+ struct pcs pcs5; /* 0x120-0x130: PCS5 PCI PLL scaling */
+ unsigned int pcsrsvd5[3]; /* 0x134-0x13C: Reserved */
+ struct pcs pcs6; /* 0x140-0x150: PCS6 AC97 PLL scaling */
+ unsigned int pcsrsvd6[3]; /* 0x154-0x15C: Reserved */
+ struct pcs pcs7; /* 0x160-0x170: PCS7 GMAC PLL scaling */
+ unsigned int pcsrsvd7[3]; /* 0x174-0x17C: Reserved */
+ struct pcs pcs8; /* 0x180-0x190: PCS8 voltage scaling */
+ unsigned int pcsrsvd8[3]; /* 0x194-0x19C: Reserved */
+ struct pcs pcs9; /* 0x1A0-0x1B0: PCS9 power control */
+ unsigned int pcsrsvd9[93]; /* 0x1B4-0x3FC: Reserved */
+ unsigned int pmspdm[40]; /* 0x400-0x4fC: Power Manager
+ Scratch Pad Memory 0 */
+};
+#endif /* __ASSEMBLY__ */
+
+/*
+ * PCU Revision Register (ro)
+ */
+#define ANDES_PCU_REV_NUMBER_PCS(x) (((x) >> 0) & 0xff)
+#define ANDES_PCU_REV_VER(x) (((x) >> 16) & 0xffff)
+
+/*
+ * Scratch Pad Info Register (ro)
+ */
+#define ANDES_PCU_SPINFO_SIZE(x) (((x) >> 0) & 0xff)
+#define ANDES_PCU_SPINFO_OFFSET(x) (((x) >> 8) & 0xf)
+
+/*
+ * SoC ID Register (ro)
+ */
+#define ANDES_PCU_SOC_ID_VER_MINOR(x) (((x) >> 0) & 0xf)
+#define ANDES_PCU_SOC_ID_VER_MAJOR(x) (((x) >> 4) & 0xfff)
+#define ANDES_PCU_SOC_ID_DEVICEID(x) (((x) >> 16) & 0xffff)
+
+/*
+ * SoC AHB Configuration Register (ro)
+ */
+#define ANDES_PCU_SOC_AHB_AHBC(x) ((x) << 0)
+#define ANDES_PCU_SOC_AHB_APBREG(x) ((x) << 1)
+#define ANDES_PCU_SOC_AHB_APB(x) ((x) << 2)
+#define ANDES_PCU_SOC_AHB_DLM1(x) ((x) << 3)
+#define ANDES_PCU_SOC_AHB_SPIROM(x) ((x) << 4)
+#define ANDES_PCU_SOC_AHB_DDR2C(x) ((x) << 5)
+#define ANDES_PCU_SOC_AHB_DDR2MEM(x) ((x) << 6)
+#define ANDES_PCU_SOC_AHB_DMAC(x) ((x) << 7)
+#define ANDES_PCU_SOC_AHB_DLM2(x) ((x) << 8)
+#define ANDES_PCU_SOC_AHB_GPU(x) ((x) << 9)
+#define ANDES_PCU_SOC_AHB_GMAC(x) ((x) << 12)
+#define ANDES_PCU_SOC_AHB_IDE(x) ((x) << 13)
+#define ANDES_PCU_SOC_AHB_USBOTG(x) ((x) << 14)
+#define ANDES_PCU_SOC_AHB_INTC(x) ((x) << 15)
+#define ANDES_PCU_SOC_AHB_LPCIO(x) ((x) << 16)
+#define ANDES_PCU_SOC_AHB_LPCREG(x) ((x) << 17)
+#define ANDES_PCU_SOC_AHB_PCIIO(x) ((x) << 18)
+#define ANDES_PCU_SOC_AHB_PCIMEM(x) ((x) << 19)
+#define ANDES_PCU_SOC_AHB_L2CC(x) ((x) << 20)
+#define ANDES_PCU_SOC_AHB_AHB2AHBREG(x) ((x) << 27)
+#define ANDES_PCU_SOC_AHB_AHB2AHBMEM0(x) ((x) << 28)
+#define ANDES_PCU_SOC_AHB_AHB2AHBMEM1(x) ((x) << 29)
+#define ANDES_PCU_SOC_AHB_AHB2AHBMEM2(x) ((x) << 30)
+#define ANDES_PCU_SOC_AHB_AHB2AHBMEM3(x) ((x) << 31)
+
+/*
+ * SoC APB Configuration Register (ro)
+ */
+#define ANDES_PCU_SOC_APB_CFC(x) ((x) << 1)
+#define ANDES_PCU_SOC_APB_SSP(x) ((x) << 2)
+#define ANDES_PCU_SOC_APB_UART1(x) ((x) << 3)
+#define ANDES_PCU_SOC_APB_SDC(x) ((x) << 5)
+#define ANDES_PCU_SOC_APB_AC97I2S(x) ((x) << 6)
+#define ANDES_PCU_SOC_APB_UART2(x) ((x) << 8)
+#define ANDES_PCU_SOC_APB_PCU(x) ((x) << 16)
+#define ANDES_PCU_SOC_APB_TMR(x) ((x) << 17)
+#define ANDES_PCU_SOC_APB_WDT(x) ((x) << 18)
+#define ANDES_PCU_SOC_APB_RTC(x) ((x) << 19)
+#define ANDES_PCU_SOC_APB_GPIO(x) ((x) << 20)
+#define ANDES_PCU_SOC_APB_I2C(x) ((x) << 22)
+#define ANDES_PCU_SOC_APB_PWM(x) ((x) << 23)
+
+/*
+ * Driving Capability and Slew Rate Control Register 0 (rw)
+ */
+#define ANDES_PCU_DCSRCR0_TRIAHB(x) (((x) & 0x1f) << 0)
+#define ANDES_PCU_DCSRCR0_LPC(x) (((x) & 0xf) << 8)
+#define ANDES_PCU_DCSRCR0_ULPI(x) (((x) & 0xf) << 12)
+#define ANDES_PCU_DCSRCR0_GMAC(x) (((x) & 0xf) << 16)
+#define ANDES_PCU_DCSRCR0_GPU(x) (((x) & 0xf) << 20)
+
+/*
+ * Driving Capability and Slew Rate Control Register 1 (rw)
+ */
+#define ANDES_PCU_DCSRCR1_I2C(x) (((x) & 0xf) << 0)
+
+/*
+ * Driving Capability and Slew Rate Control Register 2 (rw)
+ */
+#define ANDES_PCU_DCSRCR2_UART1(x) (((x) & 0xf) << 0)
+#define ANDES_PCU_DCSRCR2_UART2(x) (((x) & 0xf) << 4)
+#define ANDES_PCU_DCSRCR2_AC97(x) (((x) & 0xf) << 8)
+#define ANDES_PCU_DCSRCR2_SPI(x) (((x) & 0xf) << 12)
+#define ANDES_PCU_DCSRCR2_SD(x) (((x) & 0xf) << 16)
+#define ANDES_PCU_DCSRCR2_CFC(x) (((x) & 0xf) << 20)
+#define ANDES_PCU_DCSRCR2_GPIO(x) (((x) & 0xf) << 24)
+#define ANDES_PCU_DCSRCR2_PCU(x) (((x) & 0xf) << 28)
+
+/*
+ * Multi-function Port Setting Register 0 (rw)
+ */
+#define ANDES_PCU_MFPSR0_PCIMODE(x) ((x) << 0)
+#define ANDES_PCU_MFPSR0_IDEMODE(x) ((x) << 1)
+#define ANDES_PCU_MFPSR0_MINI_TC01(x) ((x) << 2)
+#define ANDES_PCU_MFPSR0_AHB_DEBUG(x) ((x) << 3)
+#define ANDES_PCU_MFPSR0_AHB_TARGET(x) ((x) << 4)
+#define ANDES_PCU_MFPSR0_DEFAULT_IVB(x) (((x) & 0x7) << 28)
+#define ANDES_PCU_MFPSR0_DEFAULT_ENDIAN(x) ((x) << 31)
+
+/*
+ * Multi-function Port Setting Register 1 (rw)
+ */
+#define ANDES_PCU_MFPSR1_SUSPEND(x) ((x) << 0)
+#define ANDES_PCU_MFPSR1_PWM0(x) ((x) << 1)
+#define ANDES_PCU_MFPSR1_PWM1(x) ((x) << 2)
+#define ANDES_PCU_MFPSR1_AC97CLKOUT(x) ((x) << 3)
+#define ANDES_PCU_MFPSR1_PWREN(x) ((x) << 4)
+#define ANDES_PCU_MFPSR1_PME(x) ((x) << 5)
+#define ANDES_PCU_MFPSR1_I2C(x) ((x) << 6)
+#define ANDES_PCU_MFPSR1_UART1(x) ((x) << 7)
+#define ANDES_PCU_MFPSR1_UART2(x) ((x) << 8)
+#define ANDES_PCU_MFPSR1_SPI(x) ((x) << 9)
+#define ANDES_PCU_MFPSR1_SD(x) ((x) << 10)
+#define ANDES_PCU_MFPSR1_GPUPLLSRC(x) ((x) << 27)
+#define ANDES_PCU_MFPSR1_DVOMODE(x) ((x) << 28)
+#define ANDES_PCU_MFPSR1_HSMP_FAST_REQ(x) ((x) << 29)
+#define ANDES_PCU_MFPSR1_AHB_FAST_REQ(x) ((x) << 30)
+#define ANDES_PCU_MFPSR1_PMUR_EXT_INT(x) ((x) << 31)
+
+/*
+ * DMA Engine Selection Register (rw)
+ */
+#define ANDES_PCU_DMAES_AC97RX(x) ((x) << 2)
+#define ANDES_PCU_DMAES_AC97TX(x) ((x) << 3)
+#define ANDES_PCU_DMAES_UART1RX(x) ((x) << 4)
+#define ANDES_PCU_DMAES_UART1TX(x) ((x) << 5)
+#define ANDES_PCU_DMAES_UART2RX(x) ((x) << 6)
+#define ANDES_PCU_DMAES_UART2TX(x) ((x) << 7)
+#define ANDES_PCU_DMAES_SDDMA(x) ((x) << 8)
+#define ANDES_PCU_DMAES_CFCDMA(x) ((x) << 9)
+
+/*
+ * OSC Control Register (rw)
+ */
+#define ANDES_PCU_OSCC_OSCH_OFF(x) ((x) << 0)
+#define ANDES_PCU_OSCC_OSCH_STABLE(x) ((x) << 1)
+#define ANDES_PCU_OSCC_OSCH_TRI(x) ((x) << 2)
+#define ANDES_PCU_OSCC_OSCH_RANGE(x) (((x) & 0x3) << 4)
+#define ANDES_PCU_OSCC_OSCH2_RANGE(x) (((x) & 0x3) << 6)
+#define ANDES_PCU_OSCC_OSCH3_RANGE(x) (((x) & 0x3) << 8)
+
+/*
+ * PWM Clock Divider Register (rw)
+ */
+#define ANDES_PCU_PWMCD_PWMDIV(x) (((x) & 0xf) << 0)
+
+/*
+ * SoC Misc. Register (rw)
+ */
+#define ANDES_PCU_SOCMISC_RSCPUA(x) ((x) << 0)
+#define ANDES_PCU_SOCMISC_RSCPUB(x) ((x) << 1)
+#define ANDES_PCU_SOCMISC_RSPCI(x) ((x) << 2)
+#define ANDES_PCU_SOCMISC_USBWAKE(x) ((x) << 3)
+#define ANDES_PCU_SOCMISC_EXLM_WAITA(x) (((x) & 0x3) << 4)
+#define ANDES_PCU_SOCMISC_EXLM_WAITB(x) (((x) & 0x3) << 6)
+#define ANDES_PCU_SOCMISC_DDRPLL_BYPASS(x) (((x) << 8)
+#define ANDES_PCU_SOCMISC_300MHZSEL(x) (((x) << 9)
+#define ANDES_PCU_SOCMISC_DDRDLL_SRST(x) (((x) << 10)
+#define ANDES_PCU_SOCMISC_DDRDDQ_TEST(x) (((x) << 11)
+#define ANDES_PCU_SOCMISC_DDRDLL_TEST(x) (((x) << 12)
+#define ANDES_PCU_SOCMISC_GPUPLL_BYPASS(x) (((x) << 13)
+#define ANDES_PCU_SOCMISC_ENCPUA(x) (((x) << 14)
+#define ANDES_PCU_SOCMISC_ENCPUB(x) (((x) << 15)
+#define ANDES_PCU_SOCMISC_PWON_PWBTN(x) (((x) << 16)
+#define ANDES_PCU_SOCMISC_PWON_GPIO1(x) (((x) << 17)
+#define ANDES_PCU_SOCMISC_PWON_GPIO2(x) (((x) << 18)
+#define ANDES_PCU_SOCMISC_PWON_GPIO3(x) (((x) << 19)
+#define ANDES_PCU_SOCMISC_PWON_GPIO4(x) (((x) << 20)
+#define ANDES_PCU_SOCMISC_PWON_GPIO5(x) (((x) << 21)
+#define ANDES_PCU_SOCMISC_PWON_WOL(x) (((x) << 22)
+#define ANDES_PCU_SOCMISC_PWON_RTC(x) (((x) << 23)
+#define ANDES_PCU_SOCMISC_PWON_RTCALM(x) (((x) << 24)
+#define ANDES_PCU_SOCMISC_PWON_XDBGIN(x) (((x) << 25)
+#define ANDES_PCU_SOCMISC_PWON_PME(x) (((x) << 26)
+#define ANDES_PCU_SOCMISC_PWON_PWFAIL(x) (((x) << 27)
+#define ANDES_PCU_SOCMISC_CPUA_SRSTED(x) (((x) << 28)
+#define ANDES_PCU_SOCMISC_CPUB_SRSTED(x) (((x) << 29)
+#define ANDES_PCU_SOCMISC_WD_RESET(x) (((x) << 30)
+#define ANDES_PCU_SOCMISC_HW_RESET(x) (((x) << 31)
+
+/*
+ * BSM Control Register (rw)
+ */
+#define ANDES_PCU_BSMCR_LINK0(x) (((x) & 0xf) << 0)
+#define ANDES_PCU_BSMCR_LINK1(x) (((x) & 0xf) << 4)
+#define ANDES_PCU_BSMCR_SYNCSRC(x) (((x) & 0xf) << 24)
+#define ANDES_PCU_BSMCR_CMD(x) (((x) & 0x7) << 28)
+#define ANDES_PCU_BSMCR_IE(x) ((x) << 31)
+
+/*
+ * BSM Status Register
+ */
+#define ANDES_PCU_BSMSR_CI0(x) (((x) & 0xf) << 0)
+#define ANDES_PCU_BSMSR_CI1(x) (((x) & 0xf) << 4)
+#define ANDES_PCU_BSMSR_SYNCSRC(x) (((x) & 0xf) << 24)
+#define ANDES_PCU_BSMSR_BSMST(x) (((x) & 0xf) << 28)
+
+/*
+ * Wakeup Event Sensitivity Register (rw)
+ */
+#define ANDES_PCU_WESR_POLOR(x) (((x) & 0xff) << 0)
+
+/*
+ * Wakeup Event Status Register (ro)
+ */
+#define ANDES_PCU_WEST_SIG(x) (((x) & 0xff) << 0)
+
+/*
+ * Reset Timing Register
+ */
+#define ANDES_PCU_RSTTIMING_RG0(x) (((x) & 0xff) << 0)
+#define ANDES_PCU_RSTTIMING_RG1(x) (((x) & 0xff) << 8)
+#define ANDES_PCU_RSTTIMING_RG2(x) (((x) & 0xff) << 16)
+#define ANDES_PCU_RSTTIMING_RG3(x) (((x) & 0xff) << 24)
+
+/*
+ * PCU Interrupt Status Register
+ */
+#define ANDES_PCU_INTR_ST_BSM(x) ((x) << 0)
+#define ANDES_PCU_INTR_ST_PCS1(x) ((x) << 1)
+#define ANDES_PCU_INTR_ST_PCS2(x) ((x) << 2)
+#define ANDES_PCU_INTR_ST_PCS3(x) ((x) << 3)
+#define ANDES_PCU_INTR_ST_PCS4(x) ((x) << 4)
+#define ANDES_PCU_INTR_ST_PCS5(x) ((x) << 5)
+#define ANDES_PCU_INTR_ST_PCS6(x) ((x) << 6)
+#define ANDES_PCU_INTR_ST_PCS7(x) ((x) << 7)
+#define ANDES_PCU_INTR_ST_PCS8(x) ((x) << 8)
+#define ANDES_PCU_INTR_ST_PCS9(x) ((x) << 9)
+
+/*
+ * PCSx Configuration Register
+ */
+#define ANDES_PCU_PCSX_CR_WAKEUP_EN(x) (((x) & 0xff) << 0)
+#define ANDES_PCU_PCSX_CR_LW(x) (((x) & 0xf) << 16)
+#define ANDES_PCU_PCSX_CR_LS(x) (((x) & 0xf) << 20)
+#define ANDES_PCU_PCSX_CR_TYPE(x) (((x) >> 28) & 0x7) /* (ro) */
+
+/*
+ * PCSx Parameter Register (rw)
+ */
+#define ANDES_PCU_PCSX_PARM_NEXT(x) (((x) & 0xffffff) << 0)
+#define ANDES_PCU_PCSX_PARM_SYNCSRC(x) (((x) & 0xf) << 24)
+#define ANDES_PCU_PCSX_PARM_PCSCMD(x) (((x) & 0x7) << 28)
+#define ANDES_PCU_PCSX_PARM_IE(x) (((x) << 31)
+
+/*
+ * PCSx Status Register 1
+ */
+#define ANDES_PCU_PCSX_STAT1_ERRNO(x) (((x) & 0xf) << 0)
+#define ANDES_PCU_PCSX_STAT1_ST(x) (((x) & 0x7) << 28)
+
+/*
+ * PCSx Status Register 2
+ */
+#define ANDES_PCU_PCSX_STAT2_CRNTPARM(x) (((x) & 0xffffff) << 0)
+#define ANDES_PCU_PCSX_STAT2_SYNCSRC(x) (((x) & 0xf) << 24)
+
+/*
+ * PCSx PDD Register
+ * This is reserved for PCS(1-7)
+ */
+#define ANDES_PCU_PCS8_PDD_1BYTE(x) (((x) & 0xff) << 0)
+#define ANDES_PCU_PCS8_PDD_2BYTE(x) (((x) & 0xff) << 8)
+#define ANDES_PCU_PCS8_PDD_3BYTE(x) (((x) & 0xff) << 16)
+#define ANDES_PCU_PCS8_PDD_4BYTE(x) (((x) & 0xff) << 24)
+
+#define ANDES_PCU_PCS9_PDD_TIME1(x) (((x) & 0x3f) << 0)
+#define ANDES_PCU_PCS9_PDD_TIME2(x) (((x) & 0x3f) << 6)
+#define ANDES_PCU_PCS9_PDD_TIME3(x) (((x) & 0x3f) << 12)
+#define ANDES_PCU_PCS9_PDD_TIME4(x) (((x) & 0x3f) << 18)
+#define ANDES_PCU_PCS9_PDD_TICKTYPE(x) ((x) << 24)
+#define ANDES_PCU_PCS9_PDD_GPU_SRST(x) ((x) << 27)
+#define ANDES_PCU_PCS9_PDD_PWOFFTIME(x) (((x) & 0x3) << 28)
+#define ANDES_PCU_PCS9_PDD_SUS2DRAM(x) ((x) << 30)
+#define ANDES_PCU_PCS9_PDD_CLRPWOFF_FLAG(x) ((x) << 31)
+
+#endif /* __ANDES_PCU_H */
diff --git a/include/api_public.h b/include/api_public.h
index 5940d81..4420c99 100644
--- a/include/api_public.h
+++ b/include/api_public.h
@@ -90,6 +90,9 @@
API_ENV_ENUM,
API_ENV_GET,
API_ENV_SET,
+ API_DISPLAY_GET_INFO,
+ API_DISPLAY_DRAW_BITMAP,
+ API_DISPLAY_CLEAR,
API_MAXCALL
};
@@ -152,4 +155,17 @@
int state;
};
+#define DISPLAY_TYPE_LCD 0x0001
+#define DISPLAY_TYPE_VIDEO 0x0002
+
+struct display_info {
+ int type;
+ /* screen size in pixels */
+ int pixel_width;
+ int pixel_height;
+ /* screen size in rows and columns of text */
+ int screen_rows;
+ int screen_cols;
+};
+
#endif /* _API_PUBLIC_H_ */
diff --git a/include/command.h b/include/command.h
index c270110..3912b80 100644
--- a/include/command.h
+++ b/include/command.h
@@ -64,6 +64,9 @@
extern cmd_tbl_t __u_boot_cmd_start;
extern cmd_tbl_t __u_boot_cmd_end;
+#if defined(CONFIG_CMD_RUN)
+extern int do_run(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]);
+#endif
/* common/command.c */
int _do_help (cmd_tbl_t *cmd_start, int cmd_items, cmd_tbl_t * cmdtp, int
diff --git a/include/common.h b/include/common.h
index 5ca8820..05a658c 100644
--- a/include/common.h
+++ b/include/common.h
@@ -272,6 +272,7 @@
#ifdef CONFIG_MENU
int abortboot(int bootdelay);
#endif
+extern char console_buffer[];
/* arch/$(ARCH)/lib/board.c */
void board_init_f (ulong) __attribute__ ((noreturn));
diff --git a/include/compiler.h b/include/compiler.h
index 54999a7..0734ed4 100644
--- a/include/compiler.h
+++ b/include/compiler.h
@@ -123,16 +123,10 @@
#define __WORDSIZE 32
#endif
-/* Types for `void *' pointers. */
-#if __WORDSIZE == 64
-typedef unsigned long int uintptr_t;
-#elif __WORDSIZE == 32
-typedef unsigned int uintptr_t;
-#else
-#error "__WORDSIZE has unexpected value"
-#endif
+/* Type for `void *' pointers. */
+typedef unsigned long int uintptr_t;
-#endif
+#endif /* USE_HOSTCC */
/* compiler options */
#define uninitialized_var(x) x = x
diff --git a/include/config_phylib_all_drivers.h b/include/config_phylib_all_drivers.h
index 903c7a7..1db7cec 100644
--- a/include/config_phylib_all_drivers.h
+++ b/include/config_phylib_all_drivers.h
@@ -22,6 +22,7 @@
#define CONFIG_PHY_REALTEK
#define CONFIG_PHY_NATSEMI
#define CONFIG_PHY_LXT
+#define CONFIG_PHY_ATHEROS
#ifdef CONFIG_PHYLIB_10G
#define CONFIG_PHY_TERANETICS
diff --git a/include/configs/MPC8536DS.h b/include/configs/MPC8536DS.h
index d4e3ef5..16db98f 100644
--- a/include/configs/MPC8536DS.h
+++ b/include/configs/MPC8536DS.h
@@ -131,7 +131,7 @@
#define CONFIG_SYS_CCSRBAR 0xffe00000
#define CONFIG_SYS_CCSRBAR_PHYS_LOW CONFIG_SYS_CCSRBAR
-#if defined(CONFIG_RAMBOOT_NAND) && !defined(CONFIG_NAND_SPL)
+#if defined(CONFIG_NAND_SPL)
#define CONFIG_SYS_CCSR_DO_NOT_RELOCATE
#endif
diff --git a/include/configs/MPC8548CDS.h b/include/configs/MPC8548CDS.h
index a99f8d5..1a6ba69 100644
--- a/include/configs/MPC8548CDS.h
+++ b/include/configs/MPC8548CDS.h
@@ -464,6 +464,8 @@
#define CONFIG_TSEC4_NAME "eTSEC3"
#undef CONFIG_MPC85XX_FEC
+#define CONFIG_PHY_MARVELL
+
#define TSEC1_PHY_ADDR 0
#define TSEC2_PHY_ADDR 1
#define TSEC3_PHY_ADDR 2
diff --git a/include/configs/MPC8569MDS.h b/include/configs/MPC8569MDS.h
index 19d3271..ab27b98 100644
--- a/include/configs/MPC8569MDS.h
+++ b/include/configs/MPC8569MDS.h
@@ -108,7 +108,7 @@
#define CONFIG_SYS_CCSRBAR 0xe0000000
#define CONFIG_SYS_CCSRBAR_PHYS_LOW CONFIG_SYS_CCSRBAR
-#if defined(CONFIG_RAMBOOT_NAND) && !defined(CONFIG_NAND_SPL)
+#if defined(CONFIG_NAND_SPL)
#define CONFIG_SYS_CCSR_DO_NOT_RELOCATE
#endif
diff --git a/include/configs/MPC8572DS.h b/include/configs/MPC8572DS.h
index ffee8fc..d7910e1 100644
--- a/include/configs/MPC8572DS.h
+++ b/include/configs/MPC8572DS.h
@@ -115,7 +115,7 @@
#define CONFIG_SYS_CCSRBAR 0xffe00000
#define CONFIG_SYS_CCSRBAR_PHYS_LOW CONFIG_SYS_CCSRBAR
-#if defined(CONFIG_RAMBOOT_NAND) && !defined(CONFIG_NAND_SPL)
+#if defined(CONFIG_NAND_SPL)
#define CONFIG_SYS_CCSR_DO_NOT_RELOCATE
#endif
diff --git a/include/configs/P1022DS.h b/include/configs/P1022DS.h
index 0077060..1158fec 100644
--- a/include/configs/P1022DS.h
+++ b/include/configs/P1022DS.h
@@ -173,7 +173,7 @@
#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
#define CONFIG_SYS_MONITOR_LEN (512 * 1024)
-#define CONFIG_SYS_MALLOC_LEN (6 * 1024 * 1024)
+#define CONFIG_SYS_MALLOC_LEN (10 * 1024 * 1024)
/*
* Serial Port
diff --git a/include/configs/P1_P2_RDB.h b/include/configs/P1_P2_RDB.h
index 883d44e..00fa74d 100644
--- a/include/configs/P1_P2_RDB.h
+++ b/include/configs/P1_P2_RDB.h
@@ -151,7 +151,7 @@
#define CONFIG_SYS_CCSRBAR 0xffe00000
#define CONFIG_SYS_CCSRBAR_PHYS_LOW CONFIG_SYS_CCSRBAR
-#if defined(CONFIG_RAMBOOT_NAND) && !defined(CONFIG_NAND_SPL)
+#if defined(CONFIG_NAND_SPL)
#define CONFIG_SYS_CCSR_DO_NOT_RELOCATE
#endif
diff --git a/include/configs/VCMA9.h b/include/configs/VCMA9.h
index 8b8113d..a370c15 100644
--- a/include/configs/VCMA9.h
+++ b/include/configs/VCMA9.h
@@ -29,6 +29,9 @@
#ifndef __CONFIG_H
#define __CONFIG_H
+
+#define MACH_TYPE_MPL_VCMA9 227
+
/*
* High Level Configuration Options
* (easy to change)
@@ -37,6 +40,7 @@
#define CONFIG_S3C24X0 /* in a SAMSUNG S3C24x0-type SoC */
#define CONFIG_S3C2410 /* specifically a SAMSUNG S3C2410 SoC */
#define CONFIG_VCMA9 /* on a MPL VCMA9 Board */
+#define CONFIG_MACH_TYPE MACH_TYPE_MPL_VCMA9 /* Machine type */
#define CONFIG_SYS_TEXT_BASE 0x0
diff --git a/include/configs/adp-ag101p.h b/include/configs/adp-ag101p.h
new file mode 100644
index 0000000..ffc70a6
--- /dev/null
+++ b/include/configs/adp-ag101p.h
@@ -0,0 +1,383 @@
+/*
+ * Copyright (C) 2011 Andes Technology Corporation
+ * Shawn Lin, Andes Technology Corporation <nobuhiro@andestech.com>
+ * Macpaul Lin, Andes Technology Corporation <macpaul@andestech.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
+ */
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+#include <asm/arch/ag101.h>
+
+/*
+ * CPU and Board Configuration Options
+ */
+#define CONFIG_ADP_AG101P
+
+#define CONFIG_USE_INTERRUPT
+
+#define CONFIG_SKIP_LOWLEVEL_INIT
+
+#ifndef CONFIG_SKIP_LOWLEVEL_INIT
+#define CONFIG_MEM_REMAP
+#endif
+
+#ifdef CONFIG_SKIP_LOWLEVEL_INIT
+#define CONFIG_SYS_TEXT_BASE 0x03200000
+#else
+#define CONFIG_SYS_TEXT_BASE 0x00000000
+#endif
+
+/*
+ * Timer
+ */
+
+/*
+ * According to the discussion in u-boot mailing list before,
+ * CONFIG_SYS_HZ at 1000 is mandatory.
+ */
+#define CONFIG_SYS_HZ 1000
+#define CONFIG_SYS_CLK_FREQ 39062500
+#define VERSION_CLOCK CONFIG_SYS_CLK_FREQ
+
+/*
+ * Use Externel CLOCK or PCLK
+ */
+#undef CONFIG_FTRTC010_EXTCLK
+
+#ifndef CONFIG_FTRTC010_EXTCLK
+#define CONFIG_FTRTC010_PCLK
+#endif
+
+#ifdef CONFIG_FTRTC010_EXTCLK
+#define TIMER_CLOCK 32768 /* CONFIG_FTRTC010_EXTCLK */
+#else
+#define TIMER_CLOCK CONFIG_SYS_HZ /* CONFIG_FTRTC010_PCLK */
+#endif
+
+#define TIMER_LOAD_VAL 0xffffffff
+
+/*
+ * Real Time Clock
+ */
+#define CONFIG_RTC_FTRTC010
+
+/*
+ * Real Time Clock Divider
+ * RTC_DIV_COUNT (OSC_CLK/OSC_5MHZ)
+ */
+#define OSC_5MHZ (5*1000000)
+#define OSC_CLK (4*OSC_5MHZ)
+#define RTC_DIV_COUNT (0.5) /* Why?? */
+
+/*
+ * Serial console configuration
+ */
+
+/* FTUART is a high speed NS 16C550A compatible UART, addr: 0x99600000 */
+#define CONFIG_BAUDRATE 38400
+#define CONFIG_CONS_INDEX 1
+#define CONFIG_SYS_NS16550
+#define CONFIG_SYS_NS16550_SERIAL
+#define CONFIG_SYS_NS16550_COM1 CONFIG_FTUART010_02_BASE
+#define CONFIG_SYS_NS16550_REG_SIZE -4
+#define CONFIG_SYS_NS16550_CLK ((18432000 * 20) / 25) /* AG101P */
+
+/* valid baudrates */
+#define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 }
+
+/*
+ * Ethernet
+ */
+#define CONFIG_FTMAC100
+
+#define CONFIG_BOOTDELAY 3
+
+/*
+ * SD (MMC) controller
+ */
+#define CONFIG_MMC
+#define CONFIG_CMD_MMC
+#define CONFIG_GENERIC_MMC
+#define CONFIG_DOS_PARTITION
+#define CONFIG_FTSDC010
+#define CONFIG_FTSDC010_NUMBER 1
+#define CONFIG_CMD_FAT
+
+/*
+ * Command line configuration.
+ */
+#include <config_cmd_default.h>
+
+#define CONFIG_CMD_CACHE
+#define CONFIG_CMD_DATE
+#define CONFIG_CMD_PING
+
+/*
+ * Miscellaneous configurable options
+ */
+#define CONFIG_SYS_LONGHELP /* undef to save memory */
+#define CONFIG_SYS_PROMPT "NDS32 # " /* Monitor Command Prompt */
+#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
+
+/* Print Buffer Size */
+#define CONFIG_SYS_PBSIZE \
+ (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16)
+
+/* max number of command args */
+#define CONFIG_SYS_MAXARGS 16
+
+/* Boot Argument Buffer Size */
+#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE
+
+/*
+ * Stack sizes
+ *
+ * The stack sizes are set up in start.S using the settings below
+ */
+#define CONFIG_STACKSIZE (128 * 1024) /* regular stack */
+
+/*
+ * Size of malloc() pool
+ */
+/* 512kB is suggested, (CONFIG_ENV_SIZE + 128 * 1024) was not enough */
+#define CONFIG_SYS_MALLOC_LEN (512 << 10)
+
+/*
+ * size in bytes reserved for initial data
+ */
+#define CONFIG_SYS_GBL_DATA_SIZE 128
+
+/*
+ * AHB Controller configuration
+ */
+#define CONFIG_FTAHBC020S
+
+#ifdef CONFIG_FTAHBC020S
+#include <faraday/ftahbc020s.h>
+
+/* Address of PHYS_SDRAM_0 before memory remap is at 0x(100)00000 */
+#define CONFIG_SYS_FTAHBC020S_SLAVE_BSR_BASE 0x100
+
+/*
+ * CONFIG_SYS_FTAHBC020S_SLAVE_BSR_6: this define is used in lowlevel_init.S,
+ * hence we cannot use FTAHBC020S_BSR_SIZE(2048) since it will use ffs() wrote
+ * in C language.
+ */
+#define CONFIG_SYS_FTAHBC020S_SLAVE_BSR_6 \
+ (FTAHBC020S_SLAVE_BSR_BASE(CONFIG_SYS_FTAHBC020S_SLAVE_BSR_BASE) | \
+ FTAHBC020S_SLAVE_BSR_SIZE(0xb))
+#endif
+
+/*
+ * Watchdog
+ */
+#define CONFIG_FTWDT010_WATCHDOG
+
+/*
+ * PMU Power controller configuration
+ */
+#define CONFIG_PMU
+#define CONFIG_FTPMU010_POWER
+
+#ifdef CONFIG_FTPMU010_POWER
+#include <faraday/ftpmu010.h>
+#define CONFIG_SYS_FTPMU010_PDLLCR0_HCLKOUTDIS 0x0E
+#define CONFIG_SYS_FTPMU010_SDRAMHTC (FTPMU010_SDRAMHTC_EBICTRL_DCSR | \
+ FTPMU010_SDRAMHTC_EBIDATA_DCSR | \
+ FTPMU010_SDRAMHTC_SDRAMCS_DCSR | \
+ FTPMU010_SDRAMHTC_SDRAMCTL_DCSR | \
+ FTPMU010_SDRAMHTC_CKE_DCSR | \
+ FTPMU010_SDRAMHTC_DQM_DCSR | \
+ FTPMU010_SDRAMHTC_SDCLK_DCSR)
+#endif
+
+/*
+ * SDRAM controller configuration
+ */
+#define CONFIG_FTSDMC021
+
+#ifdef CONFIG_FTSDMC021
+#include <faraday/ftsdmc021.h>
+
+#define CONFIG_SYS_FTSDMC021_TP1 (FTSDMC021_TP1_TRAS(2) | \
+ FTSDMC021_TP1_TRP(1) | \
+ FTSDMC021_TP1_TRCD(1) | \
+ FTSDMC021_TP1_TRF(3) | \
+ FTSDMC021_TP1_TWR(1) | \
+ FTSDMC021_TP1_TCL(2))
+
+#define CONFIG_SYS_FTSDMC021_TP2 (FTSDMC021_TP2_INI_PREC(4) | \
+ FTSDMC021_TP2_INI_REFT(8) | \
+ FTSDMC021_TP2_REF_INTV(0x180))
+
+/*
+ * CONFIG_SYS_FTSDMC021_CR1: this define is used in lowlevel_init.S,
+ * hence we cannot use FTSDMC021_BANK_SIZE(64) since it will use ffs() wrote in
+ * C language.
+ */
+#define CONFIG_SYS_FTSDMC021_CR1 (FTSDMC021_CR1_DDW(2) | \
+ FTSDMC021_CR1_DSZ(3) | \
+ FTSDMC021_CR1_MBW(2) | \
+ FTSDMC021_CR1_BNKSIZE(6))
+
+#define CONFIG_SYS_FTSDMC021_CR2 (FTSDMC021_CR2_IPREC | \
+ FTSDMC021_CR2_IREF | \
+ FTSDMC021_CR2_ISMR)
+
+#define CONFIG_SYS_FTSDMC021_BANK0_BASE CONFIG_SYS_FTAHBC020S_SLAVE_BSR_BASE
+#define CONFIG_SYS_FTSDMC021_BANK0_BSR (FTSDMC021_BANK_ENABLE | \
+ CONFIG_SYS_FTSDMC021_BANK0_BASE)
+
+#endif
+
+/*
+ * Physical Memory Map
+ */
+#if defined(CONFIG_MEM_REMAP) || defined(CONFIG_SKIP_LOWLEVEL_INIT)
+#define PHYS_SDRAM_0 0x00000000 /* SDRAM Bank #1 */
+#if defined(CONFIG_MEM_REMAP)
+#define PHYS_SDRAM_0_AT_INIT 0x10000000 /* SDRAM Bank #1 before remap*/
+#endif
+#else /* !CONFIG_SKIP_LOWLEVEL_INIT && !CONFIG_MEM_REMAP */
+#define PHYS_SDRAM_0 0x10000000 /* SDRAM Bank #1 */
+#endif
+
+#define CONFIG_NR_DRAM_BANKS 1 /* we have 1 bank of DRAM */
+#define PHYS_SDRAM_0_SIZE 0x04000000 /* 64 MB */
+
+#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_0
+
+#ifdef CONFIG_MEM_REMAP
+#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_SDRAM_BASE + 0xA0000 - \
+ GENERATED_GBL_DATA_SIZE)
+#else
+#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_SDRAM_BASE + 0x1000 - \
+ GENERATED_GBL_DATA_SIZE)
+#endif /* CONFIG_MEM_REMAP */
+
+/*
+ * Load address and memory test area should agree with
+ * arch/nds32/config.mk. Be careful not to overwrite U-boot itself.
+ */
+#define CONFIG_SYS_LOAD_ADDR 0x300000
+
+/* memtest works on 63 MB in DRAM */
+#define CONFIG_SYS_MEMTEST_START PHYS_SDRAM_0
+#define CONFIG_SYS_MEMTEST_END (PHYS_SDRAM_0 + 0x03F00000)
+
+/*
+ * Static memory controller configuration
+ */
+#define CONFIG_FTSMC020
+
+#ifdef CONFIG_FTSMC020
+#include <faraday/ftsmc020.h>
+
+#define CONFIG_SYS_FTSMC020_CONFIGS { \
+ { FTSMC020_BANK0_CONFIG, FTSMC020_BANK0_TIMING, }, \
+ { FTSMC020_BANK1_CONFIG, FTSMC020_BANK1_TIMING, }, \
+}
+
+#ifndef CONFIG_SKIP_LOWLEVEL_INIT /* FLASH is on BANK 0 */
+#define FTSMC020_BANK0_LOWLV_CONFIG (FTSMC020_BANK_ENABLE | \
+ FTSMC020_BANK_SIZE_32M | \
+ FTSMC020_BANK_MBW_32)
+
+#define FTSMC020_BANK0_LOWLV_TIMING (FTSMC020_TPR_RBE | \
+ FTSMC020_TPR_AST(1) | \
+ FTSMC020_TPR_CTW(1) | \
+ FTSMC020_TPR_ATI(1) | \
+ FTSMC020_TPR_AT2(1) | \
+ FTSMC020_TPR_WTC(1) | \
+ FTSMC020_TPR_AHT(1) | \
+ FTSMC020_TPR_TRNA(1))
+#endif
+
+/*
+ * FLASH on ADP_AG101P is connected to BANK0
+ * Just disalbe the other BANK to avoid detection error.
+ */
+#define FTSMC020_BANK0_CONFIG (FTSMC020_BANK_ENABLE | \
+ FTSMC020_BANK_BASE(PHYS_FLASH_1) | \
+ FTSMC020_BANK_SIZE_32M | \
+ FTSMC020_BANK_MBW_32)
+
+#define FTSMC020_BANK0_TIMING (FTSMC020_TPR_AST(3) | \
+ FTSMC020_TPR_CTW(3) | \
+ FTSMC020_TPR_ATI(0xf) | \
+ FTSMC020_TPR_AT2(3) | \
+ FTSMC020_TPR_WTC(3) | \
+ FTSMC020_TPR_AHT(3) | \
+ FTSMC020_TPR_TRNA(0xf))
+
+#define FTSMC020_BANK1_CONFIG (0x00)
+#define FTSMC020_BANK1_TIMING (0x00)
+#endif /* CONFIG_FTSMC020 */
+
+/*
+ * FLASH and environment organization
+ */
+/* use CFI framework */
+#define CONFIG_SYS_FLASH_CFI
+#define CONFIG_FLASH_CFI_DRIVER
+
+#define CONFIG_SYS_FLASH_CFI_WIDTH FLASH_CFI_16BIT
+#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE
+
+/* support JEDEC */
+
+/* Do not use CONFIG_FLASH_CFI_LEGACY to detect on board flash */
+#ifdef CONFIG_SKIP_LOWLEVEL_INIT
+#define PHYS_FLASH_1 0x80400000 /* BANK 1 */
+#else /* !CONFIG_SKIP_LOWLEVEL_INIT */
+#ifdef CONFIG_MEM_REMAP
+#define PHYS_FLASH_1 0x80000000 /* BANK 0 */
+#else
+#define PHYS_FLASH_1 0x00000000 /* BANK 0 */
+#endif /* CONFIG_MEM_REMAP */
+#endif /* CONFIG_SKIP_LOWLEVEL_INIT */
+
+#define CONFIG_SYS_FLASH_BASE PHYS_FLASH_1
+#define CONFIG_SYS_FLASH_BANKS_LIST { PHYS_FLASH_1, }
+#define CONFIG_SYS_MONITOR_BASE PHYS_FLASH_1
+
+#define CONFIG_SYS_FLASH_ERASE_TOUT 120000 /* TO for Flash Erase (ms) */
+#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* TO for Flash Write (ms) */
+
+/* max number of memory banks */
+/*
+ * There are 4 banks supported for this Controller,
+ * but we have only 1 bank connected to flash on board
+ */
+#define CONFIG_SYS_MAX_FLASH_BANKS 1
+
+/* max number of sectors on one chip */
+#define CONFIG_FLASH_SECTOR_SIZE (0x10000*2*2)
+#define CONFIG_ENV_SECT_SIZE CONFIG_FLASH_SECTOR_SIZE
+#define CONFIG_SYS_MAX_FLASH_SECT 128
+
+/* environments */
+#define CONFIG_ENV_IS_IN_FLASH
+#define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE + 0x140000)
+#define CONFIG_ENV_SIZE 8192
+#define CONFIG_ENV_OVERWRITE
+
+#endif /* __CONFIG_H */
diff --git a/include/configs/csb226.h b/include/configs/csb226.h
deleted file mode 100644
index 804469b..0000000
--- a/include/configs/csb226.h
+++ /dev/null
@@ -1,506 +0,0 @@
-/*
- * (C) Copyright 2000, 2001, 2002
- * Robert Schwebel, Pengutronix, r.schwebel@pengutronix.de.
- *
- * Configuration for the Cogent CSB226 board. For details see
- * http://www.cogcomp.com/csb_csb226.htm
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-/*
- * include/configs/csb226.h - configuration options, board specific
- */
-
-#ifndef __CONFIG_H
-#define __CONFIG_H
-
-#define DEBUG 1
-
-/*
- * High Level Configuration Options
- * (easy to change)
- */
-#define CONFIG_PXA250 1 /* This is an PXA250 CPU */
-#define CONFIG_CSB226 1 /* on a CSB226 board */
-
-#undef CONFIG_USE_IRQ /* we don't need IRQ/FIQ stuff */
- /* for timer/console/ethernet */
-
-/* we will never enable dcache, because we have to setup MMU first */
-#define CONFIG_SYS_DCACHE_OFF
-#define CONFIG_SYS_TEXT_BASE 0x0
-/*
- * Hardware drivers
- */
-
-/*
- * select serial console configuration
- */
-#define CONFIG_PXA_SERIAL
-#define CONFIG_FFUART 1 /* we use FFUART on CSB226 */
-
-/* allow to overwrite serial and ethaddr */
-#define CONFIG_ENV_OVERWRITE
-
-#define CONFIG_BAUDRATE 19200
-#undef CONFIG_MISC_INIT_R /* not used yet */
-
-
-/*
- * BOOTP options
- */
-#define CONFIG_BOOTP_BOOTFILESIZE
-#define CONFIG_BOOTP_BOOTPATH
-#define CONFIG_BOOTP_GATEWAY
-#define CONFIG_BOOTP_HOSTNAME
-
-
-/*
- * Command line configuration.
- */
-#include <config_cmd_default.h>
-
-#define CONFIG_CMD_BDI
-#define CONFIG_CMD_LOADB
-#define CONFIG_CMD_IMI
-#define CONFIG_CMD_FLASH
-#define CONFIG_CMD_MEMORY
-#define CONFIG_CMD_NET
-#define CONFIG_CMD_SAVEENV
-#define CONFIG_CMD_RUN
-#define CONFIG_CMD_ASKENV
-#define CONFIG_CMD_ECHO
-#define CONFIG_CMD_DHCP
-#define CONFIG_CMD_CACHE
-
-
-#define CONFIG_BOOTDELAY 3
-#define CONFIG_BOOTARGS "console=ttyS0,19200 ip=192.168.1.10,192.168.1.5,,255,255,255,0,csb root=/dev/nfs, ether=0,0x08000000,eth0"
-#define CONFIG_ETHADDR FF:FF:FF:FF:FF:FF
-#define CONFIG_NETMASK 255.255.255.0
-#define CONFIG_IPADDR 192.168.1.56
-#define CONFIG_SERVERIP 192.168.1.5
-#define CONFIG_BOOTCOMMAND "bootm 0x40000"
-#define CONFIG_SHOW_BOOT_PROGRESS
-
-#define CONFIG_CMDLINE_TAG 1
-
-#if defined(CONFIG_CMD_KGDB)
-#define CONFIG_KGDB_BAUDRATE 19200 /* speed to run kgdb serial port */
-#define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */
-#endif
-
-/*
- * Miscellaneous configurable options
- */
-
-/*
- * Size of malloc() pool; this lives below the uppermost 128 KiB which are
- * used for the RAM copy of the uboot code
- *
- */
-#define CONFIG_SYS_MALLOC_LEN (128*1024)
-
-#define CONFIG_SYS_LONGHELP /* undef to save memory */
-#define CONFIG_SYS_PROMPT "uboot> " /* Monitor Command Prompt */
-#define CONFIG_SYS_CBSIZE 128 /* Console I/O Buffer Size */
-#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
-#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
-#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */
-
-#define CONFIG_SYS_MEMTEST_START 0xa0400000 /* memtest works on */
-#define CONFIG_SYS_MEMTEST_END 0xa0800000 /* 4 ... 8 MB in DRAM */
-
-#define CONFIG_SYS_LOAD_ADDR 0xa3000000 /* default load address */
- /* RS: where is this documented? */
- /* RS: is this where U-Boot is */
- /* RS: relocated to in RAM? */
-
-#define CONFIG_SYS_HZ 1000
- /* RS: the oscillator is actually 3680130?? */
-#define CONFIG_SYS_CPUSPEED 0x141 /* set core clock to 200/200/100 MHz */
- /* 0101000001 */
- /* ^^^^^ Memory Speed 99.53 MHz */
- /* ^^ Run Mode Speed = 2x Mem Speed */
- /* ^^ Turbo Mode Sp. = 1x Run M. Sp. */
-
-#define CONFIG_SYS_MONITOR_LEN 0x1c000 /* 112 KiB */
-
- /* valid baudrates */
-#define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 }
-
-/*
- * Network chip
- */
-#define CONFIG_CS8900
-#define CONFIG_CS8900_BUS32
-#define CONFIG_CS8900_BASE 0x08000000
-
-/*
- * Stack sizes
- *
- * The stack sizes are set up in start.S using the settings below
- */
-#define CONFIG_STACKSIZE (128*1024) /* regular stack */
-#ifdef CONFIG_USE_IRQ
-#define CONFIG_STACKSIZE_IRQ (4*1024) /* IRQ stack */
-#define CONFIG_STACKSIZE_FIQ (4*1024) /* FIQ stack */
-#endif
-
-/*
- * Physical Memory Map
- */
-#define CONFIG_NR_DRAM_BANKS 1 /* we have 1 bank of DRAM */
-#define PHYS_SDRAM_1 0xa0000000 /* SDRAM Bank #1 */
-#define PHYS_SDRAM_1_SIZE 0x02000000 /* 32 MB */
-
-#define PHYS_FLASH_1 0x00000000 /* Flash Bank #1 */
-#define PHYS_FLASH_SIZE 0x02000000 /* 32 MB */
-
-#define CONFIG_SYS_DRAM_BASE 0xa0000000 /* RAM starts here */
-#define CONFIG_SYS_DRAM_SIZE 0x02000000
-
-#define CONFIG_SYS_FLASH_BASE PHYS_FLASH_1
-
-#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1
-#define CONFIG_SYS_INIT_SP_ADDR (GENERATED_GBL_DATA_SIZE + PHYS_SDRAM_1)
-
-# if 0
-/* FIXME: switch to _documented_ registers */
-/*
- * GPIO settings
- *
- * GP15 == nCS1 is 1
- * GP24 == SFRM is 1
- * GP25 == TXD is 1
- * GP33 == nCS5 is 1
- * GP39 == FFTXD is 1
- * GP41 == RTS is 1
- * GP47 == TXD is 1
- * GP49 == nPWE is 1
- * GP62 == LED_B is 1
- * GP63 == TDM_OE is 1
- * GP78 == nCS2 is 1
- * GP79 == nCS3 is 1
- * GP80 == nCS4 is 1
- */
-#define CONFIG_SYS_GPSR0_VAL 0x03008000
-#define CONFIG_SYS_GPSR1_VAL 0xC0028282
-#define CONFIG_SYS_GPSR2_VAL 0x0001C000
-
-/* GP02 == DON_RST is 0
- * GP23 == SCLK is 0
- * GP45 == USB_ACT is 0
- * GP60 == PLLEN is 0
- * GP61 == LED_A is 0
- * GP73 == SWUPD_LED is 0
- */
-#define CONFIG_SYS_GPCR0_VAL 0x00800004
-#define CONFIG_SYS_GPCR1_VAL 0x30002000
-#define CONFIG_SYS_GPCR2_VAL 0x00000100
-
-/* GP00 == DON_READY is input
- * GP01 == DON_OK is input
- * GP02 == DON_RST is output
- * GP03 == RESET_IND is input
- * GP07 == RES11 is input
- * GP09 == RES12 is input
- * GP11 == SWUPDATE is input
- * GP14 == nPOWEROK is input
- * GP15 == nCS1 is output
- * GP17 == RES22 is input
- * GP18 == RDY is input
- * GP23 == SCLK is output
- * GP24 == SFRM is output
- * GP25 == TXD is output
- * GP26 == RXD is input
- * GP32 == RES21 is input
- * GP33 == nCS5 is output
- * GP34 == FFRXD is input
- * GP35 == CTS is input
- * GP39 == FFTXD is output
- * GP41 == RTS is output
- * GP42 == USB_OK is input
- * GP45 == USB_ACT is output
- * GP46 == RXD is input
- * GP47 == TXD is output
- * GP49 == nPWE is output
- * GP58 == nCPUBUSINT is input
- * GP59 == LANINT is input
- * GP60 == PLLEN is output
- * GP61 == LED_A is output
- * GP62 == LED_B is output
- * GP63 == TDM_OE is output
- * GP64 == nDSPINT is input
- * GP65 == STRAP0 is input
- * GP67 == STRAP1 is input
- * GP69 == STRAP2 is input
- * GP70 == STRAP3 is input
- * GP71 == STRAP4 is input
- * GP73 == SWUPD_LED is output
- * GP78 == nCS2 is output
- * GP79 == nCS3 is output
- * GP80 == nCS4 is output
- */
-#define CONFIG_SYS_GPDR0_VAL 0x03808004
-#define CONFIG_SYS_GPDR1_VAL 0xF002A282
-#define CONFIG_SYS_GPDR2_VAL 0x0001C200
-
-/* GP15 == nCS1 is AF10
- * GP18 == RDY is AF01
- * GP23 == SCLK is AF10
- * GP24 == SFRM is AF10
- * GP25 == TXD is AF10
- * GP26 == RXD is AF01
- * GP33 == nCS5 is AF10
- * GP34 == FFRXD is AF01
- * GP35 == CTS is AF01
- * GP39 == FFTXD is AF10
- * GP41 == RTS is AF10
- * GP46 == RXD is AF10
- * GP47 == TXD is AF01
- * GP49 == nPWE is AF10
- * GP78 == nCS2 is AF10
- * GP79 == nCS3 is AF10
- * GP80 == nCS4 is AF10
- */
-#define CONFIG_SYS_GAFR0_L_VAL 0x80000000
-#define CONFIG_SYS_GAFR0_U_VAL 0x001A8010
-#define CONFIG_SYS_GAFR1_L_VAL 0x60088058
-#define CONFIG_SYS_GAFR1_U_VAL 0x00000008
-#define CONFIG_SYS_GAFR2_L_VAL 0xA0000000
-#define CONFIG_SYS_GAFR2_U_VAL 0x00000002
-
-
-/* FIXME: set GPIO_RER/FER */
-
-/* RDH = 1
- * PH = 1
- * VFS = 1
- * BFS = 1
- * SSS = 1
- */
-#define CONFIG_SYS_PSSR_VAL 0x37
-
-/*
- * Memory settings
- *
- * This is the configuration for nCS0/1 -> flash banks
- * configuration for nCS1:
- * [31] 0 - Slower Device
- * [30:28] 010 - CS deselect to CS time: 2*(2*MemClk) = 40 ns
- * [27:24] 0101 - Address to data valid in bursts: (5+1)*MemClk = 60 ns
- * [23:20] 1011 - " for first access: (11+2)*MemClk = 130 ns
- * [19] 1 - 16 Bit bus width
- * [18:16] 000 - nonburst RAM or FLASH
- * configuration for nCS0:
- * [15] 0 - Slower Device
- * [14:12] 010 - CS deselect to CS time: 2*(2*MemClk) = 40 ns
- * [11:08] 0101 - Address to data valid in bursts: (5+1)*MemClk = 60 ns
- * [07:04] 1011 - " for first access: (11+2)*MemClk = 130 ns
- * [03] 1 - 16 Bit bus width
- * [02:00] 000 - nonburst RAM or FLASH
- */
-#define CONFIG_SYS_MSC0_VAL 0x25b825b8 /* flash banks */
-
-/* This is the configuration for nCS2/3 -> TDM-Switch, DSP
- * configuration for nCS3: DSP
- * [31] 0 - Slower Device
- * [30:28] 001 - RRR3: CS deselect to CS time: 1*(2*MemClk) = 20 ns
- * [27:24] 0010 - RDN3: Address to data valid in bursts: (2+1)*MemClk = 30 ns
- * [23:20] 0011 - RDF3: Address for first access: (3+1)*MemClk = 40 ns
- * [19] 1 - 16 Bit bus width
- * [18:16] 100 - variable latency I/O
- * configuration for nCS2: TDM-Switch
- * [15] 0 - Slower Device
- * [14:12] 101 - RRR2: CS deselect to CS time: 5*(2*MemClk) = 100 ns
- * [11:08] 1001 - RDN2: Address to data valid in bursts: (9+1)*MemClk = 100 ns
- * [07:04] 0011 - RDF2: Address for first access: (3+1)*MemClk = 40 ns
- * [03] 1 - 16 Bit bus width
- * [02:00] 100 - variable latency I/O
- */
-#define CONFIG_SYS_MSC1_VAL 0x123C593C /* TDM switch, DSP */
-
-/* This is the configuration for nCS4/5 -> ExtBus, LAN Controller
- *
- * configuration for nCS5: LAN Controller
- * [31] 0 - Slower Device
- * [30:28] 001 - RRR5: CS deselect to CS time: 1*(2*MemClk) = 20 ns
- * [27:24] 0010 - RDN5: Address to data valid in bursts: (2+1)*MemClk = 30 ns
- * [23:20] 0011 - RDF5: Address for first access: (3+1)*MemClk = 40 ns
- * [19] 1 - 16 Bit bus width
- * [18:16] 100 - variable latency I/O
- * configuration for nCS4: ExtBus
- * [15] 0 - Slower Device
- * [14:12] 110 - RRR4: CS deselect to CS time: 6*(2*MemClk) = 120 ns
- * [11:08] 1100 - RDN4: Address to data valid in bursts: (12+1)*MemClk = 130 ns
- * [07:04] 1101 - RDF4: Address for first access: 13->(15+1)*MemClk = 160 ns
- * [03] 1 - 16 Bit bus width
- * [02:00] 100 - variable latency I/O
- */
-#define CONFIG_SYS_MSC2_VAL 0x123C6CDC /* extra bus, LAN controller */
-
-/* MDCNFG: SDRAM Configuration Register
- *
- * [31:29] 000 - reserved
- * [28] 0 - no SA1111 compatiblity mode
- * [27] 0 - latch return data with return clock
- * [26] 0 - alternate addressing for pair 2/3
- * [25:24] 00 - timings
- * [23] 0 - internal banks in lower partition 2/3 (not used)
- * [22:21] 00 - row address bits for partition 2/3 (not used)
- * [20:19] 00 - column address bits for partition 2/3 (not used)
- * [18] 0 - SDRAM partition 2/3 width is 32 bit
- * [17] 0 - SDRAM partition 3 disabled
- * [16] 0 - SDRAM partition 2 disabled
- * [15:13] 000 - reserved
- * [12] 1 - SA1111 compatiblity mode
- * [11] 1 - latch return data with return clock
- * [10] 0 - no alternate addressing for pair 0/1
- * [09:08] 01 - tRP=2*MemClk CL=2 tRCD=2*MemClk tRAS=5*MemClk tRC=8*MemClk
- * [7] 1 - 4 internal banks in lower partition pair
- * [06:05] 10 - 13 row address bits for partition 0/1
- * [04:03] 01 - 9 column address bits for partition 0/1
- * [02] 0 - SDRAM partition 0/1 width is 32 bit
- * [01] 0 - disable SDRAM partition 1
- * [00] 1 - enable SDRAM partition 0
- */
-/* use the configuration above but disable partition 0 */
-#define CONFIG_SYS_MDCNFG_VAL 0x000019c8
-
-/* MDREFR: SDRAM Refresh Control Register
- *
- * [32:26] 0 - reserved
- * [25] 0 - K2FREE: not free running
- * [24] 0 - K1FREE: not free running
- * [23] 1 - K0FREE: not free running
- * [22] 0 - SLFRSH: self refresh disabled
- * [21] 0 - reserved
- * [20] 0 - APD: no auto power down
- * [19] 0 - K2DB2: SDCLK2 is MemClk
- * [18] 0 - K2RUN: disable SDCLK2
- * [17] 0 - K1DB2: SDCLK1 is MemClk
- * [16] 1 - K1RUN: enable SDCLK1
- * [15] 1 - E1PIN: SDRAM clock enable
- * [14] 1 - K0DB2: SDCLK0 is MemClk
- * [13] 0 - K0RUN: disable SDCLK0
- * [12] 1 - E0PIN: disable SDCKE0
- * [11:00] 000000011000 - (64ms/8192)*MemClkFreq/32 = 24
- */
-#define CONFIG_SYS_MDREFR_VAL 0x0081D018
-
-/* MDMRS: Mode Register Set Configuration Register
- *
- * [31] 0 - reserved
- * [30:23] 00000000- MDMRS2: SDRAM2/3 MRS Value. (not used)
- * [22:20] 000 - MDCL2: SDRAM2/3 Cas Latency. (not used)
- * [19] 0 - MDADD2: SDRAM2/3 burst Type. Fixed to sequential. (not used)
- * [18:16] 010 - MDBL2: SDRAM2/3 burst Length. Fixed to 4. (not used)
- * [15] 0 - reserved
- * [14:07] 00000000- MDMRS0: SDRAM0/1 MRS Value.
- * [06:04] 010 - MDCL0: SDRAM0/1 Cas Latency.
- * [03] 0 - MDADD0: SDRAM0/1 burst Type. Fixed to sequential.
- * [02:00] 010 - MDBL0: SDRAM0/1 burst Length. Fixed to 4.
- */
-#define CONFIG_SYS_MDMRS_VAL 0x00020022
-
-/*
- * PCMCIA and CF Interfaces
- */
-#define CONFIG_SYS_MECR_VAL 0x00000000
-#define CONFIG_SYS_MCMEM0_VAL 0x00000000
-#define CONFIG_SYS_MCMEM1_VAL 0x00000000
-#define CONFIG_SYS_MCATT0_VAL 0x00000000
-#define CONFIG_SYS_MCATT1_VAL 0x00000000
-#define CONFIG_SYS_MCIO0_VAL 0x00000000
-#define CONFIG_SYS_MCIO1_VAL 0x00000000
-#endif
-
-/*
- * GPIO settings
- */
-#define CONFIG_SYS_GPSR0_VAL 0xFFFFFFFF
-#define CONFIG_SYS_GPSR1_VAL 0xFFFFFFFF
-#define CONFIG_SYS_GPSR2_VAL 0xFFFFFFFF
-#define CONFIG_SYS_GPCR0_VAL 0x08022080
-#define CONFIG_SYS_GPCR1_VAL 0x00000000
-#define CONFIG_SYS_GPCR2_VAL 0x00000000
-#define CONFIG_SYS_GPDR0_VAL 0xCD82A878
-#define CONFIG_SYS_GPDR1_VAL 0xFCFFAB80
-#define CONFIG_SYS_GPDR2_VAL 0x0001FFFF
-#define CONFIG_SYS_GAFR0_L_VAL 0x80000000
-#define CONFIG_SYS_GAFR0_U_VAL 0xA5254010
-#define CONFIG_SYS_GAFR1_L_VAL 0x599A9550
-#define CONFIG_SYS_GAFR1_U_VAL 0xAAA5AAAA
-#define CONFIG_SYS_GAFR2_L_VAL 0xAAAAAAAA
-#define CONFIG_SYS_GAFR2_U_VAL 0x00000002
-
-/* FIXME: set GPIO_RER/FER */
-
-#define CONFIG_SYS_PSSR_VAL 0x20
-
-#define CONFIG_SYS_CCCR CCCR_L27|CCCR_M2|CCCR_N10
-#define CONFIG_SYS_CKEN 0x0
-
-/*
- * Memory settings
- */
-
-#define CONFIG_SYS_MSC0_VAL 0x2ef15af0
-#define CONFIG_SYS_MSC1_VAL 0x00003ff4
-#define CONFIG_SYS_MSC2_VAL 0x7ff07ff0
-#define CONFIG_SYS_MDCNFG_VAL 0x09a909a9
-#define CONFIG_SYS_MDREFR_VAL 0x038ff030
-#define CONFIG_SYS_MDMRS_VAL 0x00220022
-#define CONFIG_SYS_FLYCNFG_VAL 0x00000000
-#define CONFIG_SYS_SXCNFG_VAL 0x00000000
-
-/*
- * PCMCIA and CF Interfaces
- */
-#define CONFIG_SYS_MECR_VAL 0x00000000
-#define CONFIG_SYS_MCMEM0_VAL 0x00000000
-#define CONFIG_SYS_MCMEM1_VAL 0x00000000
-#define CONFIG_SYS_MCATT0_VAL 0x00000000
-#define CONFIG_SYS_MCATT1_VAL 0x00000000
-#define CONFIG_SYS_MCIO0_VAL 0x00000000
-#define CONFIG_SYS_MCIO1_VAL 0x00000000
-
-#define CSB226_USER_LED0 0x00000008
-#define CSB226_USER_LED1 0x00000010
-#define CSB226_USER_LED2 0x00000020
-
-
-/*
- * FLASH and environment organization
- */
-#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max number of memory banks */
-#define CONFIG_SYS_MAX_FLASH_SECT 128 /* max number of sect. on one chip */
-
-/* timeout values are in ticks */
-#define CONFIG_SYS_FLASH_ERASE_TOUT (2*CONFIG_SYS_HZ) /* Timeout for Flash Erase */
-#define CONFIG_SYS_FLASH_WRITE_TOUT (2*CONFIG_SYS_HZ) /* Timeout for Flash Write */
-
-#define CONFIG_ENV_IS_IN_FLASH 1
-#define CONFIG_ENV_ADDR (PHYS_FLASH_1 + 0x1C000)
- /* Addr of Environment Sector */
-#define CONFIG_ENV_SIZE 0x4000 /* Total Size of Environment Sector */
-
-#endif /* __CONFIG_H */
diff --git a/include/configs/da850_am18xxevm.h b/include/configs/da850_am18xxevm.h
new file mode 100644
index 0000000..92b83ff
--- /dev/null
+++ b/include/configs/da850_am18xxevm.h
@@ -0,0 +1,245 @@
+/*
+ * Copyright (C) 2011 Texas Instruments Incorporated - http://www.ti.com/
+ *
+ * Based on davinci_dvevm.h. Original Copyrights follow:
+ *
+ * Copyright (C) 2007 Sergey Kubushyn <ksi@koi8.net>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
+ */
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+/*
+ * Board
+ */
+#define CONFIG_DRIVER_TI_EMAC
+#define CONFIG_USE_SPIFLASH
+
+
+/*
+ * SoC Configuration
+ */
+#define CONFIG_MACH_DAVINCI_DA850_EVM
+#define CONFIG_ARM926EJS /* arm926ejs CPU core */
+#define CONFIG_SOC_DA8XX /* TI DA8xx SoC */
+#define CONFIG_SYS_CLK_FREQ clk_get(DAVINCI_ARM_CLKID)
+#define CONFIG_SYS_OSCIN_FREQ 24000000
+#define CONFIG_SYS_TIMERBASE DAVINCI_TIMER0_BASE
+#define CONFIG_SYS_HZ_CLOCK clk_get(DAVINCI_AUXCLK_CLKID)
+#define CONFIG_SYS_HZ 1000
+#define CONFIG_SKIP_LOWLEVEL_INIT
+#define CONFIG_SYS_TEXT_BASE 0xc1080000
+
+/*
+ * Memory Info
+ */
+#define CONFIG_SYS_MALLOC_LEN (0x10000 + 1*1024*1024) /* malloc() len */
+#define PHYS_SDRAM_1 DAVINCI_DDR_EMIF_DATA_BASE /* DDR Start */
+#define PHYS_SDRAM_1_SIZE (64 << 20) /* SDRAM size 64MB */
+#define CONFIG_MAX_RAM_BANK_SIZE (512 << 20) /* max size from SPRS586*/
+
+/* memtest start addr */
+#define CONFIG_SYS_MEMTEST_START (PHYS_SDRAM_1 + 0x2000000)
+
+/* memtest will be run on 16MB */
+#define CONFIG_SYS_MEMTEST_END (PHYS_SDRAM_1 + 0x2000000 + 16*1024*1024)
+
+#define CONFIG_NR_DRAM_BANKS 1 /* we have 1 bank of DRAM */
+#define CONFIG_STACKSIZE (256*1024) /* regular stack */
+
+/*
+ * Serial Driver info
+ */
+#define CONFIG_SYS_NS16550
+#define CONFIG_SYS_NS16550_SERIAL
+#define CONFIG_SYS_NS16550_REG_SIZE -4 /* NS16550 register size */
+#define CONFIG_SYS_NS16550_COM1 DAVINCI_UART2_BASE /* Base address of UART2 */
+#define CONFIG_SYS_NS16550_CLK clk_get(DAVINCI_UART2_CLKID)
+#define CONFIG_CONS_INDEX 1 /* use UART0 for console */
+#define CONFIG_BAUDRATE 115200 /* Default baud rate */
+#define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 }
+
+#define CONFIG_SPI
+#define CONFIG_SPI_FLASH
+#define CONFIG_SPI_FLASH_WINBOND
+#define CONFIG_DAVINCI_SPI
+#define CONFIG_SYS_SPI_BASE DAVINCI_SPI1_BASE
+#define CONFIG_SYS_SPI_CLK clk_get(DAVINCI_SPI1_CLKID)
+#define CONFIG_SF_DEFAULT_SPEED 30000000
+#define CONFIG_ENV_SPI_MAX_HZ CONFIG_SF_DEFAULT_SPEED
+
+/*
+ * I2C Configuration
+ */
+#define CONFIG_HARD_I2C
+#define CONFIG_DRIVER_DAVINCI_I2C
+#define CONFIG_SYS_I2C_SPEED 25000
+#define CONFIG_SYS_I2C_SLAVE 10 /* Bogus, master-only in U-Boot */
+#define CONFIG_SYS_I2C_EXPANDER_ADDR 0x20
+
+/*
+ * Flash & Environment
+ */
+#ifdef CONFIG_USE_NAND
+#undef CONFIG_ENV_IS_IN_FLASH
+#define CONFIG_NAND_DAVINCI
+#define CONFIG_SYS_NO_FLASH
+#define CONFIG_ENV_IS_IN_NAND /* U-Boot env in NAND Flash */
+#define CONFIG_ENV_OFFSET 0x0 /* Block 0--not used by bootcode */
+#define CONFIG_ENV_SIZE (128 << 10)
+#define CONFIG_SYS_NAND_USE_FLASH_BBT
+#define CONFIG_SYS_NAND_4BIT_HW_ECC_OOBFIRST
+#define CONFIG_SYS_NAND_PAGE_2K
+#define CONFIG_SYS_NAND_CS 3
+#define CONFIG_SYS_NAND_BASE DAVINCI_ASYNC_EMIF_DATA_CE3_BASE
+#define CONFIG_SYS_CLE_MASK 0x10
+#define CONFIG_SYS_ALE_MASK 0x8
+#undef CONFIG_SYS_NAND_HW_ECC
+#define CONFIG_SYS_MAX_NAND_DEVICE 1 /* Max number of NAND devices */
+#define NAND_MAX_CHIPS 1
+#endif
+
+/*
+ * Network & Ethernet Configuration
+ */
+#ifdef CONFIG_DRIVER_TI_EMAC
+#define CONFIG_EMAC_MDIO_PHY_NUM 0
+#define CONFIG_MII
+#define CONFIG_BOOTP_DEFAULT
+#define CONFIG_BOOTP_DNS
+#define CONFIG_BOOTP_DNS2
+#define CONFIG_BOOTP_SEND_HOSTNAME
+#define CONFIG_NET_RETRY_COUNT 10
+#define CONFIG_NET_MULTI
+#endif
+
+#ifdef CONFIG_USE_NOR
+#define CONFIG_ENV_IS_IN_FLASH
+#define CONFIG_FLASH_CFI_DRIVER
+#define CONFIG_SYS_FLASH_CFI
+#define CONFIG_SYS_FLASH_PROTECTION
+#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max number of flash banks */
+#define CONFIG_SYS_FLASH_SECT_SZ (128 << 10) /* 128KB */
+#define CONFIG_ENV_OFFSET (CONFIG_SYS_FLASH_SECT_SZ * 3)
+#define CONFIG_ENV_SIZE (10 << 10) /* 10KB */
+#define CONFIG_SYS_FLASH_BASE DAVINCI_ASYNC_EMIF_DATA_CE2_BASE
+#define PHYS_FLASH_SIZE (8 << 20) /* Flash size 8MB */
+#define CONFIG_SYS_MAX_FLASH_SECT ((PHYS_FLASH_SIZE/CONFIG_SYS_FLASH_SECT_SZ)\
+ + 3)
+#define CONFIG_ENV_SECT_SIZE CONFIG_SYS_FLASH_SECT_SZ
+#endif
+
+#ifdef CONFIG_USE_SPIFLASH
+#undef CONFIG_ENV_IS_IN_FLASH
+#undef CONFIG_ENV_IS_IN_NAND
+#define CONFIG_ENV_IS_IN_SPI_FLASH
+#define CONFIG_ENV_SIZE (64 << 10)
+#define CONFIG_ENV_OFFSET (256 << 10)
+#define CONFIG_ENV_SECT_SIZE (64 << 10)
+#define CONFIG_SYS_NO_FLASH
+#endif
+
+/*
+ * U-Boot general configuration
+ */
+#define CONFIG_MISC_INIT_R
+#define CONFIG_BOOTFILE "uImage" /* Boot file name */
+#define CONFIG_SYS_PROMPT "U-Boot > " /* Command Prompt */
+#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
+#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16)
+#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
+#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Args Buffer Size */
+#define CONFIG_SYS_LOAD_ADDR (PHYS_SDRAM_1 + 0x700000)
+#define CONFIG_VERSION_VARIABLE
+#define CONFIG_AUTO_COMPLETE
+#define CONFIG_SYS_HUSH_PARSER
+#define CONFIG_SYS_PROMPT_HUSH_PS2 "> "
+#define CONFIG_CMDLINE_EDITING
+#define CONFIG_SYS_LONGHELP
+#define CONFIG_CRC32_VERIFY
+#define CONFIG_MX_CYCLIC
+
+/*
+ * Linux Information
+ */
+#define LINUX_BOOT_PARAM_ADDR (PHYS_SDRAM_1 + 0x100)
+#define CONFIG_HWCONFIG /* enable hwconfig */
+#define CONFIG_CMDLINE_TAG
+#define CONFIG_REVISION_TAG
+#define CONFIG_SETUP_MEMORY_TAGS
+#define CONFIG_BOOTARGS \
+ "mem=32M console=ttyS2,115200n8 root=/dev/mtdblock2 rw noinitrd ip=dhcp"
+#define CONFIG_BOOTDELAY 3
+#define CONFIG_EXTRA_ENV_SETTINGS "hwconfig=dsp:wake=yes"
+
+/*
+ * U-Boot commands
+ */
+#include <config_cmd_default.h>
+#define CONFIG_CMD_ENV
+#define CONFIG_CMD_ASKENV
+#define CONFIG_CMD_DHCP
+#define CONFIG_CMD_DIAG
+#define CONFIG_CMD_MII
+#define CONFIG_CMD_PING
+#define CONFIG_CMD_SAVES
+#define CONFIG_CMD_MEMORY
+
+#ifndef CONFIG_DRIVER_TI_EMAC
+#undef CONFIG_CMD_NET
+#undef CONFIG_CMD_DHCP
+#undef CONFIG_CMD_MII
+#undef CONFIG_CMD_PING
+#endif
+
+#ifdef CONFIG_USE_NAND
+#undef CONFIG_CMD_FLASH
+#undef CONFIG_CMD_IMLS
+#define CONFIG_CMD_NAND
+
+#define CONFIG_CMD_MTDPARTS
+#define CONFIG_MTD_DEVICE
+#define CONFIG_MTD_PARTITIONS
+#define CONFIG_LZO
+#define CONFIG_RBTREE
+#define CONFIG_CMD_UBI
+#define CONFIG_CMD_UBIFS
+#endif
+
+#ifdef CONFIG_USE_SPIFLASH
+#undef CONFIG_CMD_IMLS
+#undef CONFIG_CMD_FLASH
+#define CONFIG_CMD_SPI
+#define CONFIG_CMD_SF
+#define CONFIG_CMD_SAVEENV
+#endif
+
+#if !defined(CONFIG_USE_NAND) && \
+ !defined(CONFIG_USE_NOR) && \
+ !defined(CONFIG_USE_SPIFLASH)
+#define CONFIG_ENV_IS_NOWHERE
+#define CONFIG_SYS_NO_FLASH
+#define CONFIG_ENV_SIZE (16 << 10)
+#undef CONFIG_CMD_IMLS
+#undef CONFIG_CMD_ENV
+#endif
+
+/* additions for new relocation code, must added to all boards */
+#define CONFIG_SYS_SDRAM_BASE 0xc0000000
+#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_SDRAM_BASE + 0x1000 - \
+ /* Fix this */ GENERATED_GBL_DATA_SIZE)
+#endif /* __CONFIG_H */
diff --git a/include/configs/davinci_dm6467Tevm.h b/include/configs/davinci_dm6467Tevm.h
new file mode 100644
index 0000000..f7c994e
--- /dev/null
+++ b/include/configs/davinci_dm6467Tevm.h
@@ -0,0 +1,163 @@
+/*
+ * Copyright (C) 2011 Texas Instruments Incorporated
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+/* Spectrum Digital TMS320DM6467T EVM board */
+#define DAVINCI_DM6467EVM
+#define DAVINCI_DM6467TEVM
+#define CONFIG_SYS_USE_NAND
+#define CONFIG_SYS_NAND_SMALLPAGE
+
+#define CONFIG_SKIP_LOWLEVEL_INIT
+
+/* SoC Configuration */
+#define CONFIG_ARM926EJS /* arm926ejs CPU */
+
+/* Clock rates detection */
+#ifndef __ASSEMBLY__
+extern unsigned int davinci_arm_clk_get(void);
+#endif
+
+#define CFG_REFCLK_FREQ 33000000
+/* Arm Clock frequency */
+#define CONFIG_SYS_CLK_FREQ davinci_arm_clk_get()
+/* Timer Input clock freq */
+#define CONFIG_SYS_HZ_CLOCK (CONFIG_SYS_CLK_FREQ/2)
+#define CONFIG_SYS_TIMERBASE 0x01c21400 /* use timer 0 */
+#define CONFIG_SYS_HZ 1000
+#define CONFIG_SOC_DM646X
+
+/* EEPROM definitions for EEPROM */
+#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2
+#define CONFIG_SYS_I2C_EEPROM_ADDR 0x50
+#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 6
+#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 20
+
+/* Memory Info */
+#define CONFIG_SYS_MALLOC_LEN (1 << 20) /* 1 MiB */
+#define CONFIG_SYS_MEMTEST_START 0x80000000
+#define CONFIG_SYS_MEMTEST_END 0x81000000 /* 16MB RAM test */
+#define CONFIG_NR_DRAM_BANKS 1
+#define CONFIG_STACKSIZE (256 << 10) /* 256 KiB */
+#define PHYS_SDRAM_1 0x80000000 /* DDR Start */
+#define PHYS_SDRAM_1_SIZE (256 << 20) /* DDR size 256MB */
+
+/* Linux interfacing */
+#define CONFIG_CMDLINE_TAG
+#define CONFIG_SETUP_MEMORY_TAGS
+#define CONFIG_SYS_BARGSIZE 1024 /* Bootarg Size */
+#define CONFIG_SYS_LOAD_ADDR 0x80700000 /* kernel address */
+#define CONFIG_REVISION_TAG
+
+/* Serial Driver info */
+#define CONFIG_SYS_NS16550
+#define CONFIG_SYS_NS16550_SERIAL
+#define CONFIG_SYS_NS16550_REG_SIZE 4
+#define CONFIG_SYS_NS16550_COM1 0x01c20000
+#define CONFIG_SYS_NS16550_CLK 24000000
+#define CONFIG_CONS_INDEX 1
+#define CONFIG_BAUDRATE 115200
+#define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 }
+
+/* I2C Configuration */
+#define CONFIG_HARD_I2C
+#define CONFIG_DRIVER_DAVINCI_I2C
+#define CONFIG_SYS_I2C_SPEED 80000
+#define CONFIG_SYS_I2C_SLAVE 10
+
+/* Network & Ethernet Configuration */
+#define CONFIG_DRIVER_TI_EMAC
+#define CONFIG_EMAC_MDIO_PHY_NUM 1
+#define CONFIG_MII
+#define CONFIG_BOOTP_DEFAULT
+#define CONFIG_BOOTP_DNS
+#define CONFIG_BOOTP_DNS2
+#define CONFIG_BOOTP_SEND_HOSTNAME
+#define CONFIG_NET_RETRY_COUNT 10
+#define CONFIG_CMD_NET
+
+/* Flash & Environment */
+#define CONFIG_SYS_NO_FLASH
+#ifdef CONFIG_SYS_USE_NAND
+#define CONFIG_NAND_DAVINCI
+#define CONFIG_SYS_NAND_CS 2
+#undef CONFIG_ENV_IS_IN_FLASH
+#define CONFIG_ENV_IS_IN_NAND
+#define CONFIG_ENV_SIZE (16 << 10) /* 16 KiB */
+#define CONFIG_SYS_NAND_BASE_LIST {0x42000000, }
+#define CONFIG_SYS_NAND_HW_ECC
+#define CONFIG_SYS_MAX_NAND_DEVICE 1
+#define CONFIG_ENV_OFFSET 0
+#else
+#define CONFIG_ENV_IS_NOWHERE
+#define CONFIG_ENV_SIZE (4 << 10) /* 4 KiB */
+#endif
+
+/* U-Boot general configuration */
+#undef CONFIG_USE_IRQ /* No IRQ/FIQ in U-Boot */
+#define CONFIG_BOOTDELAY 3
+#define CONFIG_BOOTFILE "uImage" /* Boot file name */
+#define CONFIG_SYS_PROMPT "DM6467 EVM > " /* Monitor Command Prompt */
+#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
+#define CONFIG_SYS_PBSIZE \
+ (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16)
+#define CONFIG_SYS_MAXARGS 16
+#define CONFIG_VERSION_VARIABLE
+#define CONFIG_AUTO_COMPLETE
+#define CONFIG_SYS_HUSH_PARSER
+#define CONFIG_SYS_PROMPT_HUSH_PS2 "> "
+#define CONFIG_CMDLINE_EDITING
+#define CONFIG_SYS_LONGHELP
+#define CONFIG_CRC32_VERIFY
+#define CONFIG_MX_CYCLIC
+#define CONFIG_BOOTCOMMAND "source 0x82080000; dhcp; bootm"
+#define CONFIG_BOOTARGS \
+ "mem=120M console=ttyS0,115200n8 " \
+ "root=/dev/hda1 rw noinitrd ip=dhcp"
+
+/* U-Boot commands */
+#include <config_cmd_default.h>
+#define CONFIG_CMD_ASKENV
+#define CONFIG_CMD_DIAG
+#define CONFIG_CMD_I2C
+#define CONFIG_CMD_MII
+#define CONFIG_CMD_SAVES
+#define CONFIG_CMD_EEPROM
+#define CONFIG_CMD_PING
+#define CONFIG_CMD_DHCP
+#undef CONFIG_CMD_BDI
+#undef CONFIG_CMD_FPGA
+#undef CONFIG_CMD_SETGETDCR
+#ifdef CONFIG_SYS_USE_NAND
+#undef CONFIG_CMD_FLASH
+#undef CONFIG_CMD_IMLS
+#define CONFIG_CMD_NAND
+#endif
+
+#define CONFIG_MAX_RAM_BANK_SIZE (256 << 20) /* 256 MB */
+
+#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1
+#define CONFIG_SYS_INIT_RAM_SIZE 0x1000
+#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_SDRAM_BASE + \
+ CONFIG_SYS_INIT_RAM_SIZE - \
+ GENERATED_GBL_DATA_SIZE)
+
+#endif /* __CONFIG_H */
diff --git a/include/configs/davinci_dm6467evm.h b/include/configs/davinci_dm6467evm.h
index ec1c31c..c9a0cd1 100644
--- a/include/configs/davinci_dm6467evm.h
+++ b/include/configs/davinci_dm6467evm.h
@@ -65,6 +65,7 @@
#define CONFIG_SETUP_MEMORY_TAGS
#define CONFIG_SYS_BARGSIZE 1024 /* Bootarg Size */
#define CONFIG_SYS_LOAD_ADDR 0x80700000 /* kernel address */
+#define CONFIG_REVISION_TAG
/* Serial Driver info */
#define CONFIG_SYS_NS16550
diff --git a/include/configs/devkit8000.h b/include/configs/devkit8000.h
index 6c51a27..e1743dc 100644
--- a/include/configs/devkit8000.h
+++ b/include/configs/devkit8000.h
@@ -337,6 +337,7 @@
#define CONFIG_SPL_BSS_MAX_SIZE 0x80000
/* NAND boot config */
+#define CONFIG_SYS_NAND_5_ADDR_CYCLE
#define CONFIG_SYS_NAND_PAGE_COUNT 64
#define CONFIG_SYS_NAND_PAGE_SIZE 2048
#define CONFIG_SYS_NAND_OOBSIZE 64
diff --git a/include/configs/innokom.h b/include/configs/innokom.h
deleted file mode 100644
index a0a3da1..0000000
--- a/include/configs/innokom.h
+++ /dev/null
@@ -1,507 +0,0 @@
-/*
- * (C) Copyright 2000, 2001, 2002
- * Robert Schwebel, Pengutronix, r.schwebel@pengutronix.de.
- *
- * Configuration for the Auerswald Innokom CPU board.
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-/*
- * include/configs/innokom.h - configuration options, board specific
- */
-
-#ifndef __CONFIG_H
-#define __CONFIG_H
-
-/*
- * High Level Configuration Options
- * (easy to change)
- */
-#define CONFIG_PXA250 1 /* This is an PXA250 CPU */
-#define CONFIG_INNOKOM 1 /* on an Auerswald Innokom board */
-
-#undef CONFIG_USE_IRQ /* we don't need IRQ/FIQ stuff */
- /* for timer/console/ethernet */
-
-#define CONFIG_SYS_TEXT_BASE 0x0
-
-/* we will never enable dcache, because we have to setup MMU first */
-#define CONFIG_SYS_DCACHE_OFF
-
-/*
- * Hardware drivers
- */
-
-/*
- * select serial console configuration
- */
-#define CONFIG_PXA_SERIAL
-#define CONFIG_FFUART 1 /* we use FFUART on CSB226 */
-
-/* allow to overwrite serial and ethaddr */
-#define CONFIG_ENV_OVERWRITE
-
-#define CONFIG_BAUDRATE 19200
-#define CONFIG_MISC_INIT_R 1 /* we have a misc_init_r() function */
-
-
-/*
- * BOOTP options
- */
-#define CONFIG_BOOTP_BOOTFILESIZE
-#define CONFIG_BOOTP_BOOTPATH
-#define CONFIG_BOOTP_GATEWAY
-#define CONFIG_BOOTP_HOSTNAME
-
-
-/*
- * Command line configuration.
- */
-
-#define CONFIG_CMD_ASKENV
-#define CONFIG_CMD_BDI
-#define CONFIG_CMD_CACHE
-#define CONFIG_CMD_DHCP
-#define CONFIG_CMD_ECHO
-#define CONFIG_CMD_SAVEENV
-#define CONFIG_CMD_FLASH
-#define CONFIG_CMD_I2C
-#define CONFIG_CMD_IMI
-#define CONFIG_CMD_LOADB
-#define CONFIG_CMD_MEMORY
-#define CONFIG_CMD_NET
-#define CONFIG_CMD_RUN
-
-
-#define CONFIG_BOOTDELAY 3
-/* #define CONFIG_BOOTARGS "root=/dev/nfs ip=bootp console=ttyS0,19200" */
-#define CONFIG_BOOTARGS "console=ttyS0,19200"
-#define CONFIG_ETHADDR FF:FF:FF:FF:FF:FF
-#define CONFIG_NETMASK 255.255.255.0
-#define CONFIG_IPADDR 192.168.1.56
-#define CONFIG_SERVERIP 192.168.1.2
-#define CONFIG_BOOTCOMMAND "bootm 0x40000"
-#define CONFIG_SHOW_BOOT_PROGRESS
-
-#define CONFIG_CMDLINE_TAG 1
-
-/*
- * Miscellaneous configurable options
- */
-
-/*
- * Size of malloc() pool
- */
-#define CONFIG_SYS_MALLOC_LEN (256*1024)
-
-#define CONFIG_SYS_LONGHELP /* undef to save memory */
-#define CONFIG_SYS_PROMPT "uboot> " /* Monitor Command Prompt */
-#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
-#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
-#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
-#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */
-
-#define CONFIG_SYS_MEMTEST_START 0xa0400000 /* memtest works on */
-#define CONFIG_SYS_MEMTEST_END 0xa0800000 /* 4 ... 8 MB in DRAM */
-
-#define CONFIG_SYS_LOAD_ADDR 0xa3000000 /* load kernel to this address */
-
-#define CONFIG_SYS_HZ 1000
- /* RS: the oscillator is actually 3680130?? */
-
-#define CONFIG_SYS_CPUSPEED 0x141 /* set core clock to 200/200/100 MHz */
- /* 0101000001 */
- /* ^^^^^ Memory Speed 99.53 MHz */
- /* ^^ Run Mode Speed = 2x Mem Speed */
- /* ^^ Turbo Mode Sp. = 1x Run M. Sp. */
-
-#define CONFIG_SYS_MONITOR_LEN 0x20000 /* 128 KiB */
-
- /* valid baudrates */
-#define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 }
-
-/*
- * I2C bus
- */
-#define CONFIG_I2C_MV 1
-#define CONFIG_MV_I2C_REG 0x40301680
-#define CONFIG_HARD_I2C 1
-#define CONFIG_SYS_I2C_SPEED 50000
-#define CONFIG_SYS_I2C_SLAVE 0xfe
-
-#define CONFIG_ENV_IS_IN_EEPROM 1
-
-#define CONFIG_ENV_OFFSET 0x00 /* environment starts here */
-#define CONFIG_ENV_SIZE 1024 /* 1 KiB */
-#define CONFIG_SYS_I2C_EEPROM_ADDR 0x50 /* A0 = 0 (hardwired) */
-#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 5 /* 5 bits = 32 octets */
-#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 15 /* between stop and start */
-#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2 /* length of address */
-#define CONFIG_SYS_EEPROM_SIZE 4096 /* size in bytes */
-#define CONFIG_SYS_I2C_INIT_BOARD 1 /* board has it's own init */
-
-/*
- * SMSC91C111 Network Card
- */
-#define CONFIG_SMC91111 1
-#define CONFIG_SMC91111_BASE 0x14000000 /* chip select 5 */
-#undef CONFIG_SMC_USE_32_BIT /* 16 bit bus access */
-#undef CONFIG_SMC_91111_EXT_PHY /* we use internal phy */
-#define CONFIG_SMC_AUTONEG_TIMEOUT 10 /* timeout 10 seconds */
-#undef CONFIG_SHOW_ACTIVITY
-#define CONFIG_NET_RETRY_COUNT 10 /* # of retries */
-
-/*
- * Stack sizes
- *
- * The stack sizes are set up in start.S using the settings below
- */
-#define CONFIG_STACKSIZE (128*1024) /* regular stack */
-#ifdef CONFIG_USE_IRQ
-#define CONFIG_STACKSIZE_IRQ (4*1024) /* IRQ stack */
-#define CONFIG_STACKSIZE_FIQ (4*1024) /* FIQ stack */
-#endif
-
-/*
- * Physical Memory Map
- */
-#define CONFIG_NR_DRAM_BANKS 1 /* we have 1 bank of DRAM */
-#define PHYS_SDRAM_1 0xa0000000 /* SDRAM Bank #1 */
-#define PHYS_SDRAM_1_SIZE 0x04000000 /* 64 MB */
-
-#define PHYS_FLASH_1 0x00000000 /* Flash Bank #1 */
-#define PHYS_FLASH_SIZE 0x01000000 /* 16 MB */
-
-#define CONFIG_SYS_DRAM_BASE 0xa0000000 /* RAM starts here */
-#define CONFIG_SYS_DRAM_SIZE 0x04000000
-
-#define CONFIG_SYS_FLASH_BASE PHYS_FLASH_1
-
-#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1
-#define CONFIG_SYS_INIT_SP_ADDR (GENERATED_GBL_DATA_SIZE + PHYS_SDRAM_1)
-
-/*
- * JFFS2 partitions
- *
- */
-/* development flash */
-#define CONFIG_MTD_INNOKOM_16MB 1
-#undef CONFIG_MTD_INNOKOM_64MB
-
-/* production flash */
-/*
-#define CONFIG_MTD_INNOKOM_64MB 1
-#undef CONFIG_MTD_INNOKOM_16MB
-*/
-
-/* No command line, one static partition, whole device */
-#undef CONFIG_CMD_MTDPARTS
-#define CONFIG_JFFS2_DEV "nor0"
-#define CONFIG_JFFS2_PART_SIZE 0xFFFFFFFF
-#define CONFIG_JFFS2_PART_OFFSET 0x00000000
-
-/* mtdparts command line support */
-/* Note: fake mtd_id used, no linux mtd map file */
-/*
-#define CONFIG_CMD_MTDPARTS
-#define MTDIDS_DEFAULT "nor0=innokom-0"
-*/
-
-/* development flash */
-/*
-#define MTDPARTS_DEFAULT "mtdparts=innokom-0:256k(uboot),768k(kernel),8m(user),7m(data)"
-*/
-
-/* production flash */
-/*
-#define MTDPARTS_DEFAULT "mtdparts=innokom-0:256k(uboot),768k(kernel),16256k(user1),16256k(user2),32m(data)"
-*/
-
-/*
- * GPIO settings
- *
- * GP15 == nCS1 is 1
- * GP24 == SFRM is 1
- * GP25 == TXD is 1
- * GP33 == nCS5 is 1
- * GP39 == FFTXD is 1
- * GP41 == RTS is 1
- * GP47 == TXD is 1
- * GP49 == nPWE is 1
- * GP62 == LED_B is 1
- * GP63 == TDM_OE is 1
- * GP78 == nCS2 is 1
- * GP79 == nCS3 is 1
- * GP80 == nCS4 is 1
- */
-#define CONFIG_SYS_GPSR0_VAL 0x03008000
-#define CONFIG_SYS_GPSR1_VAL 0xC0028282
-#define CONFIG_SYS_GPSR2_VAL 0x0001C000
-
-/* GP02 == DON_RST is 0
- * GP23 == SCLK is 0
- * GP45 == USB_ACT is 0
- * GP60 == PLLEN is 0
- * GP61 == LED_A is 0
- * GP73 == SWUPD_LED is 0
- */
-#define CONFIG_SYS_GPCR0_VAL 0x00800004
-#define CONFIG_SYS_GPCR1_VAL 0x30002000
-#define CONFIG_SYS_GPCR2_VAL 0x00000100
-
-/* GP00 == DON_READY is input
- * GP01 == DON_OK is input
- * GP02 == DON_RST is output
- * GP03 == RESET_IND is input
- * GP07 == RES11 is input
- * GP09 == RES12 is input
- * GP11 == SWUPDATE is input
- * GP14 == nPOWEROK is input
- * GP15 == nCS1 is output
- * GP17 == RES22 is input
- * GP18 == RDY is input
- * GP23 == SCLK is output
- * GP24 == SFRM is output
- * GP25 == TXD is output
- * GP26 == RXD is input
- * GP32 == RES21 is input
- * GP33 == nCS5 is output
- * GP34 == FFRXD is input
- * GP35 == CTS is input
- * GP39 == FFTXD is output
- * GP41 == RTS is output
- * GP42 == USB_OK is input
- * GP45 == USB_ACT is output
- * GP46 == RXD is input
- * GP47 == TXD is output
- * GP49 == nPWE is output
- * GP58 == nCPUBUSINT is input
- * GP59 == LANINT is input
- * GP60 == PLLEN is output
- * GP61 == LED_A is output
- * GP62 == LED_B is output
- * GP63 == TDM_OE is output
- * GP64 == nDSPINT is input
- * GP65 == STRAP0 is input
- * GP67 == STRAP1 is input
- * GP69 == STRAP2 is input
- * GP70 == STRAP3 is input
- * GP71 == STRAP4 is input
- * GP73 == SWUPD_LED is output
- * GP78 == nCS2 is output
- * GP79 == nCS3 is output
- * GP80 == nCS4 is output
- */
-#define CONFIG_SYS_GPDR0_VAL 0x03808004
-#define CONFIG_SYS_GPDR1_VAL 0xF002A282
-#define CONFIG_SYS_GPDR2_VAL 0x0001C200
-
-/* GP15 == nCS1 is AF10
- * GP18 == RDY is AF01
- * GP23 == SCLK is AF10
- * GP24 == SFRM is AF10
- * GP25 == TXD is AF10
- * GP26 == RXD is AF01
- * GP33 == nCS5 is AF10
- * GP34 == FFRXD is AF01
- * GP35 == CTS is AF01
- * GP39 == FFTXD is AF10
- * GP41 == RTS is AF10
- * GP46 == RXD is AF10
- * GP47 == TXD is AF01
- * GP49 == nPWE is AF10
- * GP78 == nCS2 is AF10
- * GP79 == nCS3 is AF10
- * GP80 == nCS4 is AF10
- */
-#define CONFIG_SYS_GAFR0_L_VAL 0x80000000
-#define CONFIG_SYS_GAFR0_U_VAL 0x001A8010
-#define CONFIG_SYS_GAFR1_L_VAL 0x60088058
-#define CONFIG_SYS_GAFR1_U_VAL 0x00000008
-#define CONFIG_SYS_GAFR2_L_VAL 0xA0000000
-#define CONFIG_SYS_GAFR2_U_VAL 0x00000002
-
-
-/* FIXME: set GPIO_RER/FER */
-
-/* RDH = 1
- * PH = 1
- * VFS = 1
- * BFS = 1
- * SSS = 1
- */
-#define CONFIG_SYS_PSSR_VAL 0x37
-
-#define CONFIG_SYS_CCCR CCCR_L27|CCCR_M2|CCCR_N10
-#define CONFIG_SYS_CKEN 0x0
-
-/*
- * Memory settings
- *
- * This is the configuration for nCS0/1 -> flash banks
- * configuration for nCS1:
- * [31] 0 - Slower Device
- * [30:28] 010 - CS deselect to CS time: 2*(2*MemClk) = 40 ns
- * [27:24] 0101 - Address to data valid in bursts: (5+1)*MemClk = 60 ns
- * [23:20] 1011 - " for first access: (11+2)*MemClk = 130 ns
- * [19] 1 - 16 Bit bus width
- * [18:16] 000 - nonburst RAM or FLASH
- * configuration for nCS0:
- * [15] 0 - Slower Device
- * [14:12] 010 - CS deselect to CS time: 2*(2*MemClk) = 40 ns
- * [11:08] 0101 - Address to data valid in bursts: (5+1)*MemClk = 60 ns
- * [07:04] 1011 - " for first access: (11+2)*MemClk = 130 ns
- * [03] 1 - 16 Bit bus width
- * [02:00] 000 - nonburst RAM or FLASH
- */
-#define CONFIG_SYS_MSC0_VAL 0x25b825b8 /* flash banks */
-
-/* This is the configuration for nCS2/3 -> TDM-Switch, DSP
- * configuration for nCS3: DSP
- * [31] 0 - Slower Device
- * [30:28] 001 - RRR3: CS deselect to CS time: 1*(2*MemClk) = 20 ns
- * [27:24] 0010 - RDN3: Address to data valid in bursts: (2+1)*MemClk = 30 ns
- * [23:20] 0011 - RDF3: Address for first access: (3+1)*MemClk = 40 ns
- * [19] 1 - 16 Bit bus width
- * [18:16] 100 - variable latency I/O
- * configuration for nCS2: TDM-Switch
- * [15] 0 - Slower Device
- * [14:12] 101 - RRR2: CS deselect to CS time: 5*(2*MemClk) = 100 ns
- * [11:08] 1001 - RDN2: Address to data valid in bursts: (9+1)*MemClk = 100 ns
- * [07:04] 0011 - RDF2: Address for first access: (3+1)*MemClk = 40 ns
- * [03] 1 - 16 Bit bus width
- * [02:00] 100 - variable latency I/O
- */
-#define CONFIG_SYS_MSC1_VAL 0x123C593C /* TDM switch, DSP */
-
-/* This is the configuration for nCS4/5 -> ExtBus, LAN Controller
- *
- * configuration for nCS5: LAN Controller
- * [31] 0 - Slower Device
- * [30:28] 001 - RRR5: CS deselect to CS time: 1*(2*MemClk) = 20 ns
- * [27:24] 0010 - RDN5: Address to data valid in bursts: (2+1)*MemClk = 30 ns
- * [23:20] 0011 - RDF5: Address for first access: (3+1)*MemClk = 40 ns
- * [19] 1 - 16 Bit bus width
- * [18:16] 100 - variable latency I/O
- * configuration for nCS4: ExtBus
- * [15] 0 - Slower Device
- * [14:12] 110 - RRR4: CS deselect to CS time: 6*(2*MemClk) = 120 ns
- * [11:08] 1100 - RDN4: Address to data valid in bursts: (12+1)*MemClk = 130 ns
- * [07:04] 1101 - RDF4: Address for first access: 13->(15+1)*MemClk = 160 ns
- * [03] 1 - 16 Bit bus width
- * [02:00] 100 - variable latency I/O
- */
-#define CONFIG_SYS_MSC2_VAL 0x123C6CDC /* extra bus, LAN controller */
-
-/* MDCNFG: SDRAM Configuration Register
- *
- * [31:29] 000 - reserved
- * [28] 0 - no SA1111 compatiblity mode
- * [27] 0 - latch return data with return clock
- * [26] 0 - alternate addressing for pair 2/3
- * [25:24] 00 - timings
- * [23] 0 - internal banks in lower partition 2/3 (not used)
- * [22:21] 00 - row address bits for partition 2/3 (not used)
- * [20:19] 00 - column address bits for partition 2/3 (not used)
- * [18] 0 - SDRAM partition 2/3 width is 32 bit
- * [17] 0 - SDRAM partition 3 disabled
- * [16] 0 - SDRAM partition 2 disabled
- * [15:13] 000 - reserved
- * [12] 1 - SA1111 compatiblity mode
- * [11] 1 - latch return data with return clock
- * [10] 0 - no alternate addressing for pair 0/1
- * [09:08] 01 - tRP=2*MemClk CL=2 tRCD=2*MemClk tRAS=5*MemClk tRC=8*MemClk
- * [7] 1 - 4 internal banks in lower partition pair
- * [06:05] 10 - 13 row address bits for partition 0/1
- * [04:03] 01 - 9 column address bits for partition 0/1
- * [02] 0 - SDRAM partition 0/1 width is 32 bit
- * [01] 0 - disable SDRAM partition 1
- * [00] 1 - enable SDRAM partition 0
- */
-/* use the configuration above but disable partition 0 */
-#define CONFIG_SYS_MDCNFG_VAL 0x000019c8
-
-/* MDREFR: SDRAM Refresh Control Register
- *
- * [32:26] 0 - reserved
- * [25] 0 - K2FREE: not free running
- * [24] 0 - K1FREE: not free running
- * [23] 1 - K0FREE: not free running
- * [22] 0 - SLFRSH: self refresh disabled
- * [21] 0 - reserved
- * [20] 0 - APD: no auto power down
- * [19] 0 - K2DB2: SDCLK2 is MemClk
- * [18] 0 - K2RUN: disable SDCLK2
- * [17] 0 - K1DB2: SDCLK1 is MemClk
- * [16] 1 - K1RUN: enable SDCLK1
- * [15] 1 - E1PIN: SDRAM clock enable
- * [14] 1 - K0DB2: SDCLK0 is MemClk
- * [13] 0 - K0RUN: disable SDCLK0
- * [12] 1 - E0PIN: disable SDCKE0
- * [11:00] 000000011000 - (64ms/8192)*MemClkFreq/32 = 24
- */
-#define CONFIG_SYS_MDREFR_VAL 0x0081D018
-
-/* MDMRS: Mode Register Set Configuration Register
- *
- * [31] 0 - reserved
- * [30:23] 00000000- MDMRS2: SDRAM2/3 MRS Value. (not used)
- * [22:20] 000 - MDCL2: SDRAM2/3 Cas Latency. (not used)
- * [19] 0 - MDADD2: SDRAM2/3 burst Type. Fixed to sequential. (not used)
- * [18:16] 010 - MDBL2: SDRAM2/3 burst Length. Fixed to 4. (not used)
- * [15] 0 - reserved
- * [14:07] 00000000- MDMRS0: SDRAM0/1 MRS Value.
- * [06:04] 010 - MDCL0: SDRAM0/1 Cas Latency.
- * [03] 0 - MDADD0: SDRAM0/1 burst Type. Fixed to sequential.
- * [02:00] 010 - MDBL0: SDRAM0/1 burst Length. Fixed to 4.
- */
-#define CONFIG_SYS_MDMRS_VAL 0x00020022
-
-/*
- * PCMCIA and CF Interfaces
- */
-#define CONFIG_SYS_MECR_VAL 0x00000000
-#define CONFIG_SYS_MCMEM0_VAL 0x00000000
-#define CONFIG_SYS_MCMEM1_VAL 0x00000000
-#define CONFIG_SYS_MCATT0_VAL 0x00000000
-#define CONFIG_SYS_MCATT1_VAL 0x00000000
-#define CONFIG_SYS_MCIO0_VAL 0x00000000
-#define CONFIG_SYS_MCIO1_VAL 0x00000000
-
-#define CONFIG_SYS_FLYCNFG_VAL 0x00000000
-#define CONFIG_SYS_SXCNFG_VAL 0x00000000
-
-/*
-#define CSB226_USER_LED0 0x00000008
-#define CSB226_USER_LED1 0x00000010
-#define CSB226_USER_LED2 0x00000020
-*/
-
-/*
- * FLASH and environment organization
- */
-#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max number of memory banks */
-#define CONFIG_SYS_MAX_FLASH_SECT 128 /* max number of sect. on one chip */
-
-/* timeout values are in ticks */
-#define CONFIG_SYS_FLASH_ERASE_TOUT (2*CONFIG_SYS_HZ) /* Timeout for Flash Erase */
-#define CONFIG_SYS_FLASH_WRITE_TOUT (2*CONFIG_SYS_HZ) /* Timeout for Flash Write */
-
-#endif /* __CONFIG_H */
diff --git a/include/configs/integratorap.h b/include/configs/integratorap.h
index 61b8761..a1fdbb8 100644
--- a/include/configs/integratorap.h
+++ b/include/configs/integratorap.h
@@ -37,6 +37,7 @@
* High Level Configuration Options
* (easy to change)
*/
+#define CONFIG_SYS_TEXT_BASE 0x01000000
#define CONFIG_SYS_MEMTEST_START 0x100000
#define CONFIG_SYS_MEMTEST_END 0x10000000
#define CONFIG_SYS_HZ 1000
diff --git a/include/configs/integratorcp.h b/include/configs/integratorcp.h
index 7ae34b7..ccbdf44 100644
--- a/include/configs/integratorcp.h
+++ b/include/configs/integratorcp.h
@@ -37,6 +37,7 @@
* High Level Configuration Options
* (easy to change)
*/
+#define CONFIG_SYS_TEXT_BASE 0x01000000
#define CONFIG_SYS_MEMTEST_START 0x100000
#define CONFIG_SYS_MEMTEST_END 0x10000000
#define CONFIG_SYS_HZ 1000
diff --git a/include/configs/m28evk.h b/include/configs/m28evk.h
new file mode 100644
index 0000000..d4bd207
--- /dev/null
+++ b/include/configs/m28evk.h
@@ -0,0 +1,303 @@
+/*
+ * Copyright (C) 2011 Marek Vasut <marek.vasut@gmail.com>
+ * on behalf of DENX Software Engineering GmbH
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+#ifndef __M28_H__
+#define __M28_H__
+
+#include <asm/arch/regs-base.h>
+
+/*
+ * SoC configurations
+ */
+#define CONFIG_MX28 /* i.MX28 SoC */
+#define CONFIG_MXS_GPIO /* GPIO control */
+#define CONFIG_SYS_HZ 1000 /* Ticks per second */
+
+/*
+ * Define M28EVK machine type by hand until it lands in mach-types
+ */
+#define MACH_TYPE_M28EVK 3613
+
+#define CONFIG_MACH_TYPE MACH_TYPE_M28EVK
+
+#define CONFIG_SYS_NO_FLASH
+#define CONFIG_SYS_ICACHE_OFF
+#define CONFIG_SYS_DCACHE_OFF
+#define CONFIG_BOARD_EARLY_INIT_F
+#define CONFIG_ARCH_CPU_INIT
+#define CONFIG_ARCH_MISC_INIT
+
+/*
+ * SPL
+ */
+#define CONFIG_SPL
+#define CONFIG_SPL_NO_CPU_SUPPORT_CODE
+#define CONFIG_SPL_START_S_PATH "board/denx/m28evk"
+#define CONFIG_SPL_LDSCRIPT "board/denx/m28evk/u-boot-spl.lds"
+
+/*
+ * U-Boot Commands
+ */
+#include <config_cmd_default.h>
+#define CONFIG_DISPLAY_CPUINFO
+#define CONFIG_DOS_PARTITION
+
+#define CONFIG_CMD_CACHE
+#define CONFIG_CMD_DATE
+#define CONFIG_CMD_DHCP
+#define CONFIG_CMD_EEPROM
+#define CONFIG_CMD_EXT2
+#define CONFIG_CMD_FAT
+#define CONFIG_CMD_GPIO
+#define CONFIG_CMD_I2C
+#define CONFIG_CMD_MII
+#define CONFIG_CMD_MMC
+#define CONFIG_CMD_NAND
+#define CONFIG_CMD_NET
+#define CONFIG_CMD_NFS
+#define CONFIG_CMD_PING
+#define CONFIG_CMD_SETEXPR
+#define CONFIG_CMD_SF
+#define CONFIG_CMD_SPI
+#define CONFIG_CMD_USB
+
+/*
+ * Memory configurations
+ */
+#define CONFIG_NR_DRAM_BANKS 1 /* 1 bank of DRAM */
+#define PHYS_SDRAM_1 0x40000000 /* Base address */
+#define PHYS_SDRAM_1_SIZE 0x40000000 /* Max 1 GB RAM */
+#define CONFIG_STACKSIZE 0x00010000 /* 128 KB stack */
+#define CONFIG_SYS_MALLOC_LEN 0x00400000 /* 4 MB for malloc */
+#define CONFIG_SYS_GBL_DATA_SIZE 128 /* Initial data */
+#define CONFIG_SYS_MEMTEST_START 0x40000000 /* Memtest start adr */
+#define CONFIG_SYS_MEMTEST_END 0x40400000 /* 4 MB RAM test */
+#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1
+/* Point initial SP in SRAM so SPL can use it too. */
+#define CONFIG_SYS_INIT_SP_ADDR 0x00002000
+/*
+ * We need to sacrifice first 4 bytes of RAM here to avoid triggering some
+ * strange BUG in ROM corrupting first 4 bytes of RAM when loading U-Boot
+ * binary. In case there was more of this mess, 0x100 bytes are skipped.
+ */
+#define CONFIG_SYS_TEXT_BASE 0x40000100
+
+/*
+ * U-Boot general configurations
+ */
+#define CONFIG_SYS_LONGHELP
+#define CONFIG_SYS_PROMPT "=> "
+#define CONFIG_SYS_CBSIZE 1024 /* Console I/O buffer size */
+#define CONFIG_SYS_PBSIZE \
+ (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16)
+ /* Print buffer size */
+#define CONFIG_SYS_MAXARGS 32 /* Max number of command args */
+#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE
+ /* Boot argument buffer size */
+#define CONFIG_VERSION_VARIABLE /* U-BOOT version */
+#define CONFIG_AUTO_COMPLETE /* Command auto complete */
+#define CONFIG_CMDLINE_EDITING /* Command history etc */
+#define CONFIG_SYS_HUSH_PARSER
+#define CONFIG_SYS_PROMPT_HUSH_PS2 "> "
+
+/*
+ * Serial Driver
+ */
+#define CONFIG_PL011_SERIAL
+#define CONFIG_PL011_CLOCK 24000000
+#define CONFIG_PL01x_PORTS { (void *)MXS_UARTDBG_BASE }
+#define CONFIG_CONS_INDEX 0
+#define CONFIG_BAUDRATE 115200 /* Default baud rate */
+#define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 }
+
+/*
+ * MMC Driver
+ */
+#ifdef CONFIG_CMD_MMC
+#define CONFIG_MMC
+#define CONFIG_GENERIC_MMC
+#define CONFIG_MXS_MMC
+#endif
+
+/*
+ * NAND
+ */
+#ifdef CONFIG_CMD_NAND
+#define CONFIG_NAND_MXS
+#define CONFIG_APBH_DMA
+#define CONFIG_SYS_MAX_NAND_DEVICE 1
+#define CONFIG_SYS_NAND_BASE 0x60000000
+#define CONFIG_SYS_NAND_5_ADDR_CYCLE
+#define NAND_MAX_CHIPS 8
+
+/* Environment is in NAND */
+#define CONFIG_ENV_IS_IN_NAND
+#define CONFIG_ENV_SIZE (16 * 1024)
+#define CONFIG_ENV_SIZE_REDUND CONFIG_ENV_SIZE
+#define CONFIG_ENV_SECT_SIZE (128 * 1024)
+#define CONFIG_ENV_RANGE (512 * 1024)
+#define CONFIG_ENV_OFFSET 0x300000
+#define CONFIG_ENV_OFFSET_REDUND \
+ (CONFIG_ENV_OFFSET + CONFIG_ENV_RANGE)
+
+#define CONFIG_CMD_UBI
+#define CONFIG_CMD_UBIFS
+#define CONFIG_CMD_MTDPARTS
+#define CONFIG_RBTREE
+#define CONFIG_LZO
+#define CONFIG_MTD_DEVICE
+#define CONFIG_MTD_PARTITIONS
+#define MTDIDS_DEFAULT "nand0=gpmi-nand.0"
+#define MTDPARTS_DEFAULT \
+ "mtdparts=gpmi-nand.0:" \
+ "3m(bootloader)ro," \
+ "512k(environment)," \
+ "512k(redundant-environment)," \
+ "4m(kernel)," \
+ "-(filesystem)"
+#endif
+
+/*
+ * Ethernet on SOC (FEC)
+ */
+#ifdef CONFIG_CMD_NET
+#define CONFIG_NET_MULTI
+#define CONFIG_ETHPRIME "FEC0"
+#define CONFIG_FEC_MXC
+#define CONFIG_FEC_MXC_MULTI
+#define CONFIG_MII
+#define CONFIG_DISCOVER_PHY
+#define CONFIG_FEC_XCV_TYPE RMII
+#endif
+
+/*
+ * I2C
+ */
+#ifdef CONFIG_CMD_I2C
+#define CONFIG_I2C_MXS
+#define CONFIG_HARD_I2C
+#define CONFIG_SYS_I2C_SPEED 400000
+#endif
+
+/*
+ * EEPROM
+ */
+#ifdef CONFIG_CMD_EEPROM
+#define CONFIG_SYS_I2C_MULTI_EEPROMS
+#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2
+#endif
+
+/*
+ * RTC
+ */
+#ifdef CONFIG_CMD_DATE
+/* Use the internal RTC in the MXS chip */
+#define CONFIG_RTC_INTERNAL
+#ifdef CONFIG_RTC_INTERNAL
+#define CONFIG_RTC_MXS
+#else
+#define CONFIG_RTC_M41T62
+#define CONFIG_SYS_I2C_RTC_ADDR 0x68
+#define CONFIG_SYS_M41T11_BASE_YEAR 2000
+#endif
+#endif
+
+/*
+ * USB
+ */
+#ifdef CONFIG_CMD_USB
+#define CONFIG_USB_EHCI
+#define CONFIG_USB_EHCI_MXS
+#define CONFIG_EHCI_MXS_PORT 1
+#define CONFIG_EHCI_IS_TDI
+#define CONFIG_USB_STORAGE
+#endif
+
+/*
+ * SPI
+ */
+#ifdef CONFIG_CMD_SPI
+#define CONFIG_HARD_SPI
+#define CONFIG_MXS_SPI
+#define CONFIG_SPI_HALF_DUPLEX
+#define CONFIG_DEFAULT_SPI_BUS 2
+#define CONFIG_DEFAULT_SPI_MODE SPI_MODE_0
+
+/* SPI FLASH */
+#ifdef CONFIG_CMD_SF
+#define CONFIG_SPI_FLASH
+#define CONFIG_SPI_FLASH_STMICRO
+#define CONFIG_SPI_FLASH_CS 2
+#define CONFIG_SF_DEFAULT_MODE SPI_MODE_0
+#define CONFIG_SF_DEFAULT_SPEED 24000000
+
+#define CONFIG_ENV_SPI_CS 0
+#define CONFIG_ENV_SPI_BUS 2
+#define CONFIG_ENV_SPI_MAX_HZ 24000000
+#define CONFIG_ENV_SPI_MODE SPI_MODE_0
+#endif
+#endif
+
+/*
+ * Boot Linux
+ */
+#define CONFIG_CMDLINE_TAG
+#define CONFIG_SETUP_MEMORY_TAGS
+#define CONFIG_BOOTDELAY 3
+#define CONFIG_BOOTFILE "uImage"
+#define CONFIG_BOOTARGS "console=ttyAM0,115200n8 "
+#define CONFIG_BOOTCOMMAND "run bootcmd_net"
+#define CONFIG_LOADADDR 0x42000000
+#define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR
+
+/*
+ * Extra Environments
+ */
+#define CONFIG_EXTRA_ENV_SETTINGS \
+ "update_nand_full_filename=u-boot.nand\0" \
+ "update_nand_firmware_filename=u-boot.sb\0" \
+ "update_nand_firmware_maxsz=0x100000\0" \
+ "update_nand_stride=0x40\0" /* MX28 datasheet ch. 12.12 */ \
+ "update_nand_count=0x4\0" /* MX28 datasheet ch. 12.12 */ \
+ "update_nand_get_fcb_size=" /* Get size of FCB blocks */ \
+ "nand device 0 ; " \
+ "nand info ; " \
+ "setexpr fcb_sz ${update_nand_stride} * ${update_nand_count};" \
+ "setexpr update_nand_fcb ${fcb_sz} * ${nand_writesize}\0" \
+ "update_nand_full=" /* Update FCB, DBBT and FW */ \
+ "if tftp ${update_nand_full_filename} ; then " \
+ "run update_nand_get_fcb_size ; " \
+ "nand scrub -y 0x0 ${filesize} ; " \
+ "nand write.raw ${loadaddr} 0x0 ${update_nand_fcb} ; " \
+ "setexpr update_off ${loadaddr} + ${update_nand_fcb} ; " \
+ "setexpr update_sz ${filesize} - ${update_nand_fcb} ; " \
+ "nand write ${update_off} ${update_nand_fcb} ${update_sz} ; " \
+ "fi\0" \
+ "update_nand_firmware=" /* Update only firmware */ \
+ "if tftp ${update_nand_firmware_filename} ; then " \
+ "run update_nand_get_fcb_size ; " \
+ "setexpr fcb_sz ${update_nand_fcb} * 2 ; " /* FCB + DBBT */ \
+ "setexpr fw_sz ${update_nand_firmware_maxsz} * 2 ; " \
+ "setexpr fw_off ${fcb_sz} + ${update_nand_firmware_maxsz};" \
+ "nand erase ${fcb_sz} ${fw_sz} ; " \
+ "nand write ${loadaddr} ${fcb_sz} ${filesize} ; " \
+ "nand write ${loadaddr} ${fw_off} ${filesize} ; " \
+ "fi\0"
+
+#endif /* __M28_H__ */
diff --git a/include/configs/nios2-generic.h b/include/configs/nios2-generic.h
index 1395939..9ba35e8 100644
--- a/include/configs/nios2-generic.h
+++ b/include/configs/nios2-generic.h
@@ -63,6 +63,10 @@
/*
* STATUS LED
*/
+#define CONFIG_ALTERA_PIO
+#define CONFIG_SYS_ALTERA_PIO_NUM 1
+#define CONFIG_SYS_ALTERA_PIO_GPIO_NUM LED_PIO_WIDTH
+
#define CONFIG_STATUS_LED /* Enable status driver */
#define CONFIG_GPIO_LED /* Enable GPIO LED driver */
#define CONFIG_GPIO /* Enable GPIO driver */
diff --git a/include/configs/omap3_beagle.h b/include/configs/omap3_beagle.h
index ebb572e..15e40c5 100644
--- a/include/configs/omap3_beagle.h
+++ b/include/configs/omap3_beagle.h
@@ -215,7 +215,7 @@
"rdaddr=0x81000000\0" \
"usbtty=cdc_acm\0" \
"bootfile=uImage.beagle\0" \
- "console=ttyS2,115200n8\0" \
+ "console=tty02,115200n8\0" \
"mpurate=auto\0" \
"buddy=none "\
"optargs=\0" \
diff --git a/include/configs/omap4_common.h b/include/configs/omap4_common.h
index f535769..42a8f10 100644
--- a/include/configs/omap4_common.h
+++ b/include/configs/omap4_common.h
@@ -39,7 +39,7 @@
/* Get CPU defs */
#include <asm/arch/cpu.h>
-#include <asm/arch/omap4.h>
+#include <asm/arch/omap.h>
/* Display CPU and Board Info */
#define CONFIG_DISPLAY_CPUINFO 1
@@ -122,6 +122,9 @@
/* Flash */
#define CONFIG_SYS_NO_FLASH 1
+/* clocks */
+#define CONFIG_SYS_CLOCKS_ENABLE_ALL
+
/* commands to include */
#include <config_cmd_default.h>
@@ -278,4 +281,6 @@
#define CONFIG_SPL_SERIAL_SUPPORT
#define CONFIG_SPL_LDSCRIPT "arch/arm/cpu/armv7/omap-common/u-boot-spl.lds"
+#define CONFIG_SYS_ENABLE_PADS_ALL
+
#endif /* __CONFIG_OMAP4_COMMON_H */
diff --git a/include/configs/omap5_evm.h b/include/configs/omap5_evm.h
new file mode 100644
index 0000000..b763f01
--- /dev/null
+++ b/include/configs/omap5_evm.h
@@ -0,0 +1,284 @@
+/*
+ * (C) Copyright 2010
+ * Texas Instruments Incorporated.
+ * Sricharan R <r.sricharan@ti.com>
+ *
+ * Derived from OMAP4 done by:
+ * Aneesh V <aneesh@ti.com>
+ *
+ * Configuration settings for the TI EVM5430 board.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+/*
+ * High Level Configuration Options
+ */
+#define CONFIG_ARMV7 /* This is an ARM V7 CPU core */
+#define CONFIG_OMAP /* in a TI OMAP core */
+#define CONFIG_OMAP54XX /* which is a 54XX */
+#define CONFIG_OMAP5430 /* which is in a 5430 */
+#define CONFIG_5430EVM /* working with EVM */
+#define CONFIG_ARCH_CPU_INIT
+
+/* Get CPU defs */
+#include <asm/arch/cpu.h>
+#include <asm/arch/omap.h>
+
+/* Display CPU and Board Info */
+#define CONFIG_DISPLAY_CPUINFO
+#define CONFIG_DISPLAY_BOARDINFO
+
+/* Clock Defines */
+#define V_OSCK 38400000 /* Clock output from T2 */
+#define V_SCLK V_OSCK
+
+#undef CONFIG_USE_IRQ /* no support for IRQs */
+#define CONFIG_MISC_INIT_R
+
+#define CONFIG_OF_LIBFDT
+
+#define CONFIG_CMDLINE_TAG /* enable passing of ATAGs */
+#define CONFIG_SETUP_MEMORY_TAGS
+#define CONFIG_INITRD_TAG
+
+/*
+ * Size of malloc() pool
+ * Total Size Environment - 128k
+ * Malloc - add 256k
+ */
+#define CONFIG_ENV_SIZE (128 << 10)
+#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + (256 << 10))
+/* Vector Base */
+#define CONFIG_SYS_CA9_VECTOR_BASE SRAM_ROM_VECT_BASE
+
+/*
+ * Hardware drivers
+ */
+
+/*
+ * serial port - NS16550 compatible
+ */
+#define V_NS16550_CLK 48000000
+
+#define CONFIG_SYS_NS16550
+#define CONFIG_SYS_NS16550_SERIAL
+#define CONFIG_SYS_NS16550_REG_SIZE (-4)
+#define CONFIG_SYS_NS16550_CLK V_NS16550_CLK
+#define CONFIG_CONS_INDEX 3
+#define CONFIG_SYS_NS16550_COM3 UART3_BASE
+
+#define CONFIG_BAUDRATE 115200
+#define CONFIG_SYS_BAUDRATE_TABLE {4800, 9600, 19200, 38400, 57600,\
+ 115200}
+/* I2C */
+#define CONFIG_HARD_I2C
+#define CONFIG_SYS_I2C_SPEED 100000
+#define CONFIG_SYS_I2C_SLAVE 1
+#define CONFIG_DRIVER_OMAP34XX_I2C
+#define CONFIG_I2C_MULTI_BUS
+
+/* TWL6030 */
+#define CONFIG_TWL6030_POWER
+#define CONFIG_CMD_BAT
+
+/* MMC */
+#define CONFIG_GENERIC_MMC
+#define CONFIG_MMC
+#define CONFIG_OMAP_HSMMC
+#define CONFIG_DOS_PARTITION
+
+/* MMC ENV related defines */
+#define CONFIG_ENV_IS_IN_MMC
+#define CONFIG_SYS_MMC_ENV_DEV 1 /* SLOT2: eMMC(1) */
+#define CONFIG_ENV_OFFSET 0xE0000
+
+/* USB */
+#define CONFIG_MUSB_UDC
+#define CONFIG_USB_OMAP3
+
+/* USB device configuration */
+#define CONFIG_USB_DEVICE
+#define CONFIG_USB_TTY
+#define CONFIG_SYS_CONSOLE_IS_IN_ENV
+
+/* Flash */
+#define CONFIG_SYS_NO_FLASH
+
+/* Cache */
+#define CONFIG_SYS_CACHELINE_SIZE 64
+#define CONFIG_SYS_CACHELINE_SHIFT 6
+
+/* commands to include */
+#include <config_cmd_default.h>
+
+/* Enabled commands */
+#define CONFIG_CMD_EXT2 /* EXT2 Support */
+#define CONFIG_CMD_FAT /* FAT support */
+#define CONFIG_CMD_I2C /* I2C serial bus support */
+#define CONFIG_CMD_MMC /* MMC support */
+#define CONFIG_CMD_SAVEENV
+
+/* Disabled commands */
+#undef CONFIG_CMD_NET
+#undef CONFIG_CMD_NFS
+#undef CONFIG_CMD_FPGA /* FPGA configuration Support */
+#undef CONFIG_CMD_IMLS /* List all found images */
+
+/*
+ * Environment setup
+ */
+
+#define CONFIG_BOOTDELAY 3
+
+#define CONFIG_ENV_OVERWRITE
+
+#define CONFIG_EXTRA_ENV_SETTINGS \
+ "loadaddr=0x82000000\0" \
+ "console=ttyS2,115200n8\0" \
+ "usbtty=cdc_acm\0" \
+ "vram=16M\0" \
+ "mmcdev=0\0" \
+ "mmcroot=/dev/mmcblk0p2 rw\0" \
+ "mmcrootfstype=ext3 rootwait\0" \
+ "mmcargs=setenv bootargs console=${console} " \
+ "vram=${vram} " \
+ "root=${mmcroot} " \
+ "rootfstype=${mmcrootfstype}\0" \
+ "loadbootscript=fatload mmc ${mmcdev} ${loadaddr} boot.scr\0" \
+ "bootscript=echo Running bootscript from mmc${mmcdev} ...; " \
+ "source ${loadaddr}\0" \
+ "loaduimage=fatload mmc ${mmcdev} ${loadaddr} uImage\0" \
+ "mmcboot=echo Booting from mmc${mmcdev} ...; " \
+ "run mmcargs; " \
+ "bootm ${loadaddr}\0" \
+
+#define CONFIG_BOOTCOMMAND \
+ "if mmc rescan ${mmcdev}; then " \
+ "if run loadbootscript; then " \
+ "run bootscript; " \
+ "else " \
+ "if run loaduimage; then " \
+ "run mmcboot; " \
+ "fi; " \
+ "fi; " \
+ "fi"
+
+#define CONFIG_AUTO_COMPLETE 1
+
+/*
+ * Miscellaneous configurable options
+ */
+
+#define CONFIG_SYS_LONGHELP /* undef to save memory */
+#define CONFIG_SYS_HUSH_PARSER /* use "hush" command parser */
+#define CONFIG_SYS_PROMPT_HUSH_PS2 "> "
+#define CONFIG_SYS_PROMPT "OMAP5430 EVM # "
+#define CONFIG_SYS_CBSIZE 256
+/* Print Buffer Size */
+#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + \
+ sizeof(CONFIG_SYS_PROMPT) + 16)
+#define CONFIG_SYS_MAXARGS 16
+/* Boot Argument Buffer Size */
+#define CONFIG_SYS_BARGSIZE (CONFIG_SYS_CBSIZE)
+
+/*
+ * memtest setup
+ */
+#define CONFIG_SYS_MEMTEST_START 0x80000000
+#define CONFIG_SYS_MEMTEST_END (CONFIG_SYS_MEMTEST_START + (32 << 20))
+
+/* Default load address */
+#define CONFIG_SYS_LOAD_ADDR 0x80000000
+
+/* Use General purpose timer 1 */
+#define CONFIG_SYS_TIMERBASE GPT2_BASE
+#define CONFIG_SYS_PTV 2 /* Divisor: 2^(PTV+1) => 8 */
+#define CONFIG_SYS_HZ 1000
+
+/*
+ * Stack sizes
+ *
+ * The stack sizes are set up in start.S using the settings below
+ */
+#define CONFIG_STACKSIZE (128 << 10) /* Regular stack */
+#ifdef CONFIG_USE_IRQ
+#define CONFIG_STACKSIZE_IRQ (4 << 10) /* IRQ stack */
+#define CONFIG_STACKSIZE_FIQ (4 << 10) /* FIQ stack */
+#endif
+
+/*
+ * SDRAM Memory Map
+ * Even though we use two CS all the memory
+ * is mapped to one contiguous block
+ */
+#define CONFIG_NR_DRAM_BANKS 1
+
+#define CONFIG_SYS_SDRAM_BASE 0x80000000
+#define CONFIG_SYS_INIT_RAM_ADDR 0x4030D800
+#define CONFIG_SYS_INIT_RAM_SIZE 0x800
+#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_INIT_RAM_ADDR + \
+ CONFIG_SYS_INIT_RAM_SIZE - \
+ GENERATED_GBL_DATA_SIZE)
+
+#define CONFIG_SYS_EMIF_PRECALCULATED_TIMING_REGS
+
+/* Defines for SDRAM init */
+#ifndef CONFIG_SYS_EMIF_PRECALCULATED_TIMING_REGS
+#define CONFIG_SYS_AUTOMATIC_SDRAM_DETECTION
+#define CONFIG_SYS_DEFAULT_LPDDR2_TIMINGS
+#endif
+
+/* Defines for SPL */
+#define CONFIG_SPL
+#define CONFIG_SPL_TEXT_BASE 0x40304350
+#define CONFIG_SPL_MAX_SIZE 0x1E000 /* 120K */
+#define CONFIG_SPL_STACK LOW_LEVEL_SRAM_STACK
+
+#define CONFIG_SPL_BSS_START_ADDR 0x80000000
+#define CONFIG_SPL_BSS_MAX_SIZE 0x80000 /* 512 KB */
+
+#define CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR 0x300 /* address 0x60000 */
+#define CONFIG_SYS_U_BOOT_MAX_SIZE_SECTORS 0x200 /* 256 KB */
+#define CONFIG_SYS_MMC_SD_FAT_BOOT_PARTITION 1
+#define CONFIG_SPL_FAT_LOAD_PAYLOAD_NAME "u-boot.img"
+
+#define CONFIG_SPL_LIBCOMMON_SUPPORT
+#define CONFIG_SPL_LIBDISK_SUPPORT
+#define CONFIG_SPL_I2C_SUPPORT
+#define CONFIG_SPL_MMC_SUPPORT
+#define CONFIG_SPL_FAT_SUPPORT
+#define CONFIG_SPL_LIBGENERIC_SUPPORT
+#define CONFIG_SPL_SERIAL_SUPPORT
+#define CONFIG_SPL_LDSCRIPT "arch/arm/cpu/armv7/omap-common/u-boot-spl.lds"
+
+/*
+ * 1MB into the SDRAM to allow for SPL's bss at the beginning of SDRAM
+ * 64 bytes before this address should be set aside for u-boot.img's
+ * header. That is 0x800FFFC0--0x80100000 should not be used for any
+ * other needs.
+ */
+#define CONFIG_SYS_TEXT_BASE 0x80100000
+#define CONFIG_SYS_SPL_MALLOC_START 0x80200000
+#define CONFIG_SYS_SPL_MALLOC_SIZE 0x100000 /* 1 MB */
+
+#endif /* __CONFIG_H */
diff --git a/include/configs/p1_p2_rdb_pc.h b/include/configs/p1_p2_rdb_pc.h
index bcfb034..5a69902 100644
--- a/include/configs/p1_p2_rdb_pc.h
+++ b/include/configs/p1_p2_rdb_pc.h
@@ -221,7 +221,7 @@
/* IN case of NAND bootloader relocate CCSRBAR in RAMboot code not in the 4k
SPL code*/
-#if defined(CONFIG_NAND_U_BOOT) && defined(CONFIG_NAND_SPL)
+#if defined(CONFIG_NAND_SPL)
#define CONFIG_SYS_CCSR_DO_NOT_RELOCATE
#endif
diff --git a/include/configs/pm9261.h b/include/configs/pm9261.h
index 89e17b8..55455e7 100644
--- a/include/configs/pm9261.h
+++ b/include/configs/pm9261.h
@@ -52,6 +52,9 @@
#undef CONFIG_USE_IRQ /* we don't need IRQ/FIQ stuff */
#define CONFIG_SYS_TEXT_BASE 0
+#define MACH_TYPE_PM9261 1187
+#define CONFIG_MACH_TYPE MACH_TYPE_PM9261
+
/* clocks */
/* CKGR_MOR - enable main osc. */
#define CONFIG_SYS_MOR_VAL \
diff --git a/include/configs/pm9263.h b/include/configs/pm9263.h
index 1f7543c..43104a3 100644
--- a/include/configs/pm9263.h
+++ b/include/configs/pm9263.h
@@ -52,6 +52,9 @@
#undef CONFIG_USE_IRQ /* we don't need IRQ/FIQ stuff */
#define CONFIG_SYS_TEXT_BASE 0
+#define MACH_TYPE_PM9263 1475
+#define CONFIG_MACH_TYPE MACH_TYPE_PM9263
+
/* clocks */
#define CONFIG_SYS_MOR_VAL \
(AT91_PMC_MOR_MOSCEN | \
diff --git a/include/configs/pm9g45.h b/include/configs/pm9g45.h
index acc1204..d3beaf3 100644
--- a/include/configs/pm9g45.h
+++ b/include/configs/pm9g45.h
@@ -41,6 +41,9 @@
#define CONFIG_PM9G45 1 /* It's an Ronetix PM9G45 */
#define CONFIG_SYS_AT91_CPU_NAME "AT91SAM9G45"
+#define MACH_TYPE_PM9G45 2672
+#define CONFIG_MACH_TYPE MACH_TYPE_PM9G45
+
/* ARM asynchronous clock */
#define CONFIG_SYS_AT91_MAIN_CLOCK 12000000 /* from 12 MHz crystal */
#define CONFIG_SYS_AT91_SLOW_CLOCK 32768 /* slow clock xtal */
diff --git a/include/configs/vpac270.h b/include/configs/vpac270.h
index 9db4d99..dd68c66 100644
--- a/include/configs/vpac270.h
+++ b/include/configs/vpac270.h
@@ -107,7 +107,8 @@
*/
#ifdef CONFIG_CMD_MMC
#define CONFIG_MMC
-#define CONFIG_PXA_MMC
+#define CONFIG_GENERIC_MMC
+#define CONFIG_PXA_MMC_GENERIC
#define CONFIG_SYS_MMC_BASE 0xF0000000
#define CONFIG_CMD_FAT
#define CONFIG_CMD_EXT2
diff --git a/include/dataflash.h b/include/dataflash.h
index 96ac097..056e18b 100644
--- a/include/dataflash.h
+++ b/include/dataflash.h
@@ -208,6 +208,8 @@
extern int addr_dataflash (unsigned long addr);
extern int read_dataflash (unsigned long addr, unsigned long size, char *result);
extern int write_dataflash (unsigned long addr, unsigned long dest, unsigned long size);
+extern int AT91F_DataflashInit(void);
+
extern void dataflash_print_info (void);
extern void dataflash_perror (int err);
extern void AT91F_DataflashSetEnv (void);
diff --git a/include/environment.h b/include/environment.h
index 6394a96..3c145af 100644
--- a/include/environment.h
+++ b/include/environment.h
@@ -38,21 +38,22 @@
*/
#if defined(CONFIG_ENV_IS_IN_FLASH)
-# ifndef CONFIG_ENV_ADDR
-# define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + CONFIG_ENV_OFFSET)
+# ifndef CONFIG_ENV_ADDR
+# define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + CONFIG_ENV_OFFSET)
# endif
-# ifndef CONFIG_ENV_OFFSET
-# define CONFIG_ENV_OFFSET (CONFIG_ENV_ADDR - CONFIG_SYS_FLASH_BASE)
+# ifndef CONFIG_ENV_OFFSET
+# define CONFIG_ENV_OFFSET (CONFIG_ENV_ADDR - CONFIG_SYS_FLASH_BASE)
# endif
# if !defined(CONFIG_ENV_ADDR_REDUND) && defined(CONFIG_ENV_OFFSET_REDUND)
-# define CONFIG_ENV_ADDR_REDUND (CONFIG_SYS_FLASH_BASE + CONFIG_ENV_OFFSET_REDUND)
+# define CONFIG_ENV_ADDR_REDUND \
+ (CONFIG_SYS_FLASH_BASE + CONFIG_ENV_OFFSET_REDUND)
# endif
# if defined(CONFIG_ENV_SECT_SIZE) || defined(CONFIG_ENV_SIZE)
-# ifndef CONFIG_ENV_SECT_SIZE
-# define CONFIG_ENV_SECT_SIZE CONFIG_ENV_SIZE
+# ifndef CONFIG_ENV_SECT_SIZE
+# define CONFIG_ENV_SECT_SIZE CONFIG_ENV_SIZE
# endif
-# ifndef CONFIG_ENV_SIZE
-# define CONFIG_ENV_SIZE CONFIG_ENV_SECT_SIZE
+# ifndef CONFIG_ENV_SIZE
+# define CONFIG_ENV_SIZE CONFIG_ENV_SECT_SIZE
# endif
# else
# error "Both CONFIG_ENV_SECT_SIZE and CONFIG_ENV_SIZE undefined"
@@ -60,8 +61,9 @@
# if defined(CONFIG_ENV_ADDR_REDUND) && !defined(CONFIG_ENV_SIZE_REDUND)
# define CONFIG_ENV_SIZE_REDUND CONFIG_ENV_SIZE
# endif
-# if (CONFIG_ENV_ADDR >= CONFIG_SYS_MONITOR_BASE) && \
- (CONFIG_ENV_ADDR+CONFIG_ENV_SIZE) <= (CONFIG_SYS_MONITOR_BASE + CONFIG_SYS_MONITOR_LEN)
+# if (CONFIG_ENV_ADDR >= CONFIG_SYS_MONITOR_BASE) && \
+ (CONFIG_ENV_ADDR + CONFIG_ENV_SIZE) <= \
+ (CONFIG_SYS_MONITOR_BASE + CONFIG_SYS_MONITOR_LEN)
# define ENV_IS_EMBEDDED 1
# endif
# if defined(CONFIG_ENV_ADDR_REDUND) || defined(CONFIG_ENV_OFFSET_REDUND)
@@ -105,10 +107,10 @@
/* Embedded env is only supported for some flash types */
#ifdef CONFIG_ENV_IS_EMBEDDED
-# if !defined(CONFIG_ENV_IS_IN_FLASH) && \
- !defined(CONFIG_ENV_IS_IN_NAND) && \
- !defined(CONFIG_ENV_IS_IN_ONENAND) && \
- !defined(CONFIG_ENV_IS_IN_SPI_FLASH)
+# if !defined(CONFIG_ENV_IS_IN_FLASH) && \
+ !defined(CONFIG_ENV_IS_IN_NAND) && \
+ !defined(CONFIG_ENV_IS_IN_ONENAND) && \
+ !defined(CONFIG_ENV_IS_IN_SPI_FLASH)
# error "CONFIG_ENV_IS_EMBEDDED not supported for your flash type"
# endif
#endif
@@ -141,10 +143,13 @@
# define ENV_HEADER_SIZE (sizeof(uint32_t))
#endif
+#if defined(CONFIG_CMD_SAVEENV) && !defined(CONFIG_ENV_IS_NOWHERE)
+extern char *env_name_spec;
+#endif
#define ENV_SIZE (CONFIG_ENV_SIZE - ENV_HEADER_SIZE)
-typedef struct environment_s {
+typedef struct environment_s {
uint32_t crc; /* CRC32 over data bytes */
#ifdef CONFIG_SYS_REDUNDAND_ENVIRONMENT
unsigned char flags; /* active/obsolete flags */
@@ -152,6 +157,20 @@
unsigned char data[ENV_SIZE]; /* Environment data */
} env_t;
+#ifdef ENV_IS_EMBEDDED
+extern env_t environment;
+#endif /* ENV_IS_EMBEDDED */
+
+extern const unsigned char default_environment[];
+extern env_t *env_ptr;
+
+extern void env_relocate_spec(void);
+extern unsigned char env_get_char_spec(int);
+
+#if defined(CONFIG_NEEDS_MANUAL_RELOC)
+extern void env_reloc(void);
+#endif
+
#ifndef DO_DEPS_ONLY
#include <search.h>
@@ -159,14 +178,14 @@
extern struct hsearch_data env_htab;
/* Function that returns a character from the environment */
-unsigned char env_get_char (int);
+unsigned char env_get_char(int);
/* Function that returns a pointer to a value from the environment */
const unsigned char *env_get_addr(int);
-unsigned char env_get_char_memory (int index);
+unsigned char env_get_char_memory(int index);
/* Function that updates CRC of the enironment */
-void env_crc_update (void);
+void env_crc_update(void);
/* [re]set to the default environment */
void set_default_env(const char *s);
@@ -174,6 +193,6 @@
/* Import from binary representation into hash table */
int env_import(const char *buf, int check);
-#endif
+#endif /* DO_DEPS_ONLY */
-#endif /* _ENVIRONMENT_H_ */
+#endif /* _ENVIRONMENT_H_ */
diff --git a/include/fdt_support.h b/include/fdt_support.h
index c7b4605..cef3c65 100644
--- a/include/fdt_support.h
+++ b/include/fdt_support.h
@@ -28,8 +28,8 @@
#include <fdt.h>
-u32 fdt_getprop_u32_default(void *fdt, const char *path, const char *prop,
- const u32 dflt);
+u32 fdt_getprop_u32_default(const void *fdt, const char *path,
+ const char *prop, const u32 dflt);
int fdt_chosen(void *fdt, int force);
int fdt_initrd(void *fdt, ulong initrd_start, ulong initrd_end, int force);
void do_fixup_by_path(void *fdt, const char *path, const char *prop,
diff --git a/include/image.h b/include/image.h
index c56a18d..6a41c2e 100644
--- a/include/image.h
+++ b/include/image.h
@@ -107,7 +107,7 @@
#define IH_ARCH_AVR32 17 /* AVR32 */
#define IH_ARCH_ST200 18 /* STMicroelectronics ST200 */
#define IH_ARCH_SANDBOX 19 /* Sandbox architecture (test only) */
-#define IH_ARCH_NDS32 19 /* ANDES Technology - NDS32 */
+#define IH_ARCH_NDS32 20 /* ANDES Technology - NDS32 */
/*
* Image Types
diff --git a/include/lcd.h b/include/lcd.h
index 89cc90c..83b50f4 100644
--- a/include/lcd.h
+++ b/include/lcd.h
@@ -210,6 +210,8 @@
void lcd_putc (const char c);
void lcd_puts (const char *s);
void lcd_printf (const char *fmt, ...);
+void lcd_clear(void);
+int lcd_display_bitmap(ulong bmp_image, int x, int y);
/* Allow boards to customize the information displayed */
void lcd_show_board_info(void);
diff --git a/include/onenand_uboot.h b/include/onenand_uboot.h
index 92279d5..f321d8a 100644
--- a/include/onenand_uboot.h
+++ b/include/onenand_uboot.h
@@ -52,4 +52,7 @@
extern void s3c64xx_onenand_init(struct mtd_info *);
extern void s3c64xx_set_width_regs(struct onenand_chip *);
+/* SPL */
+void onenand_spl_load_image(uint32_t offs, uint32_t size, void *dst);
+
#endif /* __UBOOT_ONENAND_H */
diff --git a/include/pca9698.h b/include/pca9698.h
index 2506088..67b364e 100644
--- a/include/pca9698.h
+++ b/include/pca9698.h
@@ -1,9 +1,34 @@
+/*
+ * (C) Copyright 2011
+ * Dirk Eibach, Guntermann & Drunck GmbH, eibach@gdsys.de
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
#ifndef __PCA9698_H_
#define __PCA9698_H_
-int pca9698_direction_input(u8 chip, unsigned offset);
-int pca9698_direction_output(u8 chip, unsigned offset);
-int pca9698_get_input(u8 chip, unsigned offset);
-int pca9698_set_output(u8 chip, unsigned offset, int value);
+int pca9698_request(unsigned gpio, const char *label);
+void pca9698_free(unsigned gpio);
+int pca9698_direction_input(u8 addr, unsigned gpio);
+int pca9698_direction_output(u8 addr, unsigned gpio, int value);
+int pca9698_get_value(u8 addr, unsigned gpio);
+int pca9698_set_value(u8 addr, unsigned gpio, int value);
#endif /* __PCA9698_H_ */
diff --git a/include/search.h b/include/search.h
index b4edd43..ef53edb 100644
--- a/include/search.h
+++ b/include/search.h
@@ -91,7 +91,8 @@
extern int hdelete_r(const char *__key, struct hsearch_data *__htab);
extern ssize_t hexport_r(struct hsearch_data *__htab,
- const char __sep, char **__resp, size_t __size);
+ const char __sep, char **__resp, size_t __size,
+ int argc, char * const argv[]);
extern int himport_r(struct hsearch_data *__htab,
const char *__env, size_t __size, const char __sep,
diff --git a/include/synopsys/dwcddr21mctl.h b/include/synopsys/dwcddr21mctl.h
new file mode 100644
index 0000000..a33b122
--- /dev/null
+++ b/include/synopsys/dwcddr21mctl.h
@@ -0,0 +1,337 @@
+/*
+ * (C) Copyright 2011 Andes Technology Corp
+ * Macpaul Lin <macpaul@andestech.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
+ */
+
+/*
+ * DWCDDR21MCTL - Synopsys DWC DDR2/DDR1 Memory Controller
+ */
+#ifndef __DWCDDR21MCTL_H
+#define __DWCDDR21MCTL_H
+
+#ifndef __ASSEMBLY__
+struct dwcddr21mctl {
+ unsigned int ccr; /* Controller Configuration */
+ unsigned int dcr; /* DRAM Configuration */
+ unsigned int iocr; /* I/O Configuration */
+ unsigned int csr; /* Controller Status */
+ unsigned int drr; /* DRAM refresh */
+ unsigned int tpr0; /* SDRAM Timing Parameters 0 */
+ unsigned int tpr1; /* SDRAM Timing Parameters 1 */
+ unsigned int tpr2; /* SDRAM Timing Parameters 2 */
+ unsigned int gdllcr; /* Global DLL Control */
+ unsigned int dllcr[10]; /* DLL Control */
+ unsigned int rslr[4]; /* Rank System Lantency */
+ unsigned int rdgr[4]; /* Rank DQS Gating */
+ unsigned int dqtr[9]; /* DQ Timing */
+ unsigned int dqstr; /* DQS Timing */
+ unsigned int dqsbtr; /* DQS_b Timing */
+ unsigned int odtcr; /* ODT Configuration */
+ unsigned int dtr[2]; /* Data Training */
+ unsigned int dtar; /* Data Training Address */
+ unsigned int rsved[82]; /* Reserved */
+ unsigned int mr; /* Mode Register */
+ unsigned int emr; /* Extended Mode Register */
+ unsigned int emr2; /* Extended Mode Register 2 */
+ unsigned int emr3; /* Extended Mode Register 3 */
+ unsigned int hpcr[32]; /* Host Port Configurarion */
+ unsigned int pqcr[8]; /* Priority Queue Configuration */
+ unsigned int mmgcr; /* Memory Manager General Config */
+};
+#endif /* __ASSEMBLY__ */
+
+/*
+ * Control Configuration Register
+ */
+#define DWCDDR21MCTL_CCR_ECCEN(x) ((x) << 0)
+#define DWCDDR21MCTL_CCR_NOMRWR(x) ((x) << 1)
+#define DWCDDR21MCTL_CCR_HOSTEN(x) ((x) << 2)
+#define DWCDDR21MCTL_CCR_XBISC(x) ((x) << 3)
+#define DWCDDR21MCTL_CCR_NOAPD(x) ((x) << 4)
+#define DWCDDR21MCTL_CCR_RRB(x) ((x) << 13)
+#define DWCDDR21MCTL_CCR_DQSCFG(x) ((x) << 14)
+#define DWCDDR21MCTL_CCR_DFTLM(x) (((x) & 0x3) << 15)
+#define DWCDDR21MCTL_CCR_DFTCMP(x) ((x) << 17)
+#define DWCDDR21MCTL_CCR_FLUSH(x) ((x) << 27)
+#define DWCDDR21MCTL_CCR_ITMRST(x) ((x) << 28)
+#define DWCDDR21MCTL_CCR_IB(x) ((x) << 29)
+#define DWCDDR21MCTL_CCR_DTT(x) ((x) << 30)
+#define DWCDDR21MCTL_CCR_IT(x) ((x) << 31)
+
+/*
+ * DRAM Configuration Register
+ */
+#define DWCDDR21MCTL_DCR_DDRMD(x) ((x) << 0)
+#define DWCDDR21MCTL_DCR_DIO(x) (((x) & 0x3) << 1)
+#define DWCDDR21MCTL_DCR_DSIZE(x) (((x) & 0x7) << 3)
+#define DWCDDR21MCTL_DCR_SIO(x) (((x) & 0x7) << 6)
+#define DWCDDR21MCTL_DCR_PIO(x) ((x) << 9)
+#define DWCDDR21MCTL_DCR_RANKS(x) (((x) & 0x3) << 10)
+#define DWCDDR21MCTL_DCR_RNKALL(x) ((x) << 12)
+#define DWCDDR21MCTL_DCR_AMAP(x) (((x) & 0x3) << 13)
+#define DWCDDR21MCTL_DCR_RANK(x) (((x) & 0x3) << 25)
+#define DWCDDR21MCTL_DCR_CMD(x) (((x) & 0xf) << 27)
+#define DWCDDR21MCTL_DCR_EXE(x) ((x) << 31)
+
+/*
+ * I/O Configuration Register
+ */
+#define DWCDDR21MCTL_IOCR_RTT(x) (((x) & 0xf) << 0)
+#define DWCDDR21MCTL_IOCR_DS(x) (((x) & 0xf) << 4)
+#define DWCDDR21MCTL_IOCR_TESTEN(x) ((x) << 0x8)
+#define DWCDDR21MCTL_IOCR_RTTOH(x) (((x) & 0x7) << 26)
+#define DWCDDR21MCTL_IOCR_RTTOE(x) ((x) << 29)
+#define DWCDDR21MCTL_IOCR_DQRTT(x) ((x) << 30)
+#define DWCDDR21MCTL_IOCR_DQSRTT(x) ((x) << 31)
+
+/*
+ * Controller Status Register
+ */
+#define DWCDDR21MCTL_CSR_DRIFT(x) (((x) & 0x3ff) << 0)
+#define DWCDDR21MCTL_CSR_DFTERR(x) ((x) << 18)
+#define DWCDDR21MCTL_CSR_ECCERR(x) ((x) << 19)
+#define DWCDDR21MCTL_CSR_DTERR(x) ((x) << 20)
+#define DWCDDR21MCTL_CSR_DTIERR(x) ((x) << 21)
+#define DWCDDR21MCTL_CSR_ECCSEC(x) ((x) << 22)
+
+/*
+ * DRAM Refresh Register
+ */
+#define DWCDDR21MCTL_DRR_TRFC(x) (((x) & 0xff) << 0)
+#define DWCDDR21MCTL_DRR_TRFPRD(x) (((x) & 0xffff) << 8)
+#define DWCDDR21MCTL_DRR_RFBURST(x) (((x) & 0xf) << 24)
+#define DWCDDR21MCTL_DRR_RD(x) ((x) << 31)
+
+/*
+ * SDRAM Timing Parameters Register 0
+ */
+#define DWCDDR21MCTL_TPR0_TMRD(x) (((x) & 0x3) << 0)
+#define DWCDDR21MCTL_TPR0_TRTP(x) (((x) & 0x7) << 2)
+#define DWCDDR21MCTL_TPR0_TWTR(x) (((x) & 0x7) << 5)
+#define DWCDDR21MCTL_TPR0_TRP(x) (((x) & 0xf) << 8)
+#define DWCDDR21MCTL_TPR0_TRCD(x) (((x) & 0xf) << 12)
+#define DWCDDR21MCTL_TPR0_TRAS(x) (((x) & 0x1f) << 16)
+#define DWCDDR21MCTL_TPR0_TRRD(x) (((x) & 0xf) << 21)
+#define DWCDDR21MCTL_TPR0_TRC(x) (((x) & 0x3f) << 25)
+#define DWCDDR21MCTL_TPR0_TCCD(x) ((x) << 31)
+
+/*
+ * SDRAM Timing Parameters Register 1
+ */
+#define DWCDDR21MCTL_TPR1_TAOND(x) (((x) & 0x3) << 0)
+#define DWCDDR21MCTL_TPR1_TRTW(x) ((x) << 2)
+#define DWCDDR21MCTL_TPR1_TFAW(x) (((x) & 0x3f) << 3)
+#define DWCDDR21MCTL_TPR1_TRNKRTR(x) (((x) & 0x3) << 12)
+#define DWCDDR21MCTL_TPR1_TRNKWTW(x) (((x) & 0x3) << 14)
+#define DWCDDR21MCTL_TPR1_XCL(x) (((x) & 0xf) << 23)
+#define DWCDDR21MCTL_TPR1_XWR(x) (((x) & 0xf) << 27)
+#define DWCDDR21MCTL_TPR1_XTP(x) ((x) << 31)
+
+/*
+ * SDRAM Timing Parameters Register 2
+ */
+#define DWCDDR21MCTL_TPR2_TXS(x) (((x) & 0x3ff) << 0)
+#define DWCDDR21MCTL_TPR2_TXP(x) (((x) & 0x1f) << 10)
+#define DWCDDR21MCTL_TPR2_TCKE(x) (((x) & 0xf) << 15)
+
+/*
+ * Global DLL Control Register
+ */
+#define DWCDDR21MCTL_GDLLCR_DRES(x) (((x) & 0x3) << 0)
+#define DWCDDR21MCTL_GDLLCR_IPUMP(x) (((x) & 0x7) << 2)
+#define DWCDDR21MCTL_GDLLCR_TESTEN(x) ((x) << 5)
+#define DWCDDR21MCTL_GDLLCR_DTC(x) (((x) & 0x7) << 6)
+#define DWCDDR21MCTL_GDLLCR_ATC(x) (((x) & 0x3) << 9)
+#define DWCDDR21MCTL_GDLLCR_TESTSW(x) ((x) << 11)
+#define DWCDDR21MCTL_GDLLCR_MBIAS(x) (((x) & 0xff) << 12)
+#define DWCDDR21MCTL_GDLLCR_SBIAS(x) (((x) & 0xff) << 20)
+#define DWCDDR21MCTL_GDLLCR_LOCKDET(x) ((x) << 29)
+
+/*
+ * DLL Control Register 0-9
+ */
+#define DWCDDR21MCTL_DLLCR_SFBDLY(x) (((x) & 0x7) << 0)
+#define DWCDDR21MCTL_DLLCR_SFWDLY(x) (((x) & 0x7) << 3)
+#define DWCDDR21MCTL_DLLCR_MFBDLY(x) (((x) & 0x7) << 6)
+#define DWCDDR21MCTL_DLLCR_MFWDLY(x) (((x) & 0x7) << 9)
+#define DWCDDR21MCTL_DLLCR_SSTART(x) (((x) & 0x3) << 12)
+#define DWCDDR21MCTL_DLLCR_PHASE(x) (((x) & 0xf) << 14)
+#define DWCDDR21MCTL_DLLCR_ATESTEN(x) ((x) << 18)
+#define DWCDDR21MCTL_DLLCR_DRSVD(x) ((x) << 19)
+#define DWCDDR21MCTL_DLLCR_DD(x) ((x) << 31)
+
+/*
+ * Rank System Lantency Register
+ */
+#define DWCDDR21MCTL_RSLR_SL0(x) (((x) & 0x7) << 0)
+#define DWCDDR21MCTL_RSLR_SL1(x) (((x) & 0x7) << 3)
+#define DWCDDR21MCTL_RSLR_SL2(x) (((x) & 0x7) << 6)
+#define DWCDDR21MCTL_RSLR_SL3(x) (((x) & 0x7) << 9)
+#define DWCDDR21MCTL_RSLR_SL4(x) (((x) & 0x7) << 12)
+#define DWCDDR21MCTL_RSLR_SL5(x) (((x) & 0x7) << 15)
+#define DWCDDR21MCTL_RSLR_SL6(x) (((x) & 0x7) << 18)
+#define DWCDDR21MCTL_RSLR_SL7(x) (((x) & 0x7) << 21)
+#define DWCDDR21MCTL_RSLR_SL8(x) (((x) & 0x7) << 24)
+
+/*
+ * Rank DQS Gating Register
+ */
+#define DWCDDR21MCTL_RDGR_DQSSEL0(x) (((x) & 0x3) << 0)
+#define DWCDDR21MCTL_RDGR_DQSSEL1(x) (((x) & 0x3) << 2)
+#define DWCDDR21MCTL_RDGR_DQSSEL2(x) (((x) & 0x3) << 4)
+#define DWCDDR21MCTL_RDGR_DQSSEL3(x) (((x) & 0x3) << 6)
+#define DWCDDR21MCTL_RDGR_DQSSEL4(x) (((x) & 0x3) << 8)
+#define DWCDDR21MCTL_RDGR_DQSSEL5(x) (((x) & 0x3) << 10)
+#define DWCDDR21MCTL_RDGR_DQSSEL6(x) (((x) & 0x3) << 12)
+#define DWCDDR21MCTL_RDGR_DQSSEL7(x) (((x) & 0x3) << 14)
+#define DWCDDR21MCTL_RDGR_DQSSEL8(x) (((x) & 0x3) << 16)
+
+/*
+ * DQ Timing Register
+ */
+#define DWCDDR21MCTL_DQTR_DQDLY0(x) (((x) & 0xf) << 0)
+#define DWCDDR21MCTL_DQTR_DQDLY1(x) (((x) & 0xf) << 4)
+#define DWCDDR21MCTL_DQTR_DQDLY2(x) (((x) & 0xf) << 8)
+#define DWCDDR21MCTL_DQTR_DQDLY3(x) (((x) & 0xf) << 12)
+#define DWCDDR21MCTL_DQTR_DQDLY4(x) (((x) & 0xf) << 16)
+#define DWCDDR21MCTL_DQTR_DQDLY5(x) (((x) & 0xf) << 20)
+#define DWCDDR21MCTL_DQTR_DQDLY6(x) (((x) & 0xf) << 24)
+#define DWCDDR21MCTL_DQTR_DQDLY7(x) (((x) & 0xf) << 28)
+
+/*
+ * DQS Timing Register
+ */
+#define DWCDDR21MCTL_DQSTR_DQSDLY0(x) (((x) & 0x7) << 0)
+#define DWCDDR21MCTL_DQSTR_DQSDLY1(x) (((x) & 0x7) << 3)
+#define DWCDDR21MCTL_DQSTR_DQSDLY2(x) (((x) & 0x7) << 6)
+#define DWCDDR21MCTL_DQSTR_DQSDLY3(x) (((x) & 0x7) << 9)
+#define DWCDDR21MCTL_DQSTR_DQSDLY4(x) (((x) & 0x7) << 12)
+#define DWCDDR21MCTL_DQSTR_DQSDLY5(x) (((x) & 0x7) << 15)
+#define DWCDDR21MCTL_DQSTR_DQSDLY6(x) (((x) & 0x7) << 18)
+#define DWCDDR21MCTL_DQSTR_DQSDLY7(x) (((x) & 0x7) << 21)
+#define DWCDDR21MCTL_DQSTR_DQSDLY8(x) (((x) & 0x7) << 24)
+
+/*
+ * DQS_b (DQSBTR) Timing Register
+ */
+#define DWCDDR21MCTL_DQSBTR_DQSDLY0(x) (((x) & 0x7) << 0)
+#define DWCDDR21MCTL_DQSBTR_DQSDLY1(x) (((x) & 0x7) << 3)
+#define DWCDDR21MCTL_DQSBTR_DQSDLY2(x) (((x) & 0x7) << 6)
+#define DWCDDR21MCTL_DQSBTR_DQSDLY3(x) (((x) & 0x7) << 9)
+#define DWCDDR21MCTL_DQSBTR_DQSDLY4(x) (((x) & 0x7) << 12)
+#define DWCDDR21MCTL_DQSBTR_DQSDLY5(x) (((x) & 0x7) << 15)
+#define DWCDDR21MCTL_DQSBTR_DQSDLY6(x) (((x) & 0x7) << 18)
+#define DWCDDR21MCTL_DQSBTR_DQSDLY7(x) (((x) & 0x7) << 21)
+#define DWCDDR21MCTL_DQSBTR_DQSDLY8(x) (((x) & 0x7) << 24)
+
+/*
+ * ODT Configuration Register
+ */
+#define DWCDDR21MCTL_ODTCR_RDODT0(x) (((x) & 0xf) << 0)
+#define DWCDDR21MCTL_ODTCR_RDODT1(x) (((x) & 0xf) << 4)
+#define DWCDDR21MCTL_ODTCR_RDODT2(x) (((x) & 0xf) << 8)
+#define DWCDDR21MCTL_ODTCR_RDODT3(x) (((x) & 0xf) << 12)
+#define DWCDDR21MCTL_ODTCR_WDODT0(x) (((x) & 0xf) << 16)
+#define DWCDDR21MCTL_ODTCR_WDODT1(x) (((x) & 0xf) << 20)
+#define DWCDDR21MCTL_ODTCR_WDODT2(x) (((x) & 0xf) << 24)
+#define DWCDDR21MCTL_ODTCR_WDODT3(x) (((x) & 0xf) << 28)
+
+/*
+ * Data Training Register
+ */
+#define DWCDDR21MCTL_DTR0_DTBYTE0(x) (((x) & 0xff) << 0) /* def: 0x11 */
+#define DWCDDR21MCTL_DTR0_DTBYTE1(x) (((x) & 0xff) << 8) /* def: 0xee */
+#define DWCDDR21MCTL_DTR0_DTBYTE2(x) (((x) & 0xff) << 16) /* def: 0x22 */
+#define DWCDDR21MCTL_DTR0_DTBYTE3(x) (((x) & 0xff) << 24) /* def: 0xdd */
+
+#define DWCDDR21MCTL_DTR1_DTBYTE4(x) (((x) & 0xff) << 0) /* def: 0x44 */
+#define DWCDDR21MCTL_DTR1_DTBYTE5(x) (((x) & 0xff) << 8) /* def: 0xbb */
+#define DWCDDR21MCTL_DTR1_DTBYTE6(x) (((x) & 0xff) << 16) /* def: 0x88 */
+#define DWCDDR21MCTL_DTR1_DTBYTE7(x) (((x) & 0xff) << 24) /* def: 0x77 */
+
+/*
+ * Data Training Address Register
+ */
+#define DWCDDR21MCTL_DTAR_DTCOL(x) (((x) & 0xfff) << 0)
+#define DWCDDR21MCTL_DTAR_DTROW(x) (((x) & 0xffff) << 12)
+#define DWCDDR21MCTL_DTAR_DTBANK(x) (((x) & 0x7) << 28)
+
+/*
+ * Mode Register
+ */
+#define DWCDDR21MCTL_MR_BL(x) (((x) & 0x7) << 0)
+#define DWCDDR21MCTL_MR_BT(x) ((x) << 3)
+#define DWCDDR21MCTL_MR_CL(x) (((x) & 0x7) << 4)
+#define DWCDDR21MCTL_MR_TM(x) ((x) << 7)
+#define DWCDDR21MCTL_MR_DR(x) ((x) << 8)
+#define DWCDDR21MCTL_MR_WR(x) (((x) & 0x7) << 9)
+#define DWCDDR21MCTL_MR_PD(x) ((x) << 12)
+
+/*
+ * Extended Mode register
+ */
+#define DWCDDR21MCTL_EMR_DE(x) ((x) << 0)
+#define DWCDDR21MCTL_EMR_ODS(x) ((x) << 1)
+#define DWCDDR21MCTL_EMR_RTT2(x) ((x) << 2)
+#define DWCDDR21MCTL_EMR_AL(x) (((x) & 0x7) << 3)
+#define DWCDDR21MCTL_EMR_RTT6(x) ((x) << 6)
+#define DWCDDR21MCTL_EMR_OCD(x) (((x) & 0x7) << 7)
+#define DWCDDR21MCTL_EMR_DQS(x) ((x) << 10)
+#define DWCDDR21MCTL_EMR_RDQS(x) ((x) << 11)
+#define DWCDDR21MCTL_EMR_OE(x) ((x) << 12)
+
+#define EMR_RTT2(x) DWCDDR21MCTL_EMR_RTT2(x)
+#define EMR_RTT6(x) DWCDDR21MCTL_EMR_RTT6(x)
+
+#define DWCDDR21MCTL_EMR_RTT_DISABLED (EMR_RTT6(0) | EMR_RTT2(0))
+#define DWCDDR21MCTL_EMR_RTT_75 (EMR_RTT6(0) | EMR_RTT2(1))
+#define DWCDDR21MCTL_EMR_RTT_150 (EMR_RTT6(1) | EMR_RTT2(0))
+#define DWCDDR21MCTL_EMR_RTT_50 (EMR_RTT6(1) | EMR_RTT2(1))
+
+/*
+ * Extended Mode register 2
+ */
+#define DWCDDR21MCTL_EMR2_PASR(x) (((x) & 0x7) << 0)
+#define DWCDDR21MCTL_EMR2_DCC(x) ((x) << 3)
+#define DWCDDR21MCTL_EMR2_SRF(x) ((x) << 7)
+
+/*
+ * Extended Mode register 3: [15:0] reserved for JEDEC.
+ */
+
+/*
+ * Host port Configuration register 0-31
+ */
+#define DWCDDR21MCTL_HPCR_HPBL(x) (((x) & 0xf) << 0)
+
+/*
+ * Priority Queue Configuration register 0-7
+ */
+#define DWCDDR21MCTL_HPCR_TOUT(x) (((x) & 0xf) << 0)
+#define DWCDDR21MCTL_HPCR_TOUTX(x) (((x) & 0x3) << 8)
+#define DWCDDR21MCTL_HPCR_LPQS(x) (((x) & 0x3) << 10)
+#define DWCDDR21MCTL_HPCR_PQBL(x) (((x) & 0xff) << 12)
+#define DWCDDR21MCTL_HPCR_SWAIT(x) (((x) & 0x1f) << 20)
+#define DWCDDR21MCTL_HPCR_INTRPT(x) (((x) & 0x7) << 25)
+#define DWCDDR21MCTL_HPCR_APQS(x) ((x) << 28)
+
+/*
+ * Memory Manager General Configuration register
+ */
+#define DWCDDR21MCTL_MMGCR_UHPP(x) (((x) & 0x3) << 0)
+
+#endif /* __DWCDDR21MCTL_H */
diff --git a/include/video_font.h b/include/video_font.h
index 706e185..47957c4 100644
--- a/include/video_font.h
+++ b/include/video_font.h
@@ -29,4616 +29,4 @@
#define VIDEO_FONT_HEIGHT 16
#define VIDEO_FONT_SIZE (VIDEO_FONT_CHARS * VIDEO_FONT_HEIGHT)
-static unsigned char video_fontdata[VIDEO_FONT_SIZE] = {
-
- /* 0 0x00 '^@' */
- 0x00, /* 00000000 */
- 0x00, /* 00000000 */
- 0x00, /* 00000000 */
- 0x00, /* 00000000 */
- 0x00, /* 00000000 */
- 0x00, /* 00000000 */
- 0x00, /* 00000000 */
- 0x00, /* 00000000 */
- 0x00, /* 00000000 */
- 0x00, /* 00000000 */
- 0x00, /* 00000000 */
- 0x00, /* 00000000 */
- 0x00, /* 00000000 */
- 0x00, /* 00000000 */
- 0x00, /* 00000000 */
- 0x00, /* 00000000 */
-
- /* 1 0x01 '^A' */
- 0x00, /* 00000000 */
- 0x00, /* 00000000 */
- 0x7e, /* 01111110 */
- 0x81, /* 10000001 */
- 0xa5, /* 10100101 */
- 0x81, /* 10000001 */
- 0x81, /* 10000001 */
- 0xbd, /* 10111101 */
- 0x99, /* 10011001 */
- 0x81, /* 10000001 */
- 0x81, /* 10000001 */
- 0x7e, /* 01111110 */
- 0x00, /* 00000000 */
- 0x00, /* 00000000 */
- 0x00, /* 00000000 */
- 0x00, /* 00000000 */
-
- /* 2 0x02 '^B' */
- 0x00, /* 00000000 */
- 0x00, /* 00000000 */
- 0x7e, /* 01111110 */
- 0xff, /* 11111111 */
- 0xdb, /* 11011011 */
- 0xff, /* 11111111 */
- 0xff, /* 11111111 */
- 0xc3, /* 11000011 */
- 0xe7, /* 11100111 */
- 0xff, /* 11111111 */
- 0xff, /* 11111111 */
- 0x7e, /* 01111110 */
- 0x00, /* 00000000 */
- 0x00, /* 00000000 */
- 0x00, /* 00000000 */
- 0x00, /* 00000000 */
-
- /* 3 0x03 '^C' */
- 0x00, /* 00000000 */
- 0x00, /* 00000000 */
- 0x00, /* 00000000 */
- 0x00, /* 00000000 */
- 0x6c, /* 01101100 */
- 0xfe, /* 11111110 */
- 0xfe, /* 11111110 */
- 0xfe, /* 11111110 */
- 0xfe, /* 11111110 */
- 0x7c, /* 01111100 */
- 0x38, /* 00111000 */
- 0x10, /* 00010000 */
- 0x00, /* 00000000 */
- 0x00, /* 00000000 */
- 0x00, /* 00000000 */
- 0x00, /* 00000000 */
-
- /* 4 0x04 '^D' */
- 0x00, /* 00000000 */
- 0x00, /* 00000000 */
- 0x00, /* 00000000 */
- 0x00, /* 00000000 */
- 0x10, /* 00010000 */
- 0x38, /* 00111000 */
- 0x7c, /* 01111100 */
- 0xfe, /* 11111110 */
- 0x7c, /* 01111100 */
- 0x38, /* 00111000 */
- 0x10, /* 00010000 */
- 0x00, /* 00000000 */
- 0x00, /* 00000000 */
- 0x00, /* 00000000 */
- 0x00, /* 00000000 */
- 0x00, /* 00000000 */
-
- /* 5 0x05 '^E' */
- 0x00, /* 00000000 */
- 0x00, /* 00000000 */
- 0x00, /* 00000000 */
- 0x18, /* 00011000 */
- 0x3c, /* 00111100 */
- 0x3c, /* 00111100 */
- 0xe7, /* 11100111 */
- 0xe7, /* 11100111 */
- 0xe7, /* 11100111 */
- 0x18, /* 00011000 */
- 0x18, /* 00011000 */
- 0x3c, /* 00111100 */
- 0x00, /* 00000000 */
- 0x00, /* 00000000 */
- 0x00, /* 00000000 */
- 0x00, /* 00000000 */
-
- /* 6 0x06 '^F' */
- 0x00, /* 00000000 */
- 0x00, /* 00000000 */
- 0x00, /* 00000000 */
- 0x18, /* 00011000 */
- 0x3c, /* 00111100 */
- 0x7e, /* 01111110 */
- 0xff, /* 11111111 */
- 0xff, /* 11111111 */
- 0x7e, /* 01111110 */
- 0x18, /* 00011000 */
- 0x18, /* 00011000 */
- 0x3c, /* 00111100 */
- 0x00, /* 00000000 */
- 0x00, /* 00000000 */
- 0x00, /* 00000000 */
- 0x00, /* 00000000 */
-
- /* 7 0x07 '^G' */
- 0x00, /* 00000000 */
- 0x00, /* 00000000 */
- 0x00, /* 00000000 */
- 0x00, /* 00000000 */
- 0x00, /* 00000000 */
- 0x00, /* 00000000 */
- 0x18, /* 00011000 */
- 0x3c, /* 00111100 */
- 0x3c, /* 00111100 */
- 0x18, /* 00011000 */
- 0x00, /* 00000000 */
- 0x00, /* 00000000 */
- 0x00, /* 00000000 */
- 0x00, /* 00000000 */
- 0x00, /* 00000000 */
- 0x00, /* 00000000 */
-
- /* 8 0x08 '^H' */
- 0xff, /* 11111111 */
- 0xff, /* 11111111 */
- 0xff, /* 11111111 */
- 0xff, /* 11111111 */
- 0xff, /* 11111111 */
- 0xff, /* 11111111 */
- 0xe7, /* 11100111 */
- 0xc3, /* 11000011 */
- 0xc3, /* 11000011 */
- 0xe7, /* 11100111 */
- 0xff, /* 11111111 */
- 0xff, /* 11111111 */
- 0xff, /* 11111111 */
- 0xff, /* 11111111 */
- 0xff, /* 11111111 */
- 0xff, /* 11111111 */
-
- /* 9 0x09 '^I' */
- 0x00, /* 00000000 */
- 0x00, /* 00000000 */
- 0x00, /* 00000000 */
- 0x00, /* 00000000 */
- 0x00, /* 00000000 */
- 0x3c, /* 00111100 */
- 0x66, /* 01100110 */
- 0x42, /* 01000010 */
- 0x42, /* 01000010 */
- 0x66, /* 01100110 */
- 0x3c, /* 00111100 */
- 0x00, /* 00000000 */
- 0x00, /* 00000000 */
- 0x00, /* 00000000 */
- 0x00, /* 00000000 */
- 0x00, /* 00000000 */
-
- /* 10 0x0a '^J' */
- 0xff, /* 11111111 */
- 0xff, /* 11111111 */
- 0xff, /* 11111111 */
- 0xff, /* 11111111 */
- 0xff, /* 11111111 */
- 0xc3, /* 11000011 */
- 0x99, /* 10011001 */
- 0xbd, /* 10111101 */
- 0xbd, /* 10111101 */
- 0x99, /* 10011001 */
- 0xc3, /* 11000011 */
- 0xff, /* 11111111 */
- 0xff, /* 11111111 */
- 0xff, /* 11111111 */
- 0xff, /* 11111111 */
- 0xff, /* 11111111 */
-
- /* 11 0x0b '^K' */
- 0x00, /* 00000000 */
- 0x00, /* 00000000 */
- 0x1e, /* 00011110 */
- 0x0e, /* 00001110 */
- 0x1a, /* 00011010 */
- 0x32, /* 00110010 */
- 0x78, /* 01111000 */
- 0xcc, /* 11001100 */
- 0xcc, /* 11001100 */
- 0xcc, /* 11001100 */
- 0xcc, /* 11001100 */
- 0x78, /* 01111000 */
- 0x00, /* 00000000 */
- 0x00, /* 00000000 */
- 0x00, /* 00000000 */
- 0x00, /* 00000000 */
-
- /* 12 0x0c '^L' */
- 0x00, /* 00000000 */
- 0x00, /* 00000000 */
- 0x3c, /* 00111100 */
- 0x66, /* 01100110 */
- 0x66, /* 01100110 */
- 0x66, /* 01100110 */
- 0x66, /* 01100110 */
- 0x3c, /* 00111100 */
- 0x18, /* 00011000 */
- 0x7e, /* 01111110 */
- 0x18, /* 00011000 */
- 0x18, /* 00011000 */
- 0x00, /* 00000000 */
- 0x00, /* 00000000 */
- 0x00, /* 00000000 */
- 0x00, /* 00000000 */
-
- /* 13 0x0d '^M' */
- 0x00, /* 00000000 */
- 0x00, /* 00000000 */
- 0x3f, /* 00111111 */
- 0x33, /* 00110011 */
- 0x3f, /* 00111111 */
- 0x30, /* 00110000 */
- 0x30, /* 00110000 */
- 0x30, /* 00110000 */
- 0x30, /* 00110000 */
- 0x70, /* 01110000 */
- 0xf0, /* 11110000 */
- 0xe0, /* 11100000 */
- 0x00, /* 00000000 */
- 0x00, /* 00000000 */
- 0x00, /* 00000000 */
- 0x00, /* 00000000 */
-
- /* 14 0x0e '^N' */
- 0x00, /* 00000000 */
- 0x00, /* 00000000 */
- 0x7f, /* 01111111 */
- 0x63, /* 01100011 */
- 0x7f, /* 01111111 */
- 0x63, /* 01100011 */
- 0x63, /* 01100011 */
- 0x63, /* 01100011 */
- 0x63, /* 01100011 */
- 0x67, /* 01100111 */
- 0xe7, /* 11100111 */
- 0xe6, /* 11100110 */
- 0xc0, /* 11000000 */
- 0x00, /* 00000000 */
- 0x00, /* 00000000 */
- 0x00, /* 00000000 */
-
- /* 15 0x0f '^O' */
- 0x00, /* 00000000 */
- 0x00, /* 00000000 */
- 0x00, /* 00000000 */
- 0x18, /* 00011000 */
- 0x18, /* 00011000 */
- 0xdb, /* 11011011 */
- 0x3c, /* 00111100 */
- 0xe7, /* 11100111 */
- 0x3c, /* 00111100 */
- 0xdb, /* 11011011 */
- 0x18, /* 00011000 */
- 0x18, /* 00011000 */
- 0x00, /* 00000000 */
- 0x00, /* 00000000 */
- 0x00, /* 00000000 */
- 0x00, /* 00000000 */
-
- /* 16 0x10 '^P' */
- 0x00, /* 00000000 */
- 0x80, /* 10000000 */
- 0xc0, /* 11000000 */
- 0xe0, /* 11100000 */
- 0xf0, /* 11110000 */
- 0xf8, /* 11111000 */
- 0xfe, /* 11111110 */
- 0xf8, /* 11111000 */
- 0xf0, /* 11110000 */
- 0xe0, /* 11100000 */
- 0xc0, /* 11000000 */
- 0x80, /* 10000000 */
- 0x00, /* 00000000 */
- 0x00, /* 00000000 */
- 0x00, /* 00000000 */
- 0x00, /* 00000000 */
-
- /* 17 0x11 '^Q' */
- 0x00, /* 00000000 */
- 0x02, /* 00000010 */
- 0x06, /* 00000110 */
- 0x0e, /* 00001110 */
- 0x1e, /* 00011110 */
- 0x3e, /* 00111110 */
- 0xfe, /* 11111110 */
- 0x3e, /* 00111110 */
- 0x1e, /* 00011110 */
- 0x0e, /* 00001110 */
- 0x06, /* 00000110 */
- 0x02, /* 00000010 */
- 0x00, /* 00000000 */
- 0x00, /* 00000000 */
- 0x00, /* 00000000 */
- 0x00, /* 00000000 */
-
- /* 18 0x12 '^R' */
- 0x00, /* 00000000 */
- 0x00, /* 00000000 */
- 0x18, /* 00011000 */
- 0x3c, /* 00111100 */
- 0x7e, /* 01111110 */
- 0x18, /* 00011000 */
- 0x18, /* 00011000 */
- 0x18, /* 00011000 */
- 0x7e, /* 01111110 */
- 0x3c, /* 00111100 */
- 0x18, /* 00011000 */
- 0x00, /* 00000000 */
- 0x00, /* 00000000 */
- 0x00, /* 00000000 */
- 0x00, /* 00000000 */
- 0x00, /* 00000000 */
-
- /* 19 0x13 '^S' */
- 0x00, /* 00000000 */
- 0x00, /* 00000000 */
- 0x66, /* 01100110 */
- 0x66, /* 01100110 */
- 0x66, /* 01100110 */
- 0x66, /* 01100110 */
- 0x66, /* 01100110 */
- 0x66, /* 01100110 */
- 0x66, /* 01100110 */
- 0x00, /* 00000000 */
- 0x66, /* 01100110 */
- 0x66, /* 01100110 */
- 0x00, /* 00000000 */
- 0x00, /* 00000000 */
- 0x00, /* 00000000 */
- 0x00, /* 00000000 */
-
- /* 20 0x14 '^T' */
- 0x00, /* 00000000 */
- 0x00, /* 00000000 */
- 0x7f, /* 01111111 */
- 0xdb, /* 11011011 */
- 0xdb, /* 11011011 */
- 0xdb, /* 11011011 */
- 0x7b, /* 01111011 */
- 0x1b, /* 00011011 */
- 0x1b, /* 00011011 */
- 0x1b, /* 00011011 */
- 0x1b, /* 00011011 */
- 0x1b, /* 00011011 */
- 0x00, /* 00000000 */
- 0x00, /* 00000000 */
- 0x00, /* 00000000 */
- 0x00, /* 00000000 */
-
- /* 21 0x15 '^U' */
- 0x00, /* 00000000 */
- 0x7c, /* 01111100 */
- 0xc6, /* 11000110 */
- 0x60, /* 01100000 */
- 0x38, /* 00111000 */
- 0x6c, /* 01101100 */
- 0xc6, /* 11000110 */
- 0xc6, /* 11000110 */
- 0x6c, /* 01101100 */
- 0x38, /* 00111000 */
- 0x0c, /* 00001100 */
- 0xc6, /* 11000110 */
- 0x7c, /* 01111100 */
- 0x00, /* 00000000 */
- 0x00, /* 00000000 */
- 0x00, /* 00000000 */
-
- /* 22 0x16 '^V' */
- 0x00, /* 00000000 */
- 0x00, /* 00000000 */
- 0x00, /* 00000000 */
- 0x00, /* 00000000 */
- 0x00, /* 00000000 */
- 0x00, /* 00000000 */
- 0x00, /* 00000000 */
- 0x00, /* 00000000 */
- 0xfe, /* 11111110 */
- 0xfe, /* 11111110 */
- 0xfe, /* 11111110 */
- 0xfe, /* 11111110 */
- 0x00, /* 00000000 */
- 0x00, /* 00000000 */
- 0x00, /* 00000000 */
- 0x00, /* 00000000 */
-
- /* 23 0x17 '^W' */
- 0x00, /* 00000000 */
- 0x00, /* 00000000 */
- 0x18, /* 00011000 */
- 0x3c, /* 00111100 */
- 0x7e, /* 01111110 */
- 0x18, /* 00011000 */
- 0x18, /* 00011000 */
- 0x18, /* 00011000 */
- 0x7e, /* 01111110 */
- 0x3c, /* 00111100 */
- 0x18, /* 00011000 */
- 0x7e, /* 01111110 */
- 0x00, /* 00000000 */
- 0x00, /* 00000000 */
- 0x00, /* 00000000 */
- 0x00, /* 00000000 */
-
- /* 24 0x18 '^X' */
- 0x00, /* 00000000 */
- 0x00, /* 00000000 */
- 0x18, /* 00011000 */
- 0x3c, /* 00111100 */
- 0x7e, /* 01111110 */
- 0x18, /* 00011000 */
- 0x18, /* 00011000 */
- 0x18, /* 00011000 */
- 0x18, /* 00011000 */
- 0x18, /* 00011000 */
- 0x18, /* 00011000 */
- 0x18, /* 00011000 */
- 0x00, /* 00000000 */
- 0x00, /* 00000000 */
- 0x00, /* 00000000 */
- 0x00, /* 00000000 */
-
- /* 25 0x19 '^Y' */
- 0x00, /* 00000000 */
- 0x00, /* 00000000 */
- 0x18, /* 00011000 */
- 0x18, /* 00011000 */
- 0x18, /* 00011000 */
- 0x18, /* 00011000 */
- 0x18, /* 00011000 */
- 0x18, /* 00011000 */
- 0x18, /* 00011000 */
- 0x7e, /* 01111110 */
- 0x3c, /* 00111100 */
- 0x18, /* 00011000 */
- 0x00, /* 00000000 */
- 0x00, /* 00000000 */
- 0x00, /* 00000000 */
- 0x00, /* 00000000 */
-
- /* 26 0x1a '^Z' */
- 0x00, /* 00000000 */
- 0x00, /* 00000000 */
- 0x00, /* 00000000 */
- 0x00, /* 00000000 */
- 0x00, /* 00000000 */
- 0x18, /* 00011000 */
- 0x0c, /* 00001100 */
- 0xfe, /* 11111110 */
- 0x0c, /* 00001100 */
- 0x18, /* 00011000 */
- 0x00, /* 00000000 */
- 0x00, /* 00000000 */
- 0x00, /* 00000000 */
- 0x00, /* 00000000 */
- 0x00, /* 00000000 */
- 0x00, /* 00000000 */
-
- /* 27 0x1b '^[' */
- 0x00, /* 00000000 */
- 0x00, /* 00000000 */
- 0x00, /* 00000000 */
- 0x00, /* 00000000 */
- 0x00, /* 00000000 */
- 0x30, /* 00110000 */
- 0x60, /* 01100000 */
- 0xfe, /* 11111110 */
- 0x60, /* 01100000 */
- 0x30, /* 00110000 */
- 0x00, /* 00000000 */
- 0x00, /* 00000000 */
- 0x00, /* 00000000 */
- 0x00, /* 00000000 */
- 0x00, /* 00000000 */
- 0x00, /* 00000000 */
-
- /* 28 0x1c '^\' */
- 0x00, /* 00000000 */
- 0x00, /* 00000000 */
- 0x00, /* 00000000 */
- 0x00, /* 00000000 */
- 0x00, /* 00000000 */
- 0x00, /* 00000000 */
- 0xc0, /* 11000000 */
- 0xc0, /* 11000000 */
- 0xc0, /* 11000000 */
- 0xfe, /* 11111110 */
- 0x00, /* 00000000 */
- 0x00, /* 00000000 */
- 0x00, /* 00000000 */
- 0x00, /* 00000000 */
- 0x00, /* 00000000 */
- 0x00, /* 00000000 */
-
- /* 29 0x1d '^]' */
- 0x00, /* 00000000 */
- 0x00, /* 00000000 */
- 0x00, /* 00000000 */
- 0x00, /* 00000000 */
- 0x00, /* 00000000 */
- 0x28, /* 00101000 */
- 0x6c, /* 01101100 */
- 0xfe, /* 11111110 */
- 0x6c, /* 01101100 */
- 0x28, /* 00101000 */
- 0x00, /* 00000000 */
- 0x00, /* 00000000 */
- 0x00, /* 00000000 */
- 0x00, /* 00000000 */
- 0x00, /* 00000000 */
- 0x00, /* 00000000 */
-
- /* 30 0x1e '^^' */
- 0x00, /* 00000000 */
- 0x00, /* 00000000 */
- 0x00, /* 00000000 */
- 0x00, /* 00000000 */
- 0x10, /* 00010000 */
- 0x38, /* 00111000 */
- 0x38, /* 00111000 */
- 0x7c, /* 01111100 */
- 0x7c, /* 01111100 */
- 0xfe, /* 11111110 */
- 0xfe, /* 11111110 */
- 0x00, /* 00000000 */
- 0x00, /* 00000000 */
- 0x00, /* 00000000 */
- 0x00, /* 00000000 */
- 0x00, /* 00000000 */
-
- /* 31 0x1f '^_' */
- 0x00, /* 00000000 */
- 0x00, /* 00000000 */
- 0x00, /* 00000000 */
- 0x00, /* 00000000 */
- 0xfe, /* 11111110 */
- 0xfe, /* 11111110 */
- 0x7c, /* 01111100 */
- 0x7c, /* 01111100 */
- 0x38, /* 00111000 */
- 0x38, /* 00111000 */
- 0x10, /* 00010000 */
- 0x00, /* 00000000 */
- 0x00, /* 00000000 */
- 0x00, /* 00000000 */
- 0x00, /* 00000000 */
- 0x00, /* 00000000 */
-
- /* 32 0x20 ' ' */
- 0x00, /* 00000000 */
- 0x00, /* 00000000 */
- 0x00, /* 00000000 */
- 0x00, /* 00000000 */
- 0x00, /* 00000000 */
- 0x00, /* 00000000 */
- 0x00, /* 00000000 */
- 0x00, /* 00000000 */
- 0x00, /* 00000000 */
- 0x00, /* 00000000 */
- 0x00, /* 00000000 */
- 0x00, /* 00000000 */
- 0x00, /* 00000000 */
- 0x00, /* 00000000 */
- 0x00, /* 00000000 */
- 0x00, /* 00000000 */
-
- /* 33 0x21 '!' */
- 0x00, /* 00000000 */
- 0x00, /* 00000000 */
- 0x18, /* 00011000 */
- 0x3c, /* 00111100 */
- 0x3c, /* 00111100 */
- 0x3c, /* 00111100 */
- 0x18, /* 00011000 */
- 0x18, /* 00011000 */
- 0x18, /* 00011000 */
- 0x00, /* 00000000 */
- 0x18, /* 00011000 */
- 0x18, /* 00011000 */
- 0x00, /* 00000000 */
- 0x00, /* 00000000 */
- 0x00, /* 00000000 */
- 0x00, /* 00000000 */
-
- /* 34 0x22 '"' */
- 0x00, /* 00000000 */
- 0x66, /* 01100110 */
- 0x66, /* 01100110 */
- 0x66, /* 01100110 */
- 0x24, /* 00100100 */
- 0x00, /* 00000000 */
- 0x00, /* 00000000 */
- 0x00, /* 00000000 */
- 0x00, /* 00000000 */
- 0x00, /* 00000000 */
- 0x00, /* 00000000 */
- 0x00, /* 00000000 */
- 0x00, /* 00000000 */
- 0x00, /* 00000000 */
- 0x00, /* 00000000 */
- 0x00, /* 00000000 */
-
- /* 35 0x23 '#' */
- 0x00, /* 00000000 */
- 0x00, /* 00000000 */
- 0x00, /* 00000000 */
- 0x6c, /* 01101100 */
- 0x6c, /* 01101100 */
- 0xfe, /* 11111110 */
- 0x6c, /* 01101100 */
- 0x6c, /* 01101100 */
- 0x6c, /* 01101100 */
- 0xfe, /* 11111110 */
- 0x6c, /* 01101100 */
- 0x6c, /* 01101100 */
- 0x00, /* 00000000 */
- 0x00, /* 00000000 */
- 0x00, /* 00000000 */
- 0x00, /* 00000000 */
-
- /* 36 0x24 '$' */
- 0x18, /* 00011000 */
- 0x18, /* 00011000 */
- 0x7c, /* 01111100 */
- 0xc6, /* 11000110 */
- 0xc2, /* 11000010 */
- 0xc0, /* 11000000 */
- 0x7c, /* 01111100 */
- 0x06, /* 00000110 */
- 0x06, /* 00000110 */
- 0x86, /* 10000110 */
- 0xc6, /* 11000110 */
- 0x7c, /* 01111100 */
- 0x18, /* 00011000 */
- 0x18, /* 00011000 */
- 0x00, /* 00000000 */
- 0x00, /* 00000000 */
-
- /* 37 0x25 '%' */
- 0x00, /* 00000000 */
- 0x00, /* 00000000 */
- 0x00, /* 00000000 */
- 0x00, /* 00000000 */
- 0xc2, /* 11000010 */
- 0xc6, /* 11000110 */
- 0x0c, /* 00001100 */
- 0x18, /* 00011000 */
- 0x30, /* 00110000 */
- 0x60, /* 01100000 */
- 0xc6, /* 11000110 */
- 0x86, /* 10000110 */
- 0x00, /* 00000000 */
- 0x00, /* 00000000 */
- 0x00, /* 00000000 */
- 0x00, /* 00000000 */
-
- /* 38 0x26 '&' */
- 0x00, /* 00000000 */
- 0x00, /* 00000000 */
- 0x38, /* 00111000 */
- 0x6c, /* 01101100 */
- 0x6c, /* 01101100 */
- 0x38, /* 00111000 */
- 0x76, /* 01110110 */
- 0xdc, /* 11011100 */
- 0xcc, /* 11001100 */
- 0xcc, /* 11001100 */
- 0xcc, /* 11001100 */
- 0x76, /* 01110110 */
- 0x00, /* 00000000 */
- 0x00, /* 00000000 */
- 0x00, /* 00000000 */
- 0x00, /* 00000000 */
-
- /* 39 0x27 ''' */
- 0x00, /* 00000000 */
- 0x30, /* 00110000 */
- 0x30, /* 00110000 */
- 0x30, /* 00110000 */
- 0x60, /* 01100000 */
- 0x00, /* 00000000 */
- 0x00, /* 00000000 */
- 0x00, /* 00000000 */
- 0x00, /* 00000000 */
- 0x00, /* 00000000 */
- 0x00, /* 00000000 */
- 0x00, /* 00000000 */
- 0x00, /* 00000000 */
- 0x00, /* 00000000 */
- 0x00, /* 00000000 */
- 0x00, /* 00000000 */
-
- /* 40 0x28 '(' */
- 0x00, /* 00000000 */
- 0x00, /* 00000000 */
- 0x0c, /* 00001100 */
- 0x18, /* 00011000 */
- 0x30, /* 00110000 */
- 0x30, /* 00110000 */
- 0x30, /* 00110000 */
- 0x30, /* 00110000 */
- 0x30, /* 00110000 */
- 0x30, /* 00110000 */
- 0x18, /* 00011000 */
- 0x0c, /* 00001100 */
- 0x00, /* 00000000 */
- 0x00, /* 00000000 */
- 0x00, /* 00000000 */
- 0x00, /* 00000000 */
-
- /* 41 0x29 ')' */
- 0x00, /* 00000000 */
- 0x00, /* 00000000 */
- 0x30, /* 00110000 */
- 0x18, /* 00011000 */
- 0x0c, /* 00001100 */
- 0x0c, /* 00001100 */
- 0x0c, /* 00001100 */
- 0x0c, /* 00001100 */
- 0x0c, /* 00001100 */
- 0x0c, /* 00001100 */
- 0x18, /* 00011000 */
- 0x30, /* 00110000 */
- 0x00, /* 00000000 */
- 0x00, /* 00000000 */
- 0x00, /* 00000000 */
- 0x00, /* 00000000 */
-
- /* 42 0x2a '*' */
- 0x00, /* 00000000 */
- 0x00, /* 00000000 */
- 0x00, /* 00000000 */
- 0x00, /* 00000000 */
- 0x00, /* 00000000 */
- 0x66, /* 01100110 */
- 0x3c, /* 00111100 */
- 0xff, /* 11111111 */
- 0x3c, /* 00111100 */
- 0x66, /* 01100110 */
- 0x00, /* 00000000 */
- 0x00, /* 00000000 */
- 0x00, /* 00000000 */
- 0x00, /* 00000000 */
- 0x00, /* 00000000 */
- 0x00, /* 00000000 */
-
- /* 43 0x2b '+' */
- 0x00, /* 00000000 */
- 0x00, /* 00000000 */
- 0x00, /* 00000000 */
- 0x00, /* 00000000 */
- 0x00, /* 00000000 */
- 0x18, /* 00011000 */
- 0x18, /* 00011000 */
- 0x7e, /* 01111110 */
- 0x18, /* 00011000 */
- 0x18, /* 00011000 */
- 0x00, /* 00000000 */
- 0x00, /* 00000000 */
- 0x00, /* 00000000 */
- 0x00, /* 00000000 */
- 0x00, /* 00000000 */
- 0x00, /* 00000000 */
-
- /* 44 0x2c ',' */
- 0x00, /* 00000000 */
- 0x00, /* 00000000 */
- 0x00, /* 00000000 */
- 0x00, /* 00000000 */
- 0x00, /* 00000000 */
- 0x00, /* 00000000 */
- 0x00, /* 00000000 */
- 0x00, /* 00000000 */
- 0x00, /* 00000000 */
- 0x18, /* 00011000 */
- 0x18, /* 00011000 */
- 0x18, /* 00011000 */
- 0x30, /* 00110000 */
- 0x00, /* 00000000 */
- 0x00, /* 00000000 */
- 0x00, /* 00000000 */
-
- /* 45 0x2d '-' */
- 0x00, /* 00000000 */
- 0x00, /* 00000000 */
- 0x00, /* 00000000 */
- 0x00, /* 00000000 */
- 0x00, /* 00000000 */
- 0x00, /* 00000000 */
- 0x00, /* 00000000 */
- 0xfe, /* 11111110 */
- 0x00, /* 00000000 */
- 0x00, /* 00000000 */
- 0x00, /* 00000000 */
- 0x00, /* 00000000 */
- 0x00, /* 00000000 */
- 0x00, /* 00000000 */
- 0x00, /* 00000000 */
- 0x00, /* 00000000 */
-
- /* 46 0x2e '.' */
- 0x00, /* 00000000 */
- 0x00, /* 00000000 */
- 0x00, /* 00000000 */
- 0x00, /* 00000000 */
- 0x00, /* 00000000 */
- 0x00, /* 00000000 */
- 0x00, /* 00000000 */
- 0x00, /* 00000000 */
- 0x00, /* 00000000 */
- 0x00, /* 00000000 */
- 0x18, /* 00011000 */
- 0x18, /* 00011000 */
- 0x00, /* 00000000 */
- 0x00, /* 00000000 */
- 0x00, /* 00000000 */
- 0x00, /* 00000000 */
-
- /* 47 0x2f '/' */
- 0x00, /* 00000000 */
- 0x00, /* 00000000 */
- 0x00, /* 00000000 */
- 0x00, /* 00000000 */
- 0x02, /* 00000010 */
- 0x06, /* 00000110 */
- 0x0c, /* 00001100 */
- 0x18, /* 00011000 */
- 0x30, /* 00110000 */
- 0x60, /* 01100000 */
- 0xc0, /* 11000000 */
- 0x80, /* 10000000 */
- 0x00, /* 00000000 */
- 0x00, /* 00000000 */
- 0x00, /* 00000000 */
- 0x00, /* 00000000 */
-
- /* 48 0x30 '0' */
- 0x00, /* 00000000 */
- 0x00, /* 00000000 */
- 0x38, /* 00111000 */
- 0x6c, /* 01101100 */
- 0xc6, /* 11000110 */
- 0xc6, /* 11000110 */
- 0xd6, /* 11010110 */
- 0xd6, /* 11010110 */
- 0xc6, /* 11000110 */
- 0xc6, /* 11000110 */
- 0x6c, /* 01101100 */
- 0x38, /* 00111000 */
- 0x00, /* 00000000 */
- 0x00, /* 00000000 */
- 0x00, /* 00000000 */
- 0x00, /* 00000000 */
-
- /* 49 0x31 '1' */
- 0x00, /* 00000000 */
- 0x00, /* 00000000 */
- 0x18, /* 00011000 */
- 0x38, /* 00111000 */
- 0x78, /* 01111000 */
- 0x18, /* 00011000 */
- 0x18, /* 00011000 */
- 0x18, /* 00011000 */
- 0x18, /* 00011000 */
- 0x18, /* 00011000 */
- 0x18, /* 00011000 */
- 0x7e, /* 01111110 */
- 0x00, /* 00000000 */
- 0x00, /* 00000000 */
- 0x00, /* 00000000 */
- 0x00, /* 00000000 */
-
- /* 50 0x32 '2' */
- 0x00, /* 00000000 */
- 0x00, /* 00000000 */
- 0x7c, /* 01111100 */
- 0xc6, /* 11000110 */
- 0x06, /* 00000110 */
- 0x0c, /* 00001100 */
- 0x18, /* 00011000 */
- 0x30, /* 00110000 */
- 0x60, /* 01100000 */
- 0xc0, /* 11000000 */
- 0xc6, /* 11000110 */
- 0xfe, /* 11111110 */
- 0x00, /* 00000000 */
- 0x00, /* 00000000 */
- 0x00, /* 00000000 */
- 0x00, /* 00000000 */
-
- /* 51 0x33 '3' */
- 0x00, /* 00000000 */
- 0x00, /* 00000000 */
- 0x7c, /* 01111100 */
- 0xc6, /* 11000110 */
- 0x06, /* 00000110 */
- 0x06, /* 00000110 */
- 0x3c, /* 00111100 */
- 0x06, /* 00000110 */
- 0x06, /* 00000110 */
- 0x06, /* 00000110 */
- 0xc6, /* 11000110 */
- 0x7c, /* 01111100 */
- 0x00, /* 00000000 */
- 0x00, /* 00000000 */
- 0x00, /* 00000000 */
- 0x00, /* 00000000 */
-
- /* 52 0x34 '4' */
- 0x00, /* 00000000 */
- 0x00, /* 00000000 */
- 0x0c, /* 00001100 */
- 0x1c, /* 00011100 */
- 0x3c, /* 00111100 */
- 0x6c, /* 01101100 */
- 0xcc, /* 11001100 */
- 0xfe, /* 11111110 */
- 0x0c, /* 00001100 */
- 0x0c, /* 00001100 */
- 0x0c, /* 00001100 */
- 0x1e, /* 00011110 */
- 0x00, /* 00000000 */
- 0x00, /* 00000000 */
- 0x00, /* 00000000 */
- 0x00, /* 00000000 */
-
- /* 53 0x35 '5' */
- 0x00, /* 00000000 */
- 0x00, /* 00000000 */
- 0xfe, /* 11111110 */
- 0xc0, /* 11000000 */
- 0xc0, /* 11000000 */
- 0xc0, /* 11000000 */
- 0xfc, /* 11111100 */
- 0x06, /* 00000110 */
- 0x06, /* 00000110 */
- 0x06, /* 00000110 */
- 0xc6, /* 11000110 */
- 0x7c, /* 01111100 */
- 0x00, /* 00000000 */
- 0x00, /* 00000000 */
- 0x00, /* 00000000 */
- 0x00, /* 00000000 */
-
- /* 54 0x36 '6' */
- 0x00, /* 00000000 */
- 0x00, /* 00000000 */
- 0x38, /* 00111000 */
- 0x60, /* 01100000 */
- 0xc0, /* 11000000 */
- 0xc0, /* 11000000 */
- 0xfc, /* 11111100 */
- 0xc6, /* 11000110 */
- 0xc6, /* 11000110 */
- 0xc6, /* 11000110 */
- 0xc6, /* 11000110 */
- 0x7c, /* 01111100 */
- 0x00, /* 00000000 */
- 0x00, /* 00000000 */
- 0x00, /* 00000000 */
- 0x00, /* 00000000 */
-
- /* 55 0x37 '7' */
- 0x00, /* 00000000 */
- 0x00, /* 00000000 */
- 0xfe, /* 11111110 */
- 0xc6, /* 11000110 */
- 0x06, /* 00000110 */
- 0x06, /* 00000110 */
- 0x0c, /* 00001100 */
- 0x18, /* 00011000 */
- 0x30, /* 00110000 */
- 0x30, /* 00110000 */
- 0x30, /* 00110000 */
- 0x30, /* 00110000 */
- 0x00, /* 00000000 */
- 0x00, /* 00000000 */
- 0x00, /* 00000000 */
- 0x00, /* 00000000 */
-
- /* 56 0x38 '8' */
- 0x00, /* 00000000 */
- 0x00, /* 00000000 */
- 0x7c, /* 01111100 */
- 0xc6, /* 11000110 */
- 0xc6, /* 11000110 */
- 0xc6, /* 11000110 */
- 0x7c, /* 01111100 */
- 0xc6, /* 11000110 */
- 0xc6, /* 11000110 */
- 0xc6, /* 11000110 */
- 0xc6, /* 11000110 */
- 0x7c, /* 01111100 */
- 0x00, /* 00000000 */
- 0x00, /* 00000000 */
- 0x00, /* 00000000 */
- 0x00, /* 00000000 */
-
- /* 57 0x39 '9' */
- 0x00, /* 00000000 */
- 0x00, /* 00000000 */
- 0x7c, /* 01111100 */
- 0xc6, /* 11000110 */
- 0xc6, /* 11000110 */
- 0xc6, /* 11000110 */
- 0x7e, /* 01111110 */
- 0x06, /* 00000110 */
- 0x06, /* 00000110 */
- 0x06, /* 00000110 */
- 0x0c, /* 00001100 */
- 0x78, /* 01111000 */
- 0x00, /* 00000000 */
- 0x00, /* 00000000 */
- 0x00, /* 00000000 */
- 0x00, /* 00000000 */
-
- /* 58 0x3a ':' */
- 0x00, /* 00000000 */
- 0x00, /* 00000000 */
- 0x00, /* 00000000 */
- 0x00, /* 00000000 */
- 0x18, /* 00011000 */
- 0x18, /* 00011000 */
- 0x00, /* 00000000 */
- 0x00, /* 00000000 */
- 0x00, /* 00000000 */
- 0x18, /* 00011000 */
- 0x18, /* 00011000 */
- 0x00, /* 00000000 */
- 0x00, /* 00000000 */
- 0x00, /* 00000000 */
- 0x00, /* 00000000 */
- 0x00, /* 00000000 */
-
- /* 59 0x3b ';' */
- 0x00, /* 00000000 */
- 0x00, /* 00000000 */
- 0x00, /* 00000000 */
- 0x00, /* 00000000 */
- 0x18, /* 00011000 */
- 0x18, /* 00011000 */
- 0x00, /* 00000000 */
- 0x00, /* 00000000 */
- 0x00, /* 00000000 */
- 0x18, /* 00011000 */
- 0x18, /* 00011000 */
- 0x30, /* 00110000 */
- 0x00, /* 00000000 */
- 0x00, /* 00000000 */
- 0x00, /* 00000000 */
- 0x00, /* 00000000 */
-
- /* 60 0x3c '<' */
- 0x00, /* 00000000 */
- 0x00, /* 00000000 */
- 0x00, /* 00000000 */
- 0x06, /* 00000110 */
- 0x0c, /* 00001100 */
- 0x18, /* 00011000 */
- 0x30, /* 00110000 */
- 0x60, /* 01100000 */
- 0x30, /* 00110000 */
- 0x18, /* 00011000 */
- 0x0c, /* 00001100 */
- 0x06, /* 00000110 */
- 0x00, /* 00000000 */
- 0x00, /* 00000000 */
- 0x00, /* 00000000 */
- 0x00, /* 00000000 */
-
- /* 61 0x3d '=' */
- 0x00, /* 00000000 */
- 0x00, /* 00000000 */
- 0x00, /* 00000000 */
- 0x00, /* 00000000 */
- 0x00, /* 00000000 */
- 0x7e, /* 01111110 */
- 0x00, /* 00000000 */
- 0x00, /* 00000000 */
- 0x7e, /* 01111110 */
- 0x00, /* 00000000 */
- 0x00, /* 00000000 */
- 0x00, /* 00000000 */
- 0x00, /* 00000000 */
- 0x00, /* 00000000 */
- 0x00, /* 00000000 */
- 0x00, /* 00000000 */
-
- /* 62 0x3e '>' */
- 0x00, /* 00000000 */
- 0x00, /* 00000000 */
- 0x00, /* 00000000 */
- 0x60, /* 01100000 */
- 0x30, /* 00110000 */
- 0x18, /* 00011000 */
- 0x0c, /* 00001100 */
- 0x06, /* 00000110 */
- 0x0c, /* 00001100 */
- 0x18, /* 00011000 */
- 0x30, /* 00110000 */
- 0x60, /* 01100000 */
- 0x00, /* 00000000 */
- 0x00, /* 00000000 */
- 0x00, /* 00000000 */
- 0x00, /* 00000000 */
-
- /* 63 0x3f '?' */
- 0x00, /* 00000000 */
- 0x00, /* 00000000 */
- 0x7c, /* 01111100 */
- 0xc6, /* 11000110 */
- 0xc6, /* 11000110 */
- 0x0c, /* 00001100 */
- 0x18, /* 00011000 */
- 0x18, /* 00011000 */
- 0x18, /* 00011000 */
- 0x00, /* 00000000 */
- 0x18, /* 00011000 */
- 0x18, /* 00011000 */
- 0x00, /* 00000000 */
- 0x00, /* 00000000 */
- 0x00, /* 00000000 */
- 0x00, /* 00000000 */
-
- /* 64 0x40 '@' */
- 0x00, /* 00000000 */
- 0x00, /* 00000000 */
- 0x00, /* 00000000 */
- 0x7c, /* 01111100 */
- 0xc6, /* 11000110 */
- 0xc6, /* 11000110 */
- 0xde, /* 11011110 */
- 0xde, /* 11011110 */
- 0xde, /* 11011110 */
- 0xdc, /* 11011100 */
- 0xc0, /* 11000000 */
- 0x7c, /* 01111100 */
- 0x00, /* 00000000 */
- 0x00, /* 00000000 */
- 0x00, /* 00000000 */
- 0x00, /* 00000000 */
-
- /* 65 0x41 'A' */
- 0x00, /* 00000000 */
- 0x00, /* 00000000 */
- 0x10, /* 00010000 */
- 0x38, /* 00111000 */
- 0x6c, /* 01101100 */
- 0xc6, /* 11000110 */
- 0xc6, /* 11000110 */
- 0xfe, /* 11111110 */
- 0xc6, /* 11000110 */
- 0xc6, /* 11000110 */
- 0xc6, /* 11000110 */
- 0xc6, /* 11000110 */
- 0x00, /* 00000000 */
- 0x00, /* 00000000 */
- 0x00, /* 00000000 */
- 0x00, /* 00000000 */
-
- /* 66 0x42 'B' */
- 0x00, /* 00000000 */
- 0x00, /* 00000000 */
- 0xfc, /* 11111100 */
- 0x66, /* 01100110 */
- 0x66, /* 01100110 */
- 0x66, /* 01100110 */
- 0x7c, /* 01111100 */
- 0x66, /* 01100110 */
- 0x66, /* 01100110 */
- 0x66, /* 01100110 */
- 0x66, /* 01100110 */
- 0xfc, /* 11111100 */
- 0x00, /* 00000000 */
- 0x00, /* 00000000 */
- 0x00, /* 00000000 */
- 0x00, /* 00000000 */
-
- /* 67 0x43 'C' */
- 0x00, /* 00000000 */
- 0x00, /* 00000000 */
- 0x3c, /* 00111100 */
- 0x66, /* 01100110 */
- 0xc2, /* 11000010 */
- 0xc0, /* 11000000 */
- 0xc0, /* 11000000 */
- 0xc0, /* 11000000 */
- 0xc0, /* 11000000 */
- 0xc2, /* 11000010 */
- 0x66, /* 01100110 */
- 0x3c, /* 00111100 */
- 0x00, /* 00000000 */
- 0x00, /* 00000000 */
- 0x00, /* 00000000 */
- 0x00, /* 00000000 */
-
- /* 68 0x44 'D' */
- 0x00, /* 00000000 */
- 0x00, /* 00000000 */
- 0xf8, /* 11111000 */
- 0x6c, /* 01101100 */
- 0x66, /* 01100110 */
- 0x66, /* 01100110 */
- 0x66, /* 01100110 */
- 0x66, /* 01100110 */
- 0x66, /* 01100110 */
- 0x66, /* 01100110 */
- 0x6c, /* 01101100 */
- 0xf8, /* 11111000 */
- 0x00, /* 00000000 */
- 0x00, /* 00000000 */
- 0x00, /* 00000000 */
- 0x00, /* 00000000 */
-
- /* 69 0x45 'E' */
- 0x00, /* 00000000 */
- 0x00, /* 00000000 */
- 0xfe, /* 11111110 */
- 0x66, /* 01100110 */
- 0x62, /* 01100010 */
- 0x68, /* 01101000 */
- 0x78, /* 01111000 */
- 0x68, /* 01101000 */
- 0x60, /* 01100000 */
- 0x62, /* 01100010 */
- 0x66, /* 01100110 */
- 0xfe, /* 11111110 */
- 0x00, /* 00000000 */
- 0x00, /* 00000000 */
- 0x00, /* 00000000 */
- 0x00, /* 00000000 */
-
- /* 70 0x46 'F' */
- 0x00, /* 00000000 */
- 0x00, /* 00000000 */
- 0xfe, /* 11111110 */
- 0x66, /* 01100110 */
- 0x62, /* 01100010 */
- 0x68, /* 01101000 */
- 0x78, /* 01111000 */
- 0x68, /* 01101000 */
- 0x60, /* 01100000 */
- 0x60, /* 01100000 */
- 0x60, /* 01100000 */
- 0xf0, /* 11110000 */
- 0x00, /* 00000000 */
- 0x00, /* 00000000 */
- 0x00, /* 00000000 */
- 0x00, /* 00000000 */
-
- /* 71 0x47 'G' */
- 0x00, /* 00000000 */
- 0x00, /* 00000000 */
- 0x3c, /* 00111100 */
- 0x66, /* 01100110 */
- 0xc2, /* 11000010 */
- 0xc0, /* 11000000 */
- 0xc0, /* 11000000 */
- 0xde, /* 11011110 */
- 0xc6, /* 11000110 */
- 0xc6, /* 11000110 */
- 0x66, /* 01100110 */
- 0x3a, /* 00111010 */
- 0x00, /* 00000000 */
- 0x00, /* 00000000 */
- 0x00, /* 00000000 */
- 0x00, /* 00000000 */
-
- /* 72 0x48 'H' */
- 0x00, /* 00000000 */
- 0x00, /* 00000000 */
- 0xc6, /* 11000110 */
- 0xc6, /* 11000110 */
- 0xc6, /* 11000110 */
- 0xc6, /* 11000110 */
- 0xfe, /* 11111110 */
- 0xc6, /* 11000110 */
- 0xc6, /* 11000110 */
- 0xc6, /* 11000110 */
- 0xc6, /* 11000110 */
- 0xc6, /* 11000110 */
- 0x00, /* 00000000 */
- 0x00, /* 00000000 */
- 0x00, /* 00000000 */
- 0x00, /* 00000000 */
-
- /* 73 0x49 'I' */
- 0x00, /* 00000000 */
- 0x00, /* 00000000 */
- 0x3c, /* 00111100 */
- 0x18, /* 00011000 */
- 0x18, /* 00011000 */
- 0x18, /* 00011000 */
- 0x18, /* 00011000 */
- 0x18, /* 00011000 */
- 0x18, /* 00011000 */
- 0x18, /* 00011000 */
- 0x18, /* 00011000 */
- 0x3c, /* 00111100 */
- 0x00, /* 00000000 */
- 0x00, /* 00000000 */
- 0x00, /* 00000000 */
- 0x00, /* 00000000 */
-
- /* 74 0x4a 'J' */
- 0x00, /* 00000000 */
- 0x00, /* 00000000 */
- 0x1e, /* 00011110 */
- 0x0c, /* 00001100 */
- 0x0c, /* 00001100 */
- 0x0c, /* 00001100 */
- 0x0c, /* 00001100 */
- 0x0c, /* 00001100 */
- 0xcc, /* 11001100 */
- 0xcc, /* 11001100 */
- 0xcc, /* 11001100 */
- 0x78, /* 01111000 */
- 0x00, /* 00000000 */
- 0x00, /* 00000000 */
- 0x00, /* 00000000 */
- 0x00, /* 00000000 */
-
- /* 75 0x4b 'K' */
- 0x00, /* 00000000 */
- 0x00, /* 00000000 */
- 0xe6, /* 11100110 */
- 0x66, /* 01100110 */
- 0x66, /* 01100110 */
- 0x6c, /* 01101100 */
- 0x78, /* 01111000 */
- 0x78, /* 01111000 */
- 0x6c, /* 01101100 */
- 0x66, /* 01100110 */
- 0x66, /* 01100110 */
- 0xe6, /* 11100110 */
- 0x00, /* 00000000 */
- 0x00, /* 00000000 */
- 0x00, /* 00000000 */
- 0x00, /* 00000000 */
-
- /* 76 0x4c 'L' */
- 0x00, /* 00000000 */
- 0x00, /* 00000000 */
- 0xf0, /* 11110000 */
- 0x60, /* 01100000 */
- 0x60, /* 01100000 */
- 0x60, /* 01100000 */
- 0x60, /* 01100000 */
- 0x60, /* 01100000 */
- 0x60, /* 01100000 */
- 0x62, /* 01100010 */
- 0x66, /* 01100110 */
- 0xfe, /* 11111110 */
- 0x00, /* 00000000 */
- 0x00, /* 00000000 */
- 0x00, /* 00000000 */
- 0x00, /* 00000000 */
-
- /* 77 0x4d 'M' */
- 0x00, /* 00000000 */
- 0x00, /* 00000000 */
- 0xc6, /* 11000110 */
- 0xee, /* 11101110 */
- 0xfe, /* 11111110 */
- 0xfe, /* 11111110 */
- 0xd6, /* 11010110 */
- 0xc6, /* 11000110 */
- 0xc6, /* 11000110 */
- 0xc6, /* 11000110 */
- 0xc6, /* 11000110 */
- 0xc6, /* 11000110 */
- 0x00, /* 00000000 */
- 0x00, /* 00000000 */
- 0x00, /* 00000000 */
- 0x00, /* 00000000 */
-
- /* 78 0x4e 'N' */
- 0x00, /* 00000000 */
- 0x00, /* 00000000 */
- 0xc6, /* 11000110 */
- 0xe6, /* 11100110 */
- 0xf6, /* 11110110 */
- 0xfe, /* 11111110 */
- 0xde, /* 11011110 */
- 0xce, /* 11001110 */
- 0xc6, /* 11000110 */
- 0xc6, /* 11000110 */
- 0xc6, /* 11000110 */
- 0xc6, /* 11000110 */
- 0x00, /* 00000000 */
- 0x00, /* 00000000 */
- 0x00, /* 00000000 */
- 0x00, /* 00000000 */
-
- /* 79 0x4f 'O' */
- 0x00, /* 00000000 */
- 0x00, /* 00000000 */
- 0x7c, /* 01111100 */
- 0xc6, /* 11000110 */
- 0xc6, /* 11000110 */
- 0xc6, /* 11000110 */
- 0xc6, /* 11000110 */
- 0xc6, /* 11000110 */
- 0xc6, /* 11000110 */
- 0xc6, /* 11000110 */
- 0xc6, /* 11000110 */
- 0x7c, /* 01111100 */
- 0x00, /* 00000000 */
- 0x00, /* 00000000 */
- 0x00, /* 00000000 */
- 0x00, /* 00000000 */
-
- /* 80 0x50 'P' */
- 0x00, /* 00000000 */
- 0x00, /* 00000000 */
- 0xfc, /* 11111100 */
- 0x66, /* 01100110 */
- 0x66, /* 01100110 */
- 0x66, /* 01100110 */
- 0x7c, /* 01111100 */
- 0x60, /* 01100000 */
- 0x60, /* 01100000 */
- 0x60, /* 01100000 */
- 0x60, /* 01100000 */
- 0xf0, /* 11110000 */
- 0x00, /* 00000000 */
- 0x00, /* 00000000 */
- 0x00, /* 00000000 */
- 0x00, /* 00000000 */
-
- /* 81 0x51 'Q' */
- 0x00, /* 00000000 */
- 0x00, /* 00000000 */
- 0x7c, /* 01111100 */
- 0xc6, /* 11000110 */
- 0xc6, /* 11000110 */
- 0xc6, /* 11000110 */
- 0xc6, /* 11000110 */
- 0xc6, /* 11000110 */
- 0xc6, /* 11000110 */
- 0xd6, /* 11010110 */
- 0xde, /* 11011110 */
- 0x7c, /* 01111100 */
- 0x0c, /* 00001100 */
- 0x0e, /* 00001110 */
- 0x00, /* 00000000 */
- 0x00, /* 00000000 */
-
- /* 82 0x52 'R' */
- 0x00, /* 00000000 */
- 0x00, /* 00000000 */
- 0xfc, /* 11111100 */
- 0x66, /* 01100110 */
- 0x66, /* 01100110 */
- 0x66, /* 01100110 */
- 0x7c, /* 01111100 */
- 0x6c, /* 01101100 */
- 0x66, /* 01100110 */
- 0x66, /* 01100110 */
- 0x66, /* 01100110 */
- 0xe6, /* 11100110 */
- 0x00, /* 00000000 */
- 0x00, /* 00000000 */
- 0x00, /* 00000000 */
- 0x00, /* 00000000 */
-
- /* 83 0x53 'S' */
- 0x00, /* 00000000 */
- 0x00, /* 00000000 */
- 0x7c, /* 01111100 */
- 0xc6, /* 11000110 */
- 0xc6, /* 11000110 */
- 0x60, /* 01100000 */
- 0x38, /* 00111000 */
- 0x0c, /* 00001100 */
- 0x06, /* 00000110 */
- 0xc6, /* 11000110 */
- 0xc6, /* 11000110 */
- 0x7c, /* 01111100 */
- 0x00, /* 00000000 */
- 0x00, /* 00000000 */
- 0x00, /* 00000000 */
- 0x00, /* 00000000 */
-
- /* 84 0x54 'T' */
- 0x00, /* 00000000 */
- 0x00, /* 00000000 */
- 0x7e, /* 01111110 */
- 0x7e, /* 01111110 */
- 0x5a, /* 01011010 */
- 0x18, /* 00011000 */
- 0x18, /* 00011000 */
- 0x18, /* 00011000 */
- 0x18, /* 00011000 */
- 0x18, /* 00011000 */
- 0x18, /* 00011000 */
- 0x3c, /* 00111100 */
- 0x00, /* 00000000 */
- 0x00, /* 00000000 */
- 0x00, /* 00000000 */
- 0x00, /* 00000000 */
-
- /* 85 0x55 'U' */
- 0x00, /* 00000000 */
- 0x00, /* 00000000 */
- 0xc6, /* 11000110 */
- 0xc6, /* 11000110 */
- 0xc6, /* 11000110 */
- 0xc6, /* 11000110 */
- 0xc6, /* 11000110 */
- 0xc6, /* 11000110 */
- 0xc6, /* 11000110 */
- 0xc6, /* 11000110 */
- 0xc6, /* 11000110 */
- 0x7c, /* 01111100 */
- 0x00, /* 00000000 */
- 0x00, /* 00000000 */
- 0x00, /* 00000000 */
- 0x00, /* 00000000 */
-
- /* 86 0x56 'V' */
- 0x00, /* 00000000 */
- 0x00, /* 00000000 */
- 0xc6, /* 11000110 */
- 0xc6, /* 11000110 */
- 0xc6, /* 11000110 */
- 0xc6, /* 11000110 */
- 0xc6, /* 11000110 */
- 0xc6, /* 11000110 */
- 0xc6, /* 11000110 */
- 0x6c, /* 01101100 */
- 0x38, /* 00111000 */
- 0x10, /* 00010000 */
- 0x00, /* 00000000 */
- 0x00, /* 00000000 */
- 0x00, /* 00000000 */
- 0x00, /* 00000000 */
-
- /* 87 0x57 'W' */
- 0x00, /* 00000000 */
- 0x00, /* 00000000 */
- 0xc6, /* 11000110 */
- 0xc6, /* 11000110 */
- 0xc6, /* 11000110 */
- 0xc6, /* 11000110 */
- 0xd6, /* 11010110 */
- 0xd6, /* 11010110 */
- 0xd6, /* 11010110 */
- 0xfe, /* 11111110 */
- 0xee, /* 11101110 */
- 0x6c, /* 01101100 */
- 0x00, /* 00000000 */
- 0x00, /* 00000000 */
- 0x00, /* 00000000 */
- 0x00, /* 00000000 */
-
- /* 88 0x58 'X' */
- 0x00, /* 00000000 */
- 0x00, /* 00000000 */
- 0xc6, /* 11000110 */
- 0xc6, /* 11000110 */
- 0x6c, /* 01101100 */
- 0x7c, /* 01111100 */
- 0x38, /* 00111000 */
- 0x38, /* 00111000 */
- 0x7c, /* 01111100 */
- 0x6c, /* 01101100 */
- 0xc6, /* 11000110 */
- 0xc6, /* 11000110 */
- 0x00, /* 00000000 */
- 0x00, /* 00000000 */
- 0x00, /* 00000000 */
- 0x00, /* 00000000 */
-
- /* 89 0x59 'Y' */
- 0x00, /* 00000000 */
- 0x00, /* 00000000 */
- 0x66, /* 01100110 */
- 0x66, /* 01100110 */
- 0x66, /* 01100110 */
- 0x66, /* 01100110 */
- 0x3c, /* 00111100 */
- 0x18, /* 00011000 */
- 0x18, /* 00011000 */
- 0x18, /* 00011000 */
- 0x18, /* 00011000 */
- 0x3c, /* 00111100 */
- 0x00, /* 00000000 */
- 0x00, /* 00000000 */
- 0x00, /* 00000000 */
- 0x00, /* 00000000 */
-
- /* 90 0x5a 'Z' */
- 0x00, /* 00000000 */
- 0x00, /* 00000000 */
- 0xfe, /* 11111110 */
- 0xc6, /* 11000110 */
- 0x86, /* 10000110 */
- 0x0c, /* 00001100 */
- 0x18, /* 00011000 */
- 0x30, /* 00110000 */
- 0x60, /* 01100000 */
- 0xc2, /* 11000010 */
- 0xc6, /* 11000110 */
- 0xfe, /* 11111110 */
- 0x00, /* 00000000 */
- 0x00, /* 00000000 */
- 0x00, /* 00000000 */
- 0x00, /* 00000000 */
-
- /* 91 0x5b '[' */
- 0x00, /* 00000000 */
- 0x00, /* 00000000 */
- 0x3c, /* 00111100 */
- 0x30, /* 00110000 */
- 0x30, /* 00110000 */
- 0x30, /* 00110000 */
- 0x30, /* 00110000 */
- 0x30, /* 00110000 */
- 0x30, /* 00110000 */
- 0x30, /* 00110000 */
- 0x30, /* 00110000 */
- 0x3c, /* 00111100 */
- 0x00, /* 00000000 */
- 0x00, /* 00000000 */
- 0x00, /* 00000000 */
- 0x00, /* 00000000 */
-
- /* 92 0x5c '\' */
- 0x00, /* 00000000 */
- 0x00, /* 00000000 */
- 0x00, /* 00000000 */
- 0x80, /* 10000000 */
- 0xc0, /* 11000000 */
- 0xe0, /* 11100000 */
- 0x70, /* 01110000 */
- 0x38, /* 00111000 */
- 0x1c, /* 00011100 */
- 0x0e, /* 00001110 */
- 0x06, /* 00000110 */
- 0x02, /* 00000010 */
- 0x00, /* 00000000 */
- 0x00, /* 00000000 */
- 0x00, /* 00000000 */
- 0x00, /* 00000000 */
-
- /* 93 0x5d ']' */
- 0x00, /* 00000000 */
- 0x00, /* 00000000 */
- 0x3c, /* 00111100 */
- 0x0c, /* 00001100 */
- 0x0c, /* 00001100 */
- 0x0c, /* 00001100 */
- 0x0c, /* 00001100 */
- 0x0c, /* 00001100 */
- 0x0c, /* 00001100 */
- 0x0c, /* 00001100 */
- 0x0c, /* 00001100 */
- 0x3c, /* 00111100 */
- 0x00, /* 00000000 */
- 0x00, /* 00000000 */
- 0x00, /* 00000000 */
- 0x00, /* 00000000 */
-
- /* 94 0x5e '^' */
- 0x10, /* 00010000 */
- 0x38, /* 00111000 */
- 0x6c, /* 01101100 */
- 0xc6, /* 11000110 */
- 0x00, /* 00000000 */
- 0x00, /* 00000000 */
- 0x00, /* 00000000 */
- 0x00, /* 00000000 */
- 0x00, /* 00000000 */
- 0x00, /* 00000000 */
- 0x00, /* 00000000 */
- 0x00, /* 00000000 */
- 0x00, /* 00000000 */
- 0x00, /* 00000000 */
- 0x00, /* 00000000 */
- 0x00, /* 00000000 */
-
- /* 95 0x5f '_' */
- 0x00, /* 00000000 */
- 0x00, /* 00000000 */
- 0x00, /* 00000000 */
- 0x00, /* 00000000 */
- 0x00, /* 00000000 */
- 0x00, /* 00000000 */
- 0x00, /* 00000000 */
- 0x00, /* 00000000 */
- 0x00, /* 00000000 */
- 0x00, /* 00000000 */
- 0x00, /* 00000000 */
- 0x00, /* 00000000 */
- 0x00, /* 00000000 */
- 0xff, /* 11111111 */
- 0x00, /* 00000000 */
- 0x00, /* 00000000 */
-
- /* 96 0x60 '`' */
- 0x00, /* 00000000 */
- 0x30, /* 00110000 */
- 0x18, /* 00011000 */
- 0x0c, /* 00001100 */
- 0x00, /* 00000000 */
- 0x00, /* 00000000 */
- 0x00, /* 00000000 */
- 0x00, /* 00000000 */
- 0x00, /* 00000000 */
- 0x00, /* 00000000 */
- 0x00, /* 00000000 */
- 0x00, /* 00000000 */
- 0x00, /* 00000000 */
- 0x00, /* 00000000 */
- 0x00, /* 00000000 */
- 0x00, /* 00000000 */
-
- /* 97 0x61 'a' */
- 0x00, /* 00000000 */
- 0x00, /* 00000000 */
- 0x00, /* 00000000 */
- 0x00, /* 00000000 */
- 0x00, /* 00000000 */
- 0x78, /* 01111000 */
- 0x0c, /* 00001100 */
- 0x7c, /* 01111100 */
- 0xcc, /* 11001100 */
- 0xcc, /* 11001100 */
- 0xcc, /* 11001100 */
- 0x76, /* 01110110 */
- 0x00, /* 00000000 */
- 0x00, /* 00000000 */
- 0x00, /* 00000000 */
- 0x00, /* 00000000 */
-
- /* 98 0x62 'b' */
- 0x00, /* 00000000 */
- 0x00, /* 00000000 */
- 0xe0, /* 11100000 */
- 0x60, /* 01100000 */
- 0x60, /* 01100000 */
- 0x78, /* 01111000 */
- 0x6c, /* 01101100 */
- 0x66, /* 01100110 */
- 0x66, /* 01100110 */
- 0x66, /* 01100110 */
- 0x66, /* 01100110 */
- 0x7c, /* 01111100 */
- 0x00, /* 00000000 */
- 0x00, /* 00000000 */
- 0x00, /* 00000000 */
- 0x00, /* 00000000 */
-
- /* 99 0x63 'c' */
- 0x00, /* 00000000 */
- 0x00, /* 00000000 */
- 0x00, /* 00000000 */
- 0x00, /* 00000000 */
- 0x00, /* 00000000 */
- 0x7c, /* 01111100 */
- 0xc6, /* 11000110 */
- 0xc0, /* 11000000 */
- 0xc0, /* 11000000 */
- 0xc0, /* 11000000 */
- 0xc6, /* 11000110 */
- 0x7c, /* 01111100 */
- 0x00, /* 00000000 */
- 0x00, /* 00000000 */
- 0x00, /* 00000000 */
- 0x00, /* 00000000 */
-
- /* 100 0x64 'd' */
- 0x00, /* 00000000 */
- 0x00, /* 00000000 */
- 0x1c, /* 00011100 */
- 0x0c, /* 00001100 */
- 0x0c, /* 00001100 */
- 0x3c, /* 00111100 */
- 0x6c, /* 01101100 */
- 0xcc, /* 11001100 */
- 0xcc, /* 11001100 */
- 0xcc, /* 11001100 */
- 0xcc, /* 11001100 */
- 0x76, /* 01110110 */
- 0x00, /* 00000000 */
- 0x00, /* 00000000 */
- 0x00, /* 00000000 */
- 0x00, /* 00000000 */
-
- /* 101 0x65 'e' */
- 0x00, /* 00000000 */
- 0x00, /* 00000000 */
- 0x00, /* 00000000 */
- 0x00, /* 00000000 */
- 0x00, /* 00000000 */
- 0x7c, /* 01111100 */
- 0xc6, /* 11000110 */
- 0xfe, /* 11111110 */
- 0xc0, /* 11000000 */
- 0xc0, /* 11000000 */
- 0xc6, /* 11000110 */
- 0x7c, /* 01111100 */
- 0x00, /* 00000000 */
- 0x00, /* 00000000 */
- 0x00, /* 00000000 */
- 0x00, /* 00000000 */
-
- /* 102 0x66 'f' */
- 0x00, /* 00000000 */
- 0x00, /* 00000000 */
- 0x1c, /* 00011100 */
- 0x36, /* 00110110 */
- 0x32, /* 00110010 */
- 0x30, /* 00110000 */
- 0x78, /* 01111000 */
- 0x30, /* 00110000 */
- 0x30, /* 00110000 */
- 0x30, /* 00110000 */
- 0x30, /* 00110000 */
- 0x78, /* 01111000 */
- 0x00, /* 00000000 */
- 0x00, /* 00000000 */
- 0x00, /* 00000000 */
- 0x00, /* 00000000 */
-
- /* 103 0x67 'g' */
- 0x00, /* 00000000 */
- 0x00, /* 00000000 */
- 0x00, /* 00000000 */
- 0x00, /* 00000000 */
- 0x00, /* 00000000 */
- 0x76, /* 01110110 */
- 0xcc, /* 11001100 */
- 0xcc, /* 11001100 */
- 0xcc, /* 11001100 */
- 0xcc, /* 11001100 */
- 0xcc, /* 11001100 */
- 0x7c, /* 01111100 */
- 0x0c, /* 00001100 */
- 0xcc, /* 11001100 */
- 0x78, /* 01111000 */
- 0x00, /* 00000000 */
-
- /* 104 0x68 'h' */
- 0x00, /* 00000000 */
- 0x00, /* 00000000 */
- 0xe0, /* 11100000 */
- 0x60, /* 01100000 */
- 0x60, /* 01100000 */
- 0x6c, /* 01101100 */
- 0x76, /* 01110110 */
- 0x66, /* 01100110 */
- 0x66, /* 01100110 */
- 0x66, /* 01100110 */
- 0x66, /* 01100110 */
- 0xe6, /* 11100110 */
- 0x00, /* 00000000 */
- 0x00, /* 00000000 */
- 0x00, /* 00000000 */
- 0x00, /* 00000000 */
-
- /* 105 0x69 'i' */
- 0x00, /* 00000000 */
- 0x00, /* 00000000 */
- 0x18, /* 00011000 */
- 0x18, /* 00011000 */
- 0x00, /* 00000000 */
- 0x38, /* 00111000 */
- 0x18, /* 00011000 */
- 0x18, /* 00011000 */
- 0x18, /* 00011000 */
- 0x18, /* 00011000 */
- 0x18, /* 00011000 */
- 0x3c, /* 00111100 */
- 0x00, /* 00000000 */
- 0x00, /* 00000000 */
- 0x00, /* 00000000 */
- 0x00, /* 00000000 */
-
- /* 106 0x6a 'j' */
- 0x00, /* 00000000 */
- 0x00, /* 00000000 */
- 0x06, /* 00000110 */
- 0x06, /* 00000110 */
- 0x00, /* 00000000 */
- 0x0e, /* 00001110 */
- 0x06, /* 00000110 */
- 0x06, /* 00000110 */
- 0x06, /* 00000110 */
- 0x06, /* 00000110 */
- 0x06, /* 00000110 */
- 0x06, /* 00000110 */
- 0x66, /* 01100110 */
- 0x66, /* 01100110 */
- 0x3c, /* 00111100 */
- 0x00, /* 00000000 */
-
- /* 107 0x6b 'k' */
- 0x00, /* 00000000 */
- 0x00, /* 00000000 */
- 0xe0, /* 11100000 */
- 0x60, /* 01100000 */
- 0x60, /* 01100000 */
- 0x66, /* 01100110 */
- 0x6c, /* 01101100 */
- 0x78, /* 01111000 */
- 0x78, /* 01111000 */
- 0x6c, /* 01101100 */
- 0x66, /* 01100110 */
- 0xe6, /* 11100110 */
- 0x00, /* 00000000 */
- 0x00, /* 00000000 */
- 0x00, /* 00000000 */
- 0x00, /* 00000000 */
-
- /* 108 0x6c 'l' */
- 0x00, /* 00000000 */
- 0x00, /* 00000000 */
- 0x38, /* 00111000 */
- 0x18, /* 00011000 */
- 0x18, /* 00011000 */
- 0x18, /* 00011000 */
- 0x18, /* 00011000 */
- 0x18, /* 00011000 */
- 0x18, /* 00011000 */
- 0x18, /* 00011000 */
- 0x18, /* 00011000 */
- 0x3c, /* 00111100 */
- 0x00, /* 00000000 */
- 0x00, /* 00000000 */
- 0x00, /* 00000000 */
- 0x00, /* 00000000 */
-
- /* 109 0x6d 'm' */
- 0x00, /* 00000000 */
- 0x00, /* 00000000 */
- 0x00, /* 00000000 */
- 0x00, /* 00000000 */
- 0x00, /* 00000000 */
- 0xec, /* 11101100 */
- 0xfe, /* 11111110 */
- 0xd6, /* 11010110 */
- 0xd6, /* 11010110 */
- 0xd6, /* 11010110 */
- 0xd6, /* 11010110 */
- 0xc6, /* 11000110 */
- 0x00, /* 00000000 */
- 0x00, /* 00000000 */
- 0x00, /* 00000000 */
- 0x00, /* 00000000 */
-
- /* 110 0x6e 'n' */
- 0x00, /* 00000000 */
- 0x00, /* 00000000 */
- 0x00, /* 00000000 */
- 0x00, /* 00000000 */
- 0x00, /* 00000000 */
- 0xdc, /* 11011100 */
- 0x66, /* 01100110 */
- 0x66, /* 01100110 */
- 0x66, /* 01100110 */
- 0x66, /* 01100110 */
- 0x66, /* 01100110 */
- 0x66, /* 01100110 */
- 0x00, /* 00000000 */
- 0x00, /* 00000000 */
- 0x00, /* 00000000 */
- 0x00, /* 00000000 */
-
- /* 111 0x6f 'o' */
- 0x00, /* 00000000 */
- 0x00, /* 00000000 */
- 0x00, /* 00000000 */
- 0x00, /* 00000000 */
- 0x00, /* 00000000 */
- 0x7c, /* 01111100 */
- 0xc6, /* 11000110 */
- 0xc6, /* 11000110 */
- 0xc6, /* 11000110 */
- 0xc6, /* 11000110 */
- 0xc6, /* 11000110 */
- 0x7c, /* 01111100 */
- 0x00, /* 00000000 */
- 0x00, /* 00000000 */
- 0x00, /* 00000000 */
- 0x00, /* 00000000 */
-
- /* 112 0x70 'p' */
- 0x00, /* 00000000 */
- 0x00, /* 00000000 */
- 0x00, /* 00000000 */
- 0x00, /* 00000000 */
- 0x00, /* 00000000 */
- 0xdc, /* 11011100 */
- 0x66, /* 01100110 */
- 0x66, /* 01100110 */
- 0x66, /* 01100110 */
- 0x66, /* 01100110 */
- 0x66, /* 01100110 */
- 0x7c, /* 01111100 */
- 0x60, /* 01100000 */
- 0x60, /* 01100000 */
- 0xf0, /* 11110000 */
- 0x00, /* 00000000 */
-
- /* 113 0x71 'q' */
- 0x00, /* 00000000 */
- 0x00, /* 00000000 */
- 0x00, /* 00000000 */
- 0x00, /* 00000000 */
- 0x00, /* 00000000 */
- 0x76, /* 01110110 */
- 0xcc, /* 11001100 */
- 0xcc, /* 11001100 */
- 0xcc, /* 11001100 */
- 0xcc, /* 11001100 */
- 0xcc, /* 11001100 */
- 0x7c, /* 01111100 */
- 0x0c, /* 00001100 */
- 0x0c, /* 00001100 */
- 0x1e, /* 00011110 */
- 0x00, /* 00000000 */
-
- /* 114 0x72 'r' */
- 0x00, /* 00000000 */
- 0x00, /* 00000000 */
- 0x00, /* 00000000 */
- 0x00, /* 00000000 */
- 0x00, /* 00000000 */
- 0xdc, /* 11011100 */
- 0x76, /* 01110110 */
- 0x66, /* 01100110 */
- 0x60, /* 01100000 */
- 0x60, /* 01100000 */
- 0x60, /* 01100000 */
- 0xf0, /* 11110000 */
- 0x00, /* 00000000 */
- 0x00, /* 00000000 */
- 0x00, /* 00000000 */
- 0x00, /* 00000000 */
-
- /* 115 0x73 's' */
- 0x00, /* 00000000 */
- 0x00, /* 00000000 */
- 0x00, /* 00000000 */
- 0x00, /* 00000000 */
- 0x00, /* 00000000 */
- 0x7c, /* 01111100 */
- 0xc6, /* 11000110 */
- 0x60, /* 01100000 */
- 0x38, /* 00111000 */
- 0x0c, /* 00001100 */
- 0xc6, /* 11000110 */
- 0x7c, /* 01111100 */
- 0x00, /* 00000000 */
- 0x00, /* 00000000 */
- 0x00, /* 00000000 */
- 0x00, /* 00000000 */
-
- /* 116 0x74 't' */
- 0x00, /* 00000000 */
- 0x00, /* 00000000 */
- 0x10, /* 00010000 */
- 0x30, /* 00110000 */
- 0x30, /* 00110000 */
- 0xfc, /* 11111100 */
- 0x30, /* 00110000 */
- 0x30, /* 00110000 */
- 0x30, /* 00110000 */
- 0x30, /* 00110000 */
- 0x36, /* 00110110 */
- 0x1c, /* 00011100 */
- 0x00, /* 00000000 */
- 0x00, /* 00000000 */
- 0x00, /* 00000000 */
- 0x00, /* 00000000 */
-
- /* 117 0x75 'u' */
- 0x00, /* 00000000 */
- 0x00, /* 00000000 */
- 0x00, /* 00000000 */
- 0x00, /* 00000000 */
- 0x00, /* 00000000 */
- 0xcc, /* 11001100 */
- 0xcc, /* 11001100 */
- 0xcc, /* 11001100 */
- 0xcc, /* 11001100 */
- 0xcc, /* 11001100 */
- 0xcc, /* 11001100 */
- 0x76, /* 01110110 */
- 0x00, /* 00000000 */
- 0x00, /* 00000000 */
- 0x00, /* 00000000 */
- 0x00, /* 00000000 */
-
- /* 118 0x76 'v' */
- 0x00, /* 00000000 */
- 0x00, /* 00000000 */
- 0x00, /* 00000000 */
- 0x00, /* 00000000 */
- 0x00, /* 00000000 */
- 0xc6, /* 11000110 */
- 0xc6, /* 11000110 */
- 0xc6, /* 11000110 */
- 0xc6, /* 11000110 */
- 0xc6, /* 11000110 */
- 0x6c, /* 01101100 */
- 0x38, /* 00111000 */
- 0x00, /* 00000000 */
- 0x00, /* 00000000 */
- 0x00, /* 00000000 */
- 0x00, /* 00000000 */
-
- /* 119 0x77 'w' */
- 0x00, /* 00000000 */
- 0x00, /* 00000000 */
- 0x00, /* 00000000 */
- 0x00, /* 00000000 */
- 0x00, /* 00000000 */
- 0xc6, /* 11000110 */
- 0xc6, /* 11000110 */
- 0xd6, /* 11010110 */
- 0xd6, /* 11010110 */
- 0xd6, /* 11010110 */
- 0xfe, /* 11111110 */
- 0x6c, /* 01101100 */
- 0x00, /* 00000000 */
- 0x00, /* 00000000 */
- 0x00, /* 00000000 */
- 0x00, /* 00000000 */
-
- /* 120 0x78 'x' */
- 0x00, /* 00000000 */
- 0x00, /* 00000000 */
- 0x00, /* 00000000 */
- 0x00, /* 00000000 */
- 0x00, /* 00000000 */
- 0xc6, /* 11000110 */
- 0x6c, /* 01101100 */
- 0x38, /* 00111000 */
- 0x38, /* 00111000 */
- 0x38, /* 00111000 */
- 0x6c, /* 01101100 */
- 0xc6, /* 11000110 */
- 0x00, /* 00000000 */
- 0x00, /* 00000000 */
- 0x00, /* 00000000 */
- 0x00, /* 00000000 */
-
- /* 121 0x79 'y' */
- 0x00, /* 00000000 */
- 0x00, /* 00000000 */
- 0x00, /* 00000000 */
- 0x00, /* 00000000 */
- 0x00, /* 00000000 */
- 0xc6, /* 11000110 */
- 0xc6, /* 11000110 */
- 0xc6, /* 11000110 */
- 0xc6, /* 11000110 */
- 0xc6, /* 11000110 */
- 0xc6, /* 11000110 */
- 0x7e, /* 01111110 */
- 0x06, /* 00000110 */
- 0x0c, /* 00001100 */
- 0xf8, /* 11111000 */
- 0x00, /* 00000000 */
-
- /* 122 0x7a 'z' */
- 0x00, /* 00000000 */
- 0x00, /* 00000000 */
- 0x00, /* 00000000 */
- 0x00, /* 00000000 */
- 0x00, /* 00000000 */
- 0xfe, /* 11111110 */
- 0xcc, /* 11001100 */
- 0x18, /* 00011000 */
- 0x30, /* 00110000 */
- 0x60, /* 01100000 */
- 0xc6, /* 11000110 */
- 0xfe, /* 11111110 */
- 0x00, /* 00000000 */
- 0x00, /* 00000000 */
- 0x00, /* 00000000 */
- 0x00, /* 00000000 */
-
- /* 123 0x7b '{' */
- 0x00, /* 00000000 */
- 0x00, /* 00000000 */
- 0x0e, /* 00001110 */
- 0x18, /* 00011000 */
- 0x18, /* 00011000 */
- 0x18, /* 00011000 */
- 0x70, /* 01110000 */
- 0x18, /* 00011000 */
- 0x18, /* 00011000 */
- 0x18, /* 00011000 */
- 0x18, /* 00011000 */
- 0x0e, /* 00001110 */
- 0x00, /* 00000000 */
- 0x00, /* 00000000 */
- 0x00, /* 00000000 */
- 0x00, /* 00000000 */
-
- /* 124 0x7c '|' */
- 0x00, /* 00000000 */
- 0x00, /* 00000000 */
- 0x18, /* 00011000 */
- 0x18, /* 00011000 */
- 0x18, /* 00011000 */
- 0x18, /* 00011000 */
- 0x18, /* 00011000 */
- 0x18, /* 00011000 */
- 0x18, /* 00011000 */
- 0x18, /* 00011000 */
- 0x18, /* 00011000 */
- 0x18, /* 00011000 */
- 0x00, /* 00000000 */
- 0x00, /* 00000000 */
- 0x00, /* 00000000 */
- 0x00, /* 00000000 */
-
- /* 125 0x7d '}' */
- 0x00, /* 00000000 */
- 0x00, /* 00000000 */
- 0x70, /* 01110000 */
- 0x18, /* 00011000 */
- 0x18, /* 00011000 */
- 0x18, /* 00011000 */
- 0x0e, /* 00001110 */
- 0x18, /* 00011000 */
- 0x18, /* 00011000 */
- 0x18, /* 00011000 */
- 0x18, /* 00011000 */
- 0x70, /* 01110000 */
- 0x00, /* 00000000 */
- 0x00, /* 00000000 */
- 0x00, /* 00000000 */
- 0x00, /* 00000000 */
-
- /* 126 0x7e '~' */
- 0x00, /* 00000000 */
- 0x76, /* 01110110 */
- 0xdc, /* 11011100 */
- 0x00, /* 00000000 */
- 0x00, /* 00000000 */
- 0x00, /* 00000000 */
- 0x00, /* 00000000 */
- 0x00, /* 00000000 */
- 0x00, /* 00000000 */
- 0x00, /* 00000000 */
- 0x00, /* 00000000 */
- 0x00, /* 00000000 */
- 0x00, /* 00000000 */
- 0x00, /* 00000000 */
- 0x00, /* 00000000 */
- 0x00, /* 00000000 */
-
- /* 127 0x7f '' */
- 0x00, /* 00000000 */
- 0x00, /* 00000000 */
- 0x00, /* 00000000 */
- 0x00, /* 00000000 */
- 0x10, /* 00010000 */
- 0x38, /* 00111000 */
- 0x6c, /* 01101100 */
- 0xc6, /* 11000110 */
- 0xc6, /* 11000110 */
- 0xc6, /* 11000110 */
- 0xfe, /* 11111110 */
- 0x00, /* 00000000 */
- 0x00, /* 00000000 */
- 0x00, /* 00000000 */
- 0x00, /* 00000000 */
- 0x00, /* 00000000 */
-
- /* 128 0x80 '' */
- 0x00, /* 00000000 */
- 0x00, /* 00000000 */
- 0x3c, /* 00111100 */
- 0x66, /* 01100110 */
- 0xc2, /* 11000010 */
- 0xc0, /* 11000000 */
- 0xc0, /* 11000000 */
- 0xc0, /* 11000000 */
- 0xc0, /* 11000000 */
- 0xc2, /* 11000010 */
- 0x66, /* 01100110 */
- 0x3c, /* 00111100 */
- 0x18, /* 00011000 */
- 0x70, /* 01110000 */
- 0x00, /* 00000000 */
- 0x00, /* 00000000 */
-
- /* 129 0x81 '' */
- 0x00, /* 00000000 */
- 0x00, /* 00000000 */
- 0xcc, /* 11001100 */
- 0x00, /* 00000000 */
- 0x00, /* 00000000 */
- 0xcc, /* 11001100 */
- 0xcc, /* 11001100 */
- 0xcc, /* 11001100 */
- 0xcc, /* 11001100 */
- 0xcc, /* 11001100 */
- 0xcc, /* 11001100 */
- 0x76, /* 01110110 */
- 0x00, /* 00000000 */
- 0x00, /* 00000000 */
- 0x00, /* 00000000 */
- 0x00, /* 00000000 */
-
- /* 130 0x82 '' */
- 0x00, /* 00000000 */
- 0x0c, /* 00001100 */
- 0x18, /* 00011000 */
- 0x30, /* 00110000 */
- 0x00, /* 00000000 */
- 0x7c, /* 01111100 */
- 0xc6, /* 11000110 */
- 0xfe, /* 11111110 */
- 0xc0, /* 11000000 */
- 0xc0, /* 11000000 */
- 0xc6, /* 11000110 */
- 0x7c, /* 01111100 */
- 0x00, /* 00000000 */
- 0x00, /* 00000000 */
- 0x00, /* 00000000 */
- 0x00, /* 00000000 */
-
- /* 131 0x83 '' */
- 0x00, /* 00000000 */
- 0x10, /* 00010000 */
- 0x38, /* 00111000 */
- 0x6c, /* 01101100 */
- 0x00, /* 00000000 */
- 0x78, /* 01111000 */
- 0x0c, /* 00001100 */
- 0x7c, /* 01111100 */
- 0xcc, /* 11001100 */
- 0xcc, /* 11001100 */
- 0xcc, /* 11001100 */
- 0x76, /* 01110110 */
- 0x00, /* 00000000 */
- 0x00, /* 00000000 */
- 0x00, /* 00000000 */
- 0x00, /* 00000000 */
-
- /* 132 0x84 '' */
- 0x00, /* 00000000 */
- 0x00, /* 00000000 */
- 0xcc, /* 11001100 */
- 0x00, /* 00000000 */
- 0x00, /* 00000000 */
- 0x78, /* 01111000 */
- 0x0c, /* 00001100 */
- 0x7c, /* 01111100 */
- 0xcc, /* 11001100 */
- 0xcc, /* 11001100 */
- 0xcc, /* 11001100 */
- 0x76, /* 01110110 */
- 0x00, /* 00000000 */
- 0x00, /* 00000000 */
- 0x00, /* 00000000 */
- 0x00, /* 00000000 */
-
- /* 133 0x85 '
' */
- 0x00, /* 00000000 */
- 0x60, /* 01100000 */
- 0x30, /* 00110000 */
- 0x18, /* 00011000 */
- 0x00, /* 00000000 */
- 0x78, /* 01111000 */
- 0x0c, /* 00001100 */
- 0x7c, /* 01111100 */
- 0xcc, /* 11001100 */
- 0xcc, /* 11001100 */
- 0xcc, /* 11001100 */
- 0x76, /* 01110110 */
- 0x00, /* 00000000 */
- 0x00, /* 00000000 */
- 0x00, /* 00000000 */
- 0x00, /* 00000000 */
-
- /* 134 0x86 '' */
- 0x00, /* 00000000 */
- 0x38, /* 00111000 */
- 0x6c, /* 01101100 */
- 0x38, /* 00111000 */
- 0x00, /* 00000000 */
- 0x78, /* 01111000 */
- 0x0c, /* 00001100 */
- 0x7c, /* 01111100 */
- 0xcc, /* 11001100 */
- 0xcc, /* 11001100 */
- 0xcc, /* 11001100 */
- 0x76, /* 01110110 */
- 0x00, /* 00000000 */
- 0x00, /* 00000000 */
- 0x00, /* 00000000 */
- 0x00, /* 00000000 */
-
- /* 135 0x87 '' */
- 0x00, /* 00000000 */
- 0x00, /* 00000000 */
- 0x00, /* 00000000 */
- 0x00, /* 00000000 */
- 0x00, /* 00000000 */
- 0x7c, /* 01111100 */
- 0xc6, /* 11000110 */
- 0xc0, /* 11000000 */
- 0xc0, /* 11000000 */
- 0xc0, /* 11000000 */
- 0xc6, /* 11000110 */
- 0x7c, /* 01111100 */
- 0x18, /* 00011000 */
- 0x70, /* 01110000 */
- 0x00, /* 00000000 */
- 0x00, /* 00000000 */
-
- /* 136 0x88 '' */
- 0x00, /* 00000000 */
- 0x10, /* 00010000 */
- 0x38, /* 00111000 */
- 0x6c, /* 01101100 */
- 0x00, /* 00000000 */
- 0x7c, /* 01111100 */
- 0xc6, /* 11000110 */
- 0xfe, /* 11111110 */
- 0xc0, /* 11000000 */
- 0xc0, /* 11000000 */
- 0xc6, /* 11000110 */
- 0x7c, /* 01111100 */
- 0x00, /* 00000000 */
- 0x00, /* 00000000 */
- 0x00, /* 00000000 */
- 0x00, /* 00000000 */
-
- /* 137 0x89 '' */
- 0x00, /* 00000000 */
- 0x00, /* 00000000 */
- 0xc6, /* 11000110 */
- 0x00, /* 00000000 */
- 0x00, /* 00000000 */
- 0x7c, /* 01111100 */
- 0xc6, /* 11000110 */
- 0xfe, /* 11111110 */
- 0xc0, /* 11000000 */
- 0xc0, /* 11000000 */
- 0xc6, /* 11000110 */
- 0x7c, /* 01111100 */
- 0x00, /* 00000000 */
- 0x00, /* 00000000 */
- 0x00, /* 00000000 */
- 0x00, /* 00000000 */
-
- /* 138 0x8a '' */
- 0x00, /* 00000000 */
- 0x60, /* 01100000 */
- 0x30, /* 00110000 */
- 0x18, /* 00011000 */
- 0x00, /* 00000000 */
- 0x7c, /* 01111100 */
- 0xc6, /* 11000110 */
- 0xfe, /* 11111110 */
- 0xc0, /* 11000000 */
- 0xc0, /* 11000000 */
- 0xc6, /* 11000110 */
- 0x7c, /* 01111100 */
- 0x00, /* 00000000 */
- 0x00, /* 00000000 */
- 0x00, /* 00000000 */
- 0x00, /* 00000000 */
-
- /* 139 0x8b '' */
- 0x00, /* 00000000 */
- 0x00, /* 00000000 */
- 0x66, /* 01100110 */
- 0x00, /* 00000000 */
- 0x00, /* 00000000 */
- 0x38, /* 00111000 */
- 0x18, /* 00011000 */
- 0x18, /* 00011000 */
- 0x18, /* 00011000 */
- 0x18, /* 00011000 */
- 0x18, /* 00011000 */
- 0x3c, /* 00111100 */
- 0x00, /* 00000000 */
- 0x00, /* 00000000 */
- 0x00, /* 00000000 */
- 0x00, /* 00000000 */
-
- /* 140 0x8c '' */
- 0x00, /* 00000000 */
- 0x18, /* 00011000 */
- 0x3c, /* 00111100 */
- 0x66, /* 01100110 */
- 0x00, /* 00000000 */
- 0x38, /* 00111000 */
- 0x18, /* 00011000 */
- 0x18, /* 00011000 */
- 0x18, /* 00011000 */
- 0x18, /* 00011000 */
- 0x18, /* 00011000 */
- 0x3c, /* 00111100 */
- 0x00, /* 00000000 */
- 0x00, /* 00000000 */
- 0x00, /* 00000000 */
- 0x00, /* 00000000 */
-
- /* 141 0x8d '' */
- 0x00, /* 00000000 */
- 0x60, /* 01100000 */
- 0x30, /* 00110000 */
- 0x18, /* 00011000 */
- 0x00, /* 00000000 */
- 0x38, /* 00111000 */
- 0x18, /* 00011000 */
- 0x18, /* 00011000 */
- 0x18, /* 00011000 */
- 0x18, /* 00011000 */
- 0x18, /* 00011000 */
- 0x3c, /* 00111100 */
- 0x00, /* 00000000 */
- 0x00, /* 00000000 */
- 0x00, /* 00000000 */
- 0x00, /* 00000000 */
-
- /* 142 0x8e '' */
- 0x00, /* 00000000 */
- 0xc6, /* 11000110 */
- 0x00, /* 00000000 */
- 0x10, /* 00010000 */
- 0x38, /* 00111000 */
- 0x6c, /* 01101100 */
- 0xc6, /* 11000110 */
- 0xc6, /* 11000110 */
- 0xfe, /* 11111110 */
- 0xc6, /* 11000110 */
- 0xc6, /* 11000110 */
- 0xc6, /* 11000110 */
- 0x00, /* 00000000 */
- 0x00, /* 00000000 */
- 0x00, /* 00000000 */
- 0x00, /* 00000000 */
-
- /* 143 0x8f '' */
- 0x38, /* 00111000 */
- 0x6c, /* 01101100 */
- 0x38, /* 00111000 */
- 0x10, /* 00010000 */
- 0x38, /* 00111000 */
- 0x6c, /* 01101100 */
- 0xc6, /* 11000110 */
- 0xfe, /* 11111110 */
- 0xc6, /* 11000110 */
- 0xc6, /* 11000110 */
- 0xc6, /* 11000110 */
- 0xc6, /* 11000110 */
- 0x00, /* 00000000 */
- 0x00, /* 00000000 */
- 0x00, /* 00000000 */
- 0x00, /* 00000000 */
-
- /* 144 0x90 '' */
- 0x0c, /* 00001100 */
- 0x18, /* 00011000 */
- 0x00, /* 00000000 */
- 0xfe, /* 11111110 */
- 0x66, /* 01100110 */
- 0x62, /* 01100010 */
- 0x68, /* 01101000 */
- 0x78, /* 01111000 */
- 0x68, /* 01101000 */
- 0x62, /* 01100010 */
- 0x66, /* 01100110 */
- 0xfe, /* 11111110 */
- 0x00, /* 00000000 */
- 0x00, /* 00000000 */
- 0x00, /* 00000000 */
- 0x00, /* 00000000 */
-
- /* 145 0x91 '' */
- 0x00, /* 00000000 */
- 0x00, /* 00000000 */
- 0x00, /* 00000000 */
- 0x00, /* 00000000 */
- 0x00, /* 00000000 */
- 0xec, /* 11101100 */
- 0x36, /* 00110110 */
- 0x36, /* 00110110 */
- 0x7e, /* 01111110 */
- 0xd8, /* 11011000 */
- 0xd8, /* 11011000 */
- 0x6e, /* 01101110 */
- 0x00, /* 00000000 */
- 0x00, /* 00000000 */
- 0x00, /* 00000000 */
- 0x00, /* 00000000 */
-
- /* 146 0x92 '' */
- 0x00, /* 00000000 */
- 0x00, /* 00000000 */
- 0x3e, /* 00111110 */
- 0x6c, /* 01101100 */
- 0xcc, /* 11001100 */
- 0xcc, /* 11001100 */
- 0xfe, /* 11111110 */
- 0xcc, /* 11001100 */
- 0xcc, /* 11001100 */
- 0xcc, /* 11001100 */
- 0xcc, /* 11001100 */
- 0xce, /* 11001110 */
- 0x00, /* 00000000 */
- 0x00, /* 00000000 */
- 0x00, /* 00000000 */
- 0x00, /* 00000000 */
-
- /* 147 0x93 '' */
- 0x00, /* 00000000 */
- 0x10, /* 00010000 */
- 0x38, /* 00111000 */
- 0x6c, /* 01101100 */
- 0x00, /* 00000000 */
- 0x7c, /* 01111100 */
- 0xc6, /* 11000110 */
- 0xc6, /* 11000110 */
- 0xc6, /* 11000110 */
- 0xc6, /* 11000110 */
- 0xc6, /* 11000110 */
- 0x7c, /* 01111100 */
- 0x00, /* 00000000 */
- 0x00, /* 00000000 */
- 0x00, /* 00000000 */
- 0x00, /* 00000000 */
-
- /* 148 0x94 '' */
- 0x00, /* 00000000 */
- 0x00, /* 00000000 */
- 0xc6, /* 11000110 */
- 0x00, /* 00000000 */
- 0x00, /* 00000000 */
- 0x7c, /* 01111100 */
- 0xc6, /* 11000110 */
- 0xc6, /* 11000110 */
- 0xc6, /* 11000110 */
- 0xc6, /* 11000110 */
- 0xc6, /* 11000110 */
- 0x7c, /* 01111100 */
- 0x00, /* 00000000 */
- 0x00, /* 00000000 */
- 0x00, /* 00000000 */
- 0x00, /* 00000000 */
-
- /* 149 0x95 '' */
- 0x00, /* 00000000 */
- 0x60, /* 01100000 */
- 0x30, /* 00110000 */
- 0x18, /* 00011000 */
- 0x00, /* 00000000 */
- 0x7c, /* 01111100 */
- 0xc6, /* 11000110 */
- 0xc6, /* 11000110 */
- 0xc6, /* 11000110 */
- 0xc6, /* 11000110 */
- 0xc6, /* 11000110 */
- 0x7c, /* 01111100 */
- 0x00, /* 00000000 */
- 0x00, /* 00000000 */
- 0x00, /* 00000000 */
- 0x00, /* 00000000 */
-
- /* 150 0x96 '' */
- 0x00, /* 00000000 */
- 0x30, /* 00110000 */
- 0x78, /* 01111000 */
- 0xcc, /* 11001100 */
- 0x00, /* 00000000 */
- 0xcc, /* 11001100 */
- 0xcc, /* 11001100 */
- 0xcc, /* 11001100 */
- 0xcc, /* 11001100 */
- 0xcc, /* 11001100 */
- 0xcc, /* 11001100 */
- 0x76, /* 01110110 */
- 0x00, /* 00000000 */
- 0x00, /* 00000000 */
- 0x00, /* 00000000 */
- 0x00, /* 00000000 */
-
- /* 151 0x97 '' */
- 0x00, /* 00000000 */
- 0x60, /* 01100000 */
- 0x30, /* 00110000 */
- 0x18, /* 00011000 */
- 0x00, /* 00000000 */
- 0xcc, /* 11001100 */
- 0xcc, /* 11001100 */
- 0xcc, /* 11001100 */
- 0xcc, /* 11001100 */
- 0xcc, /* 11001100 */
- 0xcc, /* 11001100 */
- 0x76, /* 01110110 */
- 0x00, /* 00000000 */
- 0x00, /* 00000000 */
- 0x00, /* 00000000 */
- 0x00, /* 00000000 */
-
- /* 152 0x98 '' */
- 0x00, /* 00000000 */
- 0x00, /* 00000000 */
- 0xc6, /* 11000110 */
- 0x00, /* 00000000 */
- 0x00, /* 00000000 */
- 0xc6, /* 11000110 */
- 0xc6, /* 11000110 */
- 0xc6, /* 11000110 */
- 0xc6, /* 11000110 */
- 0xc6, /* 11000110 */
- 0xc6, /* 11000110 */
- 0x7e, /* 01111110 */
- 0x06, /* 00000110 */
- 0x0c, /* 00001100 */
- 0x78, /* 01111000 */
- 0x00, /* 00000000 */
-
- /* 153 0x99 '' */
- 0x00, /* 00000000 */
- 0xc6, /* 11000110 */
- 0x00, /* 00000000 */
- 0x7c, /* 01111100 */
- 0xc6, /* 11000110 */
- 0xc6, /* 11000110 */
- 0xc6, /* 11000110 */
- 0xc6, /* 11000110 */
- 0xc6, /* 11000110 */
- 0xc6, /* 11000110 */
- 0xc6, /* 11000110 */
- 0x7c, /* 01111100 */
- 0x00, /* 00000000 */
- 0x00, /* 00000000 */
- 0x00, /* 00000000 */
- 0x00, /* 00000000 */
-
- /* 154 0x9a '' */
- 0x00, /* 00000000 */
- 0xc6, /* 11000110 */
- 0x00, /* 00000000 */
- 0xc6, /* 11000110 */
- 0xc6, /* 11000110 */
- 0xc6, /* 11000110 */
- 0xc6, /* 11000110 */
- 0xc6, /* 11000110 */
- 0xc6, /* 11000110 */
- 0xc6, /* 11000110 */
- 0xc6, /* 11000110 */
- 0x7c, /* 01111100 */
- 0x00, /* 00000000 */
- 0x00, /* 00000000 */
- 0x00, /* 00000000 */
- 0x00, /* 00000000 */
-
- /* 155 0x9b '' */
- 0x00, /* 00000000 */
- 0x18, /* 00011000 */
- 0x18, /* 00011000 */
- 0x7c, /* 01111100 */
- 0xc6, /* 11000110 */
- 0xc0, /* 11000000 */
- 0xc0, /* 11000000 */
- 0xc0, /* 11000000 */
- 0xc6, /* 11000110 */
- 0x7c, /* 01111100 */
- 0x18, /* 00011000 */
- 0x18, /* 00011000 */
- 0x00, /* 00000000 */
- 0x00, /* 00000000 */
- 0x00, /* 00000000 */
- 0x00, /* 00000000 */
-
- /* 156 0x9c '' */
- 0x00, /* 00000000 */
- 0x38, /* 00111000 */
- 0x6c, /* 01101100 */
- 0x64, /* 01100100 */
- 0x60, /* 01100000 */
- 0xf0, /* 11110000 */
- 0x60, /* 01100000 */
- 0x60, /* 01100000 */
- 0x60, /* 01100000 */
- 0x60, /* 01100000 */
- 0xe6, /* 11100110 */
- 0xfc, /* 11111100 */
- 0x00, /* 00000000 */
- 0x00, /* 00000000 */
- 0x00, /* 00000000 */
- 0x00, /* 00000000 */
-
- /* 157 0x9d '' */
- 0x00, /* 00000000 */
- 0x00, /* 00000000 */
- 0x66, /* 01100110 */
- 0x66, /* 01100110 */
- 0x3c, /* 00111100 */
- 0x18, /* 00011000 */
- 0x7e, /* 01111110 */
- 0x18, /* 00011000 */
- 0x7e, /* 01111110 */
- 0x18, /* 00011000 */
- 0x18, /* 00011000 */
- 0x18, /* 00011000 */
- 0x00, /* 00000000 */
- 0x00, /* 00000000 */
- 0x00, /* 00000000 */
- 0x00, /* 00000000 */
-
- /* 158 0x9e '' */
- 0x00, /* 00000000 */
- 0xf8, /* 11111000 */
- 0xcc, /* 11001100 */
- 0xcc, /* 11001100 */
- 0xf8, /* 11111000 */
- 0xc4, /* 11000100 */
- 0xcc, /* 11001100 */
- 0xde, /* 11011110 */
- 0xcc, /* 11001100 */
- 0xcc, /* 11001100 */
- 0xcc, /* 11001100 */
- 0xc6, /* 11000110 */
- 0x00, /* 00000000 */
- 0x00, /* 00000000 */
- 0x00, /* 00000000 */
- 0x00, /* 00000000 */
-
- /* 159 0x9f '' */
- 0x00, /* 00000000 */
- 0x0e, /* 00001110 */
- 0x1b, /* 00011011 */
- 0x18, /* 00011000 */
- 0x18, /* 00011000 */
- 0x18, /* 00011000 */
- 0x7e, /* 01111110 */
- 0x18, /* 00011000 */
- 0x18, /* 00011000 */
- 0x18, /* 00011000 */
- 0xd8, /* 11011000 */
- 0x70, /* 01110000 */
- 0x00, /* 00000000 */
- 0x00, /* 00000000 */
- 0x00, /* 00000000 */
- 0x00, /* 00000000 */
-
- /* 160 0xa0 ' ' */
- 0x00, /* 00000000 */
- 0x18, /* 00011000 */
- 0x30, /* 00110000 */
- 0x60, /* 01100000 */
- 0x00, /* 00000000 */
- 0x78, /* 01111000 */
- 0x0c, /* 00001100 */
- 0x7c, /* 01111100 */
- 0xcc, /* 11001100 */
- 0xcc, /* 11001100 */
- 0xcc, /* 11001100 */
- 0x76, /* 01110110 */
- 0x00, /* 00000000 */
- 0x00, /* 00000000 */
- 0x00, /* 00000000 */
- 0x00, /* 00000000 */
-
- /* 161 0xa1 '¡' */
- 0x00, /* 00000000 */
- 0x0c, /* 00001100 */
- 0x18, /* 00011000 */
- 0x30, /* 00110000 */
- 0x00, /* 00000000 */
- 0x38, /* 00111000 */
- 0x18, /* 00011000 */
- 0x18, /* 00011000 */
- 0x18, /* 00011000 */
- 0x18, /* 00011000 */
- 0x18, /* 00011000 */
- 0x3c, /* 00111100 */
- 0x00, /* 00000000 */
- 0x00, /* 00000000 */
- 0x00, /* 00000000 */
- 0x00, /* 00000000 */
-
- /* 162 0xa2 '¢' */
- 0x00, /* 00000000 */
- 0x18, /* 00011000 */
- 0x30, /* 00110000 */
- 0x60, /* 01100000 */
- 0x00, /* 00000000 */
- 0x7c, /* 01111100 */
- 0xc6, /* 11000110 */
- 0xc6, /* 11000110 */
- 0xc6, /* 11000110 */
- 0xc6, /* 11000110 */
- 0xc6, /* 11000110 */
- 0x7c, /* 01111100 */
- 0x00, /* 00000000 */
- 0x00, /* 00000000 */
- 0x00, /* 00000000 */
- 0x00, /* 00000000 */
-
- /* 163 0xa3 '£' */
- 0x00, /* 00000000 */
- 0x18, /* 00011000 */
- 0x30, /* 00110000 */
- 0x60, /* 01100000 */
- 0x00, /* 00000000 */
- 0xcc, /* 11001100 */
- 0xcc, /* 11001100 */
- 0xcc, /* 11001100 */
- 0xcc, /* 11001100 */
- 0xcc, /* 11001100 */
- 0xcc, /* 11001100 */
- 0x76, /* 01110110 */
- 0x00, /* 00000000 */
- 0x00, /* 00000000 */
- 0x00, /* 00000000 */
- 0x00, /* 00000000 */
-
- /* 164 0xa4 '¤' */
- 0x00, /* 00000000 */
- 0x00, /* 00000000 */
- 0x76, /* 01110110 */
- 0xdc, /* 11011100 */
- 0x00, /* 00000000 */
- 0xdc, /* 11011100 */
- 0x66, /* 01100110 */
- 0x66, /* 01100110 */
- 0x66, /* 01100110 */
- 0x66, /* 01100110 */
- 0x66, /* 01100110 */
- 0x66, /* 01100110 */
- 0x00, /* 00000000 */
- 0x00, /* 00000000 */
- 0x00, /* 00000000 */
- 0x00, /* 00000000 */
-
- /* 165 0xa5 '¥' */
- 0x76, /* 01110110 */
- 0xdc, /* 11011100 */
- 0x00, /* 00000000 */
- 0xc6, /* 11000110 */
- 0xe6, /* 11100110 */
- 0xf6, /* 11110110 */
- 0xfe, /* 11111110 */
- 0xde, /* 11011110 */
- 0xce, /* 11001110 */
- 0xc6, /* 11000110 */
- 0xc6, /* 11000110 */
- 0xc6, /* 11000110 */
- 0x00, /* 00000000 */
- 0x00, /* 00000000 */
- 0x00, /* 00000000 */
- 0x00, /* 00000000 */
-
- /* 166 0xa6 '¦' */
- 0x00, /* 00000000 */
- 0x00, /* 00000000 */
- 0x3c, /* 00111100 */
- 0x6c, /* 01101100 */
- 0x6c, /* 01101100 */
- 0x3e, /* 00111110 */
- 0x00, /* 00000000 */
- 0x7e, /* 01111110 */
- 0x00, /* 00000000 */
- 0x00, /* 00000000 */
- 0x00, /* 00000000 */
- 0x00, /* 00000000 */
- 0x00, /* 00000000 */
- 0x00, /* 00000000 */
- 0x00, /* 00000000 */
- 0x00, /* 00000000 */
-
- /* 167 0xa7 '§' */
- 0x00, /* 00000000 */
- 0x00, /* 00000000 */
- 0x38, /* 00111000 */
- 0x6c, /* 01101100 */
- 0x6c, /* 01101100 */
- 0x38, /* 00111000 */
- 0x00, /* 00000000 */
- 0x7c, /* 01111100 */
- 0x00, /* 00000000 */
- 0x00, /* 00000000 */
- 0x00, /* 00000000 */
- 0x00, /* 00000000 */
- 0x00, /* 00000000 */
- 0x00, /* 00000000 */
- 0x00, /* 00000000 */
- 0x00, /* 00000000 */
-
- /* 168 0xa8 '¨' */
- 0x00, /* 00000000 */
- 0x00, /* 00000000 */
- 0x30, /* 00110000 */
- 0x30, /* 00110000 */
- 0x00, /* 00000000 */
- 0x30, /* 00110000 */
- 0x30, /* 00110000 */
- 0x60, /* 01100000 */
- 0xc0, /* 11000000 */
- 0xc6, /* 11000110 */
- 0xc6, /* 11000110 */
- 0x7c, /* 01111100 */
- 0x00, /* 00000000 */
- 0x00, /* 00000000 */
- 0x00, /* 00000000 */
- 0x00, /* 00000000 */
-
- /* 169 0xa9 '©' */
- 0x00, /* 00000000 */
- 0x00, /* 00000000 */
- 0x00, /* 00000000 */
- 0x00, /* 00000000 */
- 0x00, /* 00000000 */
- 0x00, /* 00000000 */
- 0xfe, /* 11111110 */
- 0xc0, /* 11000000 */
- 0xc0, /* 11000000 */
- 0xc0, /* 11000000 */
- 0xc0, /* 11000000 */
- 0x00, /* 00000000 */
- 0x00, /* 00000000 */
- 0x00, /* 00000000 */
- 0x00, /* 00000000 */
- 0x00, /* 00000000 */
-
- /* 170 0xaa 'ª' */
- 0x00, /* 00000000 */
- 0x00, /* 00000000 */
- 0x00, /* 00000000 */
- 0x00, /* 00000000 */
- 0x00, /* 00000000 */
- 0x00, /* 00000000 */
- 0xfe, /* 11111110 */
- 0x06, /* 00000110 */
- 0x06, /* 00000110 */
- 0x06, /* 00000110 */
- 0x06, /* 00000110 */
- 0x00, /* 00000000 */
- 0x00, /* 00000000 */
- 0x00, /* 00000000 */
- 0x00, /* 00000000 */
- 0x00, /* 00000000 */
-
- /* 171 0xab '«' */
- 0x00, /* 00000000 */
- 0x60, /* 01100000 */
- 0xe0, /* 11100000 */
- 0x62, /* 01100010 */
- 0x66, /* 01100110 */
- 0x6c, /* 01101100 */
- 0x18, /* 00011000 */
- 0x30, /* 00110000 */
- 0x60, /* 01100000 */
- 0xdc, /* 11011100 */
- 0x86, /* 10000110 */
- 0x0c, /* 00001100 */
- 0x18, /* 00011000 */
- 0x3e, /* 00111110 */
- 0x00, /* 00000000 */
- 0x00, /* 00000000 */
-
- /* 172 0xac '¬' */
- 0x00, /* 00000000 */
- 0x60, /* 01100000 */
- 0xe0, /* 11100000 */
- 0x62, /* 01100010 */
- 0x66, /* 01100110 */
- 0x6c, /* 01101100 */
- 0x18, /* 00011000 */
- 0x30, /* 00110000 */
- 0x66, /* 01100110 */
- 0xce, /* 11001110 */
- 0x9a, /* 10011010 */
- 0x3f, /* 00111111 */
- 0x06, /* 00000110 */
- 0x06, /* 00000110 */
- 0x00, /* 00000000 */
- 0x00, /* 00000000 */
-
- /* 173 0xad '' */
- 0x00, /* 00000000 */
- 0x00, /* 00000000 */
- 0x18, /* 00011000 */
- 0x18, /* 00011000 */
- 0x00, /* 00000000 */
- 0x18, /* 00011000 */
- 0x18, /* 00011000 */
- 0x18, /* 00011000 */
- 0x3c, /* 00111100 */
- 0x3c, /* 00111100 */
- 0x3c, /* 00111100 */
- 0x18, /* 00011000 */
- 0x00, /* 00000000 */
- 0x00, /* 00000000 */
- 0x00, /* 00000000 */
- 0x00, /* 00000000 */
-
- /* 174 0xae '®' */
- 0x00, /* 00000000 */
- 0x00, /* 00000000 */
- 0x00, /* 00000000 */
- 0x00, /* 00000000 */
- 0x00, /* 00000000 */
- 0x36, /* 00110110 */
- 0x6c, /* 01101100 */
- 0xd8, /* 11011000 */
- 0x6c, /* 01101100 */
- 0x36, /* 00110110 */
- 0x00, /* 00000000 */
- 0x00, /* 00000000 */
- 0x00, /* 00000000 */
- 0x00, /* 00000000 */
- 0x00, /* 00000000 */
- 0x00, /* 00000000 */
-
- /* 175 0xaf '¯' */
- 0x00, /* 00000000 */
- 0x00, /* 00000000 */
- 0x00, /* 00000000 */
- 0x00, /* 00000000 */
- 0x00, /* 00000000 */
- 0xd8, /* 11011000 */
- 0x6c, /* 01101100 */
- 0x36, /* 00110110 */
- 0x6c, /* 01101100 */
- 0xd8, /* 11011000 */
- 0x00, /* 00000000 */
- 0x00, /* 00000000 */
- 0x00, /* 00000000 */
- 0x00, /* 00000000 */
- 0x00, /* 00000000 */
- 0x00, /* 00000000 */
-
- /* 176 0xb0 '°' */
- 0x11, /* 00010001 */
- 0x44, /* 01000100 */
- 0x11, /* 00010001 */
- 0x44, /* 01000100 */
- 0x11, /* 00010001 */
- 0x44, /* 01000100 */
- 0x11, /* 00010001 */
- 0x44, /* 01000100 */
- 0x11, /* 00010001 */
- 0x44, /* 01000100 */
- 0x11, /* 00010001 */
- 0x44, /* 01000100 */
- 0x11, /* 00010001 */
- 0x44, /* 01000100 */
- 0x11, /* 00010001 */
- 0x44, /* 01000100 */
-
- /* 177 0xb1 '±' */
- 0x55, /* 01010101 */
- 0xaa, /* 10101010 */
- 0x55, /* 01010101 */
- 0xaa, /* 10101010 */
- 0x55, /* 01010101 */
- 0xaa, /* 10101010 */
- 0x55, /* 01010101 */
- 0xaa, /* 10101010 */
- 0x55, /* 01010101 */
- 0xaa, /* 10101010 */
- 0x55, /* 01010101 */
- 0xaa, /* 10101010 */
- 0x55, /* 01010101 */
- 0xaa, /* 10101010 */
- 0x55, /* 01010101 */
- 0xaa, /* 10101010 */
-
- /* 178 0xb2 '²' */
- 0xdd, /* 11011101 */
- 0x77, /* 01110111 */
- 0xdd, /* 11011101 */
- 0x77, /* 01110111 */
- 0xdd, /* 11011101 */
- 0x77, /* 01110111 */
- 0xdd, /* 11011101 */
- 0x77, /* 01110111 */
- 0xdd, /* 11011101 */
- 0x77, /* 01110111 */
- 0xdd, /* 11011101 */
- 0x77, /* 01110111 */
- 0xdd, /* 11011101 */
- 0x77, /* 01110111 */
- 0xdd, /* 11011101 */
- 0x77, /* 01110111 */
-
- /* 179 0xb3 '³' */
- 0x18, /* 00011000 */
- 0x18, /* 00011000 */
- 0x18, /* 00011000 */
- 0x18, /* 00011000 */
- 0x18, /* 00011000 */
- 0x18, /* 00011000 */
- 0x18, /* 00011000 */
- 0x18, /* 00011000 */
- 0x18, /* 00011000 */
- 0x18, /* 00011000 */
- 0x18, /* 00011000 */
- 0x18, /* 00011000 */
- 0x18, /* 00011000 */
- 0x18, /* 00011000 */
- 0x18, /* 00011000 */
- 0x18, /* 00011000 */
-
- /* 180 0xb4 '´' */
- 0x18, /* 00011000 */
- 0x18, /* 00011000 */
- 0x18, /* 00011000 */
- 0x18, /* 00011000 */
- 0x18, /* 00011000 */
- 0x18, /* 00011000 */
- 0x18, /* 00011000 */
- 0xf8, /* 11111000 */
- 0x18, /* 00011000 */
- 0x18, /* 00011000 */
- 0x18, /* 00011000 */
- 0x18, /* 00011000 */
- 0x18, /* 00011000 */
- 0x18, /* 00011000 */
- 0x18, /* 00011000 */
- 0x18, /* 00011000 */
-
- /* 181 0xb5 'µ' */
- 0x18, /* 00011000 */
- 0x18, /* 00011000 */
- 0x18, /* 00011000 */
- 0x18, /* 00011000 */
- 0x18, /* 00011000 */
- 0xf8, /* 11111000 */
- 0x18, /* 00011000 */
- 0xf8, /* 11111000 */
- 0x18, /* 00011000 */
- 0x18, /* 00011000 */
- 0x18, /* 00011000 */
- 0x18, /* 00011000 */
- 0x18, /* 00011000 */
- 0x18, /* 00011000 */
- 0x18, /* 00011000 */
- 0x18, /* 00011000 */
-
- /* 182 0xb6 '¶' */
- 0x36, /* 00110110 */
- 0x36, /* 00110110 */
- 0x36, /* 00110110 */
- 0x36, /* 00110110 */
- 0x36, /* 00110110 */
- 0x36, /* 00110110 */
- 0x36, /* 00110110 */
- 0xf6, /* 11110110 */
- 0x36, /* 00110110 */
- 0x36, /* 00110110 */
- 0x36, /* 00110110 */
- 0x36, /* 00110110 */
- 0x36, /* 00110110 */
- 0x36, /* 00110110 */
- 0x36, /* 00110110 */
- 0x36, /* 00110110 */
-
- /* 183 0xb7 '·' */
- 0x00, /* 00000000 */
- 0x00, /* 00000000 */
- 0x00, /* 00000000 */
- 0x00, /* 00000000 */
- 0x00, /* 00000000 */
- 0x00, /* 00000000 */
- 0x00, /* 00000000 */
- 0xfe, /* 11111110 */
- 0x36, /* 00110110 */
- 0x36, /* 00110110 */
- 0x36, /* 00110110 */
- 0x36, /* 00110110 */
- 0x36, /* 00110110 */
- 0x36, /* 00110110 */
- 0x36, /* 00110110 */
- 0x36, /* 00110110 */
-
- /* 184 0xb8 '¸' */
- 0x00, /* 00000000 */
- 0x00, /* 00000000 */
- 0x00, /* 00000000 */
- 0x00, /* 00000000 */
- 0x00, /* 00000000 */
- 0xf8, /* 11111000 */
- 0x18, /* 00011000 */
- 0xf8, /* 11111000 */
- 0x18, /* 00011000 */
- 0x18, /* 00011000 */
- 0x18, /* 00011000 */
- 0x18, /* 00011000 */
- 0x18, /* 00011000 */
- 0x18, /* 00011000 */
- 0x18, /* 00011000 */
- 0x18, /* 00011000 */
-
- /* 185 0xb9 '¹' */
- 0x36, /* 00110110 */
- 0x36, /* 00110110 */
- 0x36, /* 00110110 */
- 0x36, /* 00110110 */
- 0x36, /* 00110110 */
- 0xf6, /* 11110110 */
- 0x06, /* 00000110 */
- 0xf6, /* 11110110 */
- 0x36, /* 00110110 */
- 0x36, /* 00110110 */
- 0x36, /* 00110110 */
- 0x36, /* 00110110 */
- 0x36, /* 00110110 */
- 0x36, /* 00110110 */
- 0x36, /* 00110110 */
- 0x36, /* 00110110 */
-
- /* 186 0xba 'º' */
- 0x36, /* 00110110 */
- 0x36, /* 00110110 */
- 0x36, /* 00110110 */
- 0x36, /* 00110110 */
- 0x36, /* 00110110 */
- 0x36, /* 00110110 */
- 0x36, /* 00110110 */
- 0x36, /* 00110110 */
- 0x36, /* 00110110 */
- 0x36, /* 00110110 */
- 0x36, /* 00110110 */
- 0x36, /* 00110110 */
- 0x36, /* 00110110 */
- 0x36, /* 00110110 */
- 0x36, /* 00110110 */
- 0x36, /* 00110110 */
-
- /* 187 0xbb '»' */
- 0x00, /* 00000000 */
- 0x00, /* 00000000 */
- 0x00, /* 00000000 */
- 0x00, /* 00000000 */
- 0x00, /* 00000000 */
- 0xfe, /* 11111110 */
- 0x06, /* 00000110 */
- 0xf6, /* 11110110 */
- 0x36, /* 00110110 */
- 0x36, /* 00110110 */
- 0x36, /* 00110110 */
- 0x36, /* 00110110 */
- 0x36, /* 00110110 */
- 0x36, /* 00110110 */
- 0x36, /* 00110110 */
- 0x36, /* 00110110 */
-
- /* 188 0xbc '¼' */
- 0x36, /* 00110110 */
- 0x36, /* 00110110 */
- 0x36, /* 00110110 */
- 0x36, /* 00110110 */
- 0x36, /* 00110110 */
- 0xf6, /* 11110110 */
- 0x06, /* 00000110 */
- 0xfe, /* 11111110 */
- 0x00, /* 00000000 */
- 0x00, /* 00000000 */
- 0x00, /* 00000000 */
- 0x00, /* 00000000 */
- 0x00, /* 00000000 */
- 0x00, /* 00000000 */
- 0x00, /* 00000000 */
- 0x00, /* 00000000 */
-
- /* 189 0xbd '½' */
- 0x36, /* 00110110 */
- 0x36, /* 00110110 */
- 0x36, /* 00110110 */
- 0x36, /* 00110110 */
- 0x36, /* 00110110 */
- 0x36, /* 00110110 */
- 0x36, /* 00110110 */
- 0xfe, /* 11111110 */
- 0x00, /* 00000000 */
- 0x00, /* 00000000 */
- 0x00, /* 00000000 */
- 0x00, /* 00000000 */
- 0x00, /* 00000000 */
- 0x00, /* 00000000 */
- 0x00, /* 00000000 */
- 0x00, /* 00000000 */
-
- /* 190 0xbe '¾' */
- 0x18, /* 00011000 */
- 0x18, /* 00011000 */
- 0x18, /* 00011000 */
- 0x18, /* 00011000 */
- 0x18, /* 00011000 */
- 0xf8, /* 11111000 */
- 0x18, /* 00011000 */
- 0xf8, /* 11111000 */
- 0x00, /* 00000000 */
- 0x00, /* 00000000 */
- 0x00, /* 00000000 */
- 0x00, /* 00000000 */
- 0x00, /* 00000000 */
- 0x00, /* 00000000 */
- 0x00, /* 00000000 */
- 0x00, /* 00000000 */
-
- /* 191 0xbf '¿' */
- 0x00, /* 00000000 */
- 0x00, /* 00000000 */
- 0x00, /* 00000000 */
- 0x00, /* 00000000 */
- 0x00, /* 00000000 */
- 0x00, /* 00000000 */
- 0x00, /* 00000000 */
- 0xf8, /* 11111000 */
- 0x18, /* 00011000 */
- 0x18, /* 00011000 */
- 0x18, /* 00011000 */
- 0x18, /* 00011000 */
- 0x18, /* 00011000 */
- 0x18, /* 00011000 */
- 0x18, /* 00011000 */
- 0x18, /* 00011000 */
-
- /* 192 0xc0 'À' */
- 0x18, /* 00011000 */
- 0x18, /* 00011000 */
- 0x18, /* 00011000 */
- 0x18, /* 00011000 */
- 0x18, /* 00011000 */
- 0x18, /* 00011000 */
- 0x18, /* 00011000 */
- 0x1f, /* 00011111 */
- 0x00, /* 00000000 */
- 0x00, /* 00000000 */
- 0x00, /* 00000000 */
- 0x00, /* 00000000 */
- 0x00, /* 00000000 */
- 0x00, /* 00000000 */
- 0x00, /* 00000000 */
- 0x00, /* 00000000 */
-
- /* 193 0xc1 'Á' */
- 0x18, /* 00011000 */
- 0x18, /* 00011000 */
- 0x18, /* 00011000 */
- 0x18, /* 00011000 */
- 0x18, /* 00011000 */
- 0x18, /* 00011000 */
- 0x18, /* 00011000 */
- 0xff, /* 11111111 */
- 0x00, /* 00000000 */
- 0x00, /* 00000000 */
- 0x00, /* 00000000 */
- 0x00, /* 00000000 */
- 0x00, /* 00000000 */
- 0x00, /* 00000000 */
- 0x00, /* 00000000 */
- 0x00, /* 00000000 */
-
- /* 194 0xc2 'Â' */
- 0x00, /* 00000000 */
- 0x00, /* 00000000 */
- 0x00, /* 00000000 */
- 0x00, /* 00000000 */
- 0x00, /* 00000000 */
- 0x00, /* 00000000 */
- 0x00, /* 00000000 */
- 0xff, /* 11111111 */
- 0x18, /* 00011000 */
- 0x18, /* 00011000 */
- 0x18, /* 00011000 */
- 0x18, /* 00011000 */
- 0x18, /* 00011000 */
- 0x18, /* 00011000 */
- 0x18, /* 00011000 */
- 0x18, /* 00011000 */
-
- /* 195 0xc3 'Ã' */
- 0x18, /* 00011000 */
- 0x18, /* 00011000 */
- 0x18, /* 00011000 */
- 0x18, /* 00011000 */
- 0x18, /* 00011000 */
- 0x18, /* 00011000 */
- 0x18, /* 00011000 */
- 0x1f, /* 00011111 */
- 0x18, /* 00011000 */
- 0x18, /* 00011000 */
- 0x18, /* 00011000 */
- 0x18, /* 00011000 */
- 0x18, /* 00011000 */
- 0x18, /* 00011000 */
- 0x18, /* 00011000 */
- 0x18, /* 00011000 */
-
- /* 196 0xc4 'Ä' */
- 0x00, /* 00000000 */
- 0x00, /* 00000000 */
- 0x00, /* 00000000 */
- 0x00, /* 00000000 */
- 0x00, /* 00000000 */
- 0x00, /* 00000000 */
- 0x00, /* 00000000 */
- 0xff, /* 11111111 */
- 0x00, /* 00000000 */
- 0x00, /* 00000000 */
- 0x00, /* 00000000 */
- 0x00, /* 00000000 */
- 0x00, /* 00000000 */
- 0x00, /* 00000000 */
- 0x00, /* 00000000 */
- 0x00, /* 00000000 */
-
- /* 197 0xc5 'Å' */
- 0x18, /* 00011000 */
- 0x18, /* 00011000 */
- 0x18, /* 00011000 */
- 0x18, /* 00011000 */
- 0x18, /* 00011000 */
- 0x18, /* 00011000 */
- 0x18, /* 00011000 */
- 0xff, /* 11111111 */
- 0x18, /* 00011000 */
- 0x18, /* 00011000 */
- 0x18, /* 00011000 */
- 0x18, /* 00011000 */
- 0x18, /* 00011000 */
- 0x18, /* 00011000 */
- 0x18, /* 00011000 */
- 0x18, /* 00011000 */
-
- /* 198 0xc6 'Æ' */
- 0x18, /* 00011000 */
- 0x18, /* 00011000 */
- 0x18, /* 00011000 */
- 0x18, /* 00011000 */
- 0x18, /* 00011000 */
- 0x1f, /* 00011111 */
- 0x18, /* 00011000 */
- 0x1f, /* 00011111 */
- 0x18, /* 00011000 */
- 0x18, /* 00011000 */
- 0x18, /* 00011000 */
- 0x18, /* 00011000 */
- 0x18, /* 00011000 */
- 0x18, /* 00011000 */
- 0x18, /* 00011000 */
- 0x18, /* 00011000 */
-
- /* 199 0xc7 'Ç' */
- 0x36, /* 00110110 */
- 0x36, /* 00110110 */
- 0x36, /* 00110110 */
- 0x36, /* 00110110 */
- 0x36, /* 00110110 */
- 0x36, /* 00110110 */
- 0x36, /* 00110110 */
- 0x37, /* 00110111 */
- 0x36, /* 00110110 */
- 0x36, /* 00110110 */
- 0x36, /* 00110110 */
- 0x36, /* 00110110 */
- 0x36, /* 00110110 */
- 0x36, /* 00110110 */
- 0x36, /* 00110110 */
- 0x36, /* 00110110 */
-
- /* 200 0xc8 'È' */
- 0x36, /* 00110110 */
- 0x36, /* 00110110 */
- 0x36, /* 00110110 */
- 0x36, /* 00110110 */
- 0x36, /* 00110110 */
- 0x37, /* 00110111 */
- 0x30, /* 00110000 */
- 0x3f, /* 00111111 */
- 0x00, /* 00000000 */
- 0x00, /* 00000000 */
- 0x00, /* 00000000 */
- 0x00, /* 00000000 */
- 0x00, /* 00000000 */
- 0x00, /* 00000000 */
- 0x00, /* 00000000 */
- 0x00, /* 00000000 */
-
- /* 201 0xc9 'É' */
- 0x00, /* 00000000 */
- 0x00, /* 00000000 */
- 0x00, /* 00000000 */
- 0x00, /* 00000000 */
- 0x00, /* 00000000 */
- 0x3f, /* 00111111 */
- 0x30, /* 00110000 */
- 0x37, /* 00110111 */
- 0x36, /* 00110110 */
- 0x36, /* 00110110 */
- 0x36, /* 00110110 */
- 0x36, /* 00110110 */
- 0x36, /* 00110110 */
- 0x36, /* 00110110 */
- 0x36, /* 00110110 */
- 0x36, /* 00110110 */
-
- /* 202 0xca 'Ê' */
- 0x36, /* 00110110 */
- 0x36, /* 00110110 */
- 0x36, /* 00110110 */
- 0x36, /* 00110110 */
- 0x36, /* 00110110 */
- 0xf7, /* 11110111 */
- 0x00, /* 00000000 */
- 0xff, /* 11111111 */
- 0x00, /* 00000000 */
- 0x00, /* 00000000 */
- 0x00, /* 00000000 */
- 0x00, /* 00000000 */
- 0x00, /* 00000000 */
- 0x00, /* 00000000 */
- 0x00, /* 00000000 */
- 0x00, /* 00000000 */
-
- /* 203 0xcb 'Ë' */
- 0x00, /* 00000000 */
- 0x00, /* 00000000 */
- 0x00, /* 00000000 */
- 0x00, /* 00000000 */
- 0x00, /* 00000000 */
- 0xff, /* 11111111 */
- 0x00, /* 00000000 */
- 0xf7, /* 11110111 */
- 0x36, /* 00110110 */
- 0x36, /* 00110110 */
- 0x36, /* 00110110 */
- 0x36, /* 00110110 */
- 0x36, /* 00110110 */
- 0x36, /* 00110110 */
- 0x36, /* 00110110 */
- 0x36, /* 00110110 */
-
- /* 204 0xcc 'Ì' */
- 0x36, /* 00110110 */
- 0x36, /* 00110110 */
- 0x36, /* 00110110 */
- 0x36, /* 00110110 */
- 0x36, /* 00110110 */
- 0x37, /* 00110111 */
- 0x30, /* 00110000 */
- 0x37, /* 00110111 */
- 0x36, /* 00110110 */
- 0x36, /* 00110110 */
- 0x36, /* 00110110 */
- 0x36, /* 00110110 */
- 0x36, /* 00110110 */
- 0x36, /* 00110110 */
- 0x36, /* 00110110 */
- 0x36, /* 00110110 */
-
- /* 205 0xcd 'Í' */
- 0x00, /* 00000000 */
- 0x00, /* 00000000 */
- 0x00, /* 00000000 */
- 0x00, /* 00000000 */
- 0x00, /* 00000000 */
- 0xff, /* 11111111 */
- 0x00, /* 00000000 */
- 0xff, /* 11111111 */
- 0x00, /* 00000000 */
- 0x00, /* 00000000 */
- 0x00, /* 00000000 */
- 0x00, /* 00000000 */
- 0x00, /* 00000000 */
- 0x00, /* 00000000 */
- 0x00, /* 00000000 */
- 0x00, /* 00000000 */
-
- /* 206 0xce 'Î' */
- 0x36, /* 00110110 */
- 0x36, /* 00110110 */
- 0x36, /* 00110110 */
- 0x36, /* 00110110 */
- 0x36, /* 00110110 */
- 0xf7, /* 11110111 */
- 0x00, /* 00000000 */
- 0xf7, /* 11110111 */
- 0x36, /* 00110110 */
- 0x36, /* 00110110 */
- 0x36, /* 00110110 */
- 0x36, /* 00110110 */
- 0x36, /* 00110110 */
- 0x36, /* 00110110 */
- 0x36, /* 00110110 */
- 0x36, /* 00110110 */
-
- /* 207 0xcf 'Ï' */
- 0x18, /* 00011000 */
- 0x18, /* 00011000 */
- 0x18, /* 00011000 */
- 0x18, /* 00011000 */
- 0x18, /* 00011000 */
- 0xff, /* 11111111 */
- 0x00, /* 00000000 */
- 0xff, /* 11111111 */
- 0x00, /* 00000000 */
- 0x00, /* 00000000 */
- 0x00, /* 00000000 */
- 0x00, /* 00000000 */
- 0x00, /* 00000000 */
- 0x00, /* 00000000 */
- 0x00, /* 00000000 */
- 0x00, /* 00000000 */
-
- /* 208 0xd0 'Ð' */
- 0x36, /* 00110110 */
- 0x36, /* 00110110 */
- 0x36, /* 00110110 */
- 0x36, /* 00110110 */
- 0x36, /* 00110110 */
- 0x36, /* 00110110 */
- 0x36, /* 00110110 */
- 0xff, /* 11111111 */
- 0x00, /* 00000000 */
- 0x00, /* 00000000 */
- 0x00, /* 00000000 */
- 0x00, /* 00000000 */
- 0x00, /* 00000000 */
- 0x00, /* 00000000 */
- 0x00, /* 00000000 */
- 0x00, /* 00000000 */
-
- /* 209 0xd1 'Ñ' */
- 0x00, /* 00000000 */
- 0x00, /* 00000000 */
- 0x00, /* 00000000 */
- 0x00, /* 00000000 */
- 0x00, /* 00000000 */
- 0xff, /* 11111111 */
- 0x00, /* 00000000 */
- 0xff, /* 11111111 */
- 0x18, /* 00011000 */
- 0x18, /* 00011000 */
- 0x18, /* 00011000 */
- 0x18, /* 00011000 */
- 0x18, /* 00011000 */
- 0x18, /* 00011000 */
- 0x18, /* 00011000 */
- 0x18, /* 00011000 */
-
- /* 210 0xd2 'Ò' */
- 0x00, /* 00000000 */
- 0x00, /* 00000000 */
- 0x00, /* 00000000 */
- 0x00, /* 00000000 */
- 0x00, /* 00000000 */
- 0x00, /* 00000000 */
- 0x00, /* 00000000 */
- 0xff, /* 11111111 */
- 0x36, /* 00110110 */
- 0x36, /* 00110110 */
- 0x36, /* 00110110 */
- 0x36, /* 00110110 */
- 0x36, /* 00110110 */
- 0x36, /* 00110110 */
- 0x36, /* 00110110 */
- 0x36, /* 00110110 */
-
- /* 211 0xd3 'Ó' */
- 0x36, /* 00110110 */
- 0x36, /* 00110110 */
- 0x36, /* 00110110 */
- 0x36, /* 00110110 */
- 0x36, /* 00110110 */
- 0x36, /* 00110110 */
- 0x36, /* 00110110 */
- 0x3f, /* 00111111 */
- 0x00, /* 00000000 */
- 0x00, /* 00000000 */
- 0x00, /* 00000000 */
- 0x00, /* 00000000 */
- 0x00, /* 00000000 */
- 0x00, /* 00000000 */
- 0x00, /* 00000000 */
- 0x00, /* 00000000 */
-
- /* 212 0xd4 'Ô' */
- 0x18, /* 00011000 */
- 0x18, /* 00011000 */
- 0x18, /* 00011000 */
- 0x18, /* 00011000 */
- 0x18, /* 00011000 */
- 0x1f, /* 00011111 */
- 0x18, /* 00011000 */
- 0x1f, /* 00011111 */
- 0x00, /* 00000000 */
- 0x00, /* 00000000 */
- 0x00, /* 00000000 */
- 0x00, /* 00000000 */
- 0x00, /* 00000000 */
- 0x00, /* 00000000 */
- 0x00, /* 00000000 */
- 0x00, /* 00000000 */
-
- /* 213 0xd5 'Õ' */
- 0x00, /* 00000000 */
- 0x00, /* 00000000 */
- 0x00, /* 00000000 */
- 0x00, /* 00000000 */
- 0x00, /* 00000000 */
- 0x1f, /* 00011111 */
- 0x18, /* 00011000 */
- 0x1f, /* 00011111 */
- 0x18, /* 00011000 */
- 0x18, /* 00011000 */
- 0x18, /* 00011000 */
- 0x18, /* 00011000 */
- 0x18, /* 00011000 */
- 0x18, /* 00011000 */
- 0x18, /* 00011000 */
- 0x18, /* 00011000 */
-
- /* 214 0xd6 'Ö' */
- 0x00, /* 00000000 */
- 0x00, /* 00000000 */
- 0x00, /* 00000000 */
- 0x00, /* 00000000 */
- 0x00, /* 00000000 */
- 0x00, /* 00000000 */
- 0x00, /* 00000000 */
- 0x3f, /* 00111111 */
- 0x36, /* 00110110 */
- 0x36, /* 00110110 */
- 0x36, /* 00110110 */
- 0x36, /* 00110110 */
- 0x36, /* 00110110 */
- 0x36, /* 00110110 */
- 0x36, /* 00110110 */
- 0x36, /* 00110110 */
-
- /* 215 0xd7 '×' */
- 0x36, /* 00110110 */
- 0x36, /* 00110110 */
- 0x36, /* 00110110 */
- 0x36, /* 00110110 */
- 0x36, /* 00110110 */
- 0x36, /* 00110110 */
- 0x36, /* 00110110 */
- 0xff, /* 11111111 */
- 0x36, /* 00110110 */
- 0x36, /* 00110110 */
- 0x36, /* 00110110 */
- 0x36, /* 00110110 */
- 0x36, /* 00110110 */
- 0x36, /* 00110110 */
- 0x36, /* 00110110 */
- 0x36, /* 00110110 */
-
- /* 216 0xd8 'Ø' */
- 0x18, /* 00011000 */
- 0x18, /* 00011000 */
- 0x18, /* 00011000 */
- 0x18, /* 00011000 */
- 0x18, /* 00011000 */
- 0xff, /* 11111111 */
- 0x18, /* 00011000 */
- 0xff, /* 11111111 */
- 0x18, /* 00011000 */
- 0x18, /* 00011000 */
- 0x18, /* 00011000 */
- 0x18, /* 00011000 */
- 0x18, /* 00011000 */
- 0x18, /* 00011000 */
- 0x18, /* 00011000 */
- 0x18, /* 00011000 */
-
- /* 217 0xd9 'Ù' */
- 0x18, /* 00011000 */
- 0x18, /* 00011000 */
- 0x18, /* 00011000 */
- 0x18, /* 00011000 */
- 0x18, /* 00011000 */
- 0x18, /* 00011000 */
- 0x18, /* 00011000 */
- 0xf8, /* 11111000 */
- 0x00, /* 00000000 */
- 0x00, /* 00000000 */
- 0x00, /* 00000000 */
- 0x00, /* 00000000 */
- 0x00, /* 00000000 */
- 0x00, /* 00000000 */
- 0x00, /* 00000000 */
- 0x00, /* 00000000 */
-
- /* 218 0xda 'Ú' */
- 0x00, /* 00000000 */
- 0x00, /* 00000000 */
- 0x00, /* 00000000 */
- 0x00, /* 00000000 */
- 0x00, /* 00000000 */
- 0x00, /* 00000000 */
- 0x00, /* 00000000 */
- 0x1f, /* 00011111 */
- 0x18, /* 00011000 */
- 0x18, /* 00011000 */
- 0x18, /* 00011000 */
- 0x18, /* 00011000 */
- 0x18, /* 00011000 */
- 0x18, /* 00011000 */
- 0x18, /* 00011000 */
- 0x18, /* 00011000 */
-
- /* 219 0xdb 'Û' */
- 0xff, /* 11111111 */
- 0xff, /* 11111111 */
- 0xff, /* 11111111 */
- 0xff, /* 11111111 */
- 0xff, /* 11111111 */
- 0xff, /* 11111111 */
- 0xff, /* 11111111 */
- 0xff, /* 11111111 */
- 0xff, /* 11111111 */
- 0xff, /* 11111111 */
- 0xff, /* 11111111 */
- 0xff, /* 11111111 */
- 0xff, /* 11111111 */
- 0xff, /* 11111111 */
- 0xff, /* 11111111 */
- 0xff, /* 11111111 */
-
- /* 220 0xdc 'Ü' */
- 0x00, /* 00000000 */
- 0x00, /* 00000000 */
- 0x00, /* 00000000 */
- 0x00, /* 00000000 */
- 0x00, /* 00000000 */
- 0x00, /* 00000000 */
- 0x00, /* 00000000 */
- 0xff, /* 11111111 */
- 0xff, /* 11111111 */
- 0xff, /* 11111111 */
- 0xff, /* 11111111 */
- 0xff, /* 11111111 */
- 0xff, /* 11111111 */
- 0xff, /* 11111111 */
- 0xff, /* 11111111 */
- 0xff, /* 11111111 */
-
- /* 221 0xdd 'Ý' */
- 0xf0, /* 11110000 */
- 0xf0, /* 11110000 */
- 0xf0, /* 11110000 */
- 0xf0, /* 11110000 */
- 0xf0, /* 11110000 */
- 0xf0, /* 11110000 */
- 0xf0, /* 11110000 */
- 0xf0, /* 11110000 */
- 0xf0, /* 11110000 */
- 0xf0, /* 11110000 */
- 0xf0, /* 11110000 */
- 0xf0, /* 11110000 */
- 0xf0, /* 11110000 */
- 0xf0, /* 11110000 */
- 0xf0, /* 11110000 */
- 0xf0, /* 11110000 */
-
- /* 222 0xde 'Þ' */
- 0x0f, /* 00001111 */
- 0x0f, /* 00001111 */
- 0x0f, /* 00001111 */
- 0x0f, /* 00001111 */
- 0x0f, /* 00001111 */
- 0x0f, /* 00001111 */
- 0x0f, /* 00001111 */
- 0x0f, /* 00001111 */
- 0x0f, /* 00001111 */
- 0x0f, /* 00001111 */
- 0x0f, /* 00001111 */
- 0x0f, /* 00001111 */
- 0x0f, /* 00001111 */
- 0x0f, /* 00001111 */
- 0x0f, /* 00001111 */
- 0x0f, /* 00001111 */
-
- /* 223 0xdf 'ß' */
- 0xff, /* 11111111 */
- 0xff, /* 11111111 */
- 0xff, /* 11111111 */
- 0xff, /* 11111111 */
- 0xff, /* 11111111 */
- 0xff, /* 11111111 */
- 0xff, /* 11111111 */
- 0x00, /* 00000000 */
- 0x00, /* 00000000 */
- 0x00, /* 00000000 */
- 0x00, /* 00000000 */
- 0x00, /* 00000000 */
- 0x00, /* 00000000 */
- 0x00, /* 00000000 */
- 0x00, /* 00000000 */
- 0x00, /* 00000000 */
-
- /* 224 0xe0 'à' */
- 0x00, /* 00000000 */
- 0x00, /* 00000000 */
- 0x00, /* 00000000 */
- 0x00, /* 00000000 */
- 0x00, /* 00000000 */
- 0x76, /* 01110110 */
- 0xdc, /* 11011100 */
- 0xd8, /* 11011000 */
- 0xd8, /* 11011000 */
- 0xd8, /* 11011000 */
- 0xdc, /* 11011100 */
- 0x76, /* 01110110 */
- 0x00, /* 00000000 */
- 0x00, /* 00000000 */
- 0x00, /* 00000000 */
- 0x00, /* 00000000 */
-
- /* 225 0xe1 'á' */
- 0x00, /* 00000000 */
- 0x00, /* 00000000 */
- 0x78, /* 01111000 */
- 0xcc, /* 11001100 */
- 0xcc, /* 11001100 */
- 0xcc, /* 11001100 */
- 0xd8, /* 11011000 */
- 0xcc, /* 11001100 */
- 0xc6, /* 11000110 */
- 0xc6, /* 11000110 */
- 0xc6, /* 11000110 */
- 0xcc, /* 11001100 */
- 0x00, /* 00000000 */
- 0x00, /* 00000000 */
- 0x00, /* 00000000 */
- 0x00, /* 00000000 */
-
- /* 226 0xe2 'â' */
- 0x00, /* 00000000 */
- 0x00, /* 00000000 */
- 0xfe, /* 11111110 */
- 0xc6, /* 11000110 */
- 0xc6, /* 11000110 */
- 0xc0, /* 11000000 */
- 0xc0, /* 11000000 */
- 0xc0, /* 11000000 */
- 0xc0, /* 11000000 */
- 0xc0, /* 11000000 */
- 0xc0, /* 11000000 */
- 0xc0, /* 11000000 */
- 0x00, /* 00000000 */
- 0x00, /* 00000000 */
- 0x00, /* 00000000 */
- 0x00, /* 00000000 */
-
- /* 227 0xe3 'ã' */
- 0x00, /* 00000000 */
- 0x00, /* 00000000 */
- 0x00, /* 00000000 */
- 0x00, /* 00000000 */
- 0x00, /* 00000000 */
- 0xfe, /* 11111110 */
- 0x6c, /* 01101100 */
- 0x6c, /* 01101100 */
- 0x6c, /* 01101100 */
- 0x6c, /* 01101100 */
- 0x6c, /* 01101100 */
- 0x6c, /* 01101100 */
- 0x00, /* 00000000 */
- 0x00, /* 00000000 */
- 0x00, /* 00000000 */
- 0x00, /* 00000000 */
-
- /* 228 0xe4 'ä' */
- 0x00, /* 00000000 */
- 0x00, /* 00000000 */
- 0xfe, /* 11111110 */
- 0xc6, /* 11000110 */
- 0x60, /* 01100000 */
- 0x30, /* 00110000 */
- 0x18, /* 00011000 */
- 0x18, /* 00011000 */
- 0x30, /* 00110000 */
- 0x60, /* 01100000 */
- 0xc6, /* 11000110 */
- 0xfe, /* 11111110 */
- 0x00, /* 00000000 */
- 0x00, /* 00000000 */
- 0x00, /* 00000000 */
- 0x00, /* 00000000 */
-
- /* 229 0xe5 'å' */
- 0x00, /* 00000000 */
- 0x00, /* 00000000 */
- 0x00, /* 00000000 */
- 0x00, /* 00000000 */
- 0x00, /* 00000000 */
- 0x7e, /* 01111110 */
- 0xd8, /* 11011000 */
- 0xd8, /* 11011000 */
- 0xd8, /* 11011000 */
- 0xd8, /* 11011000 */
- 0xd8, /* 11011000 */
- 0x70, /* 01110000 */
- 0x00, /* 00000000 */
- 0x00, /* 00000000 */
- 0x00, /* 00000000 */
- 0x00, /* 00000000 */
-
- /* 230 0xe6 'æ' */
- 0x00, /* 00000000 */
- 0x00, /* 00000000 */
- 0x00, /* 00000000 */
- 0x00, /* 00000000 */
- 0x00, /* 00000000 */
- 0x66, /* 01100110 */
- 0x66, /* 01100110 */
- 0x66, /* 01100110 */
- 0x66, /* 01100110 */
- 0x66, /* 01100110 */
- 0x66, /* 01100110 */
- 0x7c, /* 01111100 */
- 0x60, /* 01100000 */
- 0x60, /* 01100000 */
- 0xc0, /* 11000000 */
- 0x00, /* 00000000 */
-
- /* 231 0xe7 'ç' */
- 0x00, /* 00000000 */
- 0x00, /* 00000000 */
- 0x00, /* 00000000 */
- 0x00, /* 00000000 */
- 0x76, /* 01110110 */
- 0xdc, /* 11011100 */
- 0x18, /* 00011000 */
- 0x18, /* 00011000 */
- 0x18, /* 00011000 */
- 0x18, /* 00011000 */
- 0x18, /* 00011000 */
- 0x18, /* 00011000 */
- 0x00, /* 00000000 */
- 0x00, /* 00000000 */
- 0x00, /* 00000000 */
- 0x00, /* 00000000 */
-
- /* 232 0xe8 'è' */
- 0x00, /* 00000000 */
- 0x00, /* 00000000 */
- 0x7e, /* 01111110 */
- 0x18, /* 00011000 */
- 0x3c, /* 00111100 */
- 0x66, /* 01100110 */
- 0x66, /* 01100110 */
- 0x66, /* 01100110 */
- 0x66, /* 01100110 */
- 0x3c, /* 00111100 */
- 0x18, /* 00011000 */
- 0x7e, /* 01111110 */
- 0x00, /* 00000000 */
- 0x00, /* 00000000 */
- 0x00, /* 00000000 */
- 0x00, /* 00000000 */
-
- /* 233 0xe9 'é' */
- 0x00, /* 00000000 */
- 0x00, /* 00000000 */
- 0x38, /* 00111000 */
- 0x6c, /* 01101100 */
- 0xc6, /* 11000110 */
- 0xc6, /* 11000110 */
- 0xfe, /* 11111110 */
- 0xc6, /* 11000110 */
- 0xc6, /* 11000110 */
- 0xc6, /* 11000110 */
- 0x6c, /* 01101100 */
- 0x38, /* 00111000 */
- 0x00, /* 00000000 */
- 0x00, /* 00000000 */
- 0x00, /* 00000000 */
- 0x00, /* 00000000 */
-
- /* 234 0xea 'ê' */
- 0x00, /* 00000000 */
- 0x00, /* 00000000 */
- 0x38, /* 00111000 */
- 0x6c, /* 01101100 */
- 0xc6, /* 11000110 */
- 0xc6, /* 11000110 */
- 0xc6, /* 11000110 */
- 0x6c, /* 01101100 */
- 0x6c, /* 01101100 */
- 0x6c, /* 01101100 */
- 0x6c, /* 01101100 */
- 0xee, /* 11101110 */
- 0x00, /* 00000000 */
- 0x00, /* 00000000 */
- 0x00, /* 00000000 */
- 0x00, /* 00000000 */
-
- /* 235 0xeb 'ë' */
- 0x00, /* 00000000 */
- 0x00, /* 00000000 */
- 0x1e, /* 00011110 */
- 0x30, /* 00110000 */
- 0x18, /* 00011000 */
- 0x0c, /* 00001100 */
- 0x3e, /* 00111110 */
- 0x66, /* 01100110 */
- 0x66, /* 01100110 */
- 0x66, /* 01100110 */
- 0x66, /* 01100110 */
- 0x3c, /* 00111100 */
- 0x00, /* 00000000 */
- 0x00, /* 00000000 */
- 0x00, /* 00000000 */
- 0x00, /* 00000000 */
-
- /* 236 0xec 'ì' */
- 0x00, /* 00000000 */
- 0x00, /* 00000000 */
- 0x00, /* 00000000 */
- 0x00, /* 00000000 */
- 0x00, /* 00000000 */
- 0x7e, /* 01111110 */
- 0xdb, /* 11011011 */
- 0xdb, /* 11011011 */
- 0xdb, /* 11011011 */
- 0x7e, /* 01111110 */
- 0x00, /* 00000000 */
- 0x00, /* 00000000 */
- 0x00, /* 00000000 */
- 0x00, /* 00000000 */
- 0x00, /* 00000000 */
- 0x00, /* 00000000 */
-
- /* 237 0xed 'í' */
- 0x00, /* 00000000 */
- 0x00, /* 00000000 */
- 0x00, /* 00000000 */
- 0x03, /* 00000011 */
- 0x06, /* 00000110 */
- 0x7e, /* 01111110 */
- 0xdb, /* 11011011 */
- 0xdb, /* 11011011 */
- 0xf3, /* 11110011 */
- 0x7e, /* 01111110 */
- 0x60, /* 01100000 */
- 0xc0, /* 11000000 */
- 0x00, /* 00000000 */
- 0x00, /* 00000000 */
- 0x00, /* 00000000 */
- 0x00, /* 00000000 */
-
- /* 238 0xee 'î' */
- 0x00, /* 00000000 */
- 0x00, /* 00000000 */
- 0x1c, /* 00011100 */
- 0x30, /* 00110000 */
- 0x60, /* 01100000 */
- 0x60, /* 01100000 */
- 0x7c, /* 01111100 */
- 0x60, /* 01100000 */
- 0x60, /* 01100000 */
- 0x60, /* 01100000 */
- 0x30, /* 00110000 */
- 0x1c, /* 00011100 */
- 0x00, /* 00000000 */
- 0x00, /* 00000000 */
- 0x00, /* 00000000 */
- 0x00, /* 00000000 */
-
- /* 239 0xef 'ï' */
- 0x00, /* 00000000 */
- 0x00, /* 00000000 */
- 0x00, /* 00000000 */
- 0x7c, /* 01111100 */
- 0xc6, /* 11000110 */
- 0xc6, /* 11000110 */
- 0xc6, /* 11000110 */
- 0xc6, /* 11000110 */
- 0xc6, /* 11000110 */
- 0xc6, /* 11000110 */
- 0xc6, /* 11000110 */
- 0xc6, /* 11000110 */
- 0x00, /* 00000000 */
- 0x00, /* 00000000 */
- 0x00, /* 00000000 */
- 0x00, /* 00000000 */
-
- /* 240 0xf0 'ð' */
- 0x00, /* 00000000 */
- 0x00, /* 00000000 */
- 0x00, /* 00000000 */
- 0x00, /* 00000000 */
- 0xfe, /* 11111110 */
- 0x00, /* 00000000 */
- 0x00, /* 00000000 */
- 0xfe, /* 11111110 */
- 0x00, /* 00000000 */
- 0x00, /* 00000000 */
- 0xfe, /* 11111110 */
- 0x00, /* 00000000 */
- 0x00, /* 00000000 */
- 0x00, /* 00000000 */
- 0x00, /* 00000000 */
- 0x00, /* 00000000 */
-
- /* 241 0xf1 'ñ' */
- 0x00, /* 00000000 */
- 0x00, /* 00000000 */
- 0x00, /* 00000000 */
- 0x00, /* 00000000 */
- 0x18, /* 00011000 */
- 0x18, /* 00011000 */
- 0x7e, /* 01111110 */
- 0x18, /* 00011000 */
- 0x18, /* 00011000 */
- 0x00, /* 00000000 */
- 0x00, /* 00000000 */
- 0x7e, /* 01111110 */
- 0x00, /* 00000000 */
- 0x00, /* 00000000 */
- 0x00, /* 00000000 */
- 0x00, /* 00000000 */
-
- /* 242 0xf2 'ò' */
- 0x00, /* 00000000 */
- 0x00, /* 00000000 */
- 0x00, /* 00000000 */
- 0x30, /* 00110000 */
- 0x18, /* 00011000 */
- 0x0c, /* 00001100 */
- 0x06, /* 00000110 */
- 0x0c, /* 00001100 */
- 0x18, /* 00011000 */
- 0x30, /* 00110000 */
- 0x00, /* 00000000 */
- 0x7e, /* 01111110 */
- 0x00, /* 00000000 */
- 0x00, /* 00000000 */
- 0x00, /* 00000000 */
- 0x00, /* 00000000 */
-
- /* 243 0xf3 'ó' */
- 0x00, /* 00000000 */
- 0x00, /* 00000000 */
- 0x00, /* 00000000 */
- 0x0c, /* 00001100 */
- 0x18, /* 00011000 */
- 0x30, /* 00110000 */
- 0x60, /* 01100000 */
- 0x30, /* 00110000 */
- 0x18, /* 00011000 */
- 0x0c, /* 00001100 */
- 0x00, /* 00000000 */
- 0x7e, /* 01111110 */
- 0x00, /* 00000000 */
- 0x00, /* 00000000 */
- 0x00, /* 00000000 */
- 0x00, /* 00000000 */
-
- /* 244 0xf4 'ô' */
- 0x00, /* 00000000 */
- 0x00, /* 00000000 */
- 0x0e, /* 00001110 */
- 0x1b, /* 00011011 */
- 0x1b, /* 00011011 */
- 0x18, /* 00011000 */
- 0x18, /* 00011000 */
- 0x18, /* 00011000 */
- 0x18, /* 00011000 */
- 0x18, /* 00011000 */
- 0x18, /* 00011000 */
- 0x18, /* 00011000 */
- 0x18, /* 00011000 */
- 0x18, /* 00011000 */
- 0x18, /* 00011000 */
- 0x18, /* 00011000 */
-
- /* 245 0xf5 'õ' */
- 0x18, /* 00011000 */
- 0x18, /* 00011000 */
- 0x18, /* 00011000 */
- 0x18, /* 00011000 */
- 0x18, /* 00011000 */
- 0x18, /* 00011000 */
- 0x18, /* 00011000 */
- 0x18, /* 00011000 */
- 0x18, /* 00011000 */
- 0xd8, /* 11011000 */
- 0xd8, /* 11011000 */
- 0xd8, /* 11011000 */
- 0x70, /* 01110000 */
- 0x00, /* 00000000 */
- 0x00, /* 00000000 */
- 0x00, /* 00000000 */
-
- /* 246 0xf6 'ö' */
- 0x00, /* 00000000 */
- 0x00, /* 00000000 */
- 0x00, /* 00000000 */
- 0x00, /* 00000000 */
- 0x00, /* 00000000 */
- 0x18, /* 00011000 */
- 0x00, /* 00000000 */
- 0x7e, /* 01111110 */
- 0x00, /* 00000000 */
- 0x18, /* 00011000 */
- 0x00, /* 00000000 */
- 0x00, /* 00000000 */
- 0x00, /* 00000000 */
- 0x00, /* 00000000 */
- 0x00, /* 00000000 */
- 0x00, /* 00000000 */
-
- /* 247 0xf7 '÷' */
- 0x00, /* 00000000 */
- 0x00, /* 00000000 */
- 0x00, /* 00000000 */
- 0x00, /* 00000000 */
- 0x00, /* 00000000 */
- 0x76, /* 01110110 */
- 0xdc, /* 11011100 */
- 0x00, /* 00000000 */
- 0x76, /* 01110110 */
- 0xdc, /* 11011100 */
- 0x00, /* 00000000 */
- 0x00, /* 00000000 */
- 0x00, /* 00000000 */
- 0x00, /* 00000000 */
- 0x00, /* 00000000 */
- 0x00, /* 00000000 */
-
- /* 248 0xf8 'ø' */
- 0x00, /* 00000000 */
- 0x38, /* 00111000 */
- 0x6c, /* 01101100 */
- 0x6c, /* 01101100 */
- 0x38, /* 00111000 */
- 0x00, /* 00000000 */
- 0x00, /* 00000000 */
- 0x00, /* 00000000 */
- 0x00, /* 00000000 */
- 0x00, /* 00000000 */
- 0x00, /* 00000000 */
- 0x00, /* 00000000 */
- 0x00, /* 00000000 */
- 0x00, /* 00000000 */
- 0x00, /* 00000000 */
- 0x00, /* 00000000 */
-
- /* 249 0xf9 'ù' */
- 0x00, /* 00000000 */
- 0x00, /* 00000000 */
- 0x00, /* 00000000 */
- 0x00, /* 00000000 */
- 0x00, /* 00000000 */
- 0x00, /* 00000000 */
- 0x00, /* 00000000 */
- 0x18, /* 00011000 */
- 0x18, /* 00011000 */
- 0x00, /* 00000000 */
- 0x00, /* 00000000 */
- 0x00, /* 00000000 */
- 0x00, /* 00000000 */
- 0x00, /* 00000000 */
- 0x00, /* 00000000 */
- 0x00, /* 00000000 */
-
- /* 250 0xfa 'ú' */
- 0x00, /* 00000000 */
- 0x00, /* 00000000 */
- 0x00, /* 00000000 */
- 0x00, /* 00000000 */
- 0x00, /* 00000000 */
- 0x00, /* 00000000 */
- 0x00, /* 00000000 */
- 0x18, /* 00011000 */
- 0x00, /* 00000000 */
- 0x00, /* 00000000 */
- 0x00, /* 00000000 */
- 0x00, /* 00000000 */
- 0x00, /* 00000000 */
- 0x00, /* 00000000 */
- 0x00, /* 00000000 */
- 0x00, /* 00000000 */
-
- /* 251 0xfb 'û' */
- 0x00, /* 00000000 */
- 0x0f, /* 00001111 */
- 0x0c, /* 00001100 */
- 0x0c, /* 00001100 */
- 0x0c, /* 00001100 */
- 0x0c, /* 00001100 */
- 0x0c, /* 00001100 */
- 0xec, /* 11101100 */
- 0x6c, /* 01101100 */
- 0x6c, /* 01101100 */
- 0x3c, /* 00111100 */
- 0x1c, /* 00011100 */
- 0x00, /* 00000000 */
- 0x00, /* 00000000 */
- 0x00, /* 00000000 */
- 0x00, /* 00000000 */
-
- /* 252 0xfc 'ü' */
- 0x00, /* 00000000 */
- 0x6c, /* 01101100 */
- 0x36, /* 00110110 */
- 0x36, /* 00110110 */
- 0x36, /* 00110110 */
- 0x36, /* 00110110 */
- 0x36, /* 00110110 */
- 0x00, /* 00000000 */
- 0x00, /* 00000000 */
- 0x00, /* 00000000 */
- 0x00, /* 00000000 */
- 0x00, /* 00000000 */
- 0x00, /* 00000000 */
- 0x00, /* 00000000 */
- 0x00, /* 00000000 */
- 0x00, /* 00000000 */
-
- /* 253 0xfd 'ý' */
- 0x00, /* 00000000 */
- 0x3c, /* 00111100 */
- 0x66, /* 01100110 */
- 0x0c, /* 00001100 */
- 0x18, /* 00011000 */
- 0x32, /* 00110010 */
- 0x7e, /* 01111110 */
- 0x00, /* 00000000 */
- 0x00, /* 00000000 */
- 0x00, /* 00000000 */
- 0x00, /* 00000000 */
- 0x00, /* 00000000 */
- 0x00, /* 00000000 */
- 0x00, /* 00000000 */
- 0x00, /* 00000000 */
- 0x00, /* 00000000 */
-
- /* 254 0xfe 'þ' */
- 0x00, /* 00000000 */
- 0x00, /* 00000000 */
- 0x00, /* 00000000 */
- 0x00, /* 00000000 */
- 0x7e, /* 01111110 */
- 0x7e, /* 01111110 */
- 0x7e, /* 01111110 */
- 0x7e, /* 01111110 */
- 0x7e, /* 01111110 */
- 0x7e, /* 01111110 */
- 0x7e, /* 01111110 */
- 0x00, /* 00000000 */
- 0x00, /* 00000000 */
- 0x00, /* 00000000 */
- 0x00, /* 00000000 */
- 0x00, /* 00000000 */
-
- /* 255 0xff 'ÿ' */
- 0x00, /* 00000000 */
- 0x00, /* 00000000 */
- 0x00, /* 00000000 */
- 0x00, /* 00000000 */
- 0x00, /* 00000000 */
- 0x00, /* 00000000 */
- 0x00, /* 00000000 */
- 0x00, /* 00000000 */
- 0x00, /* 00000000 */
- 0x00, /* 00000000 */
- 0x00, /* 00000000 */
- 0x00, /* 00000000 */
- 0x00, /* 00000000 */
- 0x00, /* 00000000 */
- 0x00, /* 00000000 */
- 0x00, /* 00000000 */
-
-};
-
-#endif
+#endif /* _VIDEO_FONT_ */
diff --git a/include/video_font_data.h b/include/video_font_data.h
new file mode 100644
index 0000000..c7a8b9b
--- /dev/null
+++ b/include/video_font_data.h
@@ -0,0 +1,4639 @@
+/*
+ * (C) Copyright 2000
+ * Paolo Scaffardi, AIRVENT SAM s.p.a - RIMINI(ITALY), arsenio@tin.it
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#ifndef _VIDEO_FONT_DATA_
+#define _VIDEO_FONT_DATA_
+
+static unsigned char video_fontdata[VIDEO_FONT_SIZE] = {
+
+ /* 0 0x00 '^@' */
+ 0x00, /* 00000000 */
+ 0x00, /* 00000000 */
+ 0x00, /* 00000000 */
+ 0x00, /* 00000000 */
+ 0x00, /* 00000000 */
+ 0x00, /* 00000000 */
+ 0x00, /* 00000000 */
+ 0x00, /* 00000000 */
+ 0x00, /* 00000000 */
+ 0x00, /* 00000000 */
+ 0x00, /* 00000000 */
+ 0x00, /* 00000000 */
+ 0x00, /* 00000000 */
+ 0x00, /* 00000000 */
+ 0x00, /* 00000000 */
+ 0x00, /* 00000000 */
+
+ /* 1 0x01 '^A' */
+ 0x00, /* 00000000 */
+ 0x00, /* 00000000 */
+ 0x7e, /* 01111110 */
+ 0x81, /* 10000001 */
+ 0xa5, /* 10100101 */
+ 0x81, /* 10000001 */
+ 0x81, /* 10000001 */
+ 0xbd, /* 10111101 */
+ 0x99, /* 10011001 */
+ 0x81, /* 10000001 */
+ 0x81, /* 10000001 */
+ 0x7e, /* 01111110 */
+ 0x00, /* 00000000 */
+ 0x00, /* 00000000 */
+ 0x00, /* 00000000 */
+ 0x00, /* 00000000 */
+
+ /* 2 0x02 '^B' */
+ 0x00, /* 00000000 */
+ 0x00, /* 00000000 */
+ 0x7e, /* 01111110 */
+ 0xff, /* 11111111 */
+ 0xdb, /* 11011011 */
+ 0xff, /* 11111111 */
+ 0xff, /* 11111111 */
+ 0xc3, /* 11000011 */
+ 0xe7, /* 11100111 */
+ 0xff, /* 11111111 */
+ 0xff, /* 11111111 */
+ 0x7e, /* 01111110 */
+ 0x00, /* 00000000 */
+ 0x00, /* 00000000 */
+ 0x00, /* 00000000 */
+ 0x00, /* 00000000 */
+
+ /* 3 0x03 '^C' */
+ 0x00, /* 00000000 */
+ 0x00, /* 00000000 */
+ 0x00, /* 00000000 */
+ 0x00, /* 00000000 */
+ 0x6c, /* 01101100 */
+ 0xfe, /* 11111110 */
+ 0xfe, /* 11111110 */
+ 0xfe, /* 11111110 */
+ 0xfe, /* 11111110 */
+ 0x7c, /* 01111100 */
+ 0x38, /* 00111000 */
+ 0x10, /* 00010000 */
+ 0x00, /* 00000000 */
+ 0x00, /* 00000000 */
+ 0x00, /* 00000000 */
+ 0x00, /* 00000000 */
+
+ /* 4 0x04 '^D' */
+ 0x00, /* 00000000 */
+ 0x00, /* 00000000 */
+ 0x00, /* 00000000 */
+ 0x00, /* 00000000 */
+ 0x10, /* 00010000 */
+ 0x38, /* 00111000 */
+ 0x7c, /* 01111100 */
+ 0xfe, /* 11111110 */
+ 0x7c, /* 01111100 */
+ 0x38, /* 00111000 */
+ 0x10, /* 00010000 */
+ 0x00, /* 00000000 */
+ 0x00, /* 00000000 */
+ 0x00, /* 00000000 */
+ 0x00, /* 00000000 */
+ 0x00, /* 00000000 */
+
+ /* 5 0x05 '^E' */
+ 0x00, /* 00000000 */
+ 0x00, /* 00000000 */
+ 0x00, /* 00000000 */
+ 0x18, /* 00011000 */
+ 0x3c, /* 00111100 */
+ 0x3c, /* 00111100 */
+ 0xe7, /* 11100111 */
+ 0xe7, /* 11100111 */
+ 0xe7, /* 11100111 */
+ 0x18, /* 00011000 */
+ 0x18, /* 00011000 */
+ 0x3c, /* 00111100 */
+ 0x00, /* 00000000 */
+ 0x00, /* 00000000 */
+ 0x00, /* 00000000 */
+ 0x00, /* 00000000 */
+
+ /* 6 0x06 '^F' */
+ 0x00, /* 00000000 */
+ 0x00, /* 00000000 */
+ 0x00, /* 00000000 */
+ 0x18, /* 00011000 */
+ 0x3c, /* 00111100 */
+ 0x7e, /* 01111110 */
+ 0xff, /* 11111111 */
+ 0xff, /* 11111111 */
+ 0x7e, /* 01111110 */
+ 0x18, /* 00011000 */
+ 0x18, /* 00011000 */
+ 0x3c, /* 00111100 */
+ 0x00, /* 00000000 */
+ 0x00, /* 00000000 */
+ 0x00, /* 00000000 */
+ 0x00, /* 00000000 */
+
+ /* 7 0x07 '^G' */
+ 0x00, /* 00000000 */
+ 0x00, /* 00000000 */
+ 0x00, /* 00000000 */
+ 0x00, /* 00000000 */
+ 0x00, /* 00000000 */
+ 0x00, /* 00000000 */
+ 0x18, /* 00011000 */
+ 0x3c, /* 00111100 */
+ 0x3c, /* 00111100 */
+ 0x18, /* 00011000 */
+ 0x00, /* 00000000 */
+ 0x00, /* 00000000 */
+ 0x00, /* 00000000 */
+ 0x00, /* 00000000 */
+ 0x00, /* 00000000 */
+ 0x00, /* 00000000 */
+
+ /* 8 0x08 '^H' */
+ 0xff, /* 11111111 */
+ 0xff, /* 11111111 */
+ 0xff, /* 11111111 */
+ 0xff, /* 11111111 */
+ 0xff, /* 11111111 */
+ 0xff, /* 11111111 */
+ 0xe7, /* 11100111 */
+ 0xc3, /* 11000011 */
+ 0xc3, /* 11000011 */
+ 0xe7, /* 11100111 */
+ 0xff, /* 11111111 */
+ 0xff, /* 11111111 */
+ 0xff, /* 11111111 */
+ 0xff, /* 11111111 */
+ 0xff, /* 11111111 */
+ 0xff, /* 11111111 */
+
+ /* 9 0x09 '^I' */
+ 0x00, /* 00000000 */
+ 0x00, /* 00000000 */
+ 0x00, /* 00000000 */
+ 0x00, /* 00000000 */
+ 0x00, /* 00000000 */
+ 0x3c, /* 00111100 */
+ 0x66, /* 01100110 */
+ 0x42, /* 01000010 */
+ 0x42, /* 01000010 */
+ 0x66, /* 01100110 */
+ 0x3c, /* 00111100 */
+ 0x00, /* 00000000 */
+ 0x00, /* 00000000 */
+ 0x00, /* 00000000 */
+ 0x00, /* 00000000 */
+ 0x00, /* 00000000 */
+
+ /* 10 0x0a '^J' */
+ 0xff, /* 11111111 */
+ 0xff, /* 11111111 */
+ 0xff, /* 11111111 */
+ 0xff, /* 11111111 */
+ 0xff, /* 11111111 */
+ 0xc3, /* 11000011 */
+ 0x99, /* 10011001 */
+ 0xbd, /* 10111101 */
+ 0xbd, /* 10111101 */
+ 0x99, /* 10011001 */
+ 0xc3, /* 11000011 */
+ 0xff, /* 11111111 */
+ 0xff, /* 11111111 */
+ 0xff, /* 11111111 */
+ 0xff, /* 11111111 */
+ 0xff, /* 11111111 */
+
+ /* 11 0x0b '^K' */
+ 0x00, /* 00000000 */
+ 0x00, /* 00000000 */
+ 0x1e, /* 00011110 */
+ 0x0e, /* 00001110 */
+ 0x1a, /* 00011010 */
+ 0x32, /* 00110010 */
+ 0x78, /* 01111000 */
+ 0xcc, /* 11001100 */
+ 0xcc, /* 11001100 */
+ 0xcc, /* 11001100 */
+ 0xcc, /* 11001100 */
+ 0x78, /* 01111000 */
+ 0x00, /* 00000000 */
+ 0x00, /* 00000000 */
+ 0x00, /* 00000000 */
+ 0x00, /* 00000000 */
+
+ /* 12 0x0c '^L' */
+ 0x00, /* 00000000 */
+ 0x00, /* 00000000 */
+ 0x3c, /* 00111100 */
+ 0x66, /* 01100110 */
+ 0x66, /* 01100110 */
+ 0x66, /* 01100110 */
+ 0x66, /* 01100110 */
+ 0x3c, /* 00111100 */
+ 0x18, /* 00011000 */
+ 0x7e, /* 01111110 */
+ 0x18, /* 00011000 */
+ 0x18, /* 00011000 */
+ 0x00, /* 00000000 */
+ 0x00, /* 00000000 */
+ 0x00, /* 00000000 */
+ 0x00, /* 00000000 */
+
+ /* 13 0x0d '^M' */
+ 0x00, /* 00000000 */
+ 0x00, /* 00000000 */
+ 0x3f, /* 00111111 */
+ 0x33, /* 00110011 */
+ 0x3f, /* 00111111 */
+ 0x30, /* 00110000 */
+ 0x30, /* 00110000 */
+ 0x30, /* 00110000 */
+ 0x30, /* 00110000 */
+ 0x70, /* 01110000 */
+ 0xf0, /* 11110000 */
+ 0xe0, /* 11100000 */
+ 0x00, /* 00000000 */
+ 0x00, /* 00000000 */
+ 0x00, /* 00000000 */
+ 0x00, /* 00000000 */
+
+ /* 14 0x0e '^N' */
+ 0x00, /* 00000000 */
+ 0x00, /* 00000000 */
+ 0x7f, /* 01111111 */
+ 0x63, /* 01100011 */
+ 0x7f, /* 01111111 */
+ 0x63, /* 01100011 */
+ 0x63, /* 01100011 */
+ 0x63, /* 01100011 */
+ 0x63, /* 01100011 */
+ 0x67, /* 01100111 */
+ 0xe7, /* 11100111 */
+ 0xe6, /* 11100110 */
+ 0xc0, /* 11000000 */
+ 0x00, /* 00000000 */
+ 0x00, /* 00000000 */
+ 0x00, /* 00000000 */
+
+ /* 15 0x0f '^O' */
+ 0x00, /* 00000000 */
+ 0x00, /* 00000000 */
+ 0x00, /* 00000000 */
+ 0x18, /* 00011000 */
+ 0x18, /* 00011000 */
+ 0xdb, /* 11011011 */
+ 0x3c, /* 00111100 */
+ 0xe7, /* 11100111 */
+ 0x3c, /* 00111100 */
+ 0xdb, /* 11011011 */
+ 0x18, /* 00011000 */
+ 0x18, /* 00011000 */
+ 0x00, /* 00000000 */
+ 0x00, /* 00000000 */
+ 0x00, /* 00000000 */
+ 0x00, /* 00000000 */
+
+ /* 16 0x10 '^P' */
+ 0x00, /* 00000000 */
+ 0x80, /* 10000000 */
+ 0xc0, /* 11000000 */
+ 0xe0, /* 11100000 */
+ 0xf0, /* 11110000 */
+ 0xf8, /* 11111000 */
+ 0xfe, /* 11111110 */
+ 0xf8, /* 11111000 */
+ 0xf0, /* 11110000 */
+ 0xe0, /* 11100000 */
+ 0xc0, /* 11000000 */
+ 0x80, /* 10000000 */
+ 0x00, /* 00000000 */
+ 0x00, /* 00000000 */
+ 0x00, /* 00000000 */
+ 0x00, /* 00000000 */
+
+ /* 17 0x11 '^Q' */
+ 0x00, /* 00000000 */
+ 0x02, /* 00000010 */
+ 0x06, /* 00000110 */
+ 0x0e, /* 00001110 */
+ 0x1e, /* 00011110 */
+ 0x3e, /* 00111110 */
+ 0xfe, /* 11111110 */
+ 0x3e, /* 00111110 */
+ 0x1e, /* 00011110 */
+ 0x0e, /* 00001110 */
+ 0x06, /* 00000110 */
+ 0x02, /* 00000010 */
+ 0x00, /* 00000000 */
+ 0x00, /* 00000000 */
+ 0x00, /* 00000000 */
+ 0x00, /* 00000000 */
+
+ /* 18 0x12 '^R' */
+ 0x00, /* 00000000 */
+ 0x00, /* 00000000 */
+ 0x18, /* 00011000 */
+ 0x3c, /* 00111100 */
+ 0x7e, /* 01111110 */
+ 0x18, /* 00011000 */
+ 0x18, /* 00011000 */
+ 0x18, /* 00011000 */
+ 0x7e, /* 01111110 */
+ 0x3c, /* 00111100 */
+ 0x18, /* 00011000 */
+ 0x00, /* 00000000 */
+ 0x00, /* 00000000 */
+ 0x00, /* 00000000 */
+ 0x00, /* 00000000 */
+ 0x00, /* 00000000 */
+
+ /* 19 0x13 '^S' */
+ 0x00, /* 00000000 */
+ 0x00, /* 00000000 */
+ 0x66, /* 01100110 */
+ 0x66, /* 01100110 */
+ 0x66, /* 01100110 */
+ 0x66, /* 01100110 */
+ 0x66, /* 01100110 */
+ 0x66, /* 01100110 */
+ 0x66, /* 01100110 */
+ 0x00, /* 00000000 */
+ 0x66, /* 01100110 */
+ 0x66, /* 01100110 */
+ 0x00, /* 00000000 */
+ 0x00, /* 00000000 */
+ 0x00, /* 00000000 */
+ 0x00, /* 00000000 */
+
+ /* 20 0x14 '^T' */
+ 0x00, /* 00000000 */
+ 0x00, /* 00000000 */
+ 0x7f, /* 01111111 */
+ 0xdb, /* 11011011 */
+ 0xdb, /* 11011011 */
+ 0xdb, /* 11011011 */
+ 0x7b, /* 01111011 */
+ 0x1b, /* 00011011 */
+ 0x1b, /* 00011011 */
+ 0x1b, /* 00011011 */
+ 0x1b, /* 00011011 */
+ 0x1b, /* 00011011 */
+ 0x00, /* 00000000 */
+ 0x00, /* 00000000 */
+ 0x00, /* 00000000 */
+ 0x00, /* 00000000 */
+
+ /* 21 0x15 '^U' */
+ 0x00, /* 00000000 */
+ 0x7c, /* 01111100 */
+ 0xc6, /* 11000110 */
+ 0x60, /* 01100000 */
+ 0x38, /* 00111000 */
+ 0x6c, /* 01101100 */
+ 0xc6, /* 11000110 */
+ 0xc6, /* 11000110 */
+ 0x6c, /* 01101100 */
+ 0x38, /* 00111000 */
+ 0x0c, /* 00001100 */
+ 0xc6, /* 11000110 */
+ 0x7c, /* 01111100 */
+ 0x00, /* 00000000 */
+ 0x00, /* 00000000 */
+ 0x00, /* 00000000 */
+
+ /* 22 0x16 '^V' */
+ 0x00, /* 00000000 */
+ 0x00, /* 00000000 */
+ 0x00, /* 00000000 */
+ 0x00, /* 00000000 */
+ 0x00, /* 00000000 */
+ 0x00, /* 00000000 */
+ 0x00, /* 00000000 */
+ 0x00, /* 00000000 */
+ 0xfe, /* 11111110 */
+ 0xfe, /* 11111110 */
+ 0xfe, /* 11111110 */
+ 0xfe, /* 11111110 */
+ 0x00, /* 00000000 */
+ 0x00, /* 00000000 */
+ 0x00, /* 00000000 */
+ 0x00, /* 00000000 */
+
+ /* 23 0x17 '^W' */
+ 0x00, /* 00000000 */
+ 0x00, /* 00000000 */
+ 0x18, /* 00011000 */
+ 0x3c, /* 00111100 */
+ 0x7e, /* 01111110 */
+ 0x18, /* 00011000 */
+ 0x18, /* 00011000 */
+ 0x18, /* 00011000 */
+ 0x7e, /* 01111110 */
+ 0x3c, /* 00111100 */
+ 0x18, /* 00011000 */
+ 0x7e, /* 01111110 */
+ 0x00, /* 00000000 */
+ 0x00, /* 00000000 */
+ 0x00, /* 00000000 */
+ 0x00, /* 00000000 */
+
+ /* 24 0x18 '^X' */
+ 0x00, /* 00000000 */
+ 0x00, /* 00000000 */
+ 0x18, /* 00011000 */
+ 0x3c, /* 00111100 */
+ 0x7e, /* 01111110 */
+ 0x18, /* 00011000 */
+ 0x18, /* 00011000 */
+ 0x18, /* 00011000 */
+ 0x18, /* 00011000 */
+ 0x18, /* 00011000 */
+ 0x18, /* 00011000 */
+ 0x18, /* 00011000 */
+ 0x00, /* 00000000 */
+ 0x00, /* 00000000 */
+ 0x00, /* 00000000 */
+ 0x00, /* 00000000 */
+
+ /* 25 0x19 '^Y' */
+ 0x00, /* 00000000 */
+ 0x00, /* 00000000 */
+ 0x18, /* 00011000 */
+ 0x18, /* 00011000 */
+ 0x18, /* 00011000 */
+ 0x18, /* 00011000 */
+ 0x18, /* 00011000 */
+ 0x18, /* 00011000 */
+ 0x18, /* 00011000 */
+ 0x7e, /* 01111110 */
+ 0x3c, /* 00111100 */
+ 0x18, /* 00011000 */
+ 0x00, /* 00000000 */
+ 0x00, /* 00000000 */
+ 0x00, /* 00000000 */
+ 0x00, /* 00000000 */
+
+ /* 26 0x1a '^Z' */
+ 0x00, /* 00000000 */
+ 0x00, /* 00000000 */
+ 0x00, /* 00000000 */
+ 0x00, /* 00000000 */
+ 0x00, /* 00000000 */
+ 0x18, /* 00011000 */
+ 0x0c, /* 00001100 */
+ 0xfe, /* 11111110 */
+ 0x0c, /* 00001100 */
+ 0x18, /* 00011000 */
+ 0x00, /* 00000000 */
+ 0x00, /* 00000000 */
+ 0x00, /* 00000000 */
+ 0x00, /* 00000000 */
+ 0x00, /* 00000000 */
+ 0x00, /* 00000000 */
+
+ /* 27 0x1b '^[' */
+ 0x00, /* 00000000 */
+ 0x00, /* 00000000 */
+ 0x00, /* 00000000 */
+ 0x00, /* 00000000 */
+ 0x00, /* 00000000 */
+ 0x30, /* 00110000 */
+ 0x60, /* 01100000 */
+ 0xfe, /* 11111110 */
+ 0x60, /* 01100000 */
+ 0x30, /* 00110000 */
+ 0x00, /* 00000000 */
+ 0x00, /* 00000000 */
+ 0x00, /* 00000000 */
+ 0x00, /* 00000000 */
+ 0x00, /* 00000000 */
+ 0x00, /* 00000000 */
+
+ /* 28 0x1c '^\' */
+ 0x00, /* 00000000 */
+ 0x00, /* 00000000 */
+ 0x00, /* 00000000 */
+ 0x00, /* 00000000 */
+ 0x00, /* 00000000 */
+ 0x00, /* 00000000 */
+ 0xc0, /* 11000000 */
+ 0xc0, /* 11000000 */
+ 0xc0, /* 11000000 */
+ 0xfe, /* 11111110 */
+ 0x00, /* 00000000 */
+ 0x00, /* 00000000 */
+ 0x00, /* 00000000 */
+ 0x00, /* 00000000 */
+ 0x00, /* 00000000 */
+ 0x00, /* 00000000 */
+
+ /* 29 0x1d '^]' */
+ 0x00, /* 00000000 */
+ 0x00, /* 00000000 */
+ 0x00, /* 00000000 */
+ 0x00, /* 00000000 */
+ 0x00, /* 00000000 */
+ 0x28, /* 00101000 */
+ 0x6c, /* 01101100 */
+ 0xfe, /* 11111110 */
+ 0x6c, /* 01101100 */
+ 0x28, /* 00101000 */
+ 0x00, /* 00000000 */
+ 0x00, /* 00000000 */
+ 0x00, /* 00000000 */
+ 0x00, /* 00000000 */
+ 0x00, /* 00000000 */
+ 0x00, /* 00000000 */
+
+ /* 30 0x1e '^^' */
+ 0x00, /* 00000000 */
+ 0x00, /* 00000000 */
+ 0x00, /* 00000000 */
+ 0x00, /* 00000000 */
+ 0x10, /* 00010000 */
+ 0x38, /* 00111000 */
+ 0x38, /* 00111000 */
+ 0x7c, /* 01111100 */
+ 0x7c, /* 01111100 */
+ 0xfe, /* 11111110 */
+ 0xfe, /* 11111110 */
+ 0x00, /* 00000000 */
+ 0x00, /* 00000000 */
+ 0x00, /* 00000000 */
+ 0x00, /* 00000000 */
+ 0x00, /* 00000000 */
+
+ /* 31 0x1f '^_' */
+ 0x00, /* 00000000 */
+ 0x00, /* 00000000 */
+ 0x00, /* 00000000 */
+ 0x00, /* 00000000 */
+ 0xfe, /* 11111110 */
+ 0xfe, /* 11111110 */
+ 0x7c, /* 01111100 */
+ 0x7c, /* 01111100 */
+ 0x38, /* 00111000 */
+ 0x38, /* 00111000 */
+ 0x10, /* 00010000 */
+ 0x00, /* 00000000 */
+ 0x00, /* 00000000 */
+ 0x00, /* 00000000 */
+ 0x00, /* 00000000 */
+ 0x00, /* 00000000 */
+
+ /* 32 0x20 ' ' */
+ 0x00, /* 00000000 */
+ 0x00, /* 00000000 */
+ 0x00, /* 00000000 */
+ 0x00, /* 00000000 */
+ 0x00, /* 00000000 */
+ 0x00, /* 00000000 */
+ 0x00, /* 00000000 */
+ 0x00, /* 00000000 */
+ 0x00, /* 00000000 */
+ 0x00, /* 00000000 */
+ 0x00, /* 00000000 */
+ 0x00, /* 00000000 */
+ 0x00, /* 00000000 */
+ 0x00, /* 00000000 */
+ 0x00, /* 00000000 */
+ 0x00, /* 00000000 */
+
+ /* 33 0x21 '!' */
+ 0x00, /* 00000000 */
+ 0x00, /* 00000000 */
+ 0x18, /* 00011000 */
+ 0x3c, /* 00111100 */
+ 0x3c, /* 00111100 */
+ 0x3c, /* 00111100 */
+ 0x18, /* 00011000 */
+ 0x18, /* 00011000 */
+ 0x18, /* 00011000 */
+ 0x00, /* 00000000 */
+ 0x18, /* 00011000 */
+ 0x18, /* 00011000 */
+ 0x00, /* 00000000 */
+ 0x00, /* 00000000 */
+ 0x00, /* 00000000 */
+ 0x00, /* 00000000 */
+
+ /* 34 0x22 '"' */
+ 0x00, /* 00000000 */
+ 0x66, /* 01100110 */
+ 0x66, /* 01100110 */
+ 0x66, /* 01100110 */
+ 0x24, /* 00100100 */
+ 0x00, /* 00000000 */
+ 0x00, /* 00000000 */
+ 0x00, /* 00000000 */
+ 0x00, /* 00000000 */
+ 0x00, /* 00000000 */
+ 0x00, /* 00000000 */
+ 0x00, /* 00000000 */
+ 0x00, /* 00000000 */
+ 0x00, /* 00000000 */
+ 0x00, /* 00000000 */
+ 0x00, /* 00000000 */
+
+ /* 35 0x23 '#' */
+ 0x00, /* 00000000 */
+ 0x00, /* 00000000 */
+ 0x00, /* 00000000 */
+ 0x6c, /* 01101100 */
+ 0x6c, /* 01101100 */
+ 0xfe, /* 11111110 */
+ 0x6c, /* 01101100 */
+ 0x6c, /* 01101100 */
+ 0x6c, /* 01101100 */
+ 0xfe, /* 11111110 */
+ 0x6c, /* 01101100 */
+ 0x6c, /* 01101100 */
+ 0x00, /* 00000000 */
+ 0x00, /* 00000000 */
+ 0x00, /* 00000000 */
+ 0x00, /* 00000000 */
+
+ /* 36 0x24 '$' */
+ 0x18, /* 00011000 */
+ 0x18, /* 00011000 */
+ 0x7c, /* 01111100 */
+ 0xc6, /* 11000110 */
+ 0xc2, /* 11000010 */
+ 0xc0, /* 11000000 */
+ 0x7c, /* 01111100 */
+ 0x06, /* 00000110 */
+ 0x06, /* 00000110 */
+ 0x86, /* 10000110 */
+ 0xc6, /* 11000110 */
+ 0x7c, /* 01111100 */
+ 0x18, /* 00011000 */
+ 0x18, /* 00011000 */
+ 0x00, /* 00000000 */
+ 0x00, /* 00000000 */
+
+ /* 37 0x25 '%' */
+ 0x00, /* 00000000 */
+ 0x00, /* 00000000 */
+ 0x00, /* 00000000 */
+ 0x00, /* 00000000 */
+ 0xc2, /* 11000010 */
+ 0xc6, /* 11000110 */
+ 0x0c, /* 00001100 */
+ 0x18, /* 00011000 */
+ 0x30, /* 00110000 */
+ 0x60, /* 01100000 */
+ 0xc6, /* 11000110 */
+ 0x86, /* 10000110 */
+ 0x00, /* 00000000 */
+ 0x00, /* 00000000 */
+ 0x00, /* 00000000 */
+ 0x00, /* 00000000 */
+
+ /* 38 0x26 '&' */
+ 0x00, /* 00000000 */
+ 0x00, /* 00000000 */
+ 0x38, /* 00111000 */
+ 0x6c, /* 01101100 */
+ 0x6c, /* 01101100 */
+ 0x38, /* 00111000 */
+ 0x76, /* 01110110 */
+ 0xdc, /* 11011100 */
+ 0xcc, /* 11001100 */
+ 0xcc, /* 11001100 */
+ 0xcc, /* 11001100 */
+ 0x76, /* 01110110 */
+ 0x00, /* 00000000 */
+ 0x00, /* 00000000 */
+ 0x00, /* 00000000 */
+ 0x00, /* 00000000 */
+
+ /* 39 0x27 ''' */
+ 0x00, /* 00000000 */
+ 0x30, /* 00110000 */
+ 0x30, /* 00110000 */
+ 0x30, /* 00110000 */
+ 0x60, /* 01100000 */
+ 0x00, /* 00000000 */
+ 0x00, /* 00000000 */
+ 0x00, /* 00000000 */
+ 0x00, /* 00000000 */
+ 0x00, /* 00000000 */
+ 0x00, /* 00000000 */
+ 0x00, /* 00000000 */
+ 0x00, /* 00000000 */
+ 0x00, /* 00000000 */
+ 0x00, /* 00000000 */
+ 0x00, /* 00000000 */
+
+ /* 40 0x28 '(' */
+ 0x00, /* 00000000 */
+ 0x00, /* 00000000 */
+ 0x0c, /* 00001100 */
+ 0x18, /* 00011000 */
+ 0x30, /* 00110000 */
+ 0x30, /* 00110000 */
+ 0x30, /* 00110000 */
+ 0x30, /* 00110000 */
+ 0x30, /* 00110000 */
+ 0x30, /* 00110000 */
+ 0x18, /* 00011000 */
+ 0x0c, /* 00001100 */
+ 0x00, /* 00000000 */
+ 0x00, /* 00000000 */
+ 0x00, /* 00000000 */
+ 0x00, /* 00000000 */
+
+ /* 41 0x29 ')' */
+ 0x00, /* 00000000 */
+ 0x00, /* 00000000 */
+ 0x30, /* 00110000 */
+ 0x18, /* 00011000 */
+ 0x0c, /* 00001100 */
+ 0x0c, /* 00001100 */
+ 0x0c, /* 00001100 */
+ 0x0c, /* 00001100 */
+ 0x0c, /* 00001100 */
+ 0x0c, /* 00001100 */
+ 0x18, /* 00011000 */
+ 0x30, /* 00110000 */
+ 0x00, /* 00000000 */
+ 0x00, /* 00000000 */
+ 0x00, /* 00000000 */
+ 0x00, /* 00000000 */
+
+ /* 42 0x2a '*' */
+ 0x00, /* 00000000 */
+ 0x00, /* 00000000 */
+ 0x00, /* 00000000 */
+ 0x00, /* 00000000 */
+ 0x00, /* 00000000 */
+ 0x66, /* 01100110 */
+ 0x3c, /* 00111100 */
+ 0xff, /* 11111111 */
+ 0x3c, /* 00111100 */
+ 0x66, /* 01100110 */
+ 0x00, /* 00000000 */
+ 0x00, /* 00000000 */
+ 0x00, /* 00000000 */
+ 0x00, /* 00000000 */
+ 0x00, /* 00000000 */
+ 0x00, /* 00000000 */
+
+ /* 43 0x2b '+' */
+ 0x00, /* 00000000 */
+ 0x00, /* 00000000 */
+ 0x00, /* 00000000 */
+ 0x00, /* 00000000 */
+ 0x00, /* 00000000 */
+ 0x18, /* 00011000 */
+ 0x18, /* 00011000 */
+ 0x7e, /* 01111110 */
+ 0x18, /* 00011000 */
+ 0x18, /* 00011000 */
+ 0x00, /* 00000000 */
+ 0x00, /* 00000000 */
+ 0x00, /* 00000000 */
+ 0x00, /* 00000000 */
+ 0x00, /* 00000000 */
+ 0x00, /* 00000000 */
+
+ /* 44 0x2c ',' */
+ 0x00, /* 00000000 */
+ 0x00, /* 00000000 */
+ 0x00, /* 00000000 */
+ 0x00, /* 00000000 */
+ 0x00, /* 00000000 */
+ 0x00, /* 00000000 */
+ 0x00, /* 00000000 */
+ 0x00, /* 00000000 */
+ 0x00, /* 00000000 */
+ 0x18, /* 00011000 */
+ 0x18, /* 00011000 */
+ 0x18, /* 00011000 */
+ 0x30, /* 00110000 */
+ 0x00, /* 00000000 */
+ 0x00, /* 00000000 */
+ 0x00, /* 00000000 */
+
+ /* 45 0x2d '-' */
+ 0x00, /* 00000000 */
+ 0x00, /* 00000000 */
+ 0x00, /* 00000000 */
+ 0x00, /* 00000000 */
+ 0x00, /* 00000000 */
+ 0x00, /* 00000000 */
+ 0x00, /* 00000000 */
+ 0xfe, /* 11111110 */
+ 0x00, /* 00000000 */
+ 0x00, /* 00000000 */
+ 0x00, /* 00000000 */
+ 0x00, /* 00000000 */
+ 0x00, /* 00000000 */
+ 0x00, /* 00000000 */
+ 0x00, /* 00000000 */
+ 0x00, /* 00000000 */
+
+ /* 46 0x2e '.' */
+ 0x00, /* 00000000 */
+ 0x00, /* 00000000 */
+ 0x00, /* 00000000 */
+ 0x00, /* 00000000 */
+ 0x00, /* 00000000 */
+ 0x00, /* 00000000 */
+ 0x00, /* 00000000 */
+ 0x00, /* 00000000 */
+ 0x00, /* 00000000 */
+ 0x00, /* 00000000 */
+ 0x18, /* 00011000 */
+ 0x18, /* 00011000 */
+ 0x00, /* 00000000 */
+ 0x00, /* 00000000 */
+ 0x00, /* 00000000 */
+ 0x00, /* 00000000 */
+
+ /* 47 0x2f '/' */
+ 0x00, /* 00000000 */
+ 0x00, /* 00000000 */
+ 0x00, /* 00000000 */
+ 0x00, /* 00000000 */
+ 0x02, /* 00000010 */
+ 0x06, /* 00000110 */
+ 0x0c, /* 00001100 */
+ 0x18, /* 00011000 */
+ 0x30, /* 00110000 */
+ 0x60, /* 01100000 */
+ 0xc0, /* 11000000 */
+ 0x80, /* 10000000 */
+ 0x00, /* 00000000 */
+ 0x00, /* 00000000 */
+ 0x00, /* 00000000 */
+ 0x00, /* 00000000 */
+
+ /* 48 0x30 '0' */
+ 0x00, /* 00000000 */
+ 0x00, /* 00000000 */
+ 0x38, /* 00111000 */
+ 0x6c, /* 01101100 */
+ 0xc6, /* 11000110 */
+ 0xc6, /* 11000110 */
+ 0xd6, /* 11010110 */
+ 0xd6, /* 11010110 */
+ 0xc6, /* 11000110 */
+ 0xc6, /* 11000110 */
+ 0x6c, /* 01101100 */
+ 0x38, /* 00111000 */
+ 0x00, /* 00000000 */
+ 0x00, /* 00000000 */
+ 0x00, /* 00000000 */
+ 0x00, /* 00000000 */
+
+ /* 49 0x31 '1' */
+ 0x00, /* 00000000 */
+ 0x00, /* 00000000 */
+ 0x18, /* 00011000 */
+ 0x38, /* 00111000 */
+ 0x78, /* 01111000 */
+ 0x18, /* 00011000 */
+ 0x18, /* 00011000 */
+ 0x18, /* 00011000 */
+ 0x18, /* 00011000 */
+ 0x18, /* 00011000 */
+ 0x18, /* 00011000 */
+ 0x7e, /* 01111110 */
+ 0x00, /* 00000000 */
+ 0x00, /* 00000000 */
+ 0x00, /* 00000000 */
+ 0x00, /* 00000000 */
+
+ /* 50 0x32 '2' */
+ 0x00, /* 00000000 */
+ 0x00, /* 00000000 */
+ 0x7c, /* 01111100 */
+ 0xc6, /* 11000110 */
+ 0x06, /* 00000110 */
+ 0x0c, /* 00001100 */
+ 0x18, /* 00011000 */
+ 0x30, /* 00110000 */
+ 0x60, /* 01100000 */
+ 0xc0, /* 11000000 */
+ 0xc6, /* 11000110 */
+ 0xfe, /* 11111110 */
+ 0x00, /* 00000000 */
+ 0x00, /* 00000000 */
+ 0x00, /* 00000000 */
+ 0x00, /* 00000000 */
+
+ /* 51 0x33 '3' */
+ 0x00, /* 00000000 */
+ 0x00, /* 00000000 */
+ 0x7c, /* 01111100 */
+ 0xc6, /* 11000110 */
+ 0x06, /* 00000110 */
+ 0x06, /* 00000110 */
+ 0x3c, /* 00111100 */
+ 0x06, /* 00000110 */
+ 0x06, /* 00000110 */
+ 0x06, /* 00000110 */
+ 0xc6, /* 11000110 */
+ 0x7c, /* 01111100 */
+ 0x00, /* 00000000 */
+ 0x00, /* 00000000 */
+ 0x00, /* 00000000 */
+ 0x00, /* 00000000 */
+
+ /* 52 0x34 '4' */
+ 0x00, /* 00000000 */
+ 0x00, /* 00000000 */
+ 0x0c, /* 00001100 */
+ 0x1c, /* 00011100 */
+ 0x3c, /* 00111100 */
+ 0x6c, /* 01101100 */
+ 0xcc, /* 11001100 */
+ 0xfe, /* 11111110 */
+ 0x0c, /* 00001100 */
+ 0x0c, /* 00001100 */
+ 0x0c, /* 00001100 */
+ 0x1e, /* 00011110 */
+ 0x00, /* 00000000 */
+ 0x00, /* 00000000 */
+ 0x00, /* 00000000 */
+ 0x00, /* 00000000 */
+
+ /* 53 0x35 '5' */
+ 0x00, /* 00000000 */
+ 0x00, /* 00000000 */
+ 0xfe, /* 11111110 */
+ 0xc0, /* 11000000 */
+ 0xc0, /* 11000000 */
+ 0xc0, /* 11000000 */
+ 0xfc, /* 11111100 */
+ 0x06, /* 00000110 */
+ 0x06, /* 00000110 */
+ 0x06, /* 00000110 */
+ 0xc6, /* 11000110 */
+ 0x7c, /* 01111100 */
+ 0x00, /* 00000000 */
+ 0x00, /* 00000000 */
+ 0x00, /* 00000000 */
+ 0x00, /* 00000000 */
+
+ /* 54 0x36 '6' */
+ 0x00, /* 00000000 */
+ 0x00, /* 00000000 */
+ 0x38, /* 00111000 */
+ 0x60, /* 01100000 */
+ 0xc0, /* 11000000 */
+ 0xc0, /* 11000000 */
+ 0xfc, /* 11111100 */
+ 0xc6, /* 11000110 */
+ 0xc6, /* 11000110 */
+ 0xc6, /* 11000110 */
+ 0xc6, /* 11000110 */
+ 0x7c, /* 01111100 */
+ 0x00, /* 00000000 */
+ 0x00, /* 00000000 */
+ 0x00, /* 00000000 */
+ 0x00, /* 00000000 */
+
+ /* 55 0x37 '7' */
+ 0x00, /* 00000000 */
+ 0x00, /* 00000000 */
+ 0xfe, /* 11111110 */
+ 0xc6, /* 11000110 */
+ 0x06, /* 00000110 */
+ 0x06, /* 00000110 */
+ 0x0c, /* 00001100 */
+ 0x18, /* 00011000 */
+ 0x30, /* 00110000 */
+ 0x30, /* 00110000 */
+ 0x30, /* 00110000 */
+ 0x30, /* 00110000 */
+ 0x00, /* 00000000 */
+ 0x00, /* 00000000 */
+ 0x00, /* 00000000 */
+ 0x00, /* 00000000 */
+
+ /* 56 0x38 '8' */
+ 0x00, /* 00000000 */
+ 0x00, /* 00000000 */
+ 0x7c, /* 01111100 */
+ 0xc6, /* 11000110 */
+ 0xc6, /* 11000110 */
+ 0xc6, /* 11000110 */
+ 0x7c, /* 01111100 */
+ 0xc6, /* 11000110 */
+ 0xc6, /* 11000110 */
+ 0xc6, /* 11000110 */
+ 0xc6, /* 11000110 */
+ 0x7c, /* 01111100 */
+ 0x00, /* 00000000 */
+ 0x00, /* 00000000 */
+ 0x00, /* 00000000 */
+ 0x00, /* 00000000 */
+
+ /* 57 0x39 '9' */
+ 0x00, /* 00000000 */
+ 0x00, /* 00000000 */
+ 0x7c, /* 01111100 */
+ 0xc6, /* 11000110 */
+ 0xc6, /* 11000110 */
+ 0xc6, /* 11000110 */
+ 0x7e, /* 01111110 */
+ 0x06, /* 00000110 */
+ 0x06, /* 00000110 */
+ 0x06, /* 00000110 */
+ 0x0c, /* 00001100 */
+ 0x78, /* 01111000 */
+ 0x00, /* 00000000 */
+ 0x00, /* 00000000 */
+ 0x00, /* 00000000 */
+ 0x00, /* 00000000 */
+
+ /* 58 0x3a ':' */
+ 0x00, /* 00000000 */
+ 0x00, /* 00000000 */
+ 0x00, /* 00000000 */
+ 0x00, /* 00000000 */
+ 0x18, /* 00011000 */
+ 0x18, /* 00011000 */
+ 0x00, /* 00000000 */
+ 0x00, /* 00000000 */
+ 0x00, /* 00000000 */
+ 0x18, /* 00011000 */
+ 0x18, /* 00011000 */
+ 0x00, /* 00000000 */
+ 0x00, /* 00000000 */
+ 0x00, /* 00000000 */
+ 0x00, /* 00000000 */
+ 0x00, /* 00000000 */
+
+ /* 59 0x3b ';' */
+ 0x00, /* 00000000 */
+ 0x00, /* 00000000 */
+ 0x00, /* 00000000 */
+ 0x00, /* 00000000 */
+ 0x18, /* 00011000 */
+ 0x18, /* 00011000 */
+ 0x00, /* 00000000 */
+ 0x00, /* 00000000 */
+ 0x00, /* 00000000 */
+ 0x18, /* 00011000 */
+ 0x18, /* 00011000 */
+ 0x30, /* 00110000 */
+ 0x00, /* 00000000 */
+ 0x00, /* 00000000 */
+ 0x00, /* 00000000 */
+ 0x00, /* 00000000 */
+
+ /* 60 0x3c '<' */
+ 0x00, /* 00000000 */
+ 0x00, /* 00000000 */
+ 0x00, /* 00000000 */
+ 0x06, /* 00000110 */
+ 0x0c, /* 00001100 */
+ 0x18, /* 00011000 */
+ 0x30, /* 00110000 */
+ 0x60, /* 01100000 */
+ 0x30, /* 00110000 */
+ 0x18, /* 00011000 */
+ 0x0c, /* 00001100 */
+ 0x06, /* 00000110 */
+ 0x00, /* 00000000 */
+ 0x00, /* 00000000 */
+ 0x00, /* 00000000 */
+ 0x00, /* 00000000 */
+
+ /* 61 0x3d '=' */
+ 0x00, /* 00000000 */
+ 0x00, /* 00000000 */
+ 0x00, /* 00000000 */
+ 0x00, /* 00000000 */
+ 0x00, /* 00000000 */
+ 0x7e, /* 01111110 */
+ 0x00, /* 00000000 */
+ 0x00, /* 00000000 */
+ 0x7e, /* 01111110 */
+ 0x00, /* 00000000 */
+ 0x00, /* 00000000 */
+ 0x00, /* 00000000 */
+ 0x00, /* 00000000 */
+ 0x00, /* 00000000 */
+ 0x00, /* 00000000 */
+ 0x00, /* 00000000 */
+
+ /* 62 0x3e '>' */
+ 0x00, /* 00000000 */
+ 0x00, /* 00000000 */
+ 0x00, /* 00000000 */
+ 0x60, /* 01100000 */
+ 0x30, /* 00110000 */
+ 0x18, /* 00011000 */
+ 0x0c, /* 00001100 */
+ 0x06, /* 00000110 */
+ 0x0c, /* 00001100 */
+ 0x18, /* 00011000 */
+ 0x30, /* 00110000 */
+ 0x60, /* 01100000 */
+ 0x00, /* 00000000 */
+ 0x00, /* 00000000 */
+ 0x00, /* 00000000 */
+ 0x00, /* 00000000 */
+
+ /* 63 0x3f '?' */
+ 0x00, /* 00000000 */
+ 0x00, /* 00000000 */
+ 0x7c, /* 01111100 */
+ 0xc6, /* 11000110 */
+ 0xc6, /* 11000110 */
+ 0x0c, /* 00001100 */
+ 0x18, /* 00011000 */
+ 0x18, /* 00011000 */
+ 0x18, /* 00011000 */
+ 0x00, /* 00000000 */
+ 0x18, /* 00011000 */
+ 0x18, /* 00011000 */
+ 0x00, /* 00000000 */
+ 0x00, /* 00000000 */
+ 0x00, /* 00000000 */
+ 0x00, /* 00000000 */
+
+ /* 64 0x40 '@' */
+ 0x00, /* 00000000 */
+ 0x00, /* 00000000 */
+ 0x00, /* 00000000 */
+ 0x7c, /* 01111100 */
+ 0xc6, /* 11000110 */
+ 0xc6, /* 11000110 */
+ 0xde, /* 11011110 */
+ 0xde, /* 11011110 */
+ 0xde, /* 11011110 */
+ 0xdc, /* 11011100 */
+ 0xc0, /* 11000000 */
+ 0x7c, /* 01111100 */
+ 0x00, /* 00000000 */
+ 0x00, /* 00000000 */
+ 0x00, /* 00000000 */
+ 0x00, /* 00000000 */
+
+ /* 65 0x41 'A' */
+ 0x00, /* 00000000 */
+ 0x00, /* 00000000 */
+ 0x10, /* 00010000 */
+ 0x38, /* 00111000 */
+ 0x6c, /* 01101100 */
+ 0xc6, /* 11000110 */
+ 0xc6, /* 11000110 */
+ 0xfe, /* 11111110 */
+ 0xc6, /* 11000110 */
+ 0xc6, /* 11000110 */
+ 0xc6, /* 11000110 */
+ 0xc6, /* 11000110 */
+ 0x00, /* 00000000 */
+ 0x00, /* 00000000 */
+ 0x00, /* 00000000 */
+ 0x00, /* 00000000 */
+
+ /* 66 0x42 'B' */
+ 0x00, /* 00000000 */
+ 0x00, /* 00000000 */
+ 0xfc, /* 11111100 */
+ 0x66, /* 01100110 */
+ 0x66, /* 01100110 */
+ 0x66, /* 01100110 */
+ 0x7c, /* 01111100 */
+ 0x66, /* 01100110 */
+ 0x66, /* 01100110 */
+ 0x66, /* 01100110 */
+ 0x66, /* 01100110 */
+ 0xfc, /* 11111100 */
+ 0x00, /* 00000000 */
+ 0x00, /* 00000000 */
+ 0x00, /* 00000000 */
+ 0x00, /* 00000000 */
+
+ /* 67 0x43 'C' */
+ 0x00, /* 00000000 */
+ 0x00, /* 00000000 */
+ 0x3c, /* 00111100 */
+ 0x66, /* 01100110 */
+ 0xc2, /* 11000010 */
+ 0xc0, /* 11000000 */
+ 0xc0, /* 11000000 */
+ 0xc0, /* 11000000 */
+ 0xc0, /* 11000000 */
+ 0xc2, /* 11000010 */
+ 0x66, /* 01100110 */
+ 0x3c, /* 00111100 */
+ 0x00, /* 00000000 */
+ 0x00, /* 00000000 */
+ 0x00, /* 00000000 */
+ 0x00, /* 00000000 */
+
+ /* 68 0x44 'D' */
+ 0x00, /* 00000000 */
+ 0x00, /* 00000000 */
+ 0xf8, /* 11111000 */
+ 0x6c, /* 01101100 */
+ 0x66, /* 01100110 */
+ 0x66, /* 01100110 */
+ 0x66, /* 01100110 */
+ 0x66, /* 01100110 */
+ 0x66, /* 01100110 */
+ 0x66, /* 01100110 */
+ 0x6c, /* 01101100 */
+ 0xf8, /* 11111000 */
+ 0x00, /* 00000000 */
+ 0x00, /* 00000000 */
+ 0x00, /* 00000000 */
+ 0x00, /* 00000000 */
+
+ /* 69 0x45 'E' */
+ 0x00, /* 00000000 */
+ 0x00, /* 00000000 */
+ 0xfe, /* 11111110 */
+ 0x66, /* 01100110 */
+ 0x62, /* 01100010 */
+ 0x68, /* 01101000 */
+ 0x78, /* 01111000 */
+ 0x68, /* 01101000 */
+ 0x60, /* 01100000 */
+ 0x62, /* 01100010 */
+ 0x66, /* 01100110 */
+ 0xfe, /* 11111110 */
+ 0x00, /* 00000000 */
+ 0x00, /* 00000000 */
+ 0x00, /* 00000000 */
+ 0x00, /* 00000000 */
+
+ /* 70 0x46 'F' */
+ 0x00, /* 00000000 */
+ 0x00, /* 00000000 */
+ 0xfe, /* 11111110 */
+ 0x66, /* 01100110 */
+ 0x62, /* 01100010 */
+ 0x68, /* 01101000 */
+ 0x78, /* 01111000 */
+ 0x68, /* 01101000 */
+ 0x60, /* 01100000 */
+ 0x60, /* 01100000 */
+ 0x60, /* 01100000 */
+ 0xf0, /* 11110000 */
+ 0x00, /* 00000000 */
+ 0x00, /* 00000000 */
+ 0x00, /* 00000000 */
+ 0x00, /* 00000000 */
+
+ /* 71 0x47 'G' */
+ 0x00, /* 00000000 */
+ 0x00, /* 00000000 */
+ 0x3c, /* 00111100 */
+ 0x66, /* 01100110 */
+ 0xc2, /* 11000010 */
+ 0xc0, /* 11000000 */
+ 0xc0, /* 11000000 */
+ 0xde, /* 11011110 */
+ 0xc6, /* 11000110 */
+ 0xc6, /* 11000110 */
+ 0x66, /* 01100110 */
+ 0x3a, /* 00111010 */
+ 0x00, /* 00000000 */
+ 0x00, /* 00000000 */
+ 0x00, /* 00000000 */
+ 0x00, /* 00000000 */
+
+ /* 72 0x48 'H' */
+ 0x00, /* 00000000 */
+ 0x00, /* 00000000 */
+ 0xc6, /* 11000110 */
+ 0xc6, /* 11000110 */
+ 0xc6, /* 11000110 */
+ 0xc6, /* 11000110 */
+ 0xfe, /* 11111110 */
+ 0xc6, /* 11000110 */
+ 0xc6, /* 11000110 */
+ 0xc6, /* 11000110 */
+ 0xc6, /* 11000110 */
+ 0xc6, /* 11000110 */
+ 0x00, /* 00000000 */
+ 0x00, /* 00000000 */
+ 0x00, /* 00000000 */
+ 0x00, /* 00000000 */
+
+ /* 73 0x49 'I' */
+ 0x00, /* 00000000 */
+ 0x00, /* 00000000 */
+ 0x3c, /* 00111100 */
+ 0x18, /* 00011000 */
+ 0x18, /* 00011000 */
+ 0x18, /* 00011000 */
+ 0x18, /* 00011000 */
+ 0x18, /* 00011000 */
+ 0x18, /* 00011000 */
+ 0x18, /* 00011000 */
+ 0x18, /* 00011000 */
+ 0x3c, /* 00111100 */
+ 0x00, /* 00000000 */
+ 0x00, /* 00000000 */
+ 0x00, /* 00000000 */
+ 0x00, /* 00000000 */
+
+ /* 74 0x4a 'J' */
+ 0x00, /* 00000000 */
+ 0x00, /* 00000000 */
+ 0x1e, /* 00011110 */
+ 0x0c, /* 00001100 */
+ 0x0c, /* 00001100 */
+ 0x0c, /* 00001100 */
+ 0x0c, /* 00001100 */
+ 0x0c, /* 00001100 */
+ 0xcc, /* 11001100 */
+ 0xcc, /* 11001100 */
+ 0xcc, /* 11001100 */
+ 0x78, /* 01111000 */
+ 0x00, /* 00000000 */
+ 0x00, /* 00000000 */
+ 0x00, /* 00000000 */
+ 0x00, /* 00000000 */
+
+ /* 75 0x4b 'K' */
+ 0x00, /* 00000000 */
+ 0x00, /* 00000000 */
+ 0xe6, /* 11100110 */
+ 0x66, /* 01100110 */
+ 0x66, /* 01100110 */
+ 0x6c, /* 01101100 */
+ 0x78, /* 01111000 */
+ 0x78, /* 01111000 */
+ 0x6c, /* 01101100 */
+ 0x66, /* 01100110 */
+ 0x66, /* 01100110 */
+ 0xe6, /* 11100110 */
+ 0x00, /* 00000000 */
+ 0x00, /* 00000000 */
+ 0x00, /* 00000000 */
+ 0x00, /* 00000000 */
+
+ /* 76 0x4c 'L' */
+ 0x00, /* 00000000 */
+ 0x00, /* 00000000 */
+ 0xf0, /* 11110000 */
+ 0x60, /* 01100000 */
+ 0x60, /* 01100000 */
+ 0x60, /* 01100000 */
+ 0x60, /* 01100000 */
+ 0x60, /* 01100000 */
+ 0x60, /* 01100000 */
+ 0x62, /* 01100010 */
+ 0x66, /* 01100110 */
+ 0xfe, /* 11111110 */
+ 0x00, /* 00000000 */
+ 0x00, /* 00000000 */
+ 0x00, /* 00000000 */
+ 0x00, /* 00000000 */
+
+ /* 77 0x4d 'M' */
+ 0x00, /* 00000000 */
+ 0x00, /* 00000000 */
+ 0xc6, /* 11000110 */
+ 0xee, /* 11101110 */
+ 0xfe, /* 11111110 */
+ 0xfe, /* 11111110 */
+ 0xd6, /* 11010110 */
+ 0xc6, /* 11000110 */
+ 0xc6, /* 11000110 */
+ 0xc6, /* 11000110 */
+ 0xc6, /* 11000110 */
+ 0xc6, /* 11000110 */
+ 0x00, /* 00000000 */
+ 0x00, /* 00000000 */
+ 0x00, /* 00000000 */
+ 0x00, /* 00000000 */
+
+ /* 78 0x4e 'N' */
+ 0x00, /* 00000000 */
+ 0x00, /* 00000000 */
+ 0xc6, /* 11000110 */
+ 0xe6, /* 11100110 */
+ 0xf6, /* 11110110 */
+ 0xfe, /* 11111110 */
+ 0xde, /* 11011110 */
+ 0xce, /* 11001110 */
+ 0xc6, /* 11000110 */
+ 0xc6, /* 11000110 */
+ 0xc6, /* 11000110 */
+ 0xc6, /* 11000110 */
+ 0x00, /* 00000000 */
+ 0x00, /* 00000000 */
+ 0x00, /* 00000000 */
+ 0x00, /* 00000000 */
+
+ /* 79 0x4f 'O' */
+ 0x00, /* 00000000 */
+ 0x00, /* 00000000 */
+ 0x7c, /* 01111100 */
+ 0xc6, /* 11000110 */
+ 0xc6, /* 11000110 */
+ 0xc6, /* 11000110 */
+ 0xc6, /* 11000110 */
+ 0xc6, /* 11000110 */
+ 0xc6, /* 11000110 */
+ 0xc6, /* 11000110 */
+ 0xc6, /* 11000110 */
+ 0x7c, /* 01111100 */
+ 0x00, /* 00000000 */
+ 0x00, /* 00000000 */
+ 0x00, /* 00000000 */
+ 0x00, /* 00000000 */
+
+ /* 80 0x50 'P' */
+ 0x00, /* 00000000 */
+ 0x00, /* 00000000 */
+ 0xfc, /* 11111100 */
+ 0x66, /* 01100110 */
+ 0x66, /* 01100110 */
+ 0x66, /* 01100110 */
+ 0x7c, /* 01111100 */
+ 0x60, /* 01100000 */
+ 0x60, /* 01100000 */
+ 0x60, /* 01100000 */
+ 0x60, /* 01100000 */
+ 0xf0, /* 11110000 */
+ 0x00, /* 00000000 */
+ 0x00, /* 00000000 */
+ 0x00, /* 00000000 */
+ 0x00, /* 00000000 */
+
+ /* 81 0x51 'Q' */
+ 0x00, /* 00000000 */
+ 0x00, /* 00000000 */
+ 0x7c, /* 01111100 */
+ 0xc6, /* 11000110 */
+ 0xc6, /* 11000110 */
+ 0xc6, /* 11000110 */
+ 0xc6, /* 11000110 */
+ 0xc6, /* 11000110 */
+ 0xc6, /* 11000110 */
+ 0xd6, /* 11010110 */
+ 0xde, /* 11011110 */
+ 0x7c, /* 01111100 */
+ 0x0c, /* 00001100 */
+ 0x0e, /* 00001110 */
+ 0x00, /* 00000000 */
+ 0x00, /* 00000000 */
+
+ /* 82 0x52 'R' */
+ 0x00, /* 00000000 */
+ 0x00, /* 00000000 */
+ 0xfc, /* 11111100 */
+ 0x66, /* 01100110 */
+ 0x66, /* 01100110 */
+ 0x66, /* 01100110 */
+ 0x7c, /* 01111100 */
+ 0x6c, /* 01101100 */
+ 0x66, /* 01100110 */
+ 0x66, /* 01100110 */
+ 0x66, /* 01100110 */
+ 0xe6, /* 11100110 */
+ 0x00, /* 00000000 */
+ 0x00, /* 00000000 */
+ 0x00, /* 00000000 */
+ 0x00, /* 00000000 */
+
+ /* 83 0x53 'S' */
+ 0x00, /* 00000000 */
+ 0x00, /* 00000000 */
+ 0x7c, /* 01111100 */
+ 0xc6, /* 11000110 */
+ 0xc6, /* 11000110 */
+ 0x60, /* 01100000 */
+ 0x38, /* 00111000 */
+ 0x0c, /* 00001100 */
+ 0x06, /* 00000110 */
+ 0xc6, /* 11000110 */
+ 0xc6, /* 11000110 */
+ 0x7c, /* 01111100 */
+ 0x00, /* 00000000 */
+ 0x00, /* 00000000 */
+ 0x00, /* 00000000 */
+ 0x00, /* 00000000 */
+
+ /* 84 0x54 'T' */
+ 0x00, /* 00000000 */
+ 0x00, /* 00000000 */
+ 0x7e, /* 01111110 */
+ 0x7e, /* 01111110 */
+ 0x5a, /* 01011010 */
+ 0x18, /* 00011000 */
+ 0x18, /* 00011000 */
+ 0x18, /* 00011000 */
+ 0x18, /* 00011000 */
+ 0x18, /* 00011000 */
+ 0x18, /* 00011000 */
+ 0x3c, /* 00111100 */
+ 0x00, /* 00000000 */
+ 0x00, /* 00000000 */
+ 0x00, /* 00000000 */
+ 0x00, /* 00000000 */
+
+ /* 85 0x55 'U' */
+ 0x00, /* 00000000 */
+ 0x00, /* 00000000 */
+ 0xc6, /* 11000110 */
+ 0xc6, /* 11000110 */
+ 0xc6, /* 11000110 */
+ 0xc6, /* 11000110 */
+ 0xc6, /* 11000110 */
+ 0xc6, /* 11000110 */
+ 0xc6, /* 11000110 */
+ 0xc6, /* 11000110 */
+ 0xc6, /* 11000110 */
+ 0x7c, /* 01111100 */
+ 0x00, /* 00000000 */
+ 0x00, /* 00000000 */
+ 0x00, /* 00000000 */
+ 0x00, /* 00000000 */
+
+ /* 86 0x56 'V' */
+ 0x00, /* 00000000 */
+ 0x00, /* 00000000 */
+ 0xc6, /* 11000110 */
+ 0xc6, /* 11000110 */
+ 0xc6, /* 11000110 */
+ 0xc6, /* 11000110 */
+ 0xc6, /* 11000110 */
+ 0xc6, /* 11000110 */
+ 0xc6, /* 11000110 */
+ 0x6c, /* 01101100 */
+ 0x38, /* 00111000 */
+ 0x10, /* 00010000 */
+ 0x00, /* 00000000 */
+ 0x00, /* 00000000 */
+ 0x00, /* 00000000 */
+ 0x00, /* 00000000 */
+
+ /* 87 0x57 'W' */
+ 0x00, /* 00000000 */
+ 0x00, /* 00000000 */
+ 0xc6, /* 11000110 */
+ 0xc6, /* 11000110 */
+ 0xc6, /* 11000110 */
+ 0xc6, /* 11000110 */
+ 0xd6, /* 11010110 */
+ 0xd6, /* 11010110 */
+ 0xd6, /* 11010110 */
+ 0xfe, /* 11111110 */
+ 0xee, /* 11101110 */
+ 0x6c, /* 01101100 */
+ 0x00, /* 00000000 */
+ 0x00, /* 00000000 */
+ 0x00, /* 00000000 */
+ 0x00, /* 00000000 */
+
+ /* 88 0x58 'X' */
+ 0x00, /* 00000000 */
+ 0x00, /* 00000000 */
+ 0xc6, /* 11000110 */
+ 0xc6, /* 11000110 */
+ 0x6c, /* 01101100 */
+ 0x7c, /* 01111100 */
+ 0x38, /* 00111000 */
+ 0x38, /* 00111000 */
+ 0x7c, /* 01111100 */
+ 0x6c, /* 01101100 */
+ 0xc6, /* 11000110 */
+ 0xc6, /* 11000110 */
+ 0x00, /* 00000000 */
+ 0x00, /* 00000000 */
+ 0x00, /* 00000000 */
+ 0x00, /* 00000000 */
+
+ /* 89 0x59 'Y' */
+ 0x00, /* 00000000 */
+ 0x00, /* 00000000 */
+ 0x66, /* 01100110 */
+ 0x66, /* 01100110 */
+ 0x66, /* 01100110 */
+ 0x66, /* 01100110 */
+ 0x3c, /* 00111100 */
+ 0x18, /* 00011000 */
+ 0x18, /* 00011000 */
+ 0x18, /* 00011000 */
+ 0x18, /* 00011000 */
+ 0x3c, /* 00111100 */
+ 0x00, /* 00000000 */
+ 0x00, /* 00000000 */
+ 0x00, /* 00000000 */
+ 0x00, /* 00000000 */
+
+ /* 90 0x5a 'Z' */
+ 0x00, /* 00000000 */
+ 0x00, /* 00000000 */
+ 0xfe, /* 11111110 */
+ 0xc6, /* 11000110 */
+ 0x86, /* 10000110 */
+ 0x0c, /* 00001100 */
+ 0x18, /* 00011000 */
+ 0x30, /* 00110000 */
+ 0x60, /* 01100000 */
+ 0xc2, /* 11000010 */
+ 0xc6, /* 11000110 */
+ 0xfe, /* 11111110 */
+ 0x00, /* 00000000 */
+ 0x00, /* 00000000 */
+ 0x00, /* 00000000 */
+ 0x00, /* 00000000 */
+
+ /* 91 0x5b '[' */
+ 0x00, /* 00000000 */
+ 0x00, /* 00000000 */
+ 0x3c, /* 00111100 */
+ 0x30, /* 00110000 */
+ 0x30, /* 00110000 */
+ 0x30, /* 00110000 */
+ 0x30, /* 00110000 */
+ 0x30, /* 00110000 */
+ 0x30, /* 00110000 */
+ 0x30, /* 00110000 */
+ 0x30, /* 00110000 */
+ 0x3c, /* 00111100 */
+ 0x00, /* 00000000 */
+ 0x00, /* 00000000 */
+ 0x00, /* 00000000 */
+ 0x00, /* 00000000 */
+
+ /* 92 0x5c '\' */
+ 0x00, /* 00000000 */
+ 0x00, /* 00000000 */
+ 0x00, /* 00000000 */
+ 0x80, /* 10000000 */
+ 0xc0, /* 11000000 */
+ 0xe0, /* 11100000 */
+ 0x70, /* 01110000 */
+ 0x38, /* 00111000 */
+ 0x1c, /* 00011100 */
+ 0x0e, /* 00001110 */
+ 0x06, /* 00000110 */
+ 0x02, /* 00000010 */
+ 0x00, /* 00000000 */
+ 0x00, /* 00000000 */
+ 0x00, /* 00000000 */
+ 0x00, /* 00000000 */
+
+ /* 93 0x5d ']' */
+ 0x00, /* 00000000 */
+ 0x00, /* 00000000 */
+ 0x3c, /* 00111100 */
+ 0x0c, /* 00001100 */
+ 0x0c, /* 00001100 */
+ 0x0c, /* 00001100 */
+ 0x0c, /* 00001100 */
+ 0x0c, /* 00001100 */
+ 0x0c, /* 00001100 */
+ 0x0c, /* 00001100 */
+ 0x0c, /* 00001100 */
+ 0x3c, /* 00111100 */
+ 0x00, /* 00000000 */
+ 0x00, /* 00000000 */
+ 0x00, /* 00000000 */
+ 0x00, /* 00000000 */
+
+ /* 94 0x5e '^' */
+ 0x10, /* 00010000 */
+ 0x38, /* 00111000 */
+ 0x6c, /* 01101100 */
+ 0xc6, /* 11000110 */
+ 0x00, /* 00000000 */
+ 0x00, /* 00000000 */
+ 0x00, /* 00000000 */
+ 0x00, /* 00000000 */
+ 0x00, /* 00000000 */
+ 0x00, /* 00000000 */
+ 0x00, /* 00000000 */
+ 0x00, /* 00000000 */
+ 0x00, /* 00000000 */
+ 0x00, /* 00000000 */
+ 0x00, /* 00000000 */
+ 0x00, /* 00000000 */
+
+ /* 95 0x5f '_' */
+ 0x00, /* 00000000 */
+ 0x00, /* 00000000 */
+ 0x00, /* 00000000 */
+ 0x00, /* 00000000 */
+ 0x00, /* 00000000 */
+ 0x00, /* 00000000 */
+ 0x00, /* 00000000 */
+ 0x00, /* 00000000 */
+ 0x00, /* 00000000 */
+ 0x00, /* 00000000 */
+ 0x00, /* 00000000 */
+ 0x00, /* 00000000 */
+ 0x00, /* 00000000 */
+ 0xff, /* 11111111 */
+ 0x00, /* 00000000 */
+ 0x00, /* 00000000 */
+
+ /* 96 0x60 '`' */
+ 0x00, /* 00000000 */
+ 0x30, /* 00110000 */
+ 0x18, /* 00011000 */
+ 0x0c, /* 00001100 */
+ 0x00, /* 00000000 */
+ 0x00, /* 00000000 */
+ 0x00, /* 00000000 */
+ 0x00, /* 00000000 */
+ 0x00, /* 00000000 */
+ 0x00, /* 00000000 */
+ 0x00, /* 00000000 */
+ 0x00, /* 00000000 */
+ 0x00, /* 00000000 */
+ 0x00, /* 00000000 */
+ 0x00, /* 00000000 */
+ 0x00, /* 00000000 */
+
+ /* 97 0x61 'a' */
+ 0x00, /* 00000000 */
+ 0x00, /* 00000000 */
+ 0x00, /* 00000000 */
+ 0x00, /* 00000000 */
+ 0x00, /* 00000000 */
+ 0x78, /* 01111000 */
+ 0x0c, /* 00001100 */
+ 0x7c, /* 01111100 */
+ 0xcc, /* 11001100 */
+ 0xcc, /* 11001100 */
+ 0xcc, /* 11001100 */
+ 0x76, /* 01110110 */
+ 0x00, /* 00000000 */
+ 0x00, /* 00000000 */
+ 0x00, /* 00000000 */
+ 0x00, /* 00000000 */
+
+ /* 98 0x62 'b' */
+ 0x00, /* 00000000 */
+ 0x00, /* 00000000 */
+ 0xe0, /* 11100000 */
+ 0x60, /* 01100000 */
+ 0x60, /* 01100000 */
+ 0x78, /* 01111000 */
+ 0x6c, /* 01101100 */
+ 0x66, /* 01100110 */
+ 0x66, /* 01100110 */
+ 0x66, /* 01100110 */
+ 0x66, /* 01100110 */
+ 0x7c, /* 01111100 */
+ 0x00, /* 00000000 */
+ 0x00, /* 00000000 */
+ 0x00, /* 00000000 */
+ 0x00, /* 00000000 */
+
+ /* 99 0x63 'c' */
+ 0x00, /* 00000000 */
+ 0x00, /* 00000000 */
+ 0x00, /* 00000000 */
+ 0x00, /* 00000000 */
+ 0x00, /* 00000000 */
+ 0x7c, /* 01111100 */
+ 0xc6, /* 11000110 */
+ 0xc0, /* 11000000 */
+ 0xc0, /* 11000000 */
+ 0xc0, /* 11000000 */
+ 0xc6, /* 11000110 */
+ 0x7c, /* 01111100 */
+ 0x00, /* 00000000 */
+ 0x00, /* 00000000 */
+ 0x00, /* 00000000 */
+ 0x00, /* 00000000 */
+
+ /* 100 0x64 'd' */
+ 0x00, /* 00000000 */
+ 0x00, /* 00000000 */
+ 0x1c, /* 00011100 */
+ 0x0c, /* 00001100 */
+ 0x0c, /* 00001100 */
+ 0x3c, /* 00111100 */
+ 0x6c, /* 01101100 */
+ 0xcc, /* 11001100 */
+ 0xcc, /* 11001100 */
+ 0xcc, /* 11001100 */
+ 0xcc, /* 11001100 */
+ 0x76, /* 01110110 */
+ 0x00, /* 00000000 */
+ 0x00, /* 00000000 */
+ 0x00, /* 00000000 */
+ 0x00, /* 00000000 */
+
+ /* 101 0x65 'e' */
+ 0x00, /* 00000000 */
+ 0x00, /* 00000000 */
+ 0x00, /* 00000000 */
+ 0x00, /* 00000000 */
+ 0x00, /* 00000000 */
+ 0x7c, /* 01111100 */
+ 0xc6, /* 11000110 */
+ 0xfe, /* 11111110 */
+ 0xc0, /* 11000000 */
+ 0xc0, /* 11000000 */
+ 0xc6, /* 11000110 */
+ 0x7c, /* 01111100 */
+ 0x00, /* 00000000 */
+ 0x00, /* 00000000 */
+ 0x00, /* 00000000 */
+ 0x00, /* 00000000 */
+
+ /* 102 0x66 'f' */
+ 0x00, /* 00000000 */
+ 0x00, /* 00000000 */
+ 0x1c, /* 00011100 */
+ 0x36, /* 00110110 */
+ 0x32, /* 00110010 */
+ 0x30, /* 00110000 */
+ 0x78, /* 01111000 */
+ 0x30, /* 00110000 */
+ 0x30, /* 00110000 */
+ 0x30, /* 00110000 */
+ 0x30, /* 00110000 */
+ 0x78, /* 01111000 */
+ 0x00, /* 00000000 */
+ 0x00, /* 00000000 */
+ 0x00, /* 00000000 */
+ 0x00, /* 00000000 */
+
+ /* 103 0x67 'g' */
+ 0x00, /* 00000000 */
+ 0x00, /* 00000000 */
+ 0x00, /* 00000000 */
+ 0x00, /* 00000000 */
+ 0x00, /* 00000000 */
+ 0x76, /* 01110110 */
+ 0xcc, /* 11001100 */
+ 0xcc, /* 11001100 */
+ 0xcc, /* 11001100 */
+ 0xcc, /* 11001100 */
+ 0xcc, /* 11001100 */
+ 0x7c, /* 01111100 */
+ 0x0c, /* 00001100 */
+ 0xcc, /* 11001100 */
+ 0x78, /* 01111000 */
+ 0x00, /* 00000000 */
+
+ /* 104 0x68 'h' */
+ 0x00, /* 00000000 */
+ 0x00, /* 00000000 */
+ 0xe0, /* 11100000 */
+ 0x60, /* 01100000 */
+ 0x60, /* 01100000 */
+ 0x6c, /* 01101100 */
+ 0x76, /* 01110110 */
+ 0x66, /* 01100110 */
+ 0x66, /* 01100110 */
+ 0x66, /* 01100110 */
+ 0x66, /* 01100110 */
+ 0xe6, /* 11100110 */
+ 0x00, /* 00000000 */
+ 0x00, /* 00000000 */
+ 0x00, /* 00000000 */
+ 0x00, /* 00000000 */
+
+ /* 105 0x69 'i' */
+ 0x00, /* 00000000 */
+ 0x00, /* 00000000 */
+ 0x18, /* 00011000 */
+ 0x18, /* 00011000 */
+ 0x00, /* 00000000 */
+ 0x38, /* 00111000 */
+ 0x18, /* 00011000 */
+ 0x18, /* 00011000 */
+ 0x18, /* 00011000 */
+ 0x18, /* 00011000 */
+ 0x18, /* 00011000 */
+ 0x3c, /* 00111100 */
+ 0x00, /* 00000000 */
+ 0x00, /* 00000000 */
+ 0x00, /* 00000000 */
+ 0x00, /* 00000000 */
+
+ /* 106 0x6a 'j' */
+ 0x00, /* 00000000 */
+ 0x00, /* 00000000 */
+ 0x06, /* 00000110 */
+ 0x06, /* 00000110 */
+ 0x00, /* 00000000 */
+ 0x0e, /* 00001110 */
+ 0x06, /* 00000110 */
+ 0x06, /* 00000110 */
+ 0x06, /* 00000110 */
+ 0x06, /* 00000110 */
+ 0x06, /* 00000110 */
+ 0x06, /* 00000110 */
+ 0x66, /* 01100110 */
+ 0x66, /* 01100110 */
+ 0x3c, /* 00111100 */
+ 0x00, /* 00000000 */
+
+ /* 107 0x6b 'k' */
+ 0x00, /* 00000000 */
+ 0x00, /* 00000000 */
+ 0xe0, /* 11100000 */
+ 0x60, /* 01100000 */
+ 0x60, /* 01100000 */
+ 0x66, /* 01100110 */
+ 0x6c, /* 01101100 */
+ 0x78, /* 01111000 */
+ 0x78, /* 01111000 */
+ 0x6c, /* 01101100 */
+ 0x66, /* 01100110 */
+ 0xe6, /* 11100110 */
+ 0x00, /* 00000000 */
+ 0x00, /* 00000000 */
+ 0x00, /* 00000000 */
+ 0x00, /* 00000000 */
+
+ /* 108 0x6c 'l' */
+ 0x00, /* 00000000 */
+ 0x00, /* 00000000 */
+ 0x38, /* 00111000 */
+ 0x18, /* 00011000 */
+ 0x18, /* 00011000 */
+ 0x18, /* 00011000 */
+ 0x18, /* 00011000 */
+ 0x18, /* 00011000 */
+ 0x18, /* 00011000 */
+ 0x18, /* 00011000 */
+ 0x18, /* 00011000 */
+ 0x3c, /* 00111100 */
+ 0x00, /* 00000000 */
+ 0x00, /* 00000000 */
+ 0x00, /* 00000000 */
+ 0x00, /* 00000000 */
+
+ /* 109 0x6d 'm' */
+ 0x00, /* 00000000 */
+ 0x00, /* 00000000 */
+ 0x00, /* 00000000 */
+ 0x00, /* 00000000 */
+ 0x00, /* 00000000 */
+ 0xec, /* 11101100 */
+ 0xfe, /* 11111110 */
+ 0xd6, /* 11010110 */
+ 0xd6, /* 11010110 */
+ 0xd6, /* 11010110 */
+ 0xd6, /* 11010110 */
+ 0xc6, /* 11000110 */
+ 0x00, /* 00000000 */
+ 0x00, /* 00000000 */
+ 0x00, /* 00000000 */
+ 0x00, /* 00000000 */
+
+ /* 110 0x6e 'n' */
+ 0x00, /* 00000000 */
+ 0x00, /* 00000000 */
+ 0x00, /* 00000000 */
+ 0x00, /* 00000000 */
+ 0x00, /* 00000000 */
+ 0xdc, /* 11011100 */
+ 0x66, /* 01100110 */
+ 0x66, /* 01100110 */
+ 0x66, /* 01100110 */
+ 0x66, /* 01100110 */
+ 0x66, /* 01100110 */
+ 0x66, /* 01100110 */
+ 0x00, /* 00000000 */
+ 0x00, /* 00000000 */
+ 0x00, /* 00000000 */
+ 0x00, /* 00000000 */
+
+ /* 111 0x6f 'o' */
+ 0x00, /* 00000000 */
+ 0x00, /* 00000000 */
+ 0x00, /* 00000000 */
+ 0x00, /* 00000000 */
+ 0x00, /* 00000000 */
+ 0x7c, /* 01111100 */
+ 0xc6, /* 11000110 */
+ 0xc6, /* 11000110 */
+ 0xc6, /* 11000110 */
+ 0xc6, /* 11000110 */
+ 0xc6, /* 11000110 */
+ 0x7c, /* 01111100 */
+ 0x00, /* 00000000 */
+ 0x00, /* 00000000 */
+ 0x00, /* 00000000 */
+ 0x00, /* 00000000 */
+
+ /* 112 0x70 'p' */
+ 0x00, /* 00000000 */
+ 0x00, /* 00000000 */
+ 0x00, /* 00000000 */
+ 0x00, /* 00000000 */
+ 0x00, /* 00000000 */
+ 0xdc, /* 11011100 */
+ 0x66, /* 01100110 */
+ 0x66, /* 01100110 */
+ 0x66, /* 01100110 */
+ 0x66, /* 01100110 */
+ 0x66, /* 01100110 */
+ 0x7c, /* 01111100 */
+ 0x60, /* 01100000 */
+ 0x60, /* 01100000 */
+ 0xf0, /* 11110000 */
+ 0x00, /* 00000000 */
+
+ /* 113 0x71 'q' */
+ 0x00, /* 00000000 */
+ 0x00, /* 00000000 */
+ 0x00, /* 00000000 */
+ 0x00, /* 00000000 */
+ 0x00, /* 00000000 */
+ 0x76, /* 01110110 */
+ 0xcc, /* 11001100 */
+ 0xcc, /* 11001100 */
+ 0xcc, /* 11001100 */
+ 0xcc, /* 11001100 */
+ 0xcc, /* 11001100 */
+ 0x7c, /* 01111100 */
+ 0x0c, /* 00001100 */
+ 0x0c, /* 00001100 */
+ 0x1e, /* 00011110 */
+ 0x00, /* 00000000 */
+
+ /* 114 0x72 'r' */
+ 0x00, /* 00000000 */
+ 0x00, /* 00000000 */
+ 0x00, /* 00000000 */
+ 0x00, /* 00000000 */
+ 0x00, /* 00000000 */
+ 0xdc, /* 11011100 */
+ 0x76, /* 01110110 */
+ 0x66, /* 01100110 */
+ 0x60, /* 01100000 */
+ 0x60, /* 01100000 */
+ 0x60, /* 01100000 */
+ 0xf0, /* 11110000 */
+ 0x00, /* 00000000 */
+ 0x00, /* 00000000 */
+ 0x00, /* 00000000 */
+ 0x00, /* 00000000 */
+
+ /* 115 0x73 's' */
+ 0x00, /* 00000000 */
+ 0x00, /* 00000000 */
+ 0x00, /* 00000000 */
+ 0x00, /* 00000000 */
+ 0x00, /* 00000000 */
+ 0x7c, /* 01111100 */
+ 0xc6, /* 11000110 */
+ 0x60, /* 01100000 */
+ 0x38, /* 00111000 */
+ 0x0c, /* 00001100 */
+ 0xc6, /* 11000110 */
+ 0x7c, /* 01111100 */
+ 0x00, /* 00000000 */
+ 0x00, /* 00000000 */
+ 0x00, /* 00000000 */
+ 0x00, /* 00000000 */
+
+ /* 116 0x74 't' */
+ 0x00, /* 00000000 */
+ 0x00, /* 00000000 */
+ 0x10, /* 00010000 */
+ 0x30, /* 00110000 */
+ 0x30, /* 00110000 */
+ 0xfc, /* 11111100 */
+ 0x30, /* 00110000 */
+ 0x30, /* 00110000 */
+ 0x30, /* 00110000 */
+ 0x30, /* 00110000 */
+ 0x36, /* 00110110 */
+ 0x1c, /* 00011100 */
+ 0x00, /* 00000000 */
+ 0x00, /* 00000000 */
+ 0x00, /* 00000000 */
+ 0x00, /* 00000000 */
+
+ /* 117 0x75 'u' */
+ 0x00, /* 00000000 */
+ 0x00, /* 00000000 */
+ 0x00, /* 00000000 */
+ 0x00, /* 00000000 */
+ 0x00, /* 00000000 */
+ 0xcc, /* 11001100 */
+ 0xcc, /* 11001100 */
+ 0xcc, /* 11001100 */
+ 0xcc, /* 11001100 */
+ 0xcc, /* 11001100 */
+ 0xcc, /* 11001100 */
+ 0x76, /* 01110110 */
+ 0x00, /* 00000000 */
+ 0x00, /* 00000000 */
+ 0x00, /* 00000000 */
+ 0x00, /* 00000000 */
+
+ /* 118 0x76 'v' */
+ 0x00, /* 00000000 */
+ 0x00, /* 00000000 */
+ 0x00, /* 00000000 */
+ 0x00, /* 00000000 */
+ 0x00, /* 00000000 */
+ 0xc6, /* 11000110 */
+ 0xc6, /* 11000110 */
+ 0xc6, /* 11000110 */
+ 0xc6, /* 11000110 */
+ 0xc6, /* 11000110 */
+ 0x6c, /* 01101100 */
+ 0x38, /* 00111000 */
+ 0x00, /* 00000000 */
+ 0x00, /* 00000000 */
+ 0x00, /* 00000000 */
+ 0x00, /* 00000000 */
+
+ /* 119 0x77 'w' */
+ 0x00, /* 00000000 */
+ 0x00, /* 00000000 */
+ 0x00, /* 00000000 */
+ 0x00, /* 00000000 */
+ 0x00, /* 00000000 */
+ 0xc6, /* 11000110 */
+ 0xc6, /* 11000110 */
+ 0xd6, /* 11010110 */
+ 0xd6, /* 11010110 */
+ 0xd6, /* 11010110 */
+ 0xfe, /* 11111110 */
+ 0x6c, /* 01101100 */
+ 0x00, /* 00000000 */
+ 0x00, /* 00000000 */
+ 0x00, /* 00000000 */
+ 0x00, /* 00000000 */
+
+ /* 120 0x78 'x' */
+ 0x00, /* 00000000 */
+ 0x00, /* 00000000 */
+ 0x00, /* 00000000 */
+ 0x00, /* 00000000 */
+ 0x00, /* 00000000 */
+ 0xc6, /* 11000110 */
+ 0x6c, /* 01101100 */
+ 0x38, /* 00111000 */
+ 0x38, /* 00111000 */
+ 0x38, /* 00111000 */
+ 0x6c, /* 01101100 */
+ 0xc6, /* 11000110 */
+ 0x00, /* 00000000 */
+ 0x00, /* 00000000 */
+ 0x00, /* 00000000 */
+ 0x00, /* 00000000 */
+
+ /* 121 0x79 'y' */
+ 0x00, /* 00000000 */
+ 0x00, /* 00000000 */
+ 0x00, /* 00000000 */
+ 0x00, /* 00000000 */
+ 0x00, /* 00000000 */
+ 0xc6, /* 11000110 */
+ 0xc6, /* 11000110 */
+ 0xc6, /* 11000110 */
+ 0xc6, /* 11000110 */
+ 0xc6, /* 11000110 */
+ 0xc6, /* 11000110 */
+ 0x7e, /* 01111110 */
+ 0x06, /* 00000110 */
+ 0x0c, /* 00001100 */
+ 0xf8, /* 11111000 */
+ 0x00, /* 00000000 */
+
+ /* 122 0x7a 'z' */
+ 0x00, /* 00000000 */
+ 0x00, /* 00000000 */
+ 0x00, /* 00000000 */
+ 0x00, /* 00000000 */
+ 0x00, /* 00000000 */
+ 0xfe, /* 11111110 */
+ 0xcc, /* 11001100 */
+ 0x18, /* 00011000 */
+ 0x30, /* 00110000 */
+ 0x60, /* 01100000 */
+ 0xc6, /* 11000110 */
+ 0xfe, /* 11111110 */
+ 0x00, /* 00000000 */
+ 0x00, /* 00000000 */
+ 0x00, /* 00000000 */
+ 0x00, /* 00000000 */
+
+ /* 123 0x7b '{' */
+ 0x00, /* 00000000 */
+ 0x00, /* 00000000 */
+ 0x0e, /* 00001110 */
+ 0x18, /* 00011000 */
+ 0x18, /* 00011000 */
+ 0x18, /* 00011000 */
+ 0x70, /* 01110000 */
+ 0x18, /* 00011000 */
+ 0x18, /* 00011000 */
+ 0x18, /* 00011000 */
+ 0x18, /* 00011000 */
+ 0x0e, /* 00001110 */
+ 0x00, /* 00000000 */
+ 0x00, /* 00000000 */
+ 0x00, /* 00000000 */
+ 0x00, /* 00000000 */
+
+ /* 124 0x7c '|' */
+ 0x00, /* 00000000 */
+ 0x00, /* 00000000 */
+ 0x18, /* 00011000 */
+ 0x18, /* 00011000 */
+ 0x18, /* 00011000 */
+ 0x18, /* 00011000 */
+ 0x18, /* 00011000 */
+ 0x18, /* 00011000 */
+ 0x18, /* 00011000 */
+ 0x18, /* 00011000 */
+ 0x18, /* 00011000 */
+ 0x18, /* 00011000 */
+ 0x00, /* 00000000 */
+ 0x00, /* 00000000 */
+ 0x00, /* 00000000 */
+ 0x00, /* 00000000 */
+
+ /* 125 0x7d '}' */
+ 0x00, /* 00000000 */
+ 0x00, /* 00000000 */
+ 0x70, /* 01110000 */
+ 0x18, /* 00011000 */
+ 0x18, /* 00011000 */
+ 0x18, /* 00011000 */
+ 0x0e, /* 00001110 */
+ 0x18, /* 00011000 */
+ 0x18, /* 00011000 */
+ 0x18, /* 00011000 */
+ 0x18, /* 00011000 */
+ 0x70, /* 01110000 */
+ 0x00, /* 00000000 */
+ 0x00, /* 00000000 */
+ 0x00, /* 00000000 */
+ 0x00, /* 00000000 */
+
+ /* 126 0x7e '~' */
+ 0x00, /* 00000000 */
+ 0x76, /* 01110110 */
+ 0xdc, /* 11011100 */
+ 0x00, /* 00000000 */
+ 0x00, /* 00000000 */
+ 0x00, /* 00000000 */
+ 0x00, /* 00000000 */
+ 0x00, /* 00000000 */
+ 0x00, /* 00000000 */
+ 0x00, /* 00000000 */
+ 0x00, /* 00000000 */
+ 0x00, /* 00000000 */
+ 0x00, /* 00000000 */
+ 0x00, /* 00000000 */
+ 0x00, /* 00000000 */
+ 0x00, /* 00000000 */
+
+ /* 127 0x7f '' */
+ 0x00, /* 00000000 */
+ 0x00, /* 00000000 */
+ 0x00, /* 00000000 */
+ 0x00, /* 00000000 */
+ 0x10, /* 00010000 */
+ 0x38, /* 00111000 */
+ 0x6c, /* 01101100 */
+ 0xc6, /* 11000110 */
+ 0xc6, /* 11000110 */
+ 0xc6, /* 11000110 */
+ 0xfe, /* 11111110 */
+ 0x00, /* 00000000 */
+ 0x00, /* 00000000 */
+ 0x00, /* 00000000 */
+ 0x00, /* 00000000 */
+ 0x00, /* 00000000 */
+
+ /* 128 0x80 '' */
+ 0x00, /* 00000000 */
+ 0x00, /* 00000000 */
+ 0x3c, /* 00111100 */
+ 0x66, /* 01100110 */
+ 0xc2, /* 11000010 */
+ 0xc0, /* 11000000 */
+ 0xc0, /* 11000000 */
+ 0xc0, /* 11000000 */
+ 0xc0, /* 11000000 */
+ 0xc2, /* 11000010 */
+ 0x66, /* 01100110 */
+ 0x3c, /* 00111100 */
+ 0x18, /* 00011000 */
+ 0x70, /* 01110000 */
+ 0x00, /* 00000000 */
+ 0x00, /* 00000000 */
+
+ /* 129 0x81 '' */
+ 0x00, /* 00000000 */
+ 0x00, /* 00000000 */
+ 0xcc, /* 11001100 */
+ 0x00, /* 00000000 */
+ 0x00, /* 00000000 */
+ 0xcc, /* 11001100 */
+ 0xcc, /* 11001100 */
+ 0xcc, /* 11001100 */
+ 0xcc, /* 11001100 */
+ 0xcc, /* 11001100 */
+ 0xcc, /* 11001100 */
+ 0x76, /* 01110110 */
+ 0x00, /* 00000000 */
+ 0x00, /* 00000000 */
+ 0x00, /* 00000000 */
+ 0x00, /* 00000000 */
+
+ /* 130 0x82 '' */
+ 0x00, /* 00000000 */
+ 0x0c, /* 00001100 */
+ 0x18, /* 00011000 */
+ 0x30, /* 00110000 */
+ 0x00, /* 00000000 */
+ 0x7c, /* 01111100 */
+ 0xc6, /* 11000110 */
+ 0xfe, /* 11111110 */
+ 0xc0, /* 11000000 */
+ 0xc0, /* 11000000 */
+ 0xc6, /* 11000110 */
+ 0x7c, /* 01111100 */
+ 0x00, /* 00000000 */
+ 0x00, /* 00000000 */
+ 0x00, /* 00000000 */
+ 0x00, /* 00000000 */
+
+ /* 131 0x83 '' */
+ 0x00, /* 00000000 */
+ 0x10, /* 00010000 */
+ 0x38, /* 00111000 */
+ 0x6c, /* 01101100 */
+ 0x00, /* 00000000 */
+ 0x78, /* 01111000 */
+ 0x0c, /* 00001100 */
+ 0x7c, /* 01111100 */
+ 0xcc, /* 11001100 */
+ 0xcc, /* 11001100 */
+ 0xcc, /* 11001100 */
+ 0x76, /* 01110110 */
+ 0x00, /* 00000000 */
+ 0x00, /* 00000000 */
+ 0x00, /* 00000000 */
+ 0x00, /* 00000000 */
+
+ /* 132 0x84 '' */
+ 0x00, /* 00000000 */
+ 0x00, /* 00000000 */
+ 0xcc, /* 11001100 */
+ 0x00, /* 00000000 */
+ 0x00, /* 00000000 */
+ 0x78, /* 01111000 */
+ 0x0c, /* 00001100 */
+ 0x7c, /* 01111100 */
+ 0xcc, /* 11001100 */
+ 0xcc, /* 11001100 */
+ 0xcc, /* 11001100 */
+ 0x76, /* 01110110 */
+ 0x00, /* 00000000 */
+ 0x00, /* 00000000 */
+ 0x00, /* 00000000 */
+ 0x00, /* 00000000 */
+
+ /* 133 0x85 '
' */
+ 0x00, /* 00000000 */
+ 0x60, /* 01100000 */
+ 0x30, /* 00110000 */
+ 0x18, /* 00011000 */
+ 0x00, /* 00000000 */
+ 0x78, /* 01111000 */
+ 0x0c, /* 00001100 */
+ 0x7c, /* 01111100 */
+ 0xcc, /* 11001100 */
+ 0xcc, /* 11001100 */
+ 0xcc, /* 11001100 */
+ 0x76, /* 01110110 */
+ 0x00, /* 00000000 */
+ 0x00, /* 00000000 */
+ 0x00, /* 00000000 */
+ 0x00, /* 00000000 */
+
+ /* 134 0x86 '' */
+ 0x00, /* 00000000 */
+ 0x38, /* 00111000 */
+ 0x6c, /* 01101100 */
+ 0x38, /* 00111000 */
+ 0x00, /* 00000000 */
+ 0x78, /* 01111000 */
+ 0x0c, /* 00001100 */
+ 0x7c, /* 01111100 */
+ 0xcc, /* 11001100 */
+ 0xcc, /* 11001100 */
+ 0xcc, /* 11001100 */
+ 0x76, /* 01110110 */
+ 0x00, /* 00000000 */
+ 0x00, /* 00000000 */
+ 0x00, /* 00000000 */
+ 0x00, /* 00000000 */
+
+ /* 135 0x87 '' */
+ 0x00, /* 00000000 */
+ 0x00, /* 00000000 */
+ 0x00, /* 00000000 */
+ 0x00, /* 00000000 */
+ 0x00, /* 00000000 */
+ 0x7c, /* 01111100 */
+ 0xc6, /* 11000110 */
+ 0xc0, /* 11000000 */
+ 0xc0, /* 11000000 */
+ 0xc0, /* 11000000 */
+ 0xc6, /* 11000110 */
+ 0x7c, /* 01111100 */
+ 0x18, /* 00011000 */
+ 0x70, /* 01110000 */
+ 0x00, /* 00000000 */
+ 0x00, /* 00000000 */
+
+ /* 136 0x88 '' */
+ 0x00, /* 00000000 */
+ 0x10, /* 00010000 */
+ 0x38, /* 00111000 */
+ 0x6c, /* 01101100 */
+ 0x00, /* 00000000 */
+ 0x7c, /* 01111100 */
+ 0xc6, /* 11000110 */
+ 0xfe, /* 11111110 */
+ 0xc0, /* 11000000 */
+ 0xc0, /* 11000000 */
+ 0xc6, /* 11000110 */
+ 0x7c, /* 01111100 */
+ 0x00, /* 00000000 */
+ 0x00, /* 00000000 */
+ 0x00, /* 00000000 */
+ 0x00, /* 00000000 */
+
+ /* 137 0x89 '' */
+ 0x00, /* 00000000 */
+ 0x00, /* 00000000 */
+ 0xc6, /* 11000110 */
+ 0x00, /* 00000000 */
+ 0x00, /* 00000000 */
+ 0x7c, /* 01111100 */
+ 0xc6, /* 11000110 */
+ 0xfe, /* 11111110 */
+ 0xc0, /* 11000000 */
+ 0xc0, /* 11000000 */
+ 0xc6, /* 11000110 */
+ 0x7c, /* 01111100 */
+ 0x00, /* 00000000 */
+ 0x00, /* 00000000 */
+ 0x00, /* 00000000 */
+ 0x00, /* 00000000 */
+
+ /* 138 0x8a '' */
+ 0x00, /* 00000000 */
+ 0x60, /* 01100000 */
+ 0x30, /* 00110000 */
+ 0x18, /* 00011000 */
+ 0x00, /* 00000000 */
+ 0x7c, /* 01111100 */
+ 0xc6, /* 11000110 */
+ 0xfe, /* 11111110 */
+ 0xc0, /* 11000000 */
+ 0xc0, /* 11000000 */
+ 0xc6, /* 11000110 */
+ 0x7c, /* 01111100 */
+ 0x00, /* 00000000 */
+ 0x00, /* 00000000 */
+ 0x00, /* 00000000 */
+ 0x00, /* 00000000 */
+
+ /* 139 0x8b '' */
+ 0x00, /* 00000000 */
+ 0x00, /* 00000000 */
+ 0x66, /* 01100110 */
+ 0x00, /* 00000000 */
+ 0x00, /* 00000000 */
+ 0x38, /* 00111000 */
+ 0x18, /* 00011000 */
+ 0x18, /* 00011000 */
+ 0x18, /* 00011000 */
+ 0x18, /* 00011000 */
+ 0x18, /* 00011000 */
+ 0x3c, /* 00111100 */
+ 0x00, /* 00000000 */
+ 0x00, /* 00000000 */
+ 0x00, /* 00000000 */
+ 0x00, /* 00000000 */
+
+ /* 140 0x8c '' */
+ 0x00, /* 00000000 */
+ 0x18, /* 00011000 */
+ 0x3c, /* 00111100 */
+ 0x66, /* 01100110 */
+ 0x00, /* 00000000 */
+ 0x38, /* 00111000 */
+ 0x18, /* 00011000 */
+ 0x18, /* 00011000 */
+ 0x18, /* 00011000 */
+ 0x18, /* 00011000 */
+ 0x18, /* 00011000 */
+ 0x3c, /* 00111100 */
+ 0x00, /* 00000000 */
+ 0x00, /* 00000000 */
+ 0x00, /* 00000000 */
+ 0x00, /* 00000000 */
+
+ /* 141 0x8d '' */
+ 0x00, /* 00000000 */
+ 0x60, /* 01100000 */
+ 0x30, /* 00110000 */
+ 0x18, /* 00011000 */
+ 0x00, /* 00000000 */
+ 0x38, /* 00111000 */
+ 0x18, /* 00011000 */
+ 0x18, /* 00011000 */
+ 0x18, /* 00011000 */
+ 0x18, /* 00011000 */
+ 0x18, /* 00011000 */
+ 0x3c, /* 00111100 */
+ 0x00, /* 00000000 */
+ 0x00, /* 00000000 */
+ 0x00, /* 00000000 */
+ 0x00, /* 00000000 */
+
+ /* 142 0x8e '' */
+ 0x00, /* 00000000 */
+ 0xc6, /* 11000110 */
+ 0x00, /* 00000000 */
+ 0x10, /* 00010000 */
+ 0x38, /* 00111000 */
+ 0x6c, /* 01101100 */
+ 0xc6, /* 11000110 */
+ 0xc6, /* 11000110 */
+ 0xfe, /* 11111110 */
+ 0xc6, /* 11000110 */
+ 0xc6, /* 11000110 */
+ 0xc6, /* 11000110 */
+ 0x00, /* 00000000 */
+ 0x00, /* 00000000 */
+ 0x00, /* 00000000 */
+ 0x00, /* 00000000 */
+
+ /* 143 0x8f '' */
+ 0x38, /* 00111000 */
+ 0x6c, /* 01101100 */
+ 0x38, /* 00111000 */
+ 0x10, /* 00010000 */
+ 0x38, /* 00111000 */
+ 0x6c, /* 01101100 */
+ 0xc6, /* 11000110 */
+ 0xfe, /* 11111110 */
+ 0xc6, /* 11000110 */
+ 0xc6, /* 11000110 */
+ 0xc6, /* 11000110 */
+ 0xc6, /* 11000110 */
+ 0x00, /* 00000000 */
+ 0x00, /* 00000000 */
+ 0x00, /* 00000000 */
+ 0x00, /* 00000000 */
+
+ /* 144 0x90 '' */
+ 0x0c, /* 00001100 */
+ 0x18, /* 00011000 */
+ 0x00, /* 00000000 */
+ 0xfe, /* 11111110 */
+ 0x66, /* 01100110 */
+ 0x62, /* 01100010 */
+ 0x68, /* 01101000 */
+ 0x78, /* 01111000 */
+ 0x68, /* 01101000 */
+ 0x62, /* 01100010 */
+ 0x66, /* 01100110 */
+ 0xfe, /* 11111110 */
+ 0x00, /* 00000000 */
+ 0x00, /* 00000000 */
+ 0x00, /* 00000000 */
+ 0x00, /* 00000000 */
+
+ /* 145 0x91 '' */
+ 0x00, /* 00000000 */
+ 0x00, /* 00000000 */
+ 0x00, /* 00000000 */
+ 0x00, /* 00000000 */
+ 0x00, /* 00000000 */
+ 0xec, /* 11101100 */
+ 0x36, /* 00110110 */
+ 0x36, /* 00110110 */
+ 0x7e, /* 01111110 */
+ 0xd8, /* 11011000 */
+ 0xd8, /* 11011000 */
+ 0x6e, /* 01101110 */
+ 0x00, /* 00000000 */
+ 0x00, /* 00000000 */
+ 0x00, /* 00000000 */
+ 0x00, /* 00000000 */
+
+ /* 146 0x92 '' */
+ 0x00, /* 00000000 */
+ 0x00, /* 00000000 */
+ 0x3e, /* 00111110 */
+ 0x6c, /* 01101100 */
+ 0xcc, /* 11001100 */
+ 0xcc, /* 11001100 */
+ 0xfe, /* 11111110 */
+ 0xcc, /* 11001100 */
+ 0xcc, /* 11001100 */
+ 0xcc, /* 11001100 */
+ 0xcc, /* 11001100 */
+ 0xce, /* 11001110 */
+ 0x00, /* 00000000 */
+ 0x00, /* 00000000 */
+ 0x00, /* 00000000 */
+ 0x00, /* 00000000 */
+
+ /* 147 0x93 '' */
+ 0x00, /* 00000000 */
+ 0x10, /* 00010000 */
+ 0x38, /* 00111000 */
+ 0x6c, /* 01101100 */
+ 0x00, /* 00000000 */
+ 0x7c, /* 01111100 */
+ 0xc6, /* 11000110 */
+ 0xc6, /* 11000110 */
+ 0xc6, /* 11000110 */
+ 0xc6, /* 11000110 */
+ 0xc6, /* 11000110 */
+ 0x7c, /* 01111100 */
+ 0x00, /* 00000000 */
+ 0x00, /* 00000000 */
+ 0x00, /* 00000000 */
+ 0x00, /* 00000000 */
+
+ /* 148 0x94 '' */
+ 0x00, /* 00000000 */
+ 0x00, /* 00000000 */
+ 0xc6, /* 11000110 */
+ 0x00, /* 00000000 */
+ 0x00, /* 00000000 */
+ 0x7c, /* 01111100 */
+ 0xc6, /* 11000110 */
+ 0xc6, /* 11000110 */
+ 0xc6, /* 11000110 */
+ 0xc6, /* 11000110 */
+ 0xc6, /* 11000110 */
+ 0x7c, /* 01111100 */
+ 0x00, /* 00000000 */
+ 0x00, /* 00000000 */
+ 0x00, /* 00000000 */
+ 0x00, /* 00000000 */
+
+ /* 149 0x95 '' */
+ 0x00, /* 00000000 */
+ 0x60, /* 01100000 */
+ 0x30, /* 00110000 */
+ 0x18, /* 00011000 */
+ 0x00, /* 00000000 */
+ 0x7c, /* 01111100 */
+ 0xc6, /* 11000110 */
+ 0xc6, /* 11000110 */
+ 0xc6, /* 11000110 */
+ 0xc6, /* 11000110 */
+ 0xc6, /* 11000110 */
+ 0x7c, /* 01111100 */
+ 0x00, /* 00000000 */
+ 0x00, /* 00000000 */
+ 0x00, /* 00000000 */
+ 0x00, /* 00000000 */
+
+ /* 150 0x96 '' */
+ 0x00, /* 00000000 */
+ 0x30, /* 00110000 */
+ 0x78, /* 01111000 */
+ 0xcc, /* 11001100 */
+ 0x00, /* 00000000 */
+ 0xcc, /* 11001100 */
+ 0xcc, /* 11001100 */
+ 0xcc, /* 11001100 */
+ 0xcc, /* 11001100 */
+ 0xcc, /* 11001100 */
+ 0xcc, /* 11001100 */
+ 0x76, /* 01110110 */
+ 0x00, /* 00000000 */
+ 0x00, /* 00000000 */
+ 0x00, /* 00000000 */
+ 0x00, /* 00000000 */
+
+ /* 151 0x97 '' */
+ 0x00, /* 00000000 */
+ 0x60, /* 01100000 */
+ 0x30, /* 00110000 */
+ 0x18, /* 00011000 */
+ 0x00, /* 00000000 */
+ 0xcc, /* 11001100 */
+ 0xcc, /* 11001100 */
+ 0xcc, /* 11001100 */
+ 0xcc, /* 11001100 */
+ 0xcc, /* 11001100 */
+ 0xcc, /* 11001100 */
+ 0x76, /* 01110110 */
+ 0x00, /* 00000000 */
+ 0x00, /* 00000000 */
+ 0x00, /* 00000000 */
+ 0x00, /* 00000000 */
+
+ /* 152 0x98 '' */
+ 0x00, /* 00000000 */
+ 0x00, /* 00000000 */
+ 0xc6, /* 11000110 */
+ 0x00, /* 00000000 */
+ 0x00, /* 00000000 */
+ 0xc6, /* 11000110 */
+ 0xc6, /* 11000110 */
+ 0xc6, /* 11000110 */
+ 0xc6, /* 11000110 */
+ 0xc6, /* 11000110 */
+ 0xc6, /* 11000110 */
+ 0x7e, /* 01111110 */
+ 0x06, /* 00000110 */
+ 0x0c, /* 00001100 */
+ 0x78, /* 01111000 */
+ 0x00, /* 00000000 */
+
+ /* 153 0x99 '' */
+ 0x00, /* 00000000 */
+ 0xc6, /* 11000110 */
+ 0x00, /* 00000000 */
+ 0x7c, /* 01111100 */
+ 0xc6, /* 11000110 */
+ 0xc6, /* 11000110 */
+ 0xc6, /* 11000110 */
+ 0xc6, /* 11000110 */
+ 0xc6, /* 11000110 */
+ 0xc6, /* 11000110 */
+ 0xc6, /* 11000110 */
+ 0x7c, /* 01111100 */
+ 0x00, /* 00000000 */
+ 0x00, /* 00000000 */
+ 0x00, /* 00000000 */
+ 0x00, /* 00000000 */
+
+ /* 154 0x9a '' */
+ 0x00, /* 00000000 */
+ 0xc6, /* 11000110 */
+ 0x00, /* 00000000 */
+ 0xc6, /* 11000110 */
+ 0xc6, /* 11000110 */
+ 0xc6, /* 11000110 */
+ 0xc6, /* 11000110 */
+ 0xc6, /* 11000110 */
+ 0xc6, /* 11000110 */
+ 0xc6, /* 11000110 */
+ 0xc6, /* 11000110 */
+ 0x7c, /* 01111100 */
+ 0x00, /* 00000000 */
+ 0x00, /* 00000000 */
+ 0x00, /* 00000000 */
+ 0x00, /* 00000000 */
+
+ /* 155 0x9b '' */
+ 0x00, /* 00000000 */
+ 0x18, /* 00011000 */
+ 0x18, /* 00011000 */
+ 0x7c, /* 01111100 */
+ 0xc6, /* 11000110 */
+ 0xc0, /* 11000000 */
+ 0xc0, /* 11000000 */
+ 0xc0, /* 11000000 */
+ 0xc6, /* 11000110 */
+ 0x7c, /* 01111100 */
+ 0x18, /* 00011000 */
+ 0x18, /* 00011000 */
+ 0x00, /* 00000000 */
+ 0x00, /* 00000000 */
+ 0x00, /* 00000000 */
+ 0x00, /* 00000000 */
+
+ /* 156 0x9c '' */
+ 0x00, /* 00000000 */
+ 0x38, /* 00111000 */
+ 0x6c, /* 01101100 */
+ 0x64, /* 01100100 */
+ 0x60, /* 01100000 */
+ 0xf0, /* 11110000 */
+ 0x60, /* 01100000 */
+ 0x60, /* 01100000 */
+ 0x60, /* 01100000 */
+ 0x60, /* 01100000 */
+ 0xe6, /* 11100110 */
+ 0xfc, /* 11111100 */
+ 0x00, /* 00000000 */
+ 0x00, /* 00000000 */
+ 0x00, /* 00000000 */
+ 0x00, /* 00000000 */
+
+ /* 157 0x9d '' */
+ 0x00, /* 00000000 */
+ 0x00, /* 00000000 */
+ 0x66, /* 01100110 */
+ 0x66, /* 01100110 */
+ 0x3c, /* 00111100 */
+ 0x18, /* 00011000 */
+ 0x7e, /* 01111110 */
+ 0x18, /* 00011000 */
+ 0x7e, /* 01111110 */
+ 0x18, /* 00011000 */
+ 0x18, /* 00011000 */
+ 0x18, /* 00011000 */
+ 0x00, /* 00000000 */
+ 0x00, /* 00000000 */
+ 0x00, /* 00000000 */
+ 0x00, /* 00000000 */
+
+ /* 158 0x9e '' */
+ 0x00, /* 00000000 */
+ 0xf8, /* 11111000 */
+ 0xcc, /* 11001100 */
+ 0xcc, /* 11001100 */
+ 0xf8, /* 11111000 */
+ 0xc4, /* 11000100 */
+ 0xcc, /* 11001100 */
+ 0xde, /* 11011110 */
+ 0xcc, /* 11001100 */
+ 0xcc, /* 11001100 */
+ 0xcc, /* 11001100 */
+ 0xc6, /* 11000110 */
+ 0x00, /* 00000000 */
+ 0x00, /* 00000000 */
+ 0x00, /* 00000000 */
+ 0x00, /* 00000000 */
+
+ /* 159 0x9f '' */
+ 0x00, /* 00000000 */
+ 0x0e, /* 00001110 */
+ 0x1b, /* 00011011 */
+ 0x18, /* 00011000 */
+ 0x18, /* 00011000 */
+ 0x18, /* 00011000 */
+ 0x7e, /* 01111110 */
+ 0x18, /* 00011000 */
+ 0x18, /* 00011000 */
+ 0x18, /* 00011000 */
+ 0xd8, /* 11011000 */
+ 0x70, /* 01110000 */
+ 0x00, /* 00000000 */
+ 0x00, /* 00000000 */
+ 0x00, /* 00000000 */
+ 0x00, /* 00000000 */
+
+ /* 160 0xa0 ' ' */
+ 0x00, /* 00000000 */
+ 0x18, /* 00011000 */
+ 0x30, /* 00110000 */
+ 0x60, /* 01100000 */
+ 0x00, /* 00000000 */
+ 0x78, /* 01111000 */
+ 0x0c, /* 00001100 */
+ 0x7c, /* 01111100 */
+ 0xcc, /* 11001100 */
+ 0xcc, /* 11001100 */
+ 0xcc, /* 11001100 */
+ 0x76, /* 01110110 */
+ 0x00, /* 00000000 */
+ 0x00, /* 00000000 */
+ 0x00, /* 00000000 */
+ 0x00, /* 00000000 */
+
+ /* 161 0xa1 '¡' */
+ 0x00, /* 00000000 */
+ 0x0c, /* 00001100 */
+ 0x18, /* 00011000 */
+ 0x30, /* 00110000 */
+ 0x00, /* 00000000 */
+ 0x38, /* 00111000 */
+ 0x18, /* 00011000 */
+ 0x18, /* 00011000 */
+ 0x18, /* 00011000 */
+ 0x18, /* 00011000 */
+ 0x18, /* 00011000 */
+ 0x3c, /* 00111100 */
+ 0x00, /* 00000000 */
+ 0x00, /* 00000000 */
+ 0x00, /* 00000000 */
+ 0x00, /* 00000000 */
+
+ /* 162 0xa2 '¢' */
+ 0x00, /* 00000000 */
+ 0x18, /* 00011000 */
+ 0x30, /* 00110000 */
+ 0x60, /* 01100000 */
+ 0x00, /* 00000000 */
+ 0x7c, /* 01111100 */
+ 0xc6, /* 11000110 */
+ 0xc6, /* 11000110 */
+ 0xc6, /* 11000110 */
+ 0xc6, /* 11000110 */
+ 0xc6, /* 11000110 */
+ 0x7c, /* 01111100 */
+ 0x00, /* 00000000 */
+ 0x00, /* 00000000 */
+ 0x00, /* 00000000 */
+ 0x00, /* 00000000 */
+
+ /* 163 0xa3 '£' */
+ 0x00, /* 00000000 */
+ 0x18, /* 00011000 */
+ 0x30, /* 00110000 */
+ 0x60, /* 01100000 */
+ 0x00, /* 00000000 */
+ 0xcc, /* 11001100 */
+ 0xcc, /* 11001100 */
+ 0xcc, /* 11001100 */
+ 0xcc, /* 11001100 */
+ 0xcc, /* 11001100 */
+ 0xcc, /* 11001100 */
+ 0x76, /* 01110110 */
+ 0x00, /* 00000000 */
+ 0x00, /* 00000000 */
+ 0x00, /* 00000000 */
+ 0x00, /* 00000000 */
+
+ /* 164 0xa4 '¤' */
+ 0x00, /* 00000000 */
+ 0x00, /* 00000000 */
+ 0x76, /* 01110110 */
+ 0xdc, /* 11011100 */
+ 0x00, /* 00000000 */
+ 0xdc, /* 11011100 */
+ 0x66, /* 01100110 */
+ 0x66, /* 01100110 */
+ 0x66, /* 01100110 */
+ 0x66, /* 01100110 */
+ 0x66, /* 01100110 */
+ 0x66, /* 01100110 */
+ 0x00, /* 00000000 */
+ 0x00, /* 00000000 */
+ 0x00, /* 00000000 */
+ 0x00, /* 00000000 */
+
+ /* 165 0xa5 '¥' */
+ 0x76, /* 01110110 */
+ 0xdc, /* 11011100 */
+ 0x00, /* 00000000 */
+ 0xc6, /* 11000110 */
+ 0xe6, /* 11100110 */
+ 0xf6, /* 11110110 */
+ 0xfe, /* 11111110 */
+ 0xde, /* 11011110 */
+ 0xce, /* 11001110 */
+ 0xc6, /* 11000110 */
+ 0xc6, /* 11000110 */
+ 0xc6, /* 11000110 */
+ 0x00, /* 00000000 */
+ 0x00, /* 00000000 */
+ 0x00, /* 00000000 */
+ 0x00, /* 00000000 */
+
+ /* 166 0xa6 '¦' */
+ 0x00, /* 00000000 */
+ 0x00, /* 00000000 */
+ 0x3c, /* 00111100 */
+ 0x6c, /* 01101100 */
+ 0x6c, /* 01101100 */
+ 0x3e, /* 00111110 */
+ 0x00, /* 00000000 */
+ 0x7e, /* 01111110 */
+ 0x00, /* 00000000 */
+ 0x00, /* 00000000 */
+ 0x00, /* 00000000 */
+ 0x00, /* 00000000 */
+ 0x00, /* 00000000 */
+ 0x00, /* 00000000 */
+ 0x00, /* 00000000 */
+ 0x00, /* 00000000 */
+
+ /* 167 0xa7 '§' */
+ 0x00, /* 00000000 */
+ 0x00, /* 00000000 */
+ 0x38, /* 00111000 */
+ 0x6c, /* 01101100 */
+ 0x6c, /* 01101100 */
+ 0x38, /* 00111000 */
+ 0x00, /* 00000000 */
+ 0x7c, /* 01111100 */
+ 0x00, /* 00000000 */
+ 0x00, /* 00000000 */
+ 0x00, /* 00000000 */
+ 0x00, /* 00000000 */
+ 0x00, /* 00000000 */
+ 0x00, /* 00000000 */
+ 0x00, /* 00000000 */
+ 0x00, /* 00000000 */
+
+ /* 168 0xa8 '¨' */
+ 0x00, /* 00000000 */
+ 0x00, /* 00000000 */
+ 0x30, /* 00110000 */
+ 0x30, /* 00110000 */
+ 0x00, /* 00000000 */
+ 0x30, /* 00110000 */
+ 0x30, /* 00110000 */
+ 0x60, /* 01100000 */
+ 0xc0, /* 11000000 */
+ 0xc6, /* 11000110 */
+ 0xc6, /* 11000110 */
+ 0x7c, /* 01111100 */
+ 0x00, /* 00000000 */
+ 0x00, /* 00000000 */
+ 0x00, /* 00000000 */
+ 0x00, /* 00000000 */
+
+ /* 169 0xa9 '©' */
+ 0x00, /* 00000000 */
+ 0x00, /* 00000000 */
+ 0x00, /* 00000000 */
+ 0x00, /* 00000000 */
+ 0x00, /* 00000000 */
+ 0x00, /* 00000000 */
+ 0xfe, /* 11111110 */
+ 0xc0, /* 11000000 */
+ 0xc0, /* 11000000 */
+ 0xc0, /* 11000000 */
+ 0xc0, /* 11000000 */
+ 0x00, /* 00000000 */
+ 0x00, /* 00000000 */
+ 0x00, /* 00000000 */
+ 0x00, /* 00000000 */
+ 0x00, /* 00000000 */
+
+ /* 170 0xaa 'ª' */
+ 0x00, /* 00000000 */
+ 0x00, /* 00000000 */
+ 0x00, /* 00000000 */
+ 0x00, /* 00000000 */
+ 0x00, /* 00000000 */
+ 0x00, /* 00000000 */
+ 0xfe, /* 11111110 */
+ 0x06, /* 00000110 */
+ 0x06, /* 00000110 */
+ 0x06, /* 00000110 */
+ 0x06, /* 00000110 */
+ 0x00, /* 00000000 */
+ 0x00, /* 00000000 */
+ 0x00, /* 00000000 */
+ 0x00, /* 00000000 */
+ 0x00, /* 00000000 */
+
+ /* 171 0xab '«' */
+ 0x00, /* 00000000 */
+ 0x60, /* 01100000 */
+ 0xe0, /* 11100000 */
+ 0x62, /* 01100010 */
+ 0x66, /* 01100110 */
+ 0x6c, /* 01101100 */
+ 0x18, /* 00011000 */
+ 0x30, /* 00110000 */
+ 0x60, /* 01100000 */
+ 0xdc, /* 11011100 */
+ 0x86, /* 10000110 */
+ 0x0c, /* 00001100 */
+ 0x18, /* 00011000 */
+ 0x3e, /* 00111110 */
+ 0x00, /* 00000000 */
+ 0x00, /* 00000000 */
+
+ /* 172 0xac '¬' */
+ 0x00, /* 00000000 */
+ 0x60, /* 01100000 */
+ 0xe0, /* 11100000 */
+ 0x62, /* 01100010 */
+ 0x66, /* 01100110 */
+ 0x6c, /* 01101100 */
+ 0x18, /* 00011000 */
+ 0x30, /* 00110000 */
+ 0x66, /* 01100110 */
+ 0xce, /* 11001110 */
+ 0x9a, /* 10011010 */
+ 0x3f, /* 00111111 */
+ 0x06, /* 00000110 */
+ 0x06, /* 00000110 */
+ 0x00, /* 00000000 */
+ 0x00, /* 00000000 */
+
+ /* 173 0xad '' */
+ 0x00, /* 00000000 */
+ 0x00, /* 00000000 */
+ 0x18, /* 00011000 */
+ 0x18, /* 00011000 */
+ 0x00, /* 00000000 */
+ 0x18, /* 00011000 */
+ 0x18, /* 00011000 */
+ 0x18, /* 00011000 */
+ 0x3c, /* 00111100 */
+ 0x3c, /* 00111100 */
+ 0x3c, /* 00111100 */
+ 0x18, /* 00011000 */
+ 0x00, /* 00000000 */
+ 0x00, /* 00000000 */
+ 0x00, /* 00000000 */
+ 0x00, /* 00000000 */
+
+ /* 174 0xae '®' */
+ 0x00, /* 00000000 */
+ 0x00, /* 00000000 */
+ 0x00, /* 00000000 */
+ 0x00, /* 00000000 */
+ 0x00, /* 00000000 */
+ 0x36, /* 00110110 */
+ 0x6c, /* 01101100 */
+ 0xd8, /* 11011000 */
+ 0x6c, /* 01101100 */
+ 0x36, /* 00110110 */
+ 0x00, /* 00000000 */
+ 0x00, /* 00000000 */
+ 0x00, /* 00000000 */
+ 0x00, /* 00000000 */
+ 0x00, /* 00000000 */
+ 0x00, /* 00000000 */
+
+ /* 175 0xaf '¯' */
+ 0x00, /* 00000000 */
+ 0x00, /* 00000000 */
+ 0x00, /* 00000000 */
+ 0x00, /* 00000000 */
+ 0x00, /* 00000000 */
+ 0xd8, /* 11011000 */
+ 0x6c, /* 01101100 */
+ 0x36, /* 00110110 */
+ 0x6c, /* 01101100 */
+ 0xd8, /* 11011000 */
+ 0x00, /* 00000000 */
+ 0x00, /* 00000000 */
+ 0x00, /* 00000000 */
+ 0x00, /* 00000000 */
+ 0x00, /* 00000000 */
+ 0x00, /* 00000000 */
+
+ /* 176 0xb0 '°' */
+ 0x11, /* 00010001 */
+ 0x44, /* 01000100 */
+ 0x11, /* 00010001 */
+ 0x44, /* 01000100 */
+ 0x11, /* 00010001 */
+ 0x44, /* 01000100 */
+ 0x11, /* 00010001 */
+ 0x44, /* 01000100 */
+ 0x11, /* 00010001 */
+ 0x44, /* 01000100 */
+ 0x11, /* 00010001 */
+ 0x44, /* 01000100 */
+ 0x11, /* 00010001 */
+ 0x44, /* 01000100 */
+ 0x11, /* 00010001 */
+ 0x44, /* 01000100 */
+
+ /* 177 0xb1 '±' */
+ 0x55, /* 01010101 */
+ 0xaa, /* 10101010 */
+ 0x55, /* 01010101 */
+ 0xaa, /* 10101010 */
+ 0x55, /* 01010101 */
+ 0xaa, /* 10101010 */
+ 0x55, /* 01010101 */
+ 0xaa, /* 10101010 */
+ 0x55, /* 01010101 */
+ 0xaa, /* 10101010 */
+ 0x55, /* 01010101 */
+ 0xaa, /* 10101010 */
+ 0x55, /* 01010101 */
+ 0xaa, /* 10101010 */
+ 0x55, /* 01010101 */
+ 0xaa, /* 10101010 */
+
+ /* 178 0xb2 '²' */
+ 0xdd, /* 11011101 */
+ 0x77, /* 01110111 */
+ 0xdd, /* 11011101 */
+ 0x77, /* 01110111 */
+ 0xdd, /* 11011101 */
+ 0x77, /* 01110111 */
+ 0xdd, /* 11011101 */
+ 0x77, /* 01110111 */
+ 0xdd, /* 11011101 */
+ 0x77, /* 01110111 */
+ 0xdd, /* 11011101 */
+ 0x77, /* 01110111 */
+ 0xdd, /* 11011101 */
+ 0x77, /* 01110111 */
+ 0xdd, /* 11011101 */
+ 0x77, /* 01110111 */
+
+ /* 179 0xb3 '³' */
+ 0x18, /* 00011000 */
+ 0x18, /* 00011000 */
+ 0x18, /* 00011000 */
+ 0x18, /* 00011000 */
+ 0x18, /* 00011000 */
+ 0x18, /* 00011000 */
+ 0x18, /* 00011000 */
+ 0x18, /* 00011000 */
+ 0x18, /* 00011000 */
+ 0x18, /* 00011000 */
+ 0x18, /* 00011000 */
+ 0x18, /* 00011000 */
+ 0x18, /* 00011000 */
+ 0x18, /* 00011000 */
+ 0x18, /* 00011000 */
+ 0x18, /* 00011000 */
+
+ /* 180 0xb4 '´' */
+ 0x18, /* 00011000 */
+ 0x18, /* 00011000 */
+ 0x18, /* 00011000 */
+ 0x18, /* 00011000 */
+ 0x18, /* 00011000 */
+ 0x18, /* 00011000 */
+ 0x18, /* 00011000 */
+ 0xf8, /* 11111000 */
+ 0x18, /* 00011000 */
+ 0x18, /* 00011000 */
+ 0x18, /* 00011000 */
+ 0x18, /* 00011000 */
+ 0x18, /* 00011000 */
+ 0x18, /* 00011000 */
+ 0x18, /* 00011000 */
+ 0x18, /* 00011000 */
+
+ /* 181 0xb5 'µ' */
+ 0x18, /* 00011000 */
+ 0x18, /* 00011000 */
+ 0x18, /* 00011000 */
+ 0x18, /* 00011000 */
+ 0x18, /* 00011000 */
+ 0xf8, /* 11111000 */
+ 0x18, /* 00011000 */
+ 0xf8, /* 11111000 */
+ 0x18, /* 00011000 */
+ 0x18, /* 00011000 */
+ 0x18, /* 00011000 */
+ 0x18, /* 00011000 */
+ 0x18, /* 00011000 */
+ 0x18, /* 00011000 */
+ 0x18, /* 00011000 */
+ 0x18, /* 00011000 */
+
+ /* 182 0xb6 '¶' */
+ 0x36, /* 00110110 */
+ 0x36, /* 00110110 */
+ 0x36, /* 00110110 */
+ 0x36, /* 00110110 */
+ 0x36, /* 00110110 */
+ 0x36, /* 00110110 */
+ 0x36, /* 00110110 */
+ 0xf6, /* 11110110 */
+ 0x36, /* 00110110 */
+ 0x36, /* 00110110 */
+ 0x36, /* 00110110 */
+ 0x36, /* 00110110 */
+ 0x36, /* 00110110 */
+ 0x36, /* 00110110 */
+ 0x36, /* 00110110 */
+ 0x36, /* 00110110 */
+
+ /* 183 0xb7 '·' */
+ 0x00, /* 00000000 */
+ 0x00, /* 00000000 */
+ 0x00, /* 00000000 */
+ 0x00, /* 00000000 */
+ 0x00, /* 00000000 */
+ 0x00, /* 00000000 */
+ 0x00, /* 00000000 */
+ 0xfe, /* 11111110 */
+ 0x36, /* 00110110 */
+ 0x36, /* 00110110 */
+ 0x36, /* 00110110 */
+ 0x36, /* 00110110 */
+ 0x36, /* 00110110 */
+ 0x36, /* 00110110 */
+ 0x36, /* 00110110 */
+ 0x36, /* 00110110 */
+
+ /* 184 0xb8 '¸' */
+ 0x00, /* 00000000 */
+ 0x00, /* 00000000 */
+ 0x00, /* 00000000 */
+ 0x00, /* 00000000 */
+ 0x00, /* 00000000 */
+ 0xf8, /* 11111000 */
+ 0x18, /* 00011000 */
+ 0xf8, /* 11111000 */
+ 0x18, /* 00011000 */
+ 0x18, /* 00011000 */
+ 0x18, /* 00011000 */
+ 0x18, /* 00011000 */
+ 0x18, /* 00011000 */
+ 0x18, /* 00011000 */
+ 0x18, /* 00011000 */
+ 0x18, /* 00011000 */
+
+ /* 185 0xb9 '¹' */
+ 0x36, /* 00110110 */
+ 0x36, /* 00110110 */
+ 0x36, /* 00110110 */
+ 0x36, /* 00110110 */
+ 0x36, /* 00110110 */
+ 0xf6, /* 11110110 */
+ 0x06, /* 00000110 */
+ 0xf6, /* 11110110 */
+ 0x36, /* 00110110 */
+ 0x36, /* 00110110 */
+ 0x36, /* 00110110 */
+ 0x36, /* 00110110 */
+ 0x36, /* 00110110 */
+ 0x36, /* 00110110 */
+ 0x36, /* 00110110 */
+ 0x36, /* 00110110 */
+
+ /* 186 0xba 'º' */
+ 0x36, /* 00110110 */
+ 0x36, /* 00110110 */
+ 0x36, /* 00110110 */
+ 0x36, /* 00110110 */
+ 0x36, /* 00110110 */
+ 0x36, /* 00110110 */
+ 0x36, /* 00110110 */
+ 0x36, /* 00110110 */
+ 0x36, /* 00110110 */
+ 0x36, /* 00110110 */
+ 0x36, /* 00110110 */
+ 0x36, /* 00110110 */
+ 0x36, /* 00110110 */
+ 0x36, /* 00110110 */
+ 0x36, /* 00110110 */
+ 0x36, /* 00110110 */
+
+ /* 187 0xbb '»' */
+ 0x00, /* 00000000 */
+ 0x00, /* 00000000 */
+ 0x00, /* 00000000 */
+ 0x00, /* 00000000 */
+ 0x00, /* 00000000 */
+ 0xfe, /* 11111110 */
+ 0x06, /* 00000110 */
+ 0xf6, /* 11110110 */
+ 0x36, /* 00110110 */
+ 0x36, /* 00110110 */
+ 0x36, /* 00110110 */
+ 0x36, /* 00110110 */
+ 0x36, /* 00110110 */
+ 0x36, /* 00110110 */
+ 0x36, /* 00110110 */
+ 0x36, /* 00110110 */
+
+ /* 188 0xbc '¼' */
+ 0x36, /* 00110110 */
+ 0x36, /* 00110110 */
+ 0x36, /* 00110110 */
+ 0x36, /* 00110110 */
+ 0x36, /* 00110110 */
+ 0xf6, /* 11110110 */
+ 0x06, /* 00000110 */
+ 0xfe, /* 11111110 */
+ 0x00, /* 00000000 */
+ 0x00, /* 00000000 */
+ 0x00, /* 00000000 */
+ 0x00, /* 00000000 */
+ 0x00, /* 00000000 */
+ 0x00, /* 00000000 */
+ 0x00, /* 00000000 */
+ 0x00, /* 00000000 */
+
+ /* 189 0xbd '½' */
+ 0x36, /* 00110110 */
+ 0x36, /* 00110110 */
+ 0x36, /* 00110110 */
+ 0x36, /* 00110110 */
+ 0x36, /* 00110110 */
+ 0x36, /* 00110110 */
+ 0x36, /* 00110110 */
+ 0xfe, /* 11111110 */
+ 0x00, /* 00000000 */
+ 0x00, /* 00000000 */
+ 0x00, /* 00000000 */
+ 0x00, /* 00000000 */
+ 0x00, /* 00000000 */
+ 0x00, /* 00000000 */
+ 0x00, /* 00000000 */
+ 0x00, /* 00000000 */
+
+ /* 190 0xbe '¾' */
+ 0x18, /* 00011000 */
+ 0x18, /* 00011000 */
+ 0x18, /* 00011000 */
+ 0x18, /* 00011000 */
+ 0x18, /* 00011000 */
+ 0xf8, /* 11111000 */
+ 0x18, /* 00011000 */
+ 0xf8, /* 11111000 */
+ 0x00, /* 00000000 */
+ 0x00, /* 00000000 */
+ 0x00, /* 00000000 */
+ 0x00, /* 00000000 */
+ 0x00, /* 00000000 */
+ 0x00, /* 00000000 */
+ 0x00, /* 00000000 */
+ 0x00, /* 00000000 */
+
+ /* 191 0xbf '¿' */
+ 0x00, /* 00000000 */
+ 0x00, /* 00000000 */
+ 0x00, /* 00000000 */
+ 0x00, /* 00000000 */
+ 0x00, /* 00000000 */
+ 0x00, /* 00000000 */
+ 0x00, /* 00000000 */
+ 0xf8, /* 11111000 */
+ 0x18, /* 00011000 */
+ 0x18, /* 00011000 */
+ 0x18, /* 00011000 */
+ 0x18, /* 00011000 */
+ 0x18, /* 00011000 */
+ 0x18, /* 00011000 */
+ 0x18, /* 00011000 */
+ 0x18, /* 00011000 */
+
+ /* 192 0xc0 'À' */
+ 0x18, /* 00011000 */
+ 0x18, /* 00011000 */
+ 0x18, /* 00011000 */
+ 0x18, /* 00011000 */
+ 0x18, /* 00011000 */
+ 0x18, /* 00011000 */
+ 0x18, /* 00011000 */
+ 0x1f, /* 00011111 */
+ 0x00, /* 00000000 */
+ 0x00, /* 00000000 */
+ 0x00, /* 00000000 */
+ 0x00, /* 00000000 */
+ 0x00, /* 00000000 */
+ 0x00, /* 00000000 */
+ 0x00, /* 00000000 */
+ 0x00, /* 00000000 */
+
+ /* 193 0xc1 'Á' */
+ 0x18, /* 00011000 */
+ 0x18, /* 00011000 */
+ 0x18, /* 00011000 */
+ 0x18, /* 00011000 */
+ 0x18, /* 00011000 */
+ 0x18, /* 00011000 */
+ 0x18, /* 00011000 */
+ 0xff, /* 11111111 */
+ 0x00, /* 00000000 */
+ 0x00, /* 00000000 */
+ 0x00, /* 00000000 */
+ 0x00, /* 00000000 */
+ 0x00, /* 00000000 */
+ 0x00, /* 00000000 */
+ 0x00, /* 00000000 */
+ 0x00, /* 00000000 */
+
+ /* 194 0xc2 'Â' */
+ 0x00, /* 00000000 */
+ 0x00, /* 00000000 */
+ 0x00, /* 00000000 */
+ 0x00, /* 00000000 */
+ 0x00, /* 00000000 */
+ 0x00, /* 00000000 */
+ 0x00, /* 00000000 */
+ 0xff, /* 11111111 */
+ 0x18, /* 00011000 */
+ 0x18, /* 00011000 */
+ 0x18, /* 00011000 */
+ 0x18, /* 00011000 */
+ 0x18, /* 00011000 */
+ 0x18, /* 00011000 */
+ 0x18, /* 00011000 */
+ 0x18, /* 00011000 */
+
+ /* 195 0xc3 'Ã' */
+ 0x18, /* 00011000 */
+ 0x18, /* 00011000 */
+ 0x18, /* 00011000 */
+ 0x18, /* 00011000 */
+ 0x18, /* 00011000 */
+ 0x18, /* 00011000 */
+ 0x18, /* 00011000 */
+ 0x1f, /* 00011111 */
+ 0x18, /* 00011000 */
+ 0x18, /* 00011000 */
+ 0x18, /* 00011000 */
+ 0x18, /* 00011000 */
+ 0x18, /* 00011000 */
+ 0x18, /* 00011000 */
+ 0x18, /* 00011000 */
+ 0x18, /* 00011000 */
+
+ /* 196 0xc4 'Ä' */
+ 0x00, /* 00000000 */
+ 0x00, /* 00000000 */
+ 0x00, /* 00000000 */
+ 0x00, /* 00000000 */
+ 0x00, /* 00000000 */
+ 0x00, /* 00000000 */
+ 0x00, /* 00000000 */
+ 0xff, /* 11111111 */
+ 0x00, /* 00000000 */
+ 0x00, /* 00000000 */
+ 0x00, /* 00000000 */
+ 0x00, /* 00000000 */
+ 0x00, /* 00000000 */
+ 0x00, /* 00000000 */
+ 0x00, /* 00000000 */
+ 0x00, /* 00000000 */
+
+ /* 197 0xc5 'Å' */
+ 0x18, /* 00011000 */
+ 0x18, /* 00011000 */
+ 0x18, /* 00011000 */
+ 0x18, /* 00011000 */
+ 0x18, /* 00011000 */
+ 0x18, /* 00011000 */
+ 0x18, /* 00011000 */
+ 0xff, /* 11111111 */
+ 0x18, /* 00011000 */
+ 0x18, /* 00011000 */
+ 0x18, /* 00011000 */
+ 0x18, /* 00011000 */
+ 0x18, /* 00011000 */
+ 0x18, /* 00011000 */
+ 0x18, /* 00011000 */
+ 0x18, /* 00011000 */
+
+ /* 198 0xc6 'Æ' */
+ 0x18, /* 00011000 */
+ 0x18, /* 00011000 */
+ 0x18, /* 00011000 */
+ 0x18, /* 00011000 */
+ 0x18, /* 00011000 */
+ 0x1f, /* 00011111 */
+ 0x18, /* 00011000 */
+ 0x1f, /* 00011111 */
+ 0x18, /* 00011000 */
+ 0x18, /* 00011000 */
+ 0x18, /* 00011000 */
+ 0x18, /* 00011000 */
+ 0x18, /* 00011000 */
+ 0x18, /* 00011000 */
+ 0x18, /* 00011000 */
+ 0x18, /* 00011000 */
+
+ /* 199 0xc7 'Ç' */
+ 0x36, /* 00110110 */
+ 0x36, /* 00110110 */
+ 0x36, /* 00110110 */
+ 0x36, /* 00110110 */
+ 0x36, /* 00110110 */
+ 0x36, /* 00110110 */
+ 0x36, /* 00110110 */
+ 0x37, /* 00110111 */
+ 0x36, /* 00110110 */
+ 0x36, /* 00110110 */
+ 0x36, /* 00110110 */
+ 0x36, /* 00110110 */
+ 0x36, /* 00110110 */
+ 0x36, /* 00110110 */
+ 0x36, /* 00110110 */
+ 0x36, /* 00110110 */
+
+ /* 200 0xc8 'È' */
+ 0x36, /* 00110110 */
+ 0x36, /* 00110110 */
+ 0x36, /* 00110110 */
+ 0x36, /* 00110110 */
+ 0x36, /* 00110110 */
+ 0x37, /* 00110111 */
+ 0x30, /* 00110000 */
+ 0x3f, /* 00111111 */
+ 0x00, /* 00000000 */
+ 0x00, /* 00000000 */
+ 0x00, /* 00000000 */
+ 0x00, /* 00000000 */
+ 0x00, /* 00000000 */
+ 0x00, /* 00000000 */
+ 0x00, /* 00000000 */
+ 0x00, /* 00000000 */
+
+ /* 201 0xc9 'É' */
+ 0x00, /* 00000000 */
+ 0x00, /* 00000000 */
+ 0x00, /* 00000000 */
+ 0x00, /* 00000000 */
+ 0x00, /* 00000000 */
+ 0x3f, /* 00111111 */
+ 0x30, /* 00110000 */
+ 0x37, /* 00110111 */
+ 0x36, /* 00110110 */
+ 0x36, /* 00110110 */
+ 0x36, /* 00110110 */
+ 0x36, /* 00110110 */
+ 0x36, /* 00110110 */
+ 0x36, /* 00110110 */
+ 0x36, /* 00110110 */
+ 0x36, /* 00110110 */
+
+ /* 202 0xca 'Ê' */
+ 0x36, /* 00110110 */
+ 0x36, /* 00110110 */
+ 0x36, /* 00110110 */
+ 0x36, /* 00110110 */
+ 0x36, /* 00110110 */
+ 0xf7, /* 11110111 */
+ 0x00, /* 00000000 */
+ 0xff, /* 11111111 */
+ 0x00, /* 00000000 */
+ 0x00, /* 00000000 */
+ 0x00, /* 00000000 */
+ 0x00, /* 00000000 */
+ 0x00, /* 00000000 */
+ 0x00, /* 00000000 */
+ 0x00, /* 00000000 */
+ 0x00, /* 00000000 */
+
+ /* 203 0xcb 'Ë' */
+ 0x00, /* 00000000 */
+ 0x00, /* 00000000 */
+ 0x00, /* 00000000 */
+ 0x00, /* 00000000 */
+ 0x00, /* 00000000 */
+ 0xff, /* 11111111 */
+ 0x00, /* 00000000 */
+ 0xf7, /* 11110111 */
+ 0x36, /* 00110110 */
+ 0x36, /* 00110110 */
+ 0x36, /* 00110110 */
+ 0x36, /* 00110110 */
+ 0x36, /* 00110110 */
+ 0x36, /* 00110110 */
+ 0x36, /* 00110110 */
+ 0x36, /* 00110110 */
+
+ /* 204 0xcc 'Ì' */
+ 0x36, /* 00110110 */
+ 0x36, /* 00110110 */
+ 0x36, /* 00110110 */
+ 0x36, /* 00110110 */
+ 0x36, /* 00110110 */
+ 0x37, /* 00110111 */
+ 0x30, /* 00110000 */
+ 0x37, /* 00110111 */
+ 0x36, /* 00110110 */
+ 0x36, /* 00110110 */
+ 0x36, /* 00110110 */
+ 0x36, /* 00110110 */
+ 0x36, /* 00110110 */
+ 0x36, /* 00110110 */
+ 0x36, /* 00110110 */
+ 0x36, /* 00110110 */
+
+ /* 205 0xcd 'Í' */
+ 0x00, /* 00000000 */
+ 0x00, /* 00000000 */
+ 0x00, /* 00000000 */
+ 0x00, /* 00000000 */
+ 0x00, /* 00000000 */
+ 0xff, /* 11111111 */
+ 0x00, /* 00000000 */
+ 0xff, /* 11111111 */
+ 0x00, /* 00000000 */
+ 0x00, /* 00000000 */
+ 0x00, /* 00000000 */
+ 0x00, /* 00000000 */
+ 0x00, /* 00000000 */
+ 0x00, /* 00000000 */
+ 0x00, /* 00000000 */
+ 0x00, /* 00000000 */
+
+ /* 206 0xce 'Î' */
+ 0x36, /* 00110110 */
+ 0x36, /* 00110110 */
+ 0x36, /* 00110110 */
+ 0x36, /* 00110110 */
+ 0x36, /* 00110110 */
+ 0xf7, /* 11110111 */
+ 0x00, /* 00000000 */
+ 0xf7, /* 11110111 */
+ 0x36, /* 00110110 */
+ 0x36, /* 00110110 */
+ 0x36, /* 00110110 */
+ 0x36, /* 00110110 */
+ 0x36, /* 00110110 */
+ 0x36, /* 00110110 */
+ 0x36, /* 00110110 */
+ 0x36, /* 00110110 */
+
+ /* 207 0xcf 'Ï' */
+ 0x18, /* 00011000 */
+ 0x18, /* 00011000 */
+ 0x18, /* 00011000 */
+ 0x18, /* 00011000 */
+ 0x18, /* 00011000 */
+ 0xff, /* 11111111 */
+ 0x00, /* 00000000 */
+ 0xff, /* 11111111 */
+ 0x00, /* 00000000 */
+ 0x00, /* 00000000 */
+ 0x00, /* 00000000 */
+ 0x00, /* 00000000 */
+ 0x00, /* 00000000 */
+ 0x00, /* 00000000 */
+ 0x00, /* 00000000 */
+ 0x00, /* 00000000 */
+
+ /* 208 0xd0 'Ð' */
+ 0x36, /* 00110110 */
+ 0x36, /* 00110110 */
+ 0x36, /* 00110110 */
+ 0x36, /* 00110110 */
+ 0x36, /* 00110110 */
+ 0x36, /* 00110110 */
+ 0x36, /* 00110110 */
+ 0xff, /* 11111111 */
+ 0x00, /* 00000000 */
+ 0x00, /* 00000000 */
+ 0x00, /* 00000000 */
+ 0x00, /* 00000000 */
+ 0x00, /* 00000000 */
+ 0x00, /* 00000000 */
+ 0x00, /* 00000000 */
+ 0x00, /* 00000000 */
+
+ /* 209 0xd1 'Ñ' */
+ 0x00, /* 00000000 */
+ 0x00, /* 00000000 */
+ 0x00, /* 00000000 */
+ 0x00, /* 00000000 */
+ 0x00, /* 00000000 */
+ 0xff, /* 11111111 */
+ 0x00, /* 00000000 */
+ 0xff, /* 11111111 */
+ 0x18, /* 00011000 */
+ 0x18, /* 00011000 */
+ 0x18, /* 00011000 */
+ 0x18, /* 00011000 */
+ 0x18, /* 00011000 */
+ 0x18, /* 00011000 */
+ 0x18, /* 00011000 */
+ 0x18, /* 00011000 */
+
+ /* 210 0xd2 'Ò' */
+ 0x00, /* 00000000 */
+ 0x00, /* 00000000 */
+ 0x00, /* 00000000 */
+ 0x00, /* 00000000 */
+ 0x00, /* 00000000 */
+ 0x00, /* 00000000 */
+ 0x00, /* 00000000 */
+ 0xff, /* 11111111 */
+ 0x36, /* 00110110 */
+ 0x36, /* 00110110 */
+ 0x36, /* 00110110 */
+ 0x36, /* 00110110 */
+ 0x36, /* 00110110 */
+ 0x36, /* 00110110 */
+ 0x36, /* 00110110 */
+ 0x36, /* 00110110 */
+
+ /* 211 0xd3 'Ó' */
+ 0x36, /* 00110110 */
+ 0x36, /* 00110110 */
+ 0x36, /* 00110110 */
+ 0x36, /* 00110110 */
+ 0x36, /* 00110110 */
+ 0x36, /* 00110110 */
+ 0x36, /* 00110110 */
+ 0x3f, /* 00111111 */
+ 0x00, /* 00000000 */
+ 0x00, /* 00000000 */
+ 0x00, /* 00000000 */
+ 0x00, /* 00000000 */
+ 0x00, /* 00000000 */
+ 0x00, /* 00000000 */
+ 0x00, /* 00000000 */
+ 0x00, /* 00000000 */
+
+ /* 212 0xd4 'Ô' */
+ 0x18, /* 00011000 */
+ 0x18, /* 00011000 */
+ 0x18, /* 00011000 */
+ 0x18, /* 00011000 */
+ 0x18, /* 00011000 */
+ 0x1f, /* 00011111 */
+ 0x18, /* 00011000 */
+ 0x1f, /* 00011111 */
+ 0x00, /* 00000000 */
+ 0x00, /* 00000000 */
+ 0x00, /* 00000000 */
+ 0x00, /* 00000000 */
+ 0x00, /* 00000000 */
+ 0x00, /* 00000000 */
+ 0x00, /* 00000000 */
+ 0x00, /* 00000000 */
+
+ /* 213 0xd5 'Õ' */
+ 0x00, /* 00000000 */
+ 0x00, /* 00000000 */
+ 0x00, /* 00000000 */
+ 0x00, /* 00000000 */
+ 0x00, /* 00000000 */
+ 0x1f, /* 00011111 */
+ 0x18, /* 00011000 */
+ 0x1f, /* 00011111 */
+ 0x18, /* 00011000 */
+ 0x18, /* 00011000 */
+ 0x18, /* 00011000 */
+ 0x18, /* 00011000 */
+ 0x18, /* 00011000 */
+ 0x18, /* 00011000 */
+ 0x18, /* 00011000 */
+ 0x18, /* 00011000 */
+
+ /* 214 0xd6 'Ö' */
+ 0x00, /* 00000000 */
+ 0x00, /* 00000000 */
+ 0x00, /* 00000000 */
+ 0x00, /* 00000000 */
+ 0x00, /* 00000000 */
+ 0x00, /* 00000000 */
+ 0x00, /* 00000000 */
+ 0x3f, /* 00111111 */
+ 0x36, /* 00110110 */
+ 0x36, /* 00110110 */
+ 0x36, /* 00110110 */
+ 0x36, /* 00110110 */
+ 0x36, /* 00110110 */
+ 0x36, /* 00110110 */
+ 0x36, /* 00110110 */
+ 0x36, /* 00110110 */
+
+ /* 215 0xd7 '×' */
+ 0x36, /* 00110110 */
+ 0x36, /* 00110110 */
+ 0x36, /* 00110110 */
+ 0x36, /* 00110110 */
+ 0x36, /* 00110110 */
+ 0x36, /* 00110110 */
+ 0x36, /* 00110110 */
+ 0xff, /* 11111111 */
+ 0x36, /* 00110110 */
+ 0x36, /* 00110110 */
+ 0x36, /* 00110110 */
+ 0x36, /* 00110110 */
+ 0x36, /* 00110110 */
+ 0x36, /* 00110110 */
+ 0x36, /* 00110110 */
+ 0x36, /* 00110110 */
+
+ /* 216 0xd8 'Ø' */
+ 0x18, /* 00011000 */
+ 0x18, /* 00011000 */
+ 0x18, /* 00011000 */
+ 0x18, /* 00011000 */
+ 0x18, /* 00011000 */
+ 0xff, /* 11111111 */
+ 0x18, /* 00011000 */
+ 0xff, /* 11111111 */
+ 0x18, /* 00011000 */
+ 0x18, /* 00011000 */
+ 0x18, /* 00011000 */
+ 0x18, /* 00011000 */
+ 0x18, /* 00011000 */
+ 0x18, /* 00011000 */
+ 0x18, /* 00011000 */
+ 0x18, /* 00011000 */
+
+ /* 217 0xd9 'Ù' */
+ 0x18, /* 00011000 */
+ 0x18, /* 00011000 */
+ 0x18, /* 00011000 */
+ 0x18, /* 00011000 */
+ 0x18, /* 00011000 */
+ 0x18, /* 00011000 */
+ 0x18, /* 00011000 */
+ 0xf8, /* 11111000 */
+ 0x00, /* 00000000 */
+ 0x00, /* 00000000 */
+ 0x00, /* 00000000 */
+ 0x00, /* 00000000 */
+ 0x00, /* 00000000 */
+ 0x00, /* 00000000 */
+ 0x00, /* 00000000 */
+ 0x00, /* 00000000 */
+
+ /* 218 0xda 'Ú' */
+ 0x00, /* 00000000 */
+ 0x00, /* 00000000 */
+ 0x00, /* 00000000 */
+ 0x00, /* 00000000 */
+ 0x00, /* 00000000 */
+ 0x00, /* 00000000 */
+ 0x00, /* 00000000 */
+ 0x1f, /* 00011111 */
+ 0x18, /* 00011000 */
+ 0x18, /* 00011000 */
+ 0x18, /* 00011000 */
+ 0x18, /* 00011000 */
+ 0x18, /* 00011000 */
+ 0x18, /* 00011000 */
+ 0x18, /* 00011000 */
+ 0x18, /* 00011000 */
+
+ /* 219 0xdb 'Û' */
+ 0xff, /* 11111111 */
+ 0xff, /* 11111111 */
+ 0xff, /* 11111111 */
+ 0xff, /* 11111111 */
+ 0xff, /* 11111111 */
+ 0xff, /* 11111111 */
+ 0xff, /* 11111111 */
+ 0xff, /* 11111111 */
+ 0xff, /* 11111111 */
+ 0xff, /* 11111111 */
+ 0xff, /* 11111111 */
+ 0xff, /* 11111111 */
+ 0xff, /* 11111111 */
+ 0xff, /* 11111111 */
+ 0xff, /* 11111111 */
+ 0xff, /* 11111111 */
+
+ /* 220 0xdc 'Ü' */
+ 0x00, /* 00000000 */
+ 0x00, /* 00000000 */
+ 0x00, /* 00000000 */
+ 0x00, /* 00000000 */
+ 0x00, /* 00000000 */
+ 0x00, /* 00000000 */
+ 0x00, /* 00000000 */
+ 0xff, /* 11111111 */
+ 0xff, /* 11111111 */
+ 0xff, /* 11111111 */
+ 0xff, /* 11111111 */
+ 0xff, /* 11111111 */
+ 0xff, /* 11111111 */
+ 0xff, /* 11111111 */
+ 0xff, /* 11111111 */
+ 0xff, /* 11111111 */
+
+ /* 221 0xdd 'Ý' */
+ 0xf0, /* 11110000 */
+ 0xf0, /* 11110000 */
+ 0xf0, /* 11110000 */
+ 0xf0, /* 11110000 */
+ 0xf0, /* 11110000 */
+ 0xf0, /* 11110000 */
+ 0xf0, /* 11110000 */
+ 0xf0, /* 11110000 */
+ 0xf0, /* 11110000 */
+ 0xf0, /* 11110000 */
+ 0xf0, /* 11110000 */
+ 0xf0, /* 11110000 */
+ 0xf0, /* 11110000 */
+ 0xf0, /* 11110000 */
+ 0xf0, /* 11110000 */
+ 0xf0, /* 11110000 */
+
+ /* 222 0xde 'Þ' */
+ 0x0f, /* 00001111 */
+ 0x0f, /* 00001111 */
+ 0x0f, /* 00001111 */
+ 0x0f, /* 00001111 */
+ 0x0f, /* 00001111 */
+ 0x0f, /* 00001111 */
+ 0x0f, /* 00001111 */
+ 0x0f, /* 00001111 */
+ 0x0f, /* 00001111 */
+ 0x0f, /* 00001111 */
+ 0x0f, /* 00001111 */
+ 0x0f, /* 00001111 */
+ 0x0f, /* 00001111 */
+ 0x0f, /* 00001111 */
+ 0x0f, /* 00001111 */
+ 0x0f, /* 00001111 */
+
+ /* 223 0xdf 'ß' */
+ 0xff, /* 11111111 */
+ 0xff, /* 11111111 */
+ 0xff, /* 11111111 */
+ 0xff, /* 11111111 */
+ 0xff, /* 11111111 */
+ 0xff, /* 11111111 */
+ 0xff, /* 11111111 */
+ 0x00, /* 00000000 */
+ 0x00, /* 00000000 */
+ 0x00, /* 00000000 */
+ 0x00, /* 00000000 */
+ 0x00, /* 00000000 */
+ 0x00, /* 00000000 */
+ 0x00, /* 00000000 */
+ 0x00, /* 00000000 */
+ 0x00, /* 00000000 */
+
+ /* 224 0xe0 'à' */
+ 0x00, /* 00000000 */
+ 0x00, /* 00000000 */
+ 0x00, /* 00000000 */
+ 0x00, /* 00000000 */
+ 0x00, /* 00000000 */
+ 0x76, /* 01110110 */
+ 0xdc, /* 11011100 */
+ 0xd8, /* 11011000 */
+ 0xd8, /* 11011000 */
+ 0xd8, /* 11011000 */
+ 0xdc, /* 11011100 */
+ 0x76, /* 01110110 */
+ 0x00, /* 00000000 */
+ 0x00, /* 00000000 */
+ 0x00, /* 00000000 */
+ 0x00, /* 00000000 */
+
+ /* 225 0xe1 'á' */
+ 0x00, /* 00000000 */
+ 0x00, /* 00000000 */
+ 0x78, /* 01111000 */
+ 0xcc, /* 11001100 */
+ 0xcc, /* 11001100 */
+ 0xcc, /* 11001100 */
+ 0xd8, /* 11011000 */
+ 0xcc, /* 11001100 */
+ 0xc6, /* 11000110 */
+ 0xc6, /* 11000110 */
+ 0xc6, /* 11000110 */
+ 0xcc, /* 11001100 */
+ 0x00, /* 00000000 */
+ 0x00, /* 00000000 */
+ 0x00, /* 00000000 */
+ 0x00, /* 00000000 */
+
+ /* 226 0xe2 'â' */
+ 0x00, /* 00000000 */
+ 0x00, /* 00000000 */
+ 0xfe, /* 11111110 */
+ 0xc6, /* 11000110 */
+ 0xc6, /* 11000110 */
+ 0xc0, /* 11000000 */
+ 0xc0, /* 11000000 */
+ 0xc0, /* 11000000 */
+ 0xc0, /* 11000000 */
+ 0xc0, /* 11000000 */
+ 0xc0, /* 11000000 */
+ 0xc0, /* 11000000 */
+ 0x00, /* 00000000 */
+ 0x00, /* 00000000 */
+ 0x00, /* 00000000 */
+ 0x00, /* 00000000 */
+
+ /* 227 0xe3 'ã' */
+ 0x00, /* 00000000 */
+ 0x00, /* 00000000 */
+ 0x00, /* 00000000 */
+ 0x00, /* 00000000 */
+ 0x00, /* 00000000 */
+ 0xfe, /* 11111110 */
+ 0x6c, /* 01101100 */
+ 0x6c, /* 01101100 */
+ 0x6c, /* 01101100 */
+ 0x6c, /* 01101100 */
+ 0x6c, /* 01101100 */
+ 0x6c, /* 01101100 */
+ 0x00, /* 00000000 */
+ 0x00, /* 00000000 */
+ 0x00, /* 00000000 */
+ 0x00, /* 00000000 */
+
+ /* 228 0xe4 'ä' */
+ 0x00, /* 00000000 */
+ 0x00, /* 00000000 */
+ 0xfe, /* 11111110 */
+ 0xc6, /* 11000110 */
+ 0x60, /* 01100000 */
+ 0x30, /* 00110000 */
+ 0x18, /* 00011000 */
+ 0x18, /* 00011000 */
+ 0x30, /* 00110000 */
+ 0x60, /* 01100000 */
+ 0xc6, /* 11000110 */
+ 0xfe, /* 11111110 */
+ 0x00, /* 00000000 */
+ 0x00, /* 00000000 */
+ 0x00, /* 00000000 */
+ 0x00, /* 00000000 */
+
+ /* 229 0xe5 'å' */
+ 0x00, /* 00000000 */
+ 0x00, /* 00000000 */
+ 0x00, /* 00000000 */
+ 0x00, /* 00000000 */
+ 0x00, /* 00000000 */
+ 0x7e, /* 01111110 */
+ 0xd8, /* 11011000 */
+ 0xd8, /* 11011000 */
+ 0xd8, /* 11011000 */
+ 0xd8, /* 11011000 */
+ 0xd8, /* 11011000 */
+ 0x70, /* 01110000 */
+ 0x00, /* 00000000 */
+ 0x00, /* 00000000 */
+ 0x00, /* 00000000 */
+ 0x00, /* 00000000 */
+
+ /* 230 0xe6 'æ' */
+ 0x00, /* 00000000 */
+ 0x00, /* 00000000 */
+ 0x00, /* 00000000 */
+ 0x00, /* 00000000 */
+ 0x00, /* 00000000 */
+ 0x66, /* 01100110 */
+ 0x66, /* 01100110 */
+ 0x66, /* 01100110 */
+ 0x66, /* 01100110 */
+ 0x66, /* 01100110 */
+ 0x66, /* 01100110 */
+ 0x7c, /* 01111100 */
+ 0x60, /* 01100000 */
+ 0x60, /* 01100000 */
+ 0xc0, /* 11000000 */
+ 0x00, /* 00000000 */
+
+ /* 231 0xe7 'ç' */
+ 0x00, /* 00000000 */
+ 0x00, /* 00000000 */
+ 0x00, /* 00000000 */
+ 0x00, /* 00000000 */
+ 0x76, /* 01110110 */
+ 0xdc, /* 11011100 */
+ 0x18, /* 00011000 */
+ 0x18, /* 00011000 */
+ 0x18, /* 00011000 */
+ 0x18, /* 00011000 */
+ 0x18, /* 00011000 */
+ 0x18, /* 00011000 */
+ 0x00, /* 00000000 */
+ 0x00, /* 00000000 */
+ 0x00, /* 00000000 */
+ 0x00, /* 00000000 */
+
+ /* 232 0xe8 'è' */
+ 0x00, /* 00000000 */
+ 0x00, /* 00000000 */
+ 0x7e, /* 01111110 */
+ 0x18, /* 00011000 */
+ 0x3c, /* 00111100 */
+ 0x66, /* 01100110 */
+ 0x66, /* 01100110 */
+ 0x66, /* 01100110 */
+ 0x66, /* 01100110 */
+ 0x3c, /* 00111100 */
+ 0x18, /* 00011000 */
+ 0x7e, /* 01111110 */
+ 0x00, /* 00000000 */
+ 0x00, /* 00000000 */
+ 0x00, /* 00000000 */
+ 0x00, /* 00000000 */
+
+ /* 233 0xe9 'é' */
+ 0x00, /* 00000000 */
+ 0x00, /* 00000000 */
+ 0x38, /* 00111000 */
+ 0x6c, /* 01101100 */
+ 0xc6, /* 11000110 */
+ 0xc6, /* 11000110 */
+ 0xfe, /* 11111110 */
+ 0xc6, /* 11000110 */
+ 0xc6, /* 11000110 */
+ 0xc6, /* 11000110 */
+ 0x6c, /* 01101100 */
+ 0x38, /* 00111000 */
+ 0x00, /* 00000000 */
+ 0x00, /* 00000000 */
+ 0x00, /* 00000000 */
+ 0x00, /* 00000000 */
+
+ /* 234 0xea 'ê' */
+ 0x00, /* 00000000 */
+ 0x00, /* 00000000 */
+ 0x38, /* 00111000 */
+ 0x6c, /* 01101100 */
+ 0xc6, /* 11000110 */
+ 0xc6, /* 11000110 */
+ 0xc6, /* 11000110 */
+ 0x6c, /* 01101100 */
+ 0x6c, /* 01101100 */
+ 0x6c, /* 01101100 */
+ 0x6c, /* 01101100 */
+ 0xee, /* 11101110 */
+ 0x00, /* 00000000 */
+ 0x00, /* 00000000 */
+ 0x00, /* 00000000 */
+ 0x00, /* 00000000 */
+
+ /* 235 0xeb 'ë' */
+ 0x00, /* 00000000 */
+ 0x00, /* 00000000 */
+ 0x1e, /* 00011110 */
+ 0x30, /* 00110000 */
+ 0x18, /* 00011000 */
+ 0x0c, /* 00001100 */
+ 0x3e, /* 00111110 */
+ 0x66, /* 01100110 */
+ 0x66, /* 01100110 */
+ 0x66, /* 01100110 */
+ 0x66, /* 01100110 */
+ 0x3c, /* 00111100 */
+ 0x00, /* 00000000 */
+ 0x00, /* 00000000 */
+ 0x00, /* 00000000 */
+ 0x00, /* 00000000 */
+
+ /* 236 0xec 'ì' */
+ 0x00, /* 00000000 */
+ 0x00, /* 00000000 */
+ 0x00, /* 00000000 */
+ 0x00, /* 00000000 */
+ 0x00, /* 00000000 */
+ 0x7e, /* 01111110 */
+ 0xdb, /* 11011011 */
+ 0xdb, /* 11011011 */
+ 0xdb, /* 11011011 */
+ 0x7e, /* 01111110 */
+ 0x00, /* 00000000 */
+ 0x00, /* 00000000 */
+ 0x00, /* 00000000 */
+ 0x00, /* 00000000 */
+ 0x00, /* 00000000 */
+ 0x00, /* 00000000 */
+
+ /* 237 0xed 'í' */
+ 0x00, /* 00000000 */
+ 0x00, /* 00000000 */
+ 0x00, /* 00000000 */
+ 0x03, /* 00000011 */
+ 0x06, /* 00000110 */
+ 0x7e, /* 01111110 */
+ 0xdb, /* 11011011 */
+ 0xdb, /* 11011011 */
+ 0xf3, /* 11110011 */
+ 0x7e, /* 01111110 */
+ 0x60, /* 01100000 */
+ 0xc0, /* 11000000 */
+ 0x00, /* 00000000 */
+ 0x00, /* 00000000 */
+ 0x00, /* 00000000 */
+ 0x00, /* 00000000 */
+
+ /* 238 0xee 'î' */
+ 0x00, /* 00000000 */
+ 0x00, /* 00000000 */
+ 0x1c, /* 00011100 */
+ 0x30, /* 00110000 */
+ 0x60, /* 01100000 */
+ 0x60, /* 01100000 */
+ 0x7c, /* 01111100 */
+ 0x60, /* 01100000 */
+ 0x60, /* 01100000 */
+ 0x60, /* 01100000 */
+ 0x30, /* 00110000 */
+ 0x1c, /* 00011100 */
+ 0x00, /* 00000000 */
+ 0x00, /* 00000000 */
+ 0x00, /* 00000000 */
+ 0x00, /* 00000000 */
+
+ /* 239 0xef 'ï' */
+ 0x00, /* 00000000 */
+ 0x00, /* 00000000 */
+ 0x00, /* 00000000 */
+ 0x7c, /* 01111100 */
+ 0xc6, /* 11000110 */
+ 0xc6, /* 11000110 */
+ 0xc6, /* 11000110 */
+ 0xc6, /* 11000110 */
+ 0xc6, /* 11000110 */
+ 0xc6, /* 11000110 */
+ 0xc6, /* 11000110 */
+ 0xc6, /* 11000110 */
+ 0x00, /* 00000000 */
+ 0x00, /* 00000000 */
+ 0x00, /* 00000000 */
+ 0x00, /* 00000000 */
+
+ /* 240 0xf0 'ð' */
+ 0x00, /* 00000000 */
+ 0x00, /* 00000000 */
+ 0x00, /* 00000000 */
+ 0x00, /* 00000000 */
+ 0xfe, /* 11111110 */
+ 0x00, /* 00000000 */
+ 0x00, /* 00000000 */
+ 0xfe, /* 11111110 */
+ 0x00, /* 00000000 */
+ 0x00, /* 00000000 */
+ 0xfe, /* 11111110 */
+ 0x00, /* 00000000 */
+ 0x00, /* 00000000 */
+ 0x00, /* 00000000 */
+ 0x00, /* 00000000 */
+ 0x00, /* 00000000 */
+
+ /* 241 0xf1 'ñ' */
+ 0x00, /* 00000000 */
+ 0x00, /* 00000000 */
+ 0x00, /* 00000000 */
+ 0x00, /* 00000000 */
+ 0x18, /* 00011000 */
+ 0x18, /* 00011000 */
+ 0x7e, /* 01111110 */
+ 0x18, /* 00011000 */
+ 0x18, /* 00011000 */
+ 0x00, /* 00000000 */
+ 0x00, /* 00000000 */
+ 0x7e, /* 01111110 */
+ 0x00, /* 00000000 */
+ 0x00, /* 00000000 */
+ 0x00, /* 00000000 */
+ 0x00, /* 00000000 */
+
+ /* 242 0xf2 'ò' */
+ 0x00, /* 00000000 */
+ 0x00, /* 00000000 */
+ 0x00, /* 00000000 */
+ 0x30, /* 00110000 */
+ 0x18, /* 00011000 */
+ 0x0c, /* 00001100 */
+ 0x06, /* 00000110 */
+ 0x0c, /* 00001100 */
+ 0x18, /* 00011000 */
+ 0x30, /* 00110000 */
+ 0x00, /* 00000000 */
+ 0x7e, /* 01111110 */
+ 0x00, /* 00000000 */
+ 0x00, /* 00000000 */
+ 0x00, /* 00000000 */
+ 0x00, /* 00000000 */
+
+ /* 243 0xf3 'ó' */
+ 0x00, /* 00000000 */
+ 0x00, /* 00000000 */
+ 0x00, /* 00000000 */
+ 0x0c, /* 00001100 */
+ 0x18, /* 00011000 */
+ 0x30, /* 00110000 */
+ 0x60, /* 01100000 */
+ 0x30, /* 00110000 */
+ 0x18, /* 00011000 */
+ 0x0c, /* 00001100 */
+ 0x00, /* 00000000 */
+ 0x7e, /* 01111110 */
+ 0x00, /* 00000000 */
+ 0x00, /* 00000000 */
+ 0x00, /* 00000000 */
+ 0x00, /* 00000000 */
+
+ /* 244 0xf4 'ô' */
+ 0x00, /* 00000000 */
+ 0x00, /* 00000000 */
+ 0x0e, /* 00001110 */
+ 0x1b, /* 00011011 */
+ 0x1b, /* 00011011 */
+ 0x18, /* 00011000 */
+ 0x18, /* 00011000 */
+ 0x18, /* 00011000 */
+ 0x18, /* 00011000 */
+ 0x18, /* 00011000 */
+ 0x18, /* 00011000 */
+ 0x18, /* 00011000 */
+ 0x18, /* 00011000 */
+ 0x18, /* 00011000 */
+ 0x18, /* 00011000 */
+ 0x18, /* 00011000 */
+
+ /* 245 0xf5 'õ' */
+ 0x18, /* 00011000 */
+ 0x18, /* 00011000 */
+ 0x18, /* 00011000 */
+ 0x18, /* 00011000 */
+ 0x18, /* 00011000 */
+ 0x18, /* 00011000 */
+ 0x18, /* 00011000 */
+ 0x18, /* 00011000 */
+ 0x18, /* 00011000 */
+ 0xd8, /* 11011000 */
+ 0xd8, /* 11011000 */
+ 0xd8, /* 11011000 */
+ 0x70, /* 01110000 */
+ 0x00, /* 00000000 */
+ 0x00, /* 00000000 */
+ 0x00, /* 00000000 */
+
+ /* 246 0xf6 'ö' */
+ 0x00, /* 00000000 */
+ 0x00, /* 00000000 */
+ 0x00, /* 00000000 */
+ 0x00, /* 00000000 */
+ 0x00, /* 00000000 */
+ 0x18, /* 00011000 */
+ 0x00, /* 00000000 */
+ 0x7e, /* 01111110 */
+ 0x00, /* 00000000 */
+ 0x18, /* 00011000 */
+ 0x00, /* 00000000 */
+ 0x00, /* 00000000 */
+ 0x00, /* 00000000 */
+ 0x00, /* 00000000 */
+ 0x00, /* 00000000 */
+ 0x00, /* 00000000 */
+
+ /* 247 0xf7 '÷' */
+ 0x00, /* 00000000 */
+ 0x00, /* 00000000 */
+ 0x00, /* 00000000 */
+ 0x00, /* 00000000 */
+ 0x00, /* 00000000 */
+ 0x76, /* 01110110 */
+ 0xdc, /* 11011100 */
+ 0x00, /* 00000000 */
+ 0x76, /* 01110110 */
+ 0xdc, /* 11011100 */
+ 0x00, /* 00000000 */
+ 0x00, /* 00000000 */
+ 0x00, /* 00000000 */
+ 0x00, /* 00000000 */
+ 0x00, /* 00000000 */
+ 0x00, /* 00000000 */
+
+ /* 248 0xf8 'ø' */
+ 0x00, /* 00000000 */
+ 0x38, /* 00111000 */
+ 0x6c, /* 01101100 */
+ 0x6c, /* 01101100 */
+ 0x38, /* 00111000 */
+ 0x00, /* 00000000 */
+ 0x00, /* 00000000 */
+ 0x00, /* 00000000 */
+ 0x00, /* 00000000 */
+ 0x00, /* 00000000 */
+ 0x00, /* 00000000 */
+ 0x00, /* 00000000 */
+ 0x00, /* 00000000 */
+ 0x00, /* 00000000 */
+ 0x00, /* 00000000 */
+ 0x00, /* 00000000 */
+
+ /* 249 0xf9 'ù' */
+ 0x00, /* 00000000 */
+ 0x00, /* 00000000 */
+ 0x00, /* 00000000 */
+ 0x00, /* 00000000 */
+ 0x00, /* 00000000 */
+ 0x00, /* 00000000 */
+ 0x00, /* 00000000 */
+ 0x18, /* 00011000 */
+ 0x18, /* 00011000 */
+ 0x00, /* 00000000 */
+ 0x00, /* 00000000 */
+ 0x00, /* 00000000 */
+ 0x00, /* 00000000 */
+ 0x00, /* 00000000 */
+ 0x00, /* 00000000 */
+ 0x00, /* 00000000 */
+
+ /* 250 0xfa 'ú' */
+ 0x00, /* 00000000 */
+ 0x00, /* 00000000 */
+ 0x00, /* 00000000 */
+ 0x00, /* 00000000 */
+ 0x00, /* 00000000 */
+ 0x00, /* 00000000 */
+ 0x00, /* 00000000 */
+ 0x18, /* 00011000 */
+ 0x00, /* 00000000 */
+ 0x00, /* 00000000 */
+ 0x00, /* 00000000 */
+ 0x00, /* 00000000 */
+ 0x00, /* 00000000 */
+ 0x00, /* 00000000 */
+ 0x00, /* 00000000 */
+ 0x00, /* 00000000 */
+
+ /* 251 0xfb 'û' */
+ 0x00, /* 00000000 */
+ 0x0f, /* 00001111 */
+ 0x0c, /* 00001100 */
+ 0x0c, /* 00001100 */
+ 0x0c, /* 00001100 */
+ 0x0c, /* 00001100 */
+ 0x0c, /* 00001100 */
+ 0xec, /* 11101100 */
+ 0x6c, /* 01101100 */
+ 0x6c, /* 01101100 */
+ 0x3c, /* 00111100 */
+ 0x1c, /* 00011100 */
+ 0x00, /* 00000000 */
+ 0x00, /* 00000000 */
+ 0x00, /* 00000000 */
+ 0x00, /* 00000000 */
+
+ /* 252 0xfc 'ü' */
+ 0x00, /* 00000000 */
+ 0x6c, /* 01101100 */
+ 0x36, /* 00110110 */
+ 0x36, /* 00110110 */
+ 0x36, /* 00110110 */
+ 0x36, /* 00110110 */
+ 0x36, /* 00110110 */
+ 0x00, /* 00000000 */
+ 0x00, /* 00000000 */
+ 0x00, /* 00000000 */
+ 0x00, /* 00000000 */
+ 0x00, /* 00000000 */
+ 0x00, /* 00000000 */
+ 0x00, /* 00000000 */
+ 0x00, /* 00000000 */
+ 0x00, /* 00000000 */
+
+ /* 253 0xfd 'ý' */
+ 0x00, /* 00000000 */
+ 0x3c, /* 00111100 */
+ 0x66, /* 01100110 */
+ 0x0c, /* 00001100 */
+ 0x18, /* 00011000 */
+ 0x32, /* 00110010 */
+ 0x7e, /* 01111110 */
+ 0x00, /* 00000000 */
+ 0x00, /* 00000000 */
+ 0x00, /* 00000000 */
+ 0x00, /* 00000000 */
+ 0x00, /* 00000000 */
+ 0x00, /* 00000000 */
+ 0x00, /* 00000000 */
+ 0x00, /* 00000000 */
+ 0x00, /* 00000000 */
+
+ /* 254 0xfe 'þ' */
+ 0x00, /* 00000000 */
+ 0x00, /* 00000000 */
+ 0x00, /* 00000000 */
+ 0x00, /* 00000000 */
+ 0x7e, /* 01111110 */
+ 0x7e, /* 01111110 */
+ 0x7e, /* 01111110 */
+ 0x7e, /* 01111110 */
+ 0x7e, /* 01111110 */
+ 0x7e, /* 01111110 */
+ 0x7e, /* 01111110 */
+ 0x00, /* 00000000 */
+ 0x00, /* 00000000 */
+ 0x00, /* 00000000 */
+ 0x00, /* 00000000 */
+ 0x00, /* 00000000 */
+
+ /* 255 0xff 'ÿ' */
+ 0x00, /* 00000000 */
+ 0x00, /* 00000000 */
+ 0x00, /* 00000000 */
+ 0x00, /* 00000000 */
+ 0x00, /* 00000000 */
+ 0x00, /* 00000000 */
+ 0x00, /* 00000000 */
+ 0x00, /* 00000000 */
+ 0x00, /* 00000000 */
+ 0x00, /* 00000000 */
+ 0x00, /* 00000000 */
+ 0x00, /* 00000000 */
+ 0x00, /* 00000000 */
+ 0x00, /* 00000000 */
+ 0x00, /* 00000000 */
+ 0x00, /* 00000000 */
+
+};
+
+#endif
diff --git a/lib/hashtable.c b/lib/hashtable.c
index 6895550..abd61c8 100644
--- a/lib/hashtable.c
+++ b/lib/hashtable.c
@@ -478,7 +478,8 @@
}
ssize_t hexport_r(struct hsearch_data *htab, const char sep,
- char **resp, size_t size)
+ char **resp, size_t size,
+ int argc, char * const argv[])
{
ENTRY *list[htab->size];
char *res, *p;
@@ -491,8 +492,8 @@
return (-1);
}
- debug("EXPORT table = %p, htab.size = %d, htab.filled = %d, size = %d\n",
- htab, htab->size, htab->filled, size);
+ debug("EXPORT table = %p, htab.size = %d, htab.filled = %d, "
+ "size = %zu\n", htab, htab->size, htab->filled, size);
/*
* Pass 1:
* search used entries,
@@ -502,6 +503,16 @@
if (htab->table[i].used > 0) {
ENTRY *ep = &htab->table[i].entry;
+ int arg, found = 0;
+
+ for (arg = 0; arg < argc; ++arg) {
+ if (strcmp(argv[arg], ep->key) == 0) {
+ found = 1;
+ break;
+ }
+ }
+ if ((argc > 0) && (found == 0))
+ continue;
list[n++] = ep;
@@ -539,8 +550,8 @@
/* Check if the user supplied buffer size is sufficient */
if (size) {
if (size < totlen + 1) { /* provided buffer too small */
- debug("### buffer too small: %d, but need %d\n",
- size, totlen + 1);
+ printf("Env export buffer too small: %zu, "
+ "but need %zu\n", size, totlen + 1);
__set_errno(ENOMEM);
return (-1);
}
@@ -640,7 +651,7 @@
/* we allocate new space to make sure we can write to the array */
if ((data = malloc(size)) == NULL) {
- debug("himport_r: can't malloc %d bytes\n", size);
+ debug("himport_r: can't malloc %zu bytes\n", size);
__set_errno(ENOMEM);
return 0;
}
diff --git a/nand_spl/nand_boot.c b/nand_spl/nand_boot.c
index 615ef25..bee1029 100644
--- a/nand_spl/nand_boot.c
+++ b/nand_spl/nand_boot.c
@@ -187,7 +187,6 @@
int eccbytes = CONFIG_SYS_NAND_ECCBYTES;
int eccsteps = CONFIG_SYS_NAND_ECCSTEPS;
uint8_t *p = dst;
- int stat;
nand_command(mtd, block, page, 0, NAND_CMD_READ0);
@@ -217,7 +216,7 @@
* from correct_data(). We just hope that all possible errors
* are corrected by this routine.
*/
- stat = this->ecc.correct(mtd, p, &ecc_code[i], &ecc_calc[i]);
+ this->ecc.correct(mtd, p, &ecc_code[i], &ecc_calc[i]);
}
return 0;
@@ -268,7 +267,6 @@
{
struct nand_chip nand_chip;
nand_info_t nand_info;
- int ret;
__attribute__((noreturn)) void (*uboot)(void);
/*
@@ -287,8 +285,8 @@
/*
* Load U-Boot image from NAND into RAM
*/
- ret = nand_load(&nand_info, CONFIG_SYS_NAND_U_BOOT_OFFS, CONFIG_SYS_NAND_U_BOOT_SIZE,
- (uchar *)CONFIG_SYS_NAND_U_BOOT_DST);
+ nand_load(&nand_info, CONFIG_SYS_NAND_U_BOOT_OFFS, CONFIG_SYS_NAND_U_BOOT_SIZE,
+ (uchar *)CONFIG_SYS_NAND_U_BOOT_DST);
#ifdef CONFIG_NAND_ENV_DST
nand_load(&nand_info, CONFIG_ENV_OFFSET, CONFIG_ENV_SIZE,
diff --git a/post/lib_powerpc/fpu/20001122-1.c b/post/lib_powerpc/fpu/20001122-1.c
index 4af300d..5b4f42c 100644
--- a/post/lib_powerpc/fpu/20001122-1.c
+++ b/post/lib_powerpc/fpu/20001122-1.c
@@ -34,12 +34,11 @@
int fpu_post_test_math1 (void)
{
- volatile double a, *p;
+ volatile double a;
double c, d;
volatile double b;
d = 1.0;
- p = &b;
do
{
diff --git a/spl/Makefile b/spl/Makefile
index c8317fa..6ac42a2 100644
--- a/spl/Makefile
+++ b/spl/Makefile
@@ -54,6 +54,7 @@
LIBS-$(CONFIG_SPL_LIBGENERIC_SUPPORT) += lib/libgeneric.o
LIBS-$(CONFIG_SPL_POWER_SUPPORT) += drivers/power/libpower.o
LIBS-$(CONFIG_SPL_NAND_SUPPORT) += drivers/mtd/nand/libnand.o
+LIBS-$(CONFIG_SPL_ONENAND_SUPPORT) += drivers/mtd/onenand/libonenand.o
LIBS-$(CONFIG_SPL_DMA_SUPPORT) += drivers/dma/libdma.o
LIBS-$(CONFIG_SPL_POST_MEM_SUPPORT) += post/drivers/memory.o
@@ -63,6 +64,9 @@
ifeq ($(SOC),omap4)
LIBS-y += $(CPUDIR)/omap-common/libomap-common.o
endif
+ifeq ($(SOC),omap5)
+LIBS-y += $(CPUDIR)/omap-common/libomap-common.o
+endif
START := $(addprefix $(SPLTREE)/,$(START))
LIBS := $(addprefix $(SPLTREE)/,$(sort $(LIBS-y)))
diff --git a/tools/.gitignore b/tools/.gitignore
index 07f21a3..98a5c78 100644
--- a/tools/.gitignore
+++ b/tools/.gitignore
@@ -4,6 +4,7 @@
/img2srec
/mkimage
/mpc86x_clk
+/mxsboot
/ncb
/ncp
/ubsha1
diff --git a/tools/Makefile b/tools/Makefile
index df56a25..a5f989a 100644
--- a/tools/Makefile
+++ b/tools/Makefile
@@ -66,7 +66,9 @@
BIN_FILES-$(CONFIG_CMD_NET) += gen_eth_addr$(SFX)
BIN_FILES-$(CONFIG_CMD_LOADS) += img2srec$(SFX)
BIN_FILES-$(CONFIG_XWAY_SWAP_BYTES) += xway-swap-bytes$(SFX)
+BIN_FILES-y += mkenvimage$(SFX)
BIN_FILES-y += mkimage$(SFX)
+BIN_FILES-$(CONFIG_MX28) += mxsboot$(SFX)
BIN_FILES-$(CONFIG_NETCONSOLE) += ncb$(SFX)
BIN_FILES-$(CONFIG_SHA1_CHECK_UB_IMG) += ubsha1$(SFX)
@@ -90,7 +92,9 @@
NOPED_OBJ_FILES-y += kwbimage.o
NOPED_OBJ_FILES-y += imximage.o
NOPED_OBJ_FILES-y += omapimage.o
+NOPED_OBJ_FILES-y += mkenvimage.o
NOPED_OBJ_FILES-y += mkimage.o
+OBJ_FILES-$(CONFIG_MX28) += mxsboot.o
OBJ_FILES-$(CONFIG_NETCONSOLE) += ncb.o
NOPED_OBJ_FILES-y += os_support.o
OBJ_FILES-$(CONFIG_SHA1_CHECK_UB_IMG) += ubsha1.o
@@ -111,8 +115,11 @@
# Generated LCD/video logo
LOGO_H = $(OBJTREE)/include/bmp_logo.h
+LOGO_DATA_H = $(OBJTREE)/include/bmp_logo_data.h
LOGO-$(CONFIG_LCD_LOGO) += $(LOGO_H)
+LOGO-$(CONFIG_LCD_LOGO) += $(LOGO_DATA_H)
LOGO-$(CONFIG_VIDEO_LOGO) += $(LOGO_H)
+LOGO-$(CONFIG_VIDEO_LOGO) += $(LOGO_DATA_H)
ifeq ($(LOGO_BMP),)
LOGO_BMP= logos/denx.bmp
@@ -185,6 +192,9 @@
$(HOSTCC) $(HOSTCFLAGS) $(HOSTLDFLAGS) -o $@ $^
$(HOSTSTRIP) $@
+$(obj)mkenvimage$(SFX): $(obj)crc32.o $(obj)mkenvimage.o
+ $(HOSTCC) $(HOSTCFLAGS) $(HOSTLDFLAGS) -o $@ $^
+
$(obj)mkimage$(SFX): $(obj)aisimage.o \
$(obj)crc32.o \
$(obj)default_image.o \
@@ -206,6 +216,10 @@
$(HOSTCC) $(HOSTCFLAGS) $(HOSTLDFLAGS) -o $@ $^
$(HOSTSTRIP) $@
+$(obj)mxsboot$(SFX): $(obj)mxsboot.o
+ $(HOSTCC) $(HOSTCFLAGS) $(HOSTLDFLAGS) -o $@ $^
+ $(HOSTSTRIP) $@
+
$(obj)ncb$(SFX): $(obj)ncb.o
$(HOSTCC) $(HOSTCFLAGS) $(HOSTLDFLAGS) -o $@ $^
$(HOSTSTRIP) $@
@@ -236,7 +250,10 @@
endif
$(LOGO_H): $(obj)bmp_logo $(LOGO_BMP)
- $(obj)./bmp_logo $(LOGO_BMP) >$@
+ $(obj)./bmp_logo --gen-info $(LOGO_BMP) > $@
+
+$(LOGO_DATA_H): $(obj)bmp_logo $(LOGO_BMP)
+ $(obj)./bmp_logo --gen-data $(LOGO_BMP) > $@
#########################################################################
diff --git a/tools/bmp_logo.c b/tools/bmp_logo.c
index 47228d2..b2ad3d5 100644
--- a/tools/bmp_logo.c
+++ b/tools/bmp_logo.c
@@ -1,5 +1,10 @@
#include "compiler.h"
+enum {
+ MODE_GEN_INFO,
+ MODE_GEN_DATA
+};
+
typedef struct bitmap_s { /* bitmap description */
uint16_t width;
uint16_t height;
@@ -9,6 +14,11 @@
#define DEFAULT_CMAP_SIZE 16 /* size of default color map */
+void usage(const char *prog)
+{
+ fprintf(stderr, "Usage: %s [--gen-info|--gen-data] file\n", prog);
+}
+
/*
* Neutralize little endians.
*/
@@ -39,21 +49,52 @@
exit (EXIT_FAILURE);
}
+void gen_info(bitmap_t *b, uint16_t n_colors)
+{
+ printf("/*\n"
+ " * Automatically generated by \"tools/bmp_logo\"\n"
+ " *\n"
+ " * DO NOT EDIT\n"
+ " *\n"
+ " */\n\n\n"
+ "#ifndef __BMP_LOGO_H__\n"
+ "#define __BMP_LOGO_H__\n\n"
+ "#define BMP_LOGO_WIDTH\t\t%d\n"
+ "#define BMP_LOGO_HEIGHT\t\t%d\n"
+ "#define BMP_LOGO_COLORS\t\t%d\n"
+ "#define BMP_LOGO_OFFSET\t\t%d\n\n"
+ "extern unsigned short bmp_logo_palette[];\n"
+ "extern unsigned char bmp_logo_bitmap[];\n\n"
+ "#endif /* __BMP_LOGO_H__ */\n",
+ b->width, b->height, n_colors,
+ DEFAULT_CMAP_SIZE);
+}
+
int main (int argc, char *argv[])
{
- int i, x;
+ int mode, i, x;
FILE *fp;
bitmap_t bmp;
bitmap_t *b = &bmp;
uint16_t data_offset, n_colors;
- if (argc < 2) {
- fprintf (stderr, "Usage: %s file\n", argv[0]);
+ if (argc < 3) {
+ usage(argv[0]);
exit (EXIT_FAILURE);
}
- if ((fp = fopen (argv[1], "rb")) == NULL) {
- perror (argv[1]);
+ if (!strcmp(argv[1], "--gen-info"))
+ mode = MODE_GEN_INFO;
+ else if (!strcmp(argv[1], "--gen-data"))
+ mode = MODE_GEN_DATA;
+ else {
+ usage(argv[0]);
+ exit(EXIT_FAILURE);
+ }
+
+ fp = fopen(argv[2], "rb");
+ if (!fp) {
+ perror(argv[2]);
exit (EXIT_FAILURE);
}
@@ -92,28 +133,26 @@
n_colors = 256 - DEFAULT_CMAP_SIZE;
}
- printf ("/*\n"
+ if (mode == MODE_GEN_INFO) {
+ gen_info(b, n_colors);
+ goto out;
+ }
+
+ printf("/*\n"
" * Automatically generated by \"tools/bmp_logo\"\n"
" *\n"
" * DO NOT EDIT\n"
" *\n"
" */\n\n\n"
- "#ifndef __BMP_LOGO_H__\n"
- "#define __BMP_LOGO_H__\n\n"
- "#define BMP_LOGO_WIDTH\t\t%d\n"
- "#define BMP_LOGO_HEIGHT\t\t%d\n"
- "#define BMP_LOGO_COLORS\t\t%d\n"
- "#define BMP_LOGO_OFFSET\t\t%d\n"
- "\n",
- b->width, b->height, n_colors,
- DEFAULT_CMAP_SIZE);
+ "#ifndef __BMP_LOGO_DATA_H__\n"
+ "#define __BMP_LOGO_DATA_H__\n\n");
/* allocate memory */
if ((b->data = (uint8_t *)malloc(b->width * b->height)) == NULL)
error ("Error allocating memory for file", fp);
/* read and print the palette information */
- printf ("unsigned short bmp_logo_palette[] = {\n");
+ printf("unsigned short bmp_logo_palette[] = {\n");
for (i=0; i<n_colors; ++i) {
b->palette[(int)(i*3+2)] = fgetc(fp);
@@ -137,14 +176,13 @@
printf ("\n");
printf ("};\n");
printf ("\n");
- printf ("unsigned char bmp_logo_bitmap[] = {\n");
+ printf("unsigned char bmp_logo_bitmap[] = {\n");
for (i=(b->height-1)*b->width; i>=0; i-=b->width) {
for (x = 0; x < b->width; x++) {
b->data[(uint16_t) i + x] = (uint8_t) fgetc (fp) \
+ DEFAULT_CMAP_SIZE;
}
}
- fclose (fp);
for (i=0; i<(b->height*b->width); ++i) {
if ((i%8) == 0)
@@ -156,8 +194,10 @@
}
printf ("\n"
"};\n\n"
- "#endif /* __BMP_LOGO_H__ */\n"
+ "#endif /* __BMP_LOGO_DATA_H__ */\n"
);
- return (0);
+out:
+ fclose(fp);
+ return 0;
}
diff --git a/tools/checkpatch.pl b/tools/checkpatch.pl
new file mode 100755
index 0000000..2048a44
--- /dev/null
+++ b/tools/checkpatch.pl
@@ -0,0 +1,3337 @@
+#!/usr/bin/perl -w
+# (c) 2001, Dave Jones. (the file handling bit)
+# (c) 2005, Joel Schopp <jschopp@austin.ibm.com> (the ugly bit)
+# (c) 2007,2008, Andy Whitcroft <apw@uk.ibm.com> (new conditions, test suite)
+# (c) 2008-2010 Andy Whitcroft <apw@canonical.com>
+# Licensed under the terms of the GNU GPL License version 2
+
+use strict;
+
+my $P = $0;
+$P =~ s@.*/@@g;
+
+my $V = '0.32';
+
+use Getopt::Long qw(:config no_auto_abbrev);
+
+my $quiet = 0;
+my $tree = 1;
+my $chk_signoff = 1;
+my $chk_patch = 1;
+my $tst_only;
+my $emacs = 0;
+my $terse = 0;
+my $file = 0;
+my $check = 0;
+my $summary = 1;
+my $mailback = 0;
+my $summary_file = 0;
+my $show_types = 0;
+my $root;
+my %debug;
+my %ignore_type = ();
+my @ignore = ();
+my $help = 0;
+my $configuration_file = ".checkpatch.conf";
+
+sub help {
+ my ($exitcode) = @_;
+
+ print << "EOM";
+Usage: $P [OPTION]... [FILE]...
+Version: $V
+
+Options:
+ -q, --quiet quiet
+ --no-tree run without a kernel tree
+ --no-signoff do not check for 'Signed-off-by' line
+ --patch treat FILE as patchfile (default)
+ --emacs emacs compile window format
+ --terse one line per report
+ -f, --file treat FILE as regular source file
+ --subjective, --strict enable more subjective tests
+ --ignore TYPE(,TYPE2...) ignore various comma separated message types
+ --show-types show the message "types" in the output
+ --root=PATH PATH to the kernel tree root
+ --no-summary suppress the per-file summary
+ --mailback only produce a report in case of warnings/errors
+ --summary-file include the filename in summary
+ --debug KEY=[0|1] turn on/off debugging of KEY, where KEY is one of
+ 'values', 'possible', 'type', and 'attr' (default
+ is all off)
+ --test-only=WORD report only warnings/errors containing WORD
+ literally
+ -h, --help, --version display this help and exit
+
+When FILE is - read standard input.
+EOM
+
+ exit($exitcode);
+}
+
+my $conf = which_conf($configuration_file);
+if (-f $conf) {
+ my @conf_args;
+ open(my $conffile, '<', "$conf")
+ or warn "$P: Can't find a readable $configuration_file file $!\n";
+
+ while (<$conffile>) {
+ my $line = $_;
+
+ $line =~ s/\s*\n?$//g;
+ $line =~ s/^\s*//g;
+ $line =~ s/\s+/ /g;
+
+ next if ($line =~ m/^\s*#/);
+ next if ($line =~ m/^\s*$/);
+
+ my @words = split(" ", $line);
+ foreach my $word (@words) {
+ last if ($word =~ m/^#/);
+ push (@conf_args, $word);
+ }
+ }
+ close($conffile);
+ unshift(@ARGV, @conf_args) if @conf_args;
+}
+
+GetOptions(
+ 'q|quiet+' => \$quiet,
+ 'tree!' => \$tree,
+ 'signoff!' => \$chk_signoff,
+ 'patch!' => \$chk_patch,
+ 'emacs!' => \$emacs,
+ 'terse!' => \$terse,
+ 'f|file!' => \$file,
+ 'subjective!' => \$check,
+ 'strict!' => \$check,
+ 'ignore=s' => \@ignore,
+ 'show-types!' => \$show_types,
+ 'root=s' => \$root,
+ 'summary!' => \$summary,
+ 'mailback!' => \$mailback,
+ 'summary-file!' => \$summary_file,
+
+ 'debug=s' => \%debug,
+ 'test-only=s' => \$tst_only,
+ 'h|help' => \$help,
+ 'version' => \$help
+) or help(1);
+
+help(0) if ($help);
+
+my $exit = 0;
+
+if ($#ARGV < 0) {
+ print "$P: no input files\n";
+ exit(1);
+}
+
+@ignore = split(/,/, join(',',@ignore));
+foreach my $word (@ignore) {
+ $word =~ s/\s*\n?$//g;
+ $word =~ s/^\s*//g;
+ $word =~ s/\s+/ /g;
+ $word =~ tr/[a-z]/[A-Z]/;
+
+ next if ($word =~ m/^\s*#/);
+ next if ($word =~ m/^\s*$/);
+
+ $ignore_type{$word}++;
+}
+
+my $dbg_values = 0;
+my $dbg_possible = 0;
+my $dbg_type = 0;
+my $dbg_attr = 0;
+for my $key (keys %debug) {
+ ## no critic
+ eval "\${dbg_$key} = '$debug{$key}';";
+ die "$@" if ($@);
+}
+
+my $rpt_cleaners = 0;
+
+if ($terse) {
+ $emacs = 1;
+ $quiet++;
+}
+
+if ($tree) {
+ if (defined $root) {
+ if (!top_of_kernel_tree($root)) {
+ die "$P: $root: --root does not point at a valid tree\n";
+ }
+ } else {
+ if (top_of_kernel_tree('.')) {
+ $root = '.';
+ } elsif ($0 =~ m@(.*)/scripts/[^/]*$@ &&
+ top_of_kernel_tree($1)) {
+ $root = $1;
+ }
+ }
+
+ if (!defined $root) {
+ print "Must be run from the top-level dir. of a kernel tree\n";
+ exit(2);
+ }
+}
+
+my $emitted_corrupt = 0;
+
+our $Ident = qr{
+ [A-Za-z_][A-Za-z\d_]*
+ (?:\s*\#\#\s*[A-Za-z_][A-Za-z\d_]*)*
+ }x;
+our $Storage = qr{extern|static|asmlinkage};
+our $Sparse = qr{
+ __user|
+ __kernel|
+ __force|
+ __iomem|
+ __must_check|
+ __init_refok|
+ __kprobes|
+ __ref|
+ __rcu
+ }x;
+
+# Notes to $Attribute:
+# We need \b after 'init' otherwise 'initconst' will cause a false positive in a check
+our $Attribute = qr{
+ const|
+ __percpu|
+ __nocast|
+ __safe|
+ __bitwise__|
+ __packed__|
+ __packed2__|
+ __naked|
+ __maybe_unused|
+ __always_unused|
+ __noreturn|
+ __used|
+ __cold|
+ __noclone|
+ __deprecated|
+ __read_mostly|
+ __kprobes|
+ __(?:mem|cpu|dev|)(?:initdata|initconst|init\b)|
+ ____cacheline_aligned|
+ ____cacheline_aligned_in_smp|
+ ____cacheline_internodealigned_in_smp|
+ __weak
+ }x;
+our $Modifier;
+our $Inline = qr{inline|__always_inline|noinline};
+our $Member = qr{->$Ident|\.$Ident|\[[^]]*\]};
+our $Lval = qr{$Ident(?:$Member)*};
+
+our $Constant = qr{(?:[0-9]+|0x[0-9a-fA-F]+)[UL]*};
+our $Assignment = qr{(?:\*\=|/=|%=|\+=|-=|<<=|>>=|&=|\^=|\|=|=)};
+our $Compare = qr{<=|>=|==|!=|<|>};
+our $Operators = qr{
+ <=|>=|==|!=|
+ =>|->|<<|>>|<|>|!|~|
+ &&|\|\||,|\^|\+\+|--|&|\||\+|-|\*|\/|%
+ }x;
+
+our $NonptrType;
+our $Type;
+our $Declare;
+
+our $UTF8 = qr {
+ [\x09\x0A\x0D\x20-\x7E] # ASCII
+ | [\xC2-\xDF][\x80-\xBF] # non-overlong 2-byte
+ | \xE0[\xA0-\xBF][\x80-\xBF] # excluding overlongs
+ | [\xE1-\xEC\xEE\xEF][\x80-\xBF]{2} # straight 3-byte
+ | \xED[\x80-\x9F][\x80-\xBF] # excluding surrogates
+ | \xF0[\x90-\xBF][\x80-\xBF]{2} # planes 1-3
+ | [\xF1-\xF3][\x80-\xBF]{3} # planes 4-15
+ | \xF4[\x80-\x8F][\x80-\xBF]{2} # plane 16
+}x;
+
+our $typeTypedefs = qr{(?x:
+ (?:__)?(?:u|s|be|le)(?:8|16|32|64)|
+ atomic_t
+)};
+
+our $logFunctions = qr{(?x:
+ printk(?:_ratelimited|_once|)|
+ [a-z0-9]+_(?:printk|emerg|alert|crit|err|warning|warn|notice|info|debug|dbg|vdbg|devel|cont|WARN)(?:_ratelimited|_once|)|
+ WARN(?:_RATELIMIT|_ONCE|)|
+ panic|
+ MODULE_[A-Z_]+
+)};
+
+our $signature_tags = qr{(?xi:
+ Signed-off-by:|
+ Acked-by:|
+ Tested-by:|
+ Reviewed-by:|
+ Reported-by:|
+ To:|
+ Cc:
+)};
+
+our @typeList = (
+ qr{void},
+ qr{(?:unsigned\s+)?char},
+ qr{(?:unsigned\s+)?short},
+ qr{(?:unsigned\s+)?int},
+ qr{(?:unsigned\s+)?long},
+ qr{(?:unsigned\s+)?long\s+int},
+ qr{(?:unsigned\s+)?long\s+long},
+ qr{(?:unsigned\s+)?long\s+long\s+int},
+ qr{unsigned},
+ qr{float},
+ qr{double},
+ qr{bool},
+ qr{struct\s+$Ident},
+ qr{union\s+$Ident},
+ qr{enum\s+$Ident},
+ qr{${Ident}_t},
+ qr{${Ident}_handler},
+ qr{${Ident}_handler_fn},
+);
+our @modifierList = (
+ qr{fastcall},
+);
+
+our $allowed_asm_includes = qr{(?x:
+ irq|
+ memory
+)};
+# memory.h: ARM has a custom one
+
+sub build_types {
+ my $mods = "(?x: \n" . join("|\n ", @modifierList) . "\n)";
+ my $all = "(?x: \n" . join("|\n ", @typeList) . "\n)";
+ $Modifier = qr{(?:$Attribute|$Sparse|$mods)};
+ $NonptrType = qr{
+ (?:$Modifier\s+|const\s+)*
+ (?:
+ (?:typeof|__typeof__)\s*\(\s*\**\s*$Ident\s*\)|
+ (?:$typeTypedefs\b)|
+ (?:${all}\b)
+ )
+ (?:\s+$Modifier|\s+const)*
+ }x;
+ $Type = qr{
+ $NonptrType
+ (?:[\s\*]+\s*const|[\s\*]+|(?:\s*\[\s*\])+)?
+ (?:\s+$Inline|\s+$Modifier)*
+ }x;
+ $Declare = qr{(?:$Storage\s+)?$Type};
+}
+build_types();
+
+our $match_balanced_parentheses = qr/(\((?:[^\(\)]+|(-1))*\))/;
+
+our $Typecast = qr{\s*(\(\s*$NonptrType\s*\)){0,1}\s*};
+our $LvalOrFunc = qr{($Lval)\s*($match_balanced_parentheses{0,1})\s*};
+
+sub deparenthesize {
+ my ($string) = @_;
+ return "" if (!defined($string));
+ $string =~ s@^\s*\(\s*@@g;
+ $string =~ s@\s*\)\s*$@@g;
+ $string =~ s@\s+@ @g;
+ return $string;
+}
+
+$chk_signoff = 0 if ($file);
+
+my @dep_includes = ();
+my @dep_functions = ();
+my $removal = "Documentation/feature-removal-schedule.txt";
+if ($tree && -f "$root/$removal") {
+ open(my $REMOVE, '<', "$root/$removal") ||
+ die "$P: $removal: open failed - $!\n";
+ while (<$REMOVE>) {
+ if (/^Check:\s+(.*\S)/) {
+ for my $entry (split(/[, ]+/, $1)) {
+ if ($entry =~ m@include/(.*)@) {
+ push(@dep_includes, $1);
+
+ } elsif ($entry !~ m@/@) {
+ push(@dep_functions, $entry);
+ }
+ }
+ }
+ }
+ close($REMOVE);
+}
+
+my @rawlines = ();
+my @lines = ();
+my $vname;
+for my $filename (@ARGV) {
+ my $FILE;
+ if ($file) {
+ open($FILE, '-|', "diff -u /dev/null $filename") ||
+ die "$P: $filename: diff failed - $!\n";
+ } elsif ($filename eq '-') {
+ open($FILE, '<&STDIN');
+ } else {
+ open($FILE, '<', "$filename") ||
+ die "$P: $filename: open failed - $!\n";
+ }
+ if ($filename eq '-') {
+ $vname = 'Your patch';
+ } else {
+ $vname = $filename;
+ }
+ while (<$FILE>) {
+ chomp;
+ push(@rawlines, $_);
+ }
+ close($FILE);
+ if (!process($filename)) {
+ $exit = 1;
+ }
+ @rawlines = ();
+ @lines = ();
+}
+
+exit($exit);
+
+sub top_of_kernel_tree {
+ my ($root) = @_;
+
+ my @tree_check = (
+ "COPYING", "CREDITS", "Kbuild", "MAINTAINERS", "Makefile",
+ "README", "Documentation", "arch", "include", "drivers",
+ "fs", "init", "ipc", "kernel", "lib", "scripts",
+ );
+
+ foreach my $check (@tree_check) {
+ if (! -e $root . '/' . $check) {
+ return 0;
+ }
+ }
+ return 1;
+ }
+
+sub parse_email {
+ my ($formatted_email) = @_;
+
+ my $name = "";
+ my $address = "";
+ my $comment = "";
+
+ if ($formatted_email =~ /^(.*)<(\S+\@\S+)>(.*)$/) {
+ $name = $1;
+ $address = $2;
+ $comment = $3 if defined $3;
+ } elsif ($formatted_email =~ /^\s*<(\S+\@\S+)>(.*)$/) {
+ $address = $1;
+ $comment = $2 if defined $2;
+ } elsif ($formatted_email =~ /(\S+\@\S+)(.*)$/) {
+ $address = $1;
+ $comment = $2 if defined $2;
+ $formatted_email =~ s/$address.*$//;
+ $name = $formatted_email;
+ $name =~ s/^\s+|\s+$//g;
+ $name =~ s/^\"|\"$//g;
+ # If there's a name left after stripping spaces and
+ # leading quotes, and the address doesn't have both
+ # leading and trailing angle brackets, the address
+ # is invalid. ie:
+ # "joe smith joe@smith.com" bad
+ # "joe smith <joe@smith.com" bad
+ if ($name ne "" && $address !~ /^<[^>]+>$/) {
+ $name = "";
+ $address = "";
+ $comment = "";
+ }
+ }
+
+ $name =~ s/^\s+|\s+$//g;
+ $name =~ s/^\"|\"$//g;
+ $address =~ s/^\s+|\s+$//g;
+ $address =~ s/^\<|\>$//g;
+
+ if ($name =~ /[^\w \-]/i) { ##has "must quote" chars
+ $name =~ s/(?<!\\)"/\\"/g; ##escape quotes
+ $name = "\"$name\"";
+ }
+
+ return ($name, $address, $comment);
+}
+
+sub format_email {
+ my ($name, $address) = @_;
+
+ my $formatted_email;
+
+ $name =~ s/^\s+|\s+$//g;
+ $name =~ s/^\"|\"$//g;
+ $address =~ s/^\s+|\s+$//g;
+
+ if ($name =~ /[^\w \-]/i) { ##has "must quote" chars
+ $name =~ s/(?<!\\)"/\\"/g; ##escape quotes
+ $name = "\"$name\"";
+ }
+
+ if ("$name" eq "") {
+ $formatted_email = "$address";
+ } else {
+ $formatted_email = "$name <$address>";
+ }
+
+ return $formatted_email;
+}
+
+sub which_conf {
+ my ($conf) = @_;
+
+ foreach my $path (split(/:/, ".:$ENV{HOME}:.scripts")) {
+ if (-e "$path/$conf") {
+ return "$path/$conf";
+ }
+ }
+
+ return "";
+}
+
+sub expand_tabs {
+ my ($str) = @_;
+
+ my $res = '';
+ my $n = 0;
+ for my $c (split(//, $str)) {
+ if ($c eq "\t") {
+ $res .= ' ';
+ $n++;
+ for (; ($n % 8) != 0; $n++) {
+ $res .= ' ';
+ }
+ next;
+ }
+ $res .= $c;
+ $n++;
+ }
+
+ return $res;
+}
+sub copy_spacing {
+ (my $res = shift) =~ tr/\t/ /c;
+ return $res;
+}
+
+sub line_stats {
+ my ($line) = @_;
+
+ # Drop the diff line leader and expand tabs
+ $line =~ s/^.//;
+ $line = expand_tabs($line);
+
+ # Pick the indent from the front of the line.
+ my ($white) = ($line =~ /^(\s*)/);
+
+ return (length($line), length($white));
+}
+
+my $sanitise_quote = '';
+
+sub sanitise_line_reset {
+ my ($in_comment) = @_;
+
+ if ($in_comment) {
+ $sanitise_quote = '*/';
+ } else {
+ $sanitise_quote = '';
+ }
+}
+sub sanitise_line {
+ my ($line) = @_;
+
+ my $res = '';
+ my $l = '';
+
+ my $qlen = 0;
+ my $off = 0;
+ my $c;
+
+ # Always copy over the diff marker.
+ $res = substr($line, 0, 1);
+
+ for ($off = 1; $off < length($line); $off++) {
+ $c = substr($line, $off, 1);
+
+ # Comments we are wacking completly including the begin
+ # and end, all to $;.
+ if ($sanitise_quote eq '' && substr($line, $off, 2) eq '/*') {
+ $sanitise_quote = '*/';
+
+ substr($res, $off, 2, "$;$;");
+ $off++;
+ next;
+ }
+ if ($sanitise_quote eq '*/' && substr($line, $off, 2) eq '*/') {
+ $sanitise_quote = '';
+ substr($res, $off, 2, "$;$;");
+ $off++;
+ next;
+ }
+ if ($sanitise_quote eq '' && substr($line, $off, 2) eq '//') {
+ $sanitise_quote = '//';
+
+ substr($res, $off, 2, $sanitise_quote);
+ $off++;
+ next;
+ }
+
+ # A \ in a string means ignore the next character.
+ if (($sanitise_quote eq "'" || $sanitise_quote eq '"') &&
+ $c eq "\\") {
+ substr($res, $off, 2, 'XX');
+ $off++;
+ next;
+ }
+ # Regular quotes.
+ if ($c eq "'" || $c eq '"') {
+ if ($sanitise_quote eq '') {
+ $sanitise_quote = $c;
+
+ substr($res, $off, 1, $c);
+ next;
+ } elsif ($sanitise_quote eq $c) {
+ $sanitise_quote = '';
+ }
+ }
+
+ #print "c<$c> SQ<$sanitise_quote>\n";
+ if ($off != 0 && $sanitise_quote eq '*/' && $c ne "\t") {
+ substr($res, $off, 1, $;);
+ } elsif ($off != 0 && $sanitise_quote eq '//' && $c ne "\t") {
+ substr($res, $off, 1, $;);
+ } elsif ($off != 0 && $sanitise_quote && $c ne "\t") {
+ substr($res, $off, 1, 'X');
+ } else {
+ substr($res, $off, 1, $c);
+ }
+ }
+
+ if ($sanitise_quote eq '//') {
+ $sanitise_quote = '';
+ }
+
+ # The pathname on a #include may be surrounded by '<' and '>'.
+ if ($res =~ /^.\s*\#\s*include\s+\<(.*)\>/) {
+ my $clean = 'X' x length($1);
+ $res =~ s@\<.*\>@<$clean>@;
+
+ # The whole of a #error is a string.
+ } elsif ($res =~ /^.\s*\#\s*(?:error|warning)\s+(.*)\b/) {
+ my $clean = 'X' x length($1);
+ $res =~ s@(\#\s*(?:error|warning)\s+).*@$1$clean@;
+ }
+
+ return $res;
+}
+
+sub ctx_statement_block {
+ my ($linenr, $remain, $off) = @_;
+ my $line = $linenr - 1;
+ my $blk = '';
+ my $soff = $off;
+ my $coff = $off - 1;
+ my $coff_set = 0;
+
+ my $loff = 0;
+
+ my $type = '';
+ my $level = 0;
+ my @stack = ();
+ my $p;
+ my $c;
+ my $len = 0;
+
+ my $remainder;
+ while (1) {
+ @stack = (['', 0]) if ($#stack == -1);
+
+ #warn "CSB: blk<$blk> remain<$remain>\n";
+ # If we are about to drop off the end, pull in more
+ # context.
+ if ($off >= $len) {
+ for (; $remain > 0; $line++) {
+ last if (!defined $lines[$line]);
+ next if ($lines[$line] =~ /^-/);
+ $remain--;
+ $loff = $len;
+ $blk .= $lines[$line] . "\n";
+ $len = length($blk);
+ $line++;
+ last;
+ }
+ # Bail if there is no further context.
+ #warn "CSB: blk<$blk> off<$off> len<$len>\n";
+ if ($off >= $len) {
+ last;
+ }
+ }
+ $p = $c;
+ $c = substr($blk, $off, 1);
+ $remainder = substr($blk, $off);
+
+ #warn "CSB: c<$c> type<$type> level<$level> remainder<$remainder> coff_set<$coff_set>\n";
+
+ # Handle nested #if/#else.
+ if ($remainder =~ /^#\s*(?:ifndef|ifdef|if)\s/) {
+ push(@stack, [ $type, $level ]);
+ } elsif ($remainder =~ /^#\s*(?:else|elif)\b/) {
+ ($type, $level) = @{$stack[$#stack - 1]};
+ } elsif ($remainder =~ /^#\s*endif\b/) {
+ ($type, $level) = @{pop(@stack)};
+ }
+
+ # Statement ends at the ';' or a close '}' at the
+ # outermost level.
+ if ($level == 0 && $c eq ';') {
+ last;
+ }
+
+ # An else is really a conditional as long as its not else if
+ if ($level == 0 && $coff_set == 0 &&
+ (!defined($p) || $p =~ /(?:\s|\}|\+)/) &&
+ $remainder =~ /^(else)(?:\s|{)/ &&
+ $remainder !~ /^else\s+if\b/) {
+ $coff = $off + length($1) - 1;
+ $coff_set = 1;
+ #warn "CSB: mark coff<$coff> soff<$soff> 1<$1>\n";
+ #warn "[" . substr($blk, $soff, $coff - $soff + 1) . "]\n";
+ }
+
+ if (($type eq '' || $type eq '(') && $c eq '(') {
+ $level++;
+ $type = '(';
+ }
+ if ($type eq '(' && $c eq ')') {
+ $level--;
+ $type = ($level != 0)? '(' : '';
+
+ if ($level == 0 && $coff < $soff) {
+ $coff = $off;
+ $coff_set = 1;
+ #warn "CSB: mark coff<$coff>\n";
+ }
+ }
+ if (($type eq '' || $type eq '{') && $c eq '{') {
+ $level++;
+ $type = '{';
+ }
+ if ($type eq '{' && $c eq '}') {
+ $level--;
+ $type = ($level != 0)? '{' : '';
+
+ if ($level == 0) {
+ if (substr($blk, $off + 1, 1) eq ';') {
+ $off++;
+ }
+ last;
+ }
+ }
+ $off++;
+ }
+ # We are truly at the end, so shuffle to the next line.
+ if ($off == $len) {
+ $loff = $len + 1;
+ $line++;
+ $remain--;
+ }
+
+ my $statement = substr($blk, $soff, $off - $soff + 1);
+ my $condition = substr($blk, $soff, $coff - $soff + 1);
+
+ #warn "STATEMENT<$statement>\n";
+ #warn "CONDITION<$condition>\n";
+
+ #print "coff<$coff> soff<$off> loff<$loff>\n";
+
+ return ($statement, $condition,
+ $line, $remain + 1, $off - $loff + 1, $level);
+}
+
+sub statement_lines {
+ my ($stmt) = @_;
+
+ # Strip the diff line prefixes and rip blank lines at start and end.
+ $stmt =~ s/(^|\n)./$1/g;
+ $stmt =~ s/^\s*//;
+ $stmt =~ s/\s*$//;
+
+ my @stmt_lines = ($stmt =~ /\n/g);
+
+ return $#stmt_lines + 2;
+}
+
+sub statement_rawlines {
+ my ($stmt) = @_;
+
+ my @stmt_lines = ($stmt =~ /\n/g);
+
+ return $#stmt_lines + 2;
+}
+
+sub statement_block_size {
+ my ($stmt) = @_;
+
+ $stmt =~ s/(^|\n)./$1/g;
+ $stmt =~ s/^\s*{//;
+ $stmt =~ s/}\s*$//;
+ $stmt =~ s/^\s*//;
+ $stmt =~ s/\s*$//;
+
+ my @stmt_lines = ($stmt =~ /\n/g);
+ my @stmt_statements = ($stmt =~ /;/g);
+
+ my $stmt_lines = $#stmt_lines + 2;
+ my $stmt_statements = $#stmt_statements + 1;
+
+ if ($stmt_lines > $stmt_statements) {
+ return $stmt_lines;
+ } else {
+ return $stmt_statements;
+ }
+}
+
+sub ctx_statement_full {
+ my ($linenr, $remain, $off) = @_;
+ my ($statement, $condition, $level);
+
+ my (@chunks);
+
+ # Grab the first conditional/block pair.
+ ($statement, $condition, $linenr, $remain, $off, $level) =
+ ctx_statement_block($linenr, $remain, $off);
+ #print "F: c<$condition> s<$statement> remain<$remain>\n";
+ push(@chunks, [ $condition, $statement ]);
+ if (!($remain > 0 && $condition =~ /^\s*(?:\n[+-])?\s*(?:if|else|do)\b/s)) {
+ return ($level, $linenr, @chunks);
+ }
+
+ # Pull in the following conditional/block pairs and see if they
+ # could continue the statement.
+ for (;;) {
+ ($statement, $condition, $linenr, $remain, $off, $level) =
+ ctx_statement_block($linenr, $remain, $off);
+ #print "C: c<$condition> s<$statement> remain<$remain>\n";
+ last if (!($remain > 0 && $condition =~ /^(?:\s*\n[+-])*\s*(?:else|do)\b/s));
+ #print "C: push\n";
+ push(@chunks, [ $condition, $statement ]);
+ }
+
+ return ($level, $linenr, @chunks);
+}
+
+sub ctx_block_get {
+ my ($linenr, $remain, $outer, $open, $close, $off) = @_;
+ my $line;
+ my $start = $linenr - 1;
+ my $blk = '';
+ my @o;
+ my @c;
+ my @res = ();
+
+ my $level = 0;
+ my @stack = ($level);
+ for ($line = $start; $remain > 0; $line++) {
+ next if ($rawlines[$line] =~ /^-/);
+ $remain--;
+
+ $blk .= $rawlines[$line];
+
+ # Handle nested #if/#else.
+ if ($lines[$line] =~ /^.\s*#\s*(?:ifndef|ifdef|if)\s/) {
+ push(@stack, $level);
+ } elsif ($lines[$line] =~ /^.\s*#\s*(?:else|elif)\b/) {
+ $level = $stack[$#stack - 1];
+ } elsif ($lines[$line] =~ /^.\s*#\s*endif\b/) {
+ $level = pop(@stack);
+ }
+
+ foreach my $c (split(//, $lines[$line])) {
+ ##print "C<$c>L<$level><$open$close>O<$off>\n";
+ if ($off > 0) {
+ $off--;
+ next;
+ }
+
+ if ($c eq $close && $level > 0) {
+ $level--;
+ last if ($level == 0);
+ } elsif ($c eq $open) {
+ $level++;
+ }
+ }
+
+ if (!$outer || $level <= 1) {
+ push(@res, $rawlines[$line]);
+ }
+
+ last if ($level == 0);
+ }
+
+ return ($level, @res);
+}
+sub ctx_block_outer {
+ my ($linenr, $remain) = @_;
+
+ my ($level, @r) = ctx_block_get($linenr, $remain, 1, '{', '}', 0);
+ return @r;
+}
+sub ctx_block {
+ my ($linenr, $remain) = @_;
+
+ my ($level, @r) = ctx_block_get($linenr, $remain, 0, '{', '}', 0);
+ return @r;
+}
+sub ctx_statement {
+ my ($linenr, $remain, $off) = @_;
+
+ my ($level, @r) = ctx_block_get($linenr, $remain, 0, '(', ')', $off);
+ return @r;
+}
+sub ctx_block_level {
+ my ($linenr, $remain) = @_;
+
+ return ctx_block_get($linenr, $remain, 0, '{', '}', 0);
+}
+sub ctx_statement_level {
+ my ($linenr, $remain, $off) = @_;
+
+ return ctx_block_get($linenr, $remain, 0, '(', ')', $off);
+}
+
+sub ctx_locate_comment {
+ my ($first_line, $end_line) = @_;
+
+ # Catch a comment on the end of the line itself.
+ my ($current_comment) = ($rawlines[$end_line - 1] =~ m@.*(/\*.*\*/)\s*(?:\\\s*)?$@);
+ return $current_comment if (defined $current_comment);
+
+ # Look through the context and try and figure out if there is a
+ # comment.
+ my $in_comment = 0;
+ $current_comment = '';
+ for (my $linenr = $first_line; $linenr < $end_line; $linenr++) {
+ my $line = $rawlines[$linenr - 1];
+ #warn " $line\n";
+ if ($linenr == $first_line and $line =~ m@^.\s*\*@) {
+ $in_comment = 1;
+ }
+ if ($line =~ m@/\*@) {
+ $in_comment = 1;
+ }
+ if (!$in_comment && $current_comment ne '') {
+ $current_comment = '';
+ }
+ $current_comment .= $line . "\n" if ($in_comment);
+ if ($line =~ m@\*/@) {
+ $in_comment = 0;
+ }
+ }
+
+ chomp($current_comment);
+ return($current_comment);
+}
+sub ctx_has_comment {
+ my ($first_line, $end_line) = @_;
+ my $cmt = ctx_locate_comment($first_line, $end_line);
+
+ ##print "LINE: $rawlines[$end_line - 1 ]\n";
+ ##print "CMMT: $cmt\n";
+
+ return ($cmt ne '');
+}
+
+sub raw_line {
+ my ($linenr, $cnt) = @_;
+
+ my $offset = $linenr - 1;
+ $cnt++;
+
+ my $line;
+ while ($cnt) {
+ $line = $rawlines[$offset++];
+ next if (defined($line) && $line =~ /^-/);
+ $cnt--;
+ }
+
+ return $line;
+}
+
+sub cat_vet {
+ my ($vet) = @_;
+ my ($res, $coded);
+
+ $res = '';
+ while ($vet =~ /([^[:cntrl:]]*)([[:cntrl:]]|$)/g) {
+ $res .= $1;
+ if ($2 ne '') {
+ $coded = sprintf("^%c", unpack('C', $2) + 64);
+ $res .= $coded;
+ }
+ }
+ $res =~ s/$/\$/;
+
+ return $res;
+}
+
+my $av_preprocessor = 0;
+my $av_pending;
+my @av_paren_type;
+my $av_pend_colon;
+
+sub annotate_reset {
+ $av_preprocessor = 0;
+ $av_pending = '_';
+ @av_paren_type = ('E');
+ $av_pend_colon = 'O';
+}
+
+sub annotate_values {
+ my ($stream, $type) = @_;
+
+ my $res;
+ my $var = '_' x length($stream);
+ my $cur = $stream;
+
+ print "$stream\n" if ($dbg_values > 1);
+
+ while (length($cur)) {
+ @av_paren_type = ('E') if ($#av_paren_type < 0);
+ print " <" . join('', @av_paren_type) .
+ "> <$type> <$av_pending>" if ($dbg_values > 1);
+ if ($cur =~ /^(\s+)/o) {
+ print "WS($1)\n" if ($dbg_values > 1);
+ if ($1 =~ /\n/ && $av_preprocessor) {
+ $type = pop(@av_paren_type);
+ $av_preprocessor = 0;
+ }
+
+ } elsif ($cur =~ /^(\(\s*$Type\s*)\)/ && $av_pending eq '_') {
+ print "CAST($1)\n" if ($dbg_values > 1);
+ push(@av_paren_type, $type);
+ $type = 'C';
+
+ } elsif ($cur =~ /^($Type)\s*(?:$Ident|,|\)|\(|\s*$)/) {
+ print "DECLARE($1)\n" if ($dbg_values > 1);
+ $type = 'T';
+
+ } elsif ($cur =~ /^($Modifier)\s*/) {
+ print "MODIFIER($1)\n" if ($dbg_values > 1);
+ $type = 'T';
+
+ } elsif ($cur =~ /^(\#\s*define\s*$Ident)(\(?)/o) {
+ print "DEFINE($1,$2)\n" if ($dbg_values > 1);
+ $av_preprocessor = 1;
+ push(@av_paren_type, $type);
+ if ($2 ne '') {
+ $av_pending = 'N';
+ }
+ $type = 'E';
+
+ } elsif ($cur =~ /^(\#\s*(?:undef\s*$Ident|include\b))/o) {
+ print "UNDEF($1)\n" if ($dbg_values > 1);
+ $av_preprocessor = 1;
+ push(@av_paren_type, $type);
+
+ } elsif ($cur =~ /^(\#\s*(?:ifdef|ifndef|if))/o) {
+ print "PRE_START($1)\n" if ($dbg_values > 1);
+ $av_preprocessor = 1;
+
+ push(@av_paren_type, $type);
+ push(@av_paren_type, $type);
+ $type = 'E';
+
+ } elsif ($cur =~ /^(\#\s*(?:else|elif))/o) {
+ print "PRE_RESTART($1)\n" if ($dbg_values > 1);
+ $av_preprocessor = 1;
+
+ push(@av_paren_type, $av_paren_type[$#av_paren_type]);
+
+ $type = 'E';
+
+ } elsif ($cur =~ /^(\#\s*(?:endif))/o) {
+ print "PRE_END($1)\n" if ($dbg_values > 1);
+
+ $av_preprocessor = 1;
+
+ # Assume all arms of the conditional end as this
+ # one does, and continue as if the #endif was not here.
+ pop(@av_paren_type);
+ push(@av_paren_type, $type);
+ $type = 'E';
+
+ } elsif ($cur =~ /^(\\\n)/o) {
+ print "PRECONT($1)\n" if ($dbg_values > 1);
+
+ } elsif ($cur =~ /^(__attribute__)\s*\(?/o) {
+ print "ATTR($1)\n" if ($dbg_values > 1);
+ $av_pending = $type;
+ $type = 'N';
+
+ } elsif ($cur =~ /^(sizeof)\s*(\()?/o) {
+ print "SIZEOF($1)\n" if ($dbg_values > 1);
+ if (defined $2) {
+ $av_pending = 'V';
+ }
+ $type = 'N';
+
+ } elsif ($cur =~ /^(if|while|for)\b/o) {
+ print "COND($1)\n" if ($dbg_values > 1);
+ $av_pending = 'E';
+ $type = 'N';
+
+ } elsif ($cur =~/^(case)/o) {
+ print "CASE($1)\n" if ($dbg_values > 1);
+ $av_pend_colon = 'C';
+ $type = 'N';
+
+ } elsif ($cur =~/^(return|else|goto|typeof|__typeof__)\b/o) {
+ print "KEYWORD($1)\n" if ($dbg_values > 1);
+ $type = 'N';
+
+ } elsif ($cur =~ /^(\()/o) {
+ print "PAREN('$1')\n" if ($dbg_values > 1);
+ push(@av_paren_type, $av_pending);
+ $av_pending = '_';
+ $type = 'N';
+
+ } elsif ($cur =~ /^(\))/o) {
+ my $new_type = pop(@av_paren_type);
+ if ($new_type ne '_') {
+ $type = $new_type;
+ print "PAREN('$1') -> $type\n"
+ if ($dbg_values > 1);
+ } else {
+ print "PAREN('$1')\n" if ($dbg_values > 1);
+ }
+
+ } elsif ($cur =~ /^($Ident)\s*\(/o) {
+ print "FUNC($1)\n" if ($dbg_values > 1);
+ $type = 'V';
+ $av_pending = 'V';
+
+ } elsif ($cur =~ /^($Ident\s*):(?:\s*\d+\s*(,|=|;))?/) {
+ if (defined $2 && $type eq 'C' || $type eq 'T') {
+ $av_pend_colon = 'B';
+ } elsif ($type eq 'E') {
+ $av_pend_colon = 'L';
+ }
+ print "IDENT_COLON($1,$type>$av_pend_colon)\n" if ($dbg_values > 1);
+ $type = 'V';
+
+ } elsif ($cur =~ /^($Ident|$Constant)/o) {
+ print "IDENT($1)\n" if ($dbg_values > 1);
+ $type = 'V';
+
+ } elsif ($cur =~ /^($Assignment)/o) {
+ print "ASSIGN($1)\n" if ($dbg_values > 1);
+ $type = 'N';
+
+ } elsif ($cur =~/^(;|{|})/) {
+ print "END($1)\n" if ($dbg_values > 1);
+ $type = 'E';
+ $av_pend_colon = 'O';
+
+ } elsif ($cur =~/^(,)/) {
+ print "COMMA($1)\n" if ($dbg_values > 1);
+ $type = 'C';
+
+ } elsif ($cur =~ /^(\?)/o) {
+ print "QUESTION($1)\n" if ($dbg_values > 1);
+ $type = 'N';
+
+ } elsif ($cur =~ /^(:)/o) {
+ print "COLON($1,$av_pend_colon)\n" if ($dbg_values > 1);
+
+ substr($var, length($res), 1, $av_pend_colon);
+ if ($av_pend_colon eq 'C' || $av_pend_colon eq 'L') {
+ $type = 'E';
+ } else {
+ $type = 'N';
+ }
+ $av_pend_colon = 'O';
+
+ } elsif ($cur =~ /^(\[)/o) {
+ print "CLOSE($1)\n" if ($dbg_values > 1);
+ $type = 'N';
+
+ } elsif ($cur =~ /^(-(?![->])|\+(?!\+)|\*|\&\&|\&)/o) {
+ my $variant;
+
+ print "OPV($1)\n" if ($dbg_values > 1);
+ if ($type eq 'V') {
+ $variant = 'B';
+ } else {
+ $variant = 'U';
+ }
+
+ substr($var, length($res), 1, $variant);
+ $type = 'N';
+
+ } elsif ($cur =~ /^($Operators)/o) {
+ print "OP($1)\n" if ($dbg_values > 1);
+ if ($1 ne '++' && $1 ne '--') {
+ $type = 'N';
+ }
+
+ } elsif ($cur =~ /(^.)/o) {
+ print "C($1)\n" if ($dbg_values > 1);
+ }
+ if (defined $1) {
+ $cur = substr($cur, length($1));
+ $res .= $type x length($1);
+ }
+ }
+
+ return ($res, $var);
+}
+
+sub possible {
+ my ($possible, $line) = @_;
+ my $notPermitted = qr{(?:
+ ^(?:
+ $Modifier|
+ $Storage|
+ $Type|
+ DEFINE_\S+
+ )$|
+ ^(?:
+ goto|
+ return|
+ case|
+ else|
+ asm|__asm__|
+ do
+ )(?:\s|$)|
+ ^(?:typedef|struct|enum)\b
+ )}x;
+ warn "CHECK<$possible> ($line)\n" if ($dbg_possible > 2);
+ if ($possible !~ $notPermitted) {
+ # Check for modifiers.
+ $possible =~ s/\s*$Storage\s*//g;
+ $possible =~ s/\s*$Sparse\s*//g;
+ if ($possible =~ /^\s*$/) {
+
+ } elsif ($possible =~ /\s/) {
+ $possible =~ s/\s*$Type\s*//g;
+ for my $modifier (split(' ', $possible)) {
+ if ($modifier !~ $notPermitted) {
+ warn "MODIFIER: $modifier ($possible) ($line)\n" if ($dbg_possible);
+ push(@modifierList, $modifier);
+ }
+ }
+
+ } else {
+ warn "POSSIBLE: $possible ($line)\n" if ($dbg_possible);
+ push(@typeList, $possible);
+ }
+ build_types();
+ } else {
+ warn "NOTPOSS: $possible ($line)\n" if ($dbg_possible > 1);
+ }
+}
+
+my $prefix = '';
+
+sub show_type {
+ return !defined $ignore_type{$_[0]};
+}
+
+sub report {
+ if (!show_type($_[1]) ||
+ (defined $tst_only && $_[2] !~ /\Q$tst_only\E/)) {
+ return 0;
+ }
+ my $line;
+ if ($show_types) {
+ $line = "$prefix$_[0]:$_[1]: $_[2]\n";
+ } else {
+ $line = "$prefix$_[0]: $_[2]\n";
+ }
+ $line = (split('\n', $line))[0] . "\n" if ($terse);
+
+ push(our @report, $line);
+
+ return 1;
+}
+sub report_dump {
+ our @report;
+}
+
+sub ERROR {
+ if (report("ERROR", $_[0], $_[1])) {
+ our $clean = 0;
+ our $cnt_error++;
+ }
+}
+sub WARN {
+ if (report("WARNING", $_[0], $_[1])) {
+ our $clean = 0;
+ our $cnt_warn++;
+ }
+}
+sub CHK {
+ if ($check && report("CHECK", $_[0], $_[1])) {
+ our $clean = 0;
+ our $cnt_chk++;
+ }
+}
+
+sub check_absolute_file {
+ my ($absolute, $herecurr) = @_;
+ my $file = $absolute;
+
+ ##print "absolute<$absolute>\n";
+
+ # See if any suffix of this path is a path within the tree.
+ while ($file =~ s@^[^/]*/@@) {
+ if (-f "$root/$file") {
+ ##print "file<$file>\n";
+ last;
+ }
+ }
+ if (! -f _) {
+ return 0;
+ }
+
+ # It is, so see if the prefix is acceptable.
+ my $prefix = $absolute;
+ substr($prefix, -length($file)) = '';
+
+ ##print "prefix<$prefix>\n";
+ if ($prefix ne ".../") {
+ WARN("USE_RELATIVE_PATH",
+ "use relative pathname instead of absolute in changelog text\n" . $herecurr);
+ }
+}
+
+sub process {
+ my $filename = shift;
+
+ my $linenr=0;
+ my $prevline="";
+ my $prevrawline="";
+ my $stashline="";
+ my $stashrawline="";
+
+ my $length;
+ my $indent;
+ my $previndent=0;
+ my $stashindent=0;
+
+ our $clean = 1;
+ my $signoff = 0;
+ my $is_patch = 0;
+
+ our @report = ();
+ our $cnt_lines = 0;
+ our $cnt_error = 0;
+ our $cnt_warn = 0;
+ our $cnt_chk = 0;
+
+ # Trace the real file/line as we go.
+ my $realfile = '';
+ my $realline = 0;
+ my $realcnt = 0;
+ my $here = '';
+ my $in_comment = 0;
+ my $comment_edge = 0;
+ my $first_line = 0;
+ my $p1_prefix = '';
+
+ my $prev_values = 'E';
+
+ # suppression flags
+ my %suppress_ifbraces;
+ my %suppress_whiletrailers;
+ my %suppress_export;
+
+ # Pre-scan the patch sanitizing the lines.
+ # Pre-scan the patch looking for any __setup documentation.
+ #
+ my @setup_docs = ();
+ my $setup_docs = 0;
+
+ sanitise_line_reset();
+ my $line;
+ foreach my $rawline (@rawlines) {
+ $linenr++;
+ $line = $rawline;
+
+ if ($rawline=~/^\+\+\+\s+(\S+)/) {
+ $setup_docs = 0;
+ if ($1 =~ m@Documentation/kernel-parameters.txt$@) {
+ $setup_docs = 1;
+ }
+ #next;
+ }
+ if ($rawline=~/^\@\@ -\d+(?:,\d+)? \+(\d+)(,(\d+))? \@\@/) {
+ $realline=$1-1;
+ if (defined $2) {
+ $realcnt=$3+1;
+ } else {
+ $realcnt=1+1;
+ }
+ $in_comment = 0;
+
+ # Guestimate if this is a continuing comment. Run
+ # the context looking for a comment "edge". If this
+ # edge is a close comment then we must be in a comment
+ # at context start.
+ my $edge;
+ my $cnt = $realcnt;
+ for (my $ln = $linenr + 1; $cnt > 0; $ln++) {
+ next if (defined $rawlines[$ln - 1] &&
+ $rawlines[$ln - 1] =~ /^-/);
+ $cnt--;
+ #print "RAW<$rawlines[$ln - 1]>\n";
+ last if (!defined $rawlines[$ln - 1]);
+ if ($rawlines[$ln - 1] =~ m@(/\*|\*/)@ &&
+ $rawlines[$ln - 1] !~ m@"[^"]*(?:/\*|\*/)[^"]*"@) {
+ ($edge) = $1;
+ last;
+ }
+ }
+ if (defined $edge && $edge eq '*/') {
+ $in_comment = 1;
+ }
+
+ # Guestimate if this is a continuing comment. If this
+ # is the start of a diff block and this line starts
+ # ' *' then it is very likely a comment.
+ if (!defined $edge &&
+ $rawlines[$linenr] =~ m@^.\s*(?:\*\*+| \*)(?:\s|$)@)
+ {
+ $in_comment = 1;
+ }
+
+ ##print "COMMENT:$in_comment edge<$edge> $rawline\n";
+ sanitise_line_reset($in_comment);
+
+ } elsif ($realcnt && $rawline =~ /^(?:\+| |$)/) {
+ # Standardise the strings and chars within the input to
+ # simplify matching -- only bother with positive lines.
+ $line = sanitise_line($rawline);
+ }
+ push(@lines, $line);
+
+ if ($realcnt > 1) {
+ $realcnt-- if ($line =~ /^(?:\+| |$)/);
+ } else {
+ $realcnt = 0;
+ }
+
+ #print "==>$rawline\n";
+ #print "-->$line\n";
+
+ if ($setup_docs && $line =~ /^\+/) {
+ push(@setup_docs, $line);
+ }
+ }
+
+ $prefix = '';
+
+ $realcnt = 0;
+ $linenr = 0;
+ foreach my $line (@lines) {
+ $linenr++;
+
+ my $rawline = $rawlines[$linenr - 1];
+
+#extract the line range in the file after the patch is applied
+ if ($line=~/^\@\@ -\d+(?:,\d+)? \+(\d+)(,(\d+))? \@\@/) {
+ $is_patch = 1;
+ $first_line = $linenr + 1;
+ $realline=$1-1;
+ if (defined $2) {
+ $realcnt=$3+1;
+ } else {
+ $realcnt=1+1;
+ }
+ annotate_reset();
+ $prev_values = 'E';
+
+ %suppress_ifbraces = ();
+ %suppress_whiletrailers = ();
+ %suppress_export = ();
+ next;
+
+# track the line number as we move through the hunk, note that
+# new versions of GNU diff omit the leading space on completely
+# blank context lines so we need to count that too.
+ } elsif ($line =~ /^( |\+|$)/) {
+ $realline++;
+ $realcnt-- if ($realcnt != 0);
+
+ # Measure the line length and indent.
+ ($length, $indent) = line_stats($rawline);
+
+ # Track the previous line.
+ ($prevline, $stashline) = ($stashline, $line);
+ ($previndent, $stashindent) = ($stashindent, $indent);
+ ($prevrawline, $stashrawline) = ($stashrawline, $rawline);
+
+ #warn "line<$line>\n";
+
+ } elsif ($realcnt == 1) {
+ $realcnt--;
+ }
+
+ my $hunk_line = ($realcnt != 0);
+
+#make up the handle for any error we report on this line
+ $prefix = "$filename:$realline: " if ($emacs && $file);
+ $prefix = "$filename:$linenr: " if ($emacs && !$file);
+
+ $here = "#$linenr: " if (!$file);
+ $here = "#$realline: " if ($file);
+
+ # extract the filename as it passes
+ if ($line =~ /^diff --git.*?(\S+)$/) {
+ $realfile = $1;
+ $realfile =~ s@^([^/]*)/@@;
+
+ } elsif ($line =~ /^\+\+\+\s+(\S+)/) {
+ $realfile = $1;
+ $realfile =~ s@^([^/]*)/@@;
+
+ $p1_prefix = $1;
+ if (!$file && $tree && $p1_prefix ne '' &&
+ -e "$root/$p1_prefix") {
+ WARN("PATCH_PREFIX",
+ "patch prefix '$p1_prefix' exists, appears to be a -p0 patch\n");
+ }
+
+ if ($realfile =~ m@^include/asm/@) {
+ ERROR("MODIFIED_INCLUDE_ASM",
+ "do not modify files in include/asm, change architecture specific files in include/asm-<architecture>\n" . "$here$rawline\n");
+ }
+ next;
+ }
+
+ $here .= "FILE: $realfile:$realline:" if ($realcnt != 0);
+
+ my $hereline = "$here\n$rawline\n";
+ my $herecurr = "$here\n$rawline\n";
+ my $hereprev = "$here\n$prevrawline\n$rawline\n";
+
+ $cnt_lines++ if ($realcnt != 0);
+
+# Check for incorrect file permissions
+ if ($line =~ /^new (file )?mode.*[7531]\d{0,2}$/) {
+ my $permhere = $here . "FILE: $realfile\n";
+ if ($realfile =~ /(Makefile|Kconfig|\.c|\.h|\.S|\.tmpl)$/) {
+ ERROR("EXECUTE_PERMISSIONS",
+ "do not set execute permissions for source files\n" . $permhere);
+ }
+ }
+
+# Check the patch for a signoff:
+ if ($line =~ /^\s*signed-off-by:/i) {
+ $signoff++;
+ }
+
+# Check signature styles
+ if ($line =~ /^(\s*)($signature_tags)(\s*)(.*)/) {
+ my $space_before = $1;
+ my $sign_off = $2;
+ my $space_after = $3;
+ my $email = $4;
+ my $ucfirst_sign_off = ucfirst(lc($sign_off));
+
+ if (defined $space_before && $space_before ne "") {
+ WARN("BAD_SIGN_OFF",
+ "Do not use whitespace before $ucfirst_sign_off\n" . $herecurr);
+ }
+ if ($sign_off =~ /-by:$/i && $sign_off ne $ucfirst_sign_off) {
+ WARN("BAD_SIGN_OFF",
+ "'$ucfirst_sign_off' is the preferred signature form\n" . $herecurr);
+ }
+ if (!defined $space_after || $space_after ne " ") {
+ WARN("BAD_SIGN_OFF",
+ "Use a single space after $ucfirst_sign_off\n" . $herecurr);
+ }
+
+ my ($email_name, $email_address, $comment) = parse_email($email);
+ my $suggested_email = format_email(($email_name, $email_address));
+ if ($suggested_email eq "") {
+ ERROR("BAD_SIGN_OFF",
+ "Unrecognized email address: '$email'\n" . $herecurr);
+ } else {
+ my $dequoted = $suggested_email;
+ $dequoted =~ s/^"//;
+ $dequoted =~ s/" </ </;
+ # Don't force email to have quotes
+ # Allow just an angle bracketed address
+ if ("$dequoted$comment" ne $email &&
+ "<$email_address>$comment" ne $email &&
+ "$suggested_email$comment" ne $email) {
+ WARN("BAD_SIGN_OFF",
+ "email address '$email' might be better as '$suggested_email$comment'\n" . $herecurr);
+ }
+ }
+ }
+
+# Check for wrappage within a valid hunk of the file
+ if ($realcnt != 0 && $line !~ m{^(?:\+|-| |\\ No newline|$)}) {
+ ERROR("CORRUPTED_PATCH",
+ "patch seems to be corrupt (line wrapped?)\n" .
+ $herecurr) if (!$emitted_corrupt++);
+ }
+
+# Check for absolute kernel paths.
+ if ($tree) {
+ while ($line =~ m{(?:^|\s)(/\S*)}g) {
+ my $file = $1;
+
+ if ($file =~ m{^(.*?)(?::\d+)+:?$} &&
+ check_absolute_file($1, $herecurr)) {
+ #
+ } else {
+ check_absolute_file($file, $herecurr);
+ }
+ }
+ }
+
+# UTF-8 regex found at http://www.w3.org/International/questions/qa-forms-utf-8.en.php
+ if (($realfile =~ /^$/ || $line =~ /^\+/) &&
+ $rawline !~ m/^$UTF8*$/) {
+ my ($utf8_prefix) = ($rawline =~ /^($UTF8*)/);
+
+ my $blank = copy_spacing($rawline);
+ my $ptr = substr($blank, 0, length($utf8_prefix)) . "^";
+ my $hereptr = "$hereline$ptr\n";
+
+ CHK("INVALID_UTF8",
+ "Invalid UTF-8, patch and commit message should be encoded in UTF-8\n" . $hereptr);
+ }
+
+# ignore non-hunk lines and lines being removed
+ next if (!$hunk_line || $line =~ /^-/);
+
+#trailing whitespace
+ if ($line =~ /^\+.*\015/) {
+ my $herevet = "$here\n" . cat_vet($rawline) . "\n";
+ ERROR("DOS_LINE_ENDINGS",
+ "DOS line endings\n" . $herevet);
+
+ } elsif ($rawline =~ /^\+.*\S\s+$/ || $rawline =~ /^\+\s+$/) {
+ my $herevet = "$here\n" . cat_vet($rawline) . "\n";
+ ERROR("TRAILING_WHITESPACE",
+ "trailing whitespace\n" . $herevet);
+ $rpt_cleaners = 1;
+ }
+
+# check for Kconfig help text having a real description
+# Only applies when adding the entry originally, after that we do not have
+# sufficient context to determine whether it is indeed long enough.
+ if ($realfile =~ /Kconfig/ &&
+ $line =~ /\+\s*(?:---)?help(?:---)?$/) {
+ my $length = 0;
+ my $cnt = $realcnt;
+ my $ln = $linenr + 1;
+ my $f;
+ my $is_end = 0;
+ while ($cnt > 0 && defined $lines[$ln - 1]) {
+ $f = $lines[$ln - 1];
+ $cnt-- if ($lines[$ln - 1] !~ /^-/);
+ $is_end = $lines[$ln - 1] =~ /^\+/;
+ $ln++;
+
+ next if ($f =~ /^-/);
+ $f =~ s/^.//;
+ $f =~ s/#.*//;
+ $f =~ s/^\s+//;
+ next if ($f =~ /^$/);
+ if ($f =~ /^\s*config\s/) {
+ $is_end = 1;
+ last;
+ }
+ $length++;
+ }
+ WARN("CONFIG_DESCRIPTION",
+ "please write a paragraph that describes the config symbol fully\n" . $herecurr) if ($is_end && $length < 4);
+ #print "is_end<$is_end> length<$length>\n";
+ }
+
+# check we are in a valid source file if not then ignore this hunk
+ next if ($realfile !~ /\.(h|c|s|S|pl|sh)$/);
+
+#80 column limit
+ if ($line =~ /^\+/ && $prevrawline !~ /\/\*\*/ &&
+ $rawline !~ /^.\s*\*\s*\@$Ident\s/ &&
+ !($line =~ /^\+\s*$logFunctions\s*\(\s*(?:(KERN_\S+\s*|[^"]*))?"[X\t]*"\s*(?:|,|\)\s*;)\s*$/ ||
+ $line =~ /^\+\s*"[^"]*"\s*(?:\s*|,|\)\s*;)\s*$/) &&
+ $length > 80)
+ {
+ WARN("LONG_LINE",
+ "line over 80 characters\n" . $herecurr);
+ }
+
+# check for spaces before a quoted newline
+ if ($rawline =~ /^.*\".*\s\\n/) {
+ WARN("QUOTED_WHITESPACE_BEFORE_NEWLINE",
+ "unnecessary whitespace before a quoted newline\n" . $herecurr);
+ }
+
+# check for adding lines without a newline.
+ if ($line =~ /^\+/ && defined $lines[$linenr] && $lines[$linenr] =~ /^\\ No newline at end of file/) {
+ WARN("MISSING_EOF_NEWLINE",
+ "adding a line without newline at end of file\n" . $herecurr);
+ }
+
+# Blackfin: use hi/lo macros
+ if ($realfile =~ m@arch/blackfin/.*\.S$@) {
+ if ($line =~ /\.[lL][[:space:]]*=.*&[[:space:]]*0x[fF][fF][fF][fF]/) {
+ my $herevet = "$here\n" . cat_vet($line) . "\n";
+ ERROR("LO_MACRO",
+ "use the LO() macro, not (... & 0xFFFF)\n" . $herevet);
+ }
+ if ($line =~ /\.[hH][[:space:]]*=.*>>[[:space:]]*16/) {
+ my $herevet = "$here\n" . cat_vet($line) . "\n";
+ ERROR("HI_MACRO",
+ "use the HI() macro, not (... >> 16)\n" . $herevet);
+ }
+ }
+
+# check we are in a valid source file C or perl if not then ignore this hunk
+ next if ($realfile !~ /\.(h|c|pl)$/);
+
+# at the beginning of a line any tabs must come first and anything
+# more than 8 must use tabs.
+ if ($rawline =~ /^\+\s* \t\s*\S/ ||
+ $rawline =~ /^\+\s* \s*/) {
+ my $herevet = "$here\n" . cat_vet($rawline) . "\n";
+ ERROR("CODE_INDENT",
+ "code indent should use tabs where possible\n" . $herevet);
+ $rpt_cleaners = 1;
+ }
+
+# check for space before tabs.
+ if ($rawline =~ /^\+/ && $rawline =~ / \t/) {
+ my $herevet = "$here\n" . cat_vet($rawline) . "\n";
+ WARN("SPACE_BEFORE_TAB",
+ "please, no space before tabs\n" . $herevet);
+ }
+
+# check for spaces at the beginning of a line.
+# Exceptions:
+# 1) within comments
+# 2) indented preprocessor commands
+# 3) hanging labels
+ if ($rawline =~ /^\+ / && $line !~ /\+ *(?:$;|#|$Ident:)/) {
+ my $herevet = "$here\n" . cat_vet($rawline) . "\n";
+ WARN("LEADING_SPACE",
+ "please, no spaces at the start of a line\n" . $herevet);
+ }
+
+# check we are in a valid C source file if not then ignore this hunk
+ next if ($realfile !~ /\.(h|c)$/);
+
+# check for RCS/CVS revision markers
+ if ($rawline =~ /^\+.*\$(Revision|Log|Id)(?:\$|)/) {
+ WARN("CVS_KEYWORD",
+ "CVS style keyword markers, these will _not_ be updated\n". $herecurr);
+ }
+
+# Blackfin: don't use __builtin_bfin_[cs]sync
+ if ($line =~ /__builtin_bfin_csync/) {
+ my $herevet = "$here\n" . cat_vet($line) . "\n";
+ ERROR("CSYNC",
+ "use the CSYNC() macro in asm/blackfin.h\n" . $herevet);
+ }
+ if ($line =~ /__builtin_bfin_ssync/) {
+ my $herevet = "$here\n" . cat_vet($line) . "\n";
+ ERROR("SSYNC",
+ "use the SSYNC() macro in asm/blackfin.h\n" . $herevet);
+ }
+
+# Check for potential 'bare' types
+ my ($stat, $cond, $line_nr_next, $remain_next, $off_next,
+ $realline_next);
+ if ($realcnt && $line =~ /.\s*\S/) {
+ ($stat, $cond, $line_nr_next, $remain_next, $off_next) =
+ ctx_statement_block($linenr, $realcnt, 0);
+ $stat =~ s/\n./\n /g;
+ $cond =~ s/\n./\n /g;
+
+ # Find the real next line.
+ $realline_next = $line_nr_next;
+ if (defined $realline_next &&
+ (!defined $lines[$realline_next - 1] ||
+ substr($lines[$realline_next - 1], $off_next) =~ /^\s*$/)) {
+ $realline_next++;
+ }
+
+ my $s = $stat;
+ $s =~ s/{.*$//s;
+
+ # Ignore goto labels.
+ if ($s =~ /$Ident:\*$/s) {
+
+ # Ignore functions being called
+ } elsif ($s =~ /^.\s*$Ident\s*\(/s) {
+
+ } elsif ($s =~ /^.\s*else\b/s) {
+
+ # declarations always start with types
+ } elsif ($prev_values eq 'E' && $s =~ /^.\s*(?:$Storage\s+)?(?:$Inline\s+)?(?:const\s+)?((?:\s*$Ident)+?)\b(?:\s+$Sparse)?\s*\**\s*(?:$Ident|\(\*[^\)]*\))(?:\s*$Modifier)?\s*(?:;|=|,|\()/s) {
+ my $type = $1;
+ $type =~ s/\s+/ /g;
+ possible($type, "A:" . $s);
+
+ # definitions in global scope can only start with types
+ } elsif ($s =~ /^.(?:$Storage\s+)?(?:$Inline\s+)?(?:const\s+)?($Ident)\b\s*(?!:)/s) {
+ possible($1, "B:" . $s);
+ }
+
+ # any (foo ... *) is a pointer cast, and foo is a type
+ while ($s =~ /\(($Ident)(?:\s+$Sparse)*[\s\*]+\s*\)/sg) {
+ possible($1, "C:" . $s);
+ }
+
+ # Check for any sort of function declaration.
+ # int foo(something bar, other baz);
+ # void (*store_gdt)(x86_descr_ptr *);
+ if ($prev_values eq 'E' && $s =~ /^(.(?:typedef\s*)?(?:(?:$Storage|$Inline)\s*)*\s*$Type\s*(?:\b$Ident|\(\*\s*$Ident\))\s*)\(/s) {
+ my ($name_len) = length($1);
+
+ my $ctx = $s;
+ substr($ctx, 0, $name_len + 1, '');
+ $ctx =~ s/\)[^\)]*$//;
+
+ for my $arg (split(/\s*,\s*/, $ctx)) {
+ if ($arg =~ /^(?:const\s+)?($Ident)(?:\s+$Sparse)*\s*\**\s*(:?\b$Ident)?$/s || $arg =~ /^($Ident)$/s) {
+
+ possible($1, "D:" . $s);
+ }
+ }
+ }
+
+ }
+
+#
+# Checks which may be anchored in the context.
+#
+
+# Check for switch () and associated case and default
+# statements should be at the same indent.
+ if ($line=~/\bswitch\s*\(.*\)/) {
+ my $err = '';
+ my $sep = '';
+ my @ctx = ctx_block_outer($linenr, $realcnt);
+ shift(@ctx);
+ for my $ctx (@ctx) {
+ my ($clen, $cindent) = line_stats($ctx);
+ if ($ctx =~ /^\+\s*(case\s+|default:)/ &&
+ $indent != $cindent) {
+ $err .= "$sep$ctx\n";
+ $sep = '';
+ } else {
+ $sep = "[...]\n";
+ }
+ }
+ if ($err ne '') {
+ ERROR("SWITCH_CASE_INDENT_LEVEL",
+ "switch and case should be at the same indent\n$hereline$err");
+ }
+ }
+
+# if/while/etc brace do not go on next line, unless defining a do while loop,
+# or if that brace on the next line is for something else
+ if ($line =~ /(.*)\b((?:if|while|for|switch)\s*\(|do\b|else\b)/ && $line !~ /^.\s*\#/) {
+ my $pre_ctx = "$1$2";
+
+ my ($level, @ctx) = ctx_statement_level($linenr, $realcnt, 0);
+ my $ctx_cnt = $realcnt - $#ctx - 1;
+ my $ctx = join("\n", @ctx);
+
+ my $ctx_ln = $linenr;
+ my $ctx_skip = $realcnt;
+
+ while ($ctx_skip > $ctx_cnt || ($ctx_skip == $ctx_cnt &&
+ defined $lines[$ctx_ln - 1] &&
+ $lines[$ctx_ln - 1] =~ /^-/)) {
+ ##print "SKIP<$ctx_skip> CNT<$ctx_cnt>\n";
+ $ctx_skip-- if (!defined $lines[$ctx_ln - 1] || $lines[$ctx_ln - 1] !~ /^-/);
+ $ctx_ln++;
+ }
+
+ #print "realcnt<$realcnt> ctx_cnt<$ctx_cnt>\n";
+ #print "pre<$pre_ctx>\nline<$line>\nctx<$ctx>\nnext<$lines[$ctx_ln - 1]>\n";
+
+ if ($ctx !~ /{\s*/ && defined($lines[$ctx_ln -1]) && $lines[$ctx_ln - 1] =~ /^\+\s*{/) {
+ ERROR("OPEN_BRACE",
+ "that open brace { should be on the previous line\n" .
+ "$here\n$ctx\n$rawlines[$ctx_ln - 1]\n");
+ }
+ if ($level == 0 && $pre_ctx !~ /}\s*while\s*\($/ &&
+ $ctx =~ /\)\s*\;\s*$/ &&
+ defined $lines[$ctx_ln - 1])
+ {
+ my ($nlength, $nindent) = line_stats($lines[$ctx_ln - 1]);
+ if ($nindent > $indent) {
+ WARN("TRAILING_SEMICOLON",
+ "trailing semicolon indicates no statements, indent implies otherwise\n" .
+ "$here\n$ctx\n$rawlines[$ctx_ln - 1]\n");
+ }
+ }
+ }
+
+# Check relative indent for conditionals and blocks.
+ if ($line =~ /\b(?:(?:if|while|for)\s*\(|do\b)/ && $line !~ /^.\s*#/ && $line !~ /\}\s*while\s*/) {
+ my ($s, $c) = ($stat, $cond);
+
+ substr($s, 0, length($c), '');
+
+ # Make sure we remove the line prefixes as we have
+ # none on the first line, and are going to readd them
+ # where necessary.
+ $s =~ s/\n./\n/gs;
+
+ # Find out how long the conditional actually is.
+ my @newlines = ($c =~ /\n/gs);
+ my $cond_lines = 1 + $#newlines;
+
+ # We want to check the first line inside the block
+ # starting at the end of the conditional, so remove:
+ # 1) any blank line termination
+ # 2) any opening brace { on end of the line
+ # 3) any do (...) {
+ my $continuation = 0;
+ my $check = 0;
+ $s =~ s/^.*\bdo\b//;
+ $s =~ s/^\s*{//;
+ if ($s =~ s/^\s*\\//) {
+ $continuation = 1;
+ }
+ if ($s =~ s/^\s*?\n//) {
+ $check = 1;
+ $cond_lines++;
+ }
+
+ # Also ignore a loop construct at the end of a
+ # preprocessor statement.
+ if (($prevline =~ /^.\s*#\s*define\s/ ||
+ $prevline =~ /\\\s*$/) && $continuation == 0) {
+ $check = 0;
+ }
+
+ my $cond_ptr = -1;
+ $continuation = 0;
+ while ($cond_ptr != $cond_lines) {
+ $cond_ptr = $cond_lines;
+
+ # If we see an #else/#elif then the code
+ # is not linear.
+ if ($s =~ /^\s*\#\s*(?:else|elif)/) {
+ $check = 0;
+ }
+
+ # Ignore:
+ # 1) blank lines, they should be at 0,
+ # 2) preprocessor lines, and
+ # 3) labels.
+ if ($continuation ||
+ $s =~ /^\s*?\n/ ||
+ $s =~ /^\s*#\s*?/ ||
+ $s =~ /^\s*$Ident\s*:/) {
+ $continuation = ($s =~ /^.*?\\\n/) ? 1 : 0;
+ if ($s =~ s/^.*?\n//) {
+ $cond_lines++;
+ }
+ }
+ }
+
+ my (undef, $sindent) = line_stats("+" . $s);
+ my $stat_real = raw_line($linenr, $cond_lines);
+
+ # Check if either of these lines are modified, else
+ # this is not this patch's fault.
+ if (!defined($stat_real) ||
+ $stat !~ /^\+/ && $stat_real !~ /^\+/) {
+ $check = 0;
+ }
+ if (defined($stat_real) && $cond_lines > 1) {
+ $stat_real = "[...]\n$stat_real";
+ }
+
+ #print "line<$line> prevline<$prevline> indent<$indent> sindent<$sindent> check<$check> continuation<$continuation> s<$s> cond_lines<$cond_lines> stat_real<$stat_real> stat<$stat>\n";
+
+ if ($check && (($sindent % 8) != 0 ||
+ ($sindent <= $indent && $s ne ''))) {
+ WARN("SUSPECT_CODE_INDENT",
+ "suspect code indent for conditional statements ($indent, $sindent)\n" . $herecurr . "$stat_real\n");
+ }
+ }
+
+ # Track the 'values' across context and added lines.
+ my $opline = $line; $opline =~ s/^./ /;
+ my ($curr_values, $curr_vars) =
+ annotate_values($opline . "\n", $prev_values);
+ $curr_values = $prev_values . $curr_values;
+ if ($dbg_values) {
+ my $outline = $opline; $outline =~ s/\t/ /g;
+ print "$linenr > .$outline\n";
+ print "$linenr > $curr_values\n";
+ print "$linenr > $curr_vars\n";
+ }
+ $prev_values = substr($curr_values, -1);
+
+#ignore lines not being added
+ if ($line=~/^[^\+]/) {next;}
+
+# TEST: allow direct testing of the type matcher.
+ if ($dbg_type) {
+ if ($line =~ /^.\s*$Declare\s*$/) {
+ ERROR("TEST_TYPE",
+ "TEST: is type\n" . $herecurr);
+ } elsif ($dbg_type > 1 && $line =~ /^.+($Declare)/) {
+ ERROR("TEST_NOT_TYPE",
+ "TEST: is not type ($1 is)\n". $herecurr);
+ }
+ next;
+ }
+# TEST: allow direct testing of the attribute matcher.
+ if ($dbg_attr) {
+ if ($line =~ /^.\s*$Modifier\s*$/) {
+ ERROR("TEST_ATTR",
+ "TEST: is attr\n" . $herecurr);
+ } elsif ($dbg_attr > 1 && $line =~ /^.+($Modifier)/) {
+ ERROR("TEST_NOT_ATTR",
+ "TEST: is not attr ($1 is)\n". $herecurr);
+ }
+ next;
+ }
+
+# check for initialisation to aggregates open brace on the next line
+ if ($line =~ /^.\s*{/ &&
+ $prevline =~ /(?:^|[^=])=\s*$/) {
+ ERROR("OPEN_BRACE",
+ "that open brace { should be on the previous line\n" . $hereprev);
+ }
+
+#
+# Checks which are anchored on the added line.
+#
+
+# check for malformed paths in #include statements (uses RAW line)
+ if ($rawline =~ m{^.\s*\#\s*include\s+[<"](.*)[">]}) {
+ my $path = $1;
+ if ($path =~ m{//}) {
+ ERROR("MALFORMED_INCLUDE",
+ "malformed #include filename\n" .
+ $herecurr);
+ }
+ }
+
+# no C99 // comments
+ if ($line =~ m{//}) {
+ ERROR("C99_COMMENTS",
+ "do not use C99 // comments\n" . $herecurr);
+ }
+ # Remove C99 comments.
+ $line =~ s@//.*@@;
+ $opline =~ s@//.*@@;
+
+# EXPORT_SYMBOL should immediately follow the thing it is exporting, consider
+# the whole statement.
+#print "APW <$lines[$realline_next - 1]>\n";
+ if (defined $realline_next &&
+ exists $lines[$realline_next - 1] &&
+ !defined $suppress_export{$realline_next} &&
+ ($lines[$realline_next - 1] =~ /EXPORT_SYMBOL.*\((.*)\)/ ||
+ $lines[$realline_next - 1] =~ /EXPORT_UNUSED_SYMBOL.*\((.*)\)/)) {
+ # Handle definitions which produce identifiers with
+ # a prefix:
+ # XXX(foo);
+ # EXPORT_SYMBOL(something_foo);
+ my $name = $1;
+ if ($stat =~ /^.([A-Z_]+)\s*\(\s*($Ident)/ &&
+ $name =~ /^${Ident}_$2/) {
+#print "FOO C name<$name>\n";
+ $suppress_export{$realline_next} = 1;
+
+ } elsif ($stat !~ /(?:
+ \n.}\s*$|
+ ^.DEFINE_$Ident\(\Q$name\E\)|
+ ^.DECLARE_$Ident\(\Q$name\E\)|
+ ^.LIST_HEAD\(\Q$name\E\)|
+ ^.(?:$Storage\s+)?$Type\s*\(\s*\*\s*\Q$name\E\s*\)\s*\(|
+ \b\Q$name\E(?:\s+$Attribute)*\s*(?:;|=|\[|\()
+ )/x) {
+#print "FOO A<$lines[$realline_next - 1]> stat<$stat> name<$name>\n";
+ $suppress_export{$realline_next} = 2;
+ } else {
+ $suppress_export{$realline_next} = 1;
+ }
+ }
+ if (!defined $suppress_export{$linenr} &&
+ $prevline =~ /^.\s*$/ &&
+ ($line =~ /EXPORT_SYMBOL.*\((.*)\)/ ||
+ $line =~ /EXPORT_UNUSED_SYMBOL.*\((.*)\)/)) {
+#print "FOO B <$lines[$linenr - 1]>\n";
+ $suppress_export{$linenr} = 2;
+ }
+ if (defined $suppress_export{$linenr} &&
+ $suppress_export{$linenr} == 2) {
+ WARN("EXPORT_SYMBOL",
+ "EXPORT_SYMBOL(foo); should immediately follow its function/variable\n" . $herecurr);
+ }
+
+# check for global initialisers.
+ if ($line =~ /^.$Type\s*$Ident\s*(?:\s+$Modifier)*\s*=\s*(0|NULL|false)\s*;/) {
+ ERROR("GLOBAL_INITIALISERS",
+ "do not initialise globals to 0 or NULL\n" .
+ $herecurr);
+ }
+# check for static initialisers.
+ if ($line =~ /\bstatic\s.*=\s*(0|NULL|false)\s*;/) {
+ ERROR("INITIALISED_STATIC",
+ "do not initialise statics to 0 or NULL\n" .
+ $herecurr);
+ }
+
+# check for static const char * arrays.
+ if ($line =~ /\bstatic\s+const\s+char\s*\*\s*(\w+)\s*\[\s*\]\s*=\s*/) {
+ WARN("STATIC_CONST_CHAR_ARRAY",
+ "static const char * array should probably be static const char * const\n" .
+ $herecurr);
+ }
+
+# check for static char foo[] = "bar" declarations.
+ if ($line =~ /\bstatic\s+char\s+(\w+)\s*\[\s*\]\s*=\s*"/) {
+ WARN("STATIC_CONST_CHAR_ARRAY",
+ "static char array declaration should probably be static const char\n" .
+ $herecurr);
+ }
+
+# check for declarations of struct pci_device_id
+ if ($line =~ /\bstruct\s+pci_device_id\s+\w+\s*\[\s*\]\s*\=\s*\{/) {
+ WARN("DEFINE_PCI_DEVICE_TABLE",
+ "Use DEFINE_PCI_DEVICE_TABLE for struct pci_device_id\n" . $herecurr);
+ }
+
+# check for new typedefs, only function parameters and sparse annotations
+# make sense.
+ if ($line =~ /\btypedef\s/ &&
+ $line !~ /\btypedef\s+$Type\s*\(\s*\*?$Ident\s*\)\s*\(/ &&
+ $line !~ /\btypedef\s+$Type\s+$Ident\s*\(/ &&
+ $line !~ /\b$typeTypedefs\b/ &&
+ $line !~ /\b__bitwise(?:__|)\b/) {
+ WARN("NEW_TYPEDEFS",
+ "do not add new typedefs\n" . $herecurr);
+ }
+
+# * goes on variable not on type
+ # (char*[ const])
+ if ($line =~ m{\($NonptrType(\s*(?:$Modifier\b\s*|\*\s*)+)\)}) {
+ my ($from, $to) = ($1, $1);
+
+ # Should start with a space.
+ $to =~ s/^(\S)/ $1/;
+ # Should not end with a space.
+ $to =~ s/\s+$//;
+ # '*'s should not have spaces between.
+ while ($to =~ s/\*\s+\*/\*\*/) {
+ }
+
+ #print "from<$from> to<$to>\n";
+ if ($from ne $to) {
+ ERROR("POINTER_LOCATION",
+ "\"(foo$from)\" should be \"(foo$to)\"\n" . $herecurr);
+ }
+ } elsif ($line =~ m{\b$NonptrType(\s*(?:$Modifier\b\s*|\*\s*)+)($Ident)}) {
+ my ($from, $to, $ident) = ($1, $1, $2);
+
+ # Should start with a space.
+ $to =~ s/^(\S)/ $1/;
+ # Should not end with a space.
+ $to =~ s/\s+$//;
+ # '*'s should not have spaces between.
+ while ($to =~ s/\*\s+\*/\*\*/) {
+ }
+ # Modifiers should have spaces.
+ $to =~ s/(\b$Modifier$)/$1 /;
+
+ #print "from<$from> to<$to> ident<$ident>\n";
+ if ($from ne $to && $ident !~ /^$Modifier$/) {
+ ERROR("POINTER_LOCATION",
+ "\"foo${from}bar\" should be \"foo${to}bar\"\n" . $herecurr);
+ }
+ }
+
+# # no BUG() or BUG_ON()
+# if ($line =~ /\b(BUG|BUG_ON)\b/) {
+# print "Try to use WARN_ON & Recovery code rather than BUG() or BUG_ON()\n";
+# print "$herecurr";
+# $clean = 0;
+# }
+
+ if ($line =~ /\bLINUX_VERSION_CODE\b/) {
+ WARN("LINUX_VERSION_CODE",
+ "LINUX_VERSION_CODE should be avoided, code should be for the version to which it is merged\n" . $herecurr);
+ }
+
+# check for uses of printk_ratelimit
+ if ($line =~ /\bprintk_ratelimit\s*\(/) {
+ WARN("PRINTK_RATELIMITED",
+"Prefer printk_ratelimited or pr_<level>_ratelimited to printk_ratelimit\n" . $herecurr);
+ }
+
+# printk should use KERN_* levels. Note that follow on printk's on the
+# same line do not need a level, so we use the current block context
+# to try and find and validate the current printk. In summary the current
+# printk includes all preceding printk's which have no newline on the end.
+# we assume the first bad printk is the one to report.
+ if ($line =~ /\bprintk\((?!KERN_)\s*"/) {
+ my $ok = 0;
+ for (my $ln = $linenr - 1; $ln >= $first_line; $ln--) {
+ #print "CHECK<$lines[$ln - 1]\n";
+ # we have a preceding printk if it ends
+ # with "\n" ignore it, else it is to blame
+ if ($lines[$ln - 1] =~ m{\bprintk\(}) {
+ if ($rawlines[$ln - 1] !~ m{\\n"}) {
+ $ok = 1;
+ }
+ last;
+ }
+ }
+ if ($ok == 0) {
+ WARN("PRINTK_WITHOUT_KERN_LEVEL",
+ "printk() should include KERN_ facility level\n" . $herecurr);
+ }
+ }
+
+# function brace can't be on same line, except for #defines of do while,
+# or if closed on same line
+ if (($line=~/$Type\s*$Ident\(.*\).*\s{/) and
+ !($line=~/\#\s*define.*do\s{/) and !($line=~/}/)) {
+ ERROR("OPEN_BRACE",
+ "open brace '{' following function declarations go on the next line\n" . $herecurr);
+ }
+
+# open braces for enum, union and struct go on the same line.
+ if ($line =~ /^.\s*{/ &&
+ $prevline =~ /^.\s*(?:typedef\s+)?(enum|union|struct)(?:\s+$Ident)?\s*$/) {
+ ERROR("OPEN_BRACE",
+ "open brace '{' following $1 go on the same line\n" . $hereprev);
+ }
+
+# missing space after union, struct or enum definition
+ if ($line =~ /^.\s*(?:typedef\s+)?(enum|union|struct)(?:\s+$Ident)?(?:\s+$Ident)?[=\{]/) {
+ WARN("SPACING",
+ "missing space after $1 definition\n" . $herecurr);
+ }
+
+# check for spacing round square brackets; allowed:
+# 1. with a type on the left -- int [] a;
+# 2. at the beginning of a line for slice initialisers -- [0...10] = 5,
+# 3. inside a curly brace -- = { [0...10] = 5 }
+ while ($line =~ /(.*?\s)\[/g) {
+ my ($where, $prefix) = ($-[1], $1);
+ if ($prefix !~ /$Type\s+$/ &&
+ ($where != 0 || $prefix !~ /^.\s+$/) &&
+ $prefix !~ /{\s+$/) {
+ ERROR("BRACKET_SPACE",
+ "space prohibited before open square bracket '['\n" . $herecurr);
+ }
+ }
+
+# check for spaces between functions and their parentheses.
+ while ($line =~ /($Ident)\s+\(/g) {
+ my $name = $1;
+ my $ctx_before = substr($line, 0, $-[1]);
+ my $ctx = "$ctx_before$name";
+
+ # Ignore those directives where spaces _are_ permitted.
+ if ($name =~ /^(?:
+ if|for|while|switch|return|case|
+ volatile|__volatile__|
+ __attribute__|format|__extension__|
+ asm|__asm__)$/x)
+ {
+
+ # cpp #define statements have non-optional spaces, ie
+ # if there is a space between the name and the open
+ # parenthesis it is simply not a parameter group.
+ } elsif ($ctx_before =~ /^.\s*\#\s*define\s*$/) {
+
+ # cpp #elif statement condition may start with a (
+ } elsif ($ctx =~ /^.\s*\#\s*elif\s*$/) {
+
+ # If this whole things ends with a type its most
+ # likely a typedef for a function.
+ } elsif ($ctx =~ /$Type$/) {
+
+ } else {
+ WARN("SPACING",
+ "space prohibited between function name and open parenthesis '('\n" . $herecurr);
+ }
+ }
+# Check operator spacing.
+ if (!($line=~/\#\s*include/)) {
+ my $ops = qr{
+ <<=|>>=|<=|>=|==|!=|
+ \+=|-=|\*=|\/=|%=|\^=|\|=|&=|
+ =>|->|<<|>>|<|>|=|!|~|
+ &&|\|\||,|\^|\+\+|--|&|\||\+|-|\*|\/|%|
+ \?|:
+ }x;
+ my @elements = split(/($ops|;)/, $opline);
+ my $off = 0;
+
+ my $blank = copy_spacing($opline);
+
+ for (my $n = 0; $n < $#elements; $n += 2) {
+ $off += length($elements[$n]);
+
+ # Pick up the preceding and succeeding characters.
+ my $ca = substr($opline, 0, $off);
+ my $cc = '';
+ if (length($opline) >= ($off + length($elements[$n + 1]))) {
+ $cc = substr($opline, $off + length($elements[$n + 1]));
+ }
+ my $cb = "$ca$;$cc";
+
+ my $a = '';
+ $a = 'V' if ($elements[$n] ne '');
+ $a = 'W' if ($elements[$n] =~ /\s$/);
+ $a = 'C' if ($elements[$n] =~ /$;$/);
+ $a = 'B' if ($elements[$n] =~ /(\[|\()$/);
+ $a = 'O' if ($elements[$n] eq '');
+ $a = 'E' if ($ca =~ /^\s*$/);
+
+ my $op = $elements[$n + 1];
+
+ my $c = '';
+ if (defined $elements[$n + 2]) {
+ $c = 'V' if ($elements[$n + 2] ne '');
+ $c = 'W' if ($elements[$n + 2] =~ /^\s/);
+ $c = 'C' if ($elements[$n + 2] =~ /^$;/);
+ $c = 'B' if ($elements[$n + 2] =~ /^(\)|\]|;)/);
+ $c = 'O' if ($elements[$n + 2] eq '');
+ $c = 'E' if ($elements[$n + 2] =~ /^\s*\\$/);
+ } else {
+ $c = 'E';
+ }
+
+ my $ctx = "${a}x${c}";
+
+ my $at = "(ctx:$ctx)";
+
+ my $ptr = substr($blank, 0, $off) . "^";
+ my $hereptr = "$hereline$ptr\n";
+
+ # Pull out the value of this operator.
+ my $op_type = substr($curr_values, $off + 1, 1);
+
+ # Get the full operator variant.
+ my $opv = $op . substr($curr_vars, $off, 1);
+
+ # Ignore operators passed as parameters.
+ if ($op_type ne 'V' &&
+ $ca =~ /\s$/ && $cc =~ /^\s*,/) {
+
+# # Ignore comments
+# } elsif ($op =~ /^$;+$/) {
+
+ # ; should have either the end of line or a space or \ after it
+ } elsif ($op eq ';') {
+ if ($ctx !~ /.x[WEBC]/ &&
+ $cc !~ /^\\/ && $cc !~ /^;/) {
+ ERROR("SPACING",
+ "space required after that '$op' $at\n" . $hereptr);
+ }
+
+ # // is a comment
+ } elsif ($op eq '//') {
+
+ # No spaces for:
+ # ->
+ # : when part of a bitfield
+ } elsif ($op eq '->' || $opv eq ':B') {
+ if ($ctx =~ /Wx.|.xW/) {
+ ERROR("SPACING",
+ "spaces prohibited around that '$op' $at\n" . $hereptr);
+ }
+
+ # , must have a space on the right.
+ } elsif ($op eq ',') {
+ if ($ctx !~ /.x[WEC]/ && $cc !~ /^}/) {
+ ERROR("SPACING",
+ "space required after that '$op' $at\n" . $hereptr);
+ }
+
+ # '*' as part of a type definition -- reported already.
+ } elsif ($opv eq '*_') {
+ #warn "'*' is part of type\n";
+
+ # unary operators should have a space before and
+ # none after. May be left adjacent to another
+ # unary operator, or a cast
+ } elsif ($op eq '!' || $op eq '~' ||
+ $opv eq '*U' || $opv eq '-U' ||
+ $opv eq '&U' || $opv eq '&&U') {
+ if ($ctx !~ /[WEBC]x./ && $ca !~ /(?:\)|!|~|\*|-|\&|\||\+\+|\-\-|\{)$/) {
+ ERROR("SPACING",
+ "space required before that '$op' $at\n" . $hereptr);
+ }
+ if ($op eq '*' && $cc =~/\s*$Modifier\b/) {
+ # A unary '*' may be const
+
+ } elsif ($ctx =~ /.xW/) {
+ ERROR("SPACING",
+ "space prohibited after that '$op' $at\n" . $hereptr);
+ }
+
+ # unary ++ and unary -- are allowed no space on one side.
+ } elsif ($op eq '++' or $op eq '--') {
+ if ($ctx !~ /[WEOBC]x[^W]/ && $ctx !~ /[^W]x[WOBEC]/) {
+ ERROR("SPACING",
+ "space required one side of that '$op' $at\n" . $hereptr);
+ }
+ if ($ctx =~ /Wx[BE]/ ||
+ ($ctx =~ /Wx./ && $cc =~ /^;/)) {
+ ERROR("SPACING",
+ "space prohibited before that '$op' $at\n" . $hereptr);
+ }
+ if ($ctx =~ /ExW/) {
+ ERROR("SPACING",
+ "space prohibited after that '$op' $at\n" . $hereptr);
+ }
+
+
+ # << and >> may either have or not have spaces both sides
+ } elsif ($op eq '<<' or $op eq '>>' or
+ $op eq '&' or $op eq '^' or $op eq '|' or
+ $op eq '+' or $op eq '-' or
+ $op eq '*' or $op eq '/' or
+ $op eq '%')
+ {
+ if ($ctx =~ /Wx[^WCE]|[^WCE]xW/) {
+ ERROR("SPACING",
+ "need consistent spacing around '$op' $at\n" .
+ $hereptr);
+ }
+
+ # A colon needs no spaces before when it is
+ # terminating a case value or a label.
+ } elsif ($opv eq ':C' || $opv eq ':L') {
+ if ($ctx =~ /Wx./) {
+ ERROR("SPACING",
+ "space prohibited before that '$op' $at\n" . $hereptr);
+ }
+
+ # All the others need spaces both sides.
+ } elsif ($ctx !~ /[EWC]x[CWE]/) {
+ my $ok = 0;
+
+ # Ignore email addresses <foo@bar>
+ if (($op eq '<' &&
+ $cc =~ /^\S+\@\S+>/) ||
+ ($op eq '>' &&
+ $ca =~ /<\S+\@\S+$/))
+ {
+ $ok = 1;
+ }
+
+ # Ignore ?:
+ if (($opv eq ':O' && $ca =~ /\?$/) ||
+ ($op eq '?' && $cc =~ /^:/)) {
+ $ok = 1;
+ }
+
+ if ($ok == 0) {
+ ERROR("SPACING",
+ "spaces required around that '$op' $at\n" . $hereptr);
+ }
+ }
+ $off += length($elements[$n + 1]);
+ }
+ }
+
+# check for multiple assignments
+ if ($line =~ /^.\s*$Lval\s*=\s*$Lval\s*=(?!=)/) {
+ CHK("MULTIPLE_ASSIGNMENTS",
+ "multiple assignments should be avoided\n" . $herecurr);
+ }
+
+## # check for multiple declarations, allowing for a function declaration
+## # continuation.
+## if ($line =~ /^.\s*$Type\s+$Ident(?:\s*=[^,{]*)?\s*,\s*$Ident.*/ &&
+## $line !~ /^.\s*$Type\s+$Ident(?:\s*=[^,{]*)?\s*,\s*$Type\s*$Ident.*/) {
+##
+## # Remove any bracketed sections to ensure we do not
+## # falsly report the parameters of functions.
+## my $ln = $line;
+## while ($ln =~ s/\([^\(\)]*\)//g) {
+## }
+## if ($ln =~ /,/) {
+## WARN("MULTIPLE_DECLARATION",
+## "declaring multiple variables together should be avoided\n" . $herecurr);
+## }
+## }
+
+#need space before brace following if, while, etc
+ if (($line =~ /\(.*\){/ && $line !~ /\($Type\){/) ||
+ $line =~ /do{/) {
+ ERROR("SPACING",
+ "space required before the open brace '{'\n" . $herecurr);
+ }
+
+# closing brace should have a space following it when it has anything
+# on the line
+ if ($line =~ /}(?!(?:,|;|\)))\S/) {
+ ERROR("SPACING",
+ "space required after that close brace '}'\n" . $herecurr);
+ }
+
+# check spacing on square brackets
+ if ($line =~ /\[\s/ && $line !~ /\[\s*$/) {
+ ERROR("SPACING",
+ "space prohibited after that open square bracket '['\n" . $herecurr);
+ }
+ if ($line =~ /\s\]/) {
+ ERROR("SPACING",
+ "space prohibited before that close square bracket ']'\n" . $herecurr);
+ }
+
+# check spacing on parentheses
+ if ($line =~ /\(\s/ && $line !~ /\(\s*(?:\\)?$/ &&
+ $line !~ /for\s*\(\s+;/) {
+ ERROR("SPACING",
+ "space prohibited after that open parenthesis '('\n" . $herecurr);
+ }
+ if ($line =~ /(\s+)\)/ && $line !~ /^.\s*\)/ &&
+ $line !~ /for\s*\(.*;\s+\)/ &&
+ $line !~ /:\s+\)/) {
+ ERROR("SPACING",
+ "space prohibited before that close parenthesis ')'\n" . $herecurr);
+ }
+
+#goto labels aren't indented, allow a single space however
+ if ($line=~/^.\s+[A-Za-z\d_]+:(?![0-9]+)/ and
+ !($line=~/^. [A-Za-z\d_]+:/) and !($line=~/^.\s+default:/)) {
+ WARN("INDENTED_LABEL",
+ "labels should not be indented\n" . $herecurr);
+ }
+
+# Return is not a function.
+ if (defined($stat) && $stat =~ /^.\s*return(\s*)(\(.*);/s) {
+ my $spacing = $1;
+ my $value = $2;
+
+ # Flatten any parentheses
+ $value =~ s/\(/ \(/g;
+ $value =~ s/\)/\) /g;
+ while ($value =~ s/\[[^\{\}]*\]/1/ ||
+ $value !~ /(?:$Ident|-?$Constant)\s*
+ $Compare\s*
+ (?:$Ident|-?$Constant)/x &&
+ $value =~ s/\([^\(\)]*\)/1/) {
+ }
+#print "value<$value>\n";
+ if ($value =~ /^\s*(?:$Ident|-?$Constant)\s*$/) {
+ ERROR("RETURN_PARENTHESES",
+ "return is not a function, parentheses are not required\n" . $herecurr);
+
+ } elsif ($spacing !~ /\s+/) {
+ ERROR("SPACING",
+ "space required before the open parenthesis '('\n" . $herecurr);
+ }
+ }
+# Return of what appears to be an errno should normally be -'ve
+ if ($line =~ /^.\s*return\s*(E[A-Z]*)\s*;/) {
+ my $name = $1;
+ if ($name ne 'EOF' && $name ne 'ERROR') {
+ WARN("USE_NEGATIVE_ERRNO",
+ "return of an errno should typically be -ve (return -$1)\n" . $herecurr);
+ }
+ }
+
+# typecasts on min/max could be min_t/max_t
+ if ($line =~ /^\+(?:.*?)\b(min|max)\s*\($Typecast{0,1}($LvalOrFunc)\s*,\s*$Typecast{0,1}($LvalOrFunc)\s*\)/) {
+ if (defined $2 || defined $8) {
+ my $call = $1;
+ my $cast1 = deparenthesize($2);
+ my $arg1 = $3;
+ my $cast2 = deparenthesize($8);
+ my $arg2 = $9;
+ my $cast;
+
+ if ($cast1 ne "" && $cast2 ne "") {
+ $cast = "$cast1 or $cast2";
+ } elsif ($cast1 ne "") {
+ $cast = $cast1;
+ } else {
+ $cast = $cast2;
+ }
+ WARN("MINMAX",
+ "$call() should probably be ${call}_t($cast, $arg1, $arg2)\n" . $herecurr);
+ }
+ }
+
+# Need a space before open parenthesis after if, while etc
+ if ($line=~/\b(if|while|for|switch)\(/) {
+ ERROR("SPACING", "space required before the open parenthesis '('\n" . $herecurr);
+ }
+
+# Check for illegal assignment in if conditional -- and check for trailing
+# statements after the conditional.
+ if ($line =~ /do\s*(?!{)/) {
+ my ($stat_next) = ctx_statement_block($line_nr_next,
+ $remain_next, $off_next);
+ $stat_next =~ s/\n./\n /g;
+ ##print "stat<$stat> stat_next<$stat_next>\n";
+
+ if ($stat_next =~ /^\s*while\b/) {
+ # If the statement carries leading newlines,
+ # then count those as offsets.
+ my ($whitespace) =
+ ($stat_next =~ /^((?:\s*\n[+-])*\s*)/s);
+ my $offset =
+ statement_rawlines($whitespace) - 1;
+
+ $suppress_whiletrailers{$line_nr_next +
+ $offset} = 1;
+ }
+ }
+ if (!defined $suppress_whiletrailers{$linenr} &&
+ $line =~ /\b(?:if|while|for)\s*\(/ && $line !~ /^.\s*#/) {
+ my ($s, $c) = ($stat, $cond);
+
+ if ($c =~ /\bif\s*\(.*[^<>!=]=[^=].*/s) {
+ ERROR("ASSIGN_IN_IF",
+ "do not use assignment in if condition\n" . $herecurr);
+ }
+
+ # Find out what is on the end of the line after the
+ # conditional.
+ substr($s, 0, length($c), '');
+ $s =~ s/\n.*//g;
+ $s =~ s/$;//g; # Remove any comments
+ if (length($c) && $s !~ /^\s*{?\s*\\*\s*$/ &&
+ $c !~ /}\s*while\s*/)
+ {
+ # Find out how long the conditional actually is.
+ my @newlines = ($c =~ /\n/gs);
+ my $cond_lines = 1 + $#newlines;
+ my $stat_real = '';
+
+ $stat_real = raw_line($linenr, $cond_lines)
+ . "\n" if ($cond_lines);
+ if (defined($stat_real) && $cond_lines > 1) {
+ $stat_real = "[...]\n$stat_real";
+ }
+
+ ERROR("TRAILING_STATEMENTS",
+ "trailing statements should be on next line\n" . $herecurr . $stat_real);
+ }
+ }
+
+# Check for bitwise tests written as boolean
+ if ($line =~ /
+ (?:
+ (?:\[|\(|\&\&|\|\|)
+ \s*0[xX][0-9]+\s*
+ (?:\&\&|\|\|)
+ |
+ (?:\&\&|\|\|)
+ \s*0[xX][0-9]+\s*
+ (?:\&\&|\|\||\)|\])
+ )/x)
+ {
+ WARN("HEXADECIMAL_BOOLEAN_TEST",
+ "boolean test with hexadecimal, perhaps just 1 \& or \|?\n" . $herecurr);
+ }
+
+# if and else should not have general statements after it
+ if ($line =~ /^.\s*(?:}\s*)?else\b(.*)/) {
+ my $s = $1;
+ $s =~ s/$;//g; # Remove any comments
+ if ($s !~ /^\s*(?:\sif|(?:{|)\s*\\?\s*$)/) {
+ ERROR("TRAILING_STATEMENTS",
+ "trailing statements should be on next line\n" . $herecurr);
+ }
+ }
+# if should not continue a brace
+ if ($line =~ /}\s*if\b/) {
+ ERROR("TRAILING_STATEMENTS",
+ "trailing statements should be on next line\n" .
+ $herecurr);
+ }
+# case and default should not have general statements after them
+ if ($line =~ /^.\s*(?:case\s*.*|default\s*):/g &&
+ $line !~ /\G(?:
+ (?:\s*$;*)(?:\s*{)?(?:\s*$;*)(?:\s*\\)?\s*$|
+ \s*return\s+
+ )/xg)
+ {
+ ERROR("TRAILING_STATEMENTS",
+ "trailing statements should be on next line\n" . $herecurr);
+ }
+
+ # Check for }<nl>else {, these must be at the same
+ # indent level to be relevant to each other.
+ if ($prevline=~/}\s*$/ and $line=~/^.\s*else\s*/ and
+ $previndent == $indent) {
+ ERROR("ELSE_AFTER_BRACE",
+ "else should follow close brace '}'\n" . $hereprev);
+ }
+
+ if ($prevline=~/}\s*$/ and $line=~/^.\s*while\s*/ and
+ $previndent == $indent) {
+ my ($s, $c) = ctx_statement_block($linenr, $realcnt, 0);
+
+ # Find out what is on the end of the line after the
+ # conditional.
+ substr($s, 0, length($c), '');
+ $s =~ s/\n.*//g;
+
+ if ($s =~ /^\s*;/) {
+ ERROR("WHILE_AFTER_BRACE",
+ "while should follow close brace '}'\n" . $hereprev);
+ }
+ }
+
+#studly caps, commented out until figure out how to distinguish between use of existing and adding new
+# if (($line=~/[\w_][a-z\d]+[A-Z]/) and !($line=~/print/)) {
+# print "No studly caps, use _\n";
+# print "$herecurr";
+# $clean = 0;
+# }
+
+#no spaces allowed after \ in define
+ if ($line=~/\#\s*define.*\\\s$/) {
+ WARN("WHITESPACE_AFTER_LINE_CONTINUATION",
+ "Whitepspace after \\ makes next lines useless\n" . $herecurr);
+ }
+
+#warn if <asm/foo.h> is #included and <linux/foo.h> is available (uses RAW line)
+ if ($tree && $rawline =~ m{^.\s*\#\s*include\s*\<asm\/(.*)\.h\>}) {
+ my $file = "$1.h";
+ my $checkfile = "include/linux/$file";
+ if (-f "$root/$checkfile" &&
+ $realfile ne $checkfile &&
+ $1 !~ /$allowed_asm_includes/)
+ {
+ if ($realfile =~ m{^arch/}) {
+ CHK("ARCH_INCLUDE_LINUX",
+ "Consider using #include <linux/$file> instead of <asm/$file>\n" . $herecurr);
+ } else {
+ WARN("INCLUDE_LINUX",
+ "Use #include <linux/$file> instead of <asm/$file>\n" . $herecurr);
+ }
+ }
+ }
+
+# multi-statement macros should be enclosed in a do while loop, grab the
+# first statement and ensure its the whole macro if its not enclosed
+# in a known good container
+ if ($realfile !~ m@/vmlinux.lds.h$@ &&
+ $line =~ /^.\s*\#\s*define\s*$Ident(\()?/) {
+ my $ln = $linenr;
+ my $cnt = $realcnt;
+ my ($off, $dstat, $dcond, $rest);
+ my $ctx = '';
+
+ my $args = defined($1);
+
+ # Find the end of the macro and limit our statement
+ # search to that.
+ while ($cnt > 0 && defined $lines[$ln - 1] &&
+ $lines[$ln - 1] =~ /^(?:-|..*\\$)/)
+ {
+ $ctx .= $rawlines[$ln - 1] . "\n";
+ $cnt-- if ($lines[$ln - 1] !~ /^-/);
+ $ln++;
+ }
+ $ctx .= $rawlines[$ln - 1];
+
+ ($dstat, $dcond, $ln, $cnt, $off) =
+ ctx_statement_block($linenr, $ln - $linenr + 1, 0);
+ #print "dstat<$dstat> dcond<$dcond> cnt<$cnt> off<$off>\n";
+ #print "LINE<$lines[$ln-1]> len<" . length($lines[$ln-1]) . "\n";
+
+ # Extract the remainder of the define (if any) and
+ # rip off surrounding spaces, and trailing \'s.
+ $rest = '';
+ while ($off != 0 || ($cnt > 0 && $rest =~ /\\\s*$/)) {
+ #print "ADDING cnt<$cnt> $off <" . substr($lines[$ln - 1], $off) . "> rest<$rest>\n";
+ if ($off != 0 || $lines[$ln - 1] !~ /^-/) {
+ $rest .= substr($lines[$ln - 1], $off) . "\n";
+ $cnt--;
+ }
+ $ln++;
+ $off = 0;
+ }
+ $rest =~ s/\\\n.//g;
+ $rest =~ s/^\s*//s;
+ $rest =~ s/\s*$//s;
+
+ # Clean up the original statement.
+ if ($args) {
+ substr($dstat, 0, length($dcond), '');
+ } else {
+ $dstat =~ s/^.\s*\#\s*define\s+$Ident\s*//;
+ }
+ $dstat =~ s/$;//g;
+ $dstat =~ s/\\\n.//g;
+ $dstat =~ s/^\s*//s;
+ $dstat =~ s/\s*$//s;
+
+ # Flatten any parentheses and braces
+ while ($dstat =~ s/\([^\(\)]*\)/1/ ||
+ $dstat =~ s/\{[^\{\}]*\}/1/ ||
+ $dstat =~ s/\[[^\{\}]*\]/1/)
+ {
+ }
+
+ my $exceptions = qr{
+ $Declare|
+ module_param_named|
+ MODULE_PARAM_DESC|
+ DECLARE_PER_CPU|
+ DEFINE_PER_CPU|
+ __typeof__\(|
+ union|
+ struct|
+ \.$Ident\s*=\s*|
+ ^\"|\"$
+ }x;
+ #print "REST<$rest> dstat<$dstat> ctx<$ctx>\n";
+ if ($rest ne '' && $rest ne ',') {
+ if ($rest !~ /while\s*\(/ &&
+ $dstat !~ /$exceptions/)
+ {
+ ERROR("MULTISTATEMENT_MACRO_USE_DO_WHILE",
+ "Macros with multiple statements should be enclosed in a do - while loop\n" . "$here\n$ctx\n");
+ }
+
+ } elsif ($ctx !~ /;/) {
+ if ($dstat ne '' &&
+ $dstat !~ /^(?:$Ident|-?$Constant)$/ &&
+ $dstat !~ /$exceptions/ &&
+ $dstat !~ /^\.$Ident\s*=/ &&
+ $dstat =~ /$Operators/)
+ {
+ ERROR("COMPLEX_MACRO",
+ "Macros with complex values should be enclosed in parenthesis\n" . "$here\n$ctx\n");
+ }
+ }
+ }
+
+# make sure symbols are always wrapped with VMLINUX_SYMBOL() ...
+# all assignments may have only one of the following with an assignment:
+# .
+# ALIGN(...)
+# VMLINUX_SYMBOL(...)
+ if ($realfile eq 'vmlinux.lds.h' && $line =~ /(?:(?:^|\s)$Ident\s*=|=\s*$Ident(?:\s|$))/) {
+ WARN("MISSING_VMLINUX_SYMBOL",
+ "vmlinux.lds.h needs VMLINUX_SYMBOL() around C-visible symbols\n" . $herecurr);
+ }
+
+# check for redundant bracing round if etc
+ if ($line =~ /(^.*)\bif\b/ && $1 !~ /else\s*$/) {
+ my ($level, $endln, @chunks) =
+ ctx_statement_full($linenr, $realcnt, 1);
+ #print "chunks<$#chunks> linenr<$linenr> endln<$endln> level<$level>\n";
+ #print "APW: <<$chunks[1][0]>><<$chunks[1][1]>>\n";
+ if ($#chunks > 0 && $level == 0) {
+ my $allowed = 0;
+ my $seen = 0;
+ my $herectx = $here . "\n";
+ my $ln = $linenr - 1;
+ for my $chunk (@chunks) {
+ my ($cond, $block) = @{$chunk};
+
+ # If the condition carries leading newlines, then count those as offsets.
+ my ($whitespace) = ($cond =~ /^((?:\s*\n[+-])*\s*)/s);
+ my $offset = statement_rawlines($whitespace) - 1;
+
+ #print "COND<$cond> whitespace<$whitespace> offset<$offset>\n";
+
+ # We have looked at and allowed this specific line.
+ $suppress_ifbraces{$ln + $offset} = 1;
+
+ $herectx .= "$rawlines[$ln + $offset]\n[...]\n";
+ $ln += statement_rawlines($block) - 1;
+
+ substr($block, 0, length($cond), '');
+
+ $seen++ if ($block =~ /^\s*{/);
+
+ #print "cond<$cond> block<$block> allowed<$allowed>\n";
+ if (statement_lines($cond) > 1) {
+ #print "APW: ALLOWED: cond<$cond>\n";
+ $allowed = 1;
+ }
+ if ($block =~/\b(?:if|for|while)\b/) {
+ #print "APW: ALLOWED: block<$block>\n";
+ $allowed = 1;
+ }
+ if (statement_block_size($block) > 1) {
+ #print "APW: ALLOWED: lines block<$block>\n";
+ $allowed = 1;
+ }
+ }
+ if ($seen && !$allowed) {
+ WARN("BRACES",
+ "braces {} are not necessary for any arm of this statement\n" . $herectx);
+ }
+ }
+ }
+ if (!defined $suppress_ifbraces{$linenr - 1} &&
+ $line =~ /\b(if|while|for|else)\b/) {
+ my $allowed = 0;
+
+ # Check the pre-context.
+ if (substr($line, 0, $-[0]) =~ /(\}\s*)$/) {
+ #print "APW: ALLOWED: pre<$1>\n";
+ $allowed = 1;
+ }
+
+ my ($level, $endln, @chunks) =
+ ctx_statement_full($linenr, $realcnt, $-[0]);
+
+ # Check the condition.
+ my ($cond, $block) = @{$chunks[0]};
+ #print "CHECKING<$linenr> cond<$cond> block<$block>\n";
+ if (defined $cond) {
+ substr($block, 0, length($cond), '');
+ }
+ if (statement_lines($cond) > 1) {
+ #print "APW: ALLOWED: cond<$cond>\n";
+ $allowed = 1;
+ }
+ if ($block =~/\b(?:if|for|while)\b/) {
+ #print "APW: ALLOWED: block<$block>\n";
+ $allowed = 1;
+ }
+ if (statement_block_size($block) > 1) {
+ #print "APW: ALLOWED: lines block<$block>\n";
+ $allowed = 1;
+ }
+ # Check the post-context.
+ if (defined $chunks[1]) {
+ my ($cond, $block) = @{$chunks[1]};
+ if (defined $cond) {
+ substr($block, 0, length($cond), '');
+ }
+ if ($block =~ /^\s*\{/) {
+ #print "APW: ALLOWED: chunk-1 block<$block>\n";
+ $allowed = 1;
+ }
+ }
+ if ($level == 0 && $block =~ /^\s*\{/ && !$allowed) {
+ my $herectx = $here . "\n";;
+ my $cnt = statement_rawlines($block);
+
+ for (my $n = 0; $n < $cnt; $n++) {
+ $herectx .= raw_line($linenr, $n) . "\n";;
+ }
+
+ WARN("BRACES",
+ "braces {} are not necessary for single statement blocks\n" . $herectx);
+ }
+ }
+
+# don't include deprecated include files (uses RAW line)
+ for my $inc (@dep_includes) {
+ if ($rawline =~ m@^.\s*\#\s*include\s*\<$inc>@) {
+ ERROR("DEPRECATED_INCLUDE",
+ "Don't use <$inc>: see Documentation/feature-removal-schedule.txt\n" . $herecurr);
+ }
+ }
+
+# don't use deprecated functions
+ for my $func (@dep_functions) {
+ if ($line =~ /\b$func\b/) {
+ ERROR("DEPRECATED_FUNCTION",
+ "Don't use $func(): see Documentation/feature-removal-schedule.txt\n" . $herecurr);
+ }
+ }
+
+# no volatiles please
+ my $asm_volatile = qr{\b(__asm__|asm)\s+(__volatile__|volatile)\b};
+ if ($line =~ /\bvolatile\b/ && $line !~ /$asm_volatile/) {
+ WARN("VOLATILE",
+ "Use of volatile is usually wrong: see Documentation/volatile-considered-harmful.txt\n" . $herecurr);
+ }
+
+# warn about #if 0
+ if ($line =~ /^.\s*\#\s*if\s+0\b/) {
+ CHK("REDUNDANT_CODE",
+ "if this code is redundant consider removing it\n" .
+ $herecurr);
+ }
+
+# check for needless kfree() checks
+ if ($prevline =~ /\bif\s*\(([^\)]*)\)/) {
+ my $expr = $1;
+ if ($line =~ /\bkfree\(\Q$expr\E\);/) {
+ WARN("NEEDLESS_KFREE",
+ "kfree(NULL) is safe this check is probably not required\n" . $hereprev);
+ }
+ }
+# check for needless usb_free_urb() checks
+ if ($prevline =~ /\bif\s*\(([^\)]*)\)/) {
+ my $expr = $1;
+ if ($line =~ /\busb_free_urb\(\Q$expr\E\);/) {
+ WARN("NEEDLESS_USB_FREE_URB",
+ "usb_free_urb(NULL) is safe this check is probably not required\n" . $hereprev);
+ }
+ }
+
+# prefer usleep_range over udelay
+ if ($line =~ /\budelay\s*\(\s*(\w+)\s*\)/) {
+ # ignore udelay's < 10, however
+ if (! (($1 =~ /(\d+)/) && ($1 < 10)) ) {
+ CHK("USLEEP_RANGE",
+ "usleep_range is preferred over udelay; see Documentation/timers/timers-howto.txt\n" . $line);
+ }
+ }
+
+# warn about unexpectedly long msleep's
+ if ($line =~ /\bmsleep\s*\((\d+)\);/) {
+ if ($1 < 20) {
+ WARN("MSLEEP",
+ "msleep < 20ms can sleep for up to 20ms; see Documentation/timers/timers-howto.txt\n" . $line);
+ }
+ }
+
+# warn about #ifdefs in C files
+# if ($line =~ /^.\s*\#\s*if(|n)def/ && ($realfile =~ /\.c$/)) {
+# print "#ifdef in C files should be avoided\n";
+# print "$herecurr";
+# $clean = 0;
+# }
+
+# warn about spacing in #ifdefs
+ if ($line =~ /^.\s*\#\s*(ifdef|ifndef|elif)\s\s+/) {
+ ERROR("SPACING",
+ "exactly one space required after that #$1\n" . $herecurr);
+ }
+
+# check for spinlock_t definitions without a comment.
+ if ($line =~ /^.\s*(struct\s+mutex|spinlock_t)\s+\S+;/ ||
+ $line =~ /^.\s*(DEFINE_MUTEX)\s*\(/) {
+ my $which = $1;
+ if (!ctx_has_comment($first_line, $linenr)) {
+ CHK("UNCOMMENTED_DEFINITION",
+ "$1 definition without comment\n" . $herecurr);
+ }
+ }
+# check for memory barriers without a comment.
+ if ($line =~ /\b(mb|rmb|wmb|read_barrier_depends|smp_mb|smp_rmb|smp_wmb|smp_read_barrier_depends)\(/) {
+ if (!ctx_has_comment($first_line, $linenr)) {
+ CHK("MEMORY_BARRIER",
+ "memory barrier without comment\n" . $herecurr);
+ }
+ }
+# check of hardware specific defines
+ if ($line =~ m@^.\s*\#\s*if.*\b(__i386__|__powerpc64__|__sun__|__s390x__)\b@ && $realfile !~ m@include/asm-@) {
+ CHK("ARCH_DEFINES",
+ "architecture specific defines should be avoided\n" . $herecurr);
+ }
+
+# Check that the storage class is at the beginning of a declaration
+ if ($line =~ /\b$Storage\b/ && $line !~ /^.\s*$Storage\b/) {
+ WARN("STORAGE_CLASS",
+ "storage class should be at the beginning of the declaration\n" . $herecurr)
+ }
+
+# check the location of the inline attribute, that it is between
+# storage class and type.
+ if ($line =~ /\b$Type\s+$Inline\b/ ||
+ $line =~ /\b$Inline\s+$Storage\b/) {
+ ERROR("INLINE_LOCATION",
+ "inline keyword should sit between storage class and type\n" . $herecurr);
+ }
+
+# Check for __inline__ and __inline, prefer inline
+ if ($line =~ /\b(__inline__|__inline)\b/) {
+ WARN("INLINE",
+ "plain inline is preferred over $1\n" . $herecurr);
+ }
+
+# Check for __attribute__ packed, prefer __packed
+ if ($line =~ /\b__attribute__\s*\(\s*\(.*\bpacked\b/) {
+ WARN("PREFER_PACKED",
+ "__packed is preferred over __attribute__((packed))\n" . $herecurr);
+ }
+
+# Check for __attribute__ aligned, prefer __aligned
+ if ($line =~ /\b__attribute__\s*\(\s*\(.*aligned/) {
+ WARN("PREFER_ALIGNED",
+ "__aligned(size) is preferred over __attribute__((aligned(size)))\n" . $herecurr);
+ }
+
+# check for sizeof(&)
+ if ($line =~ /\bsizeof\s*\(\s*\&/) {
+ WARN("SIZEOF_ADDRESS",
+ "sizeof(& should be avoided\n" . $herecurr);
+ }
+
+# check for line continuations in quoted strings with odd counts of "
+ if ($rawline =~ /\\$/ && $rawline =~ tr/"/"/ % 2) {
+ WARN("LINE_CONTINUATIONS",
+ "Avoid line continuations in quoted strings\n" . $herecurr);
+ }
+
+# check for new externs in .c files.
+ if ($realfile =~ /\.c$/ && defined $stat &&
+ $stat =~ /^.\s*(?:extern\s+)?$Type\s+($Ident)(\s*)\(/s)
+ {
+ my $function_name = $1;
+ my $paren_space = $2;
+
+ my $s = $stat;
+ if (defined $cond) {
+ substr($s, 0, length($cond), '');
+ }
+ if ($s =~ /^\s*;/ &&
+ $function_name ne 'uninitialized_var')
+ {
+ WARN("AVOID_EXTERNS",
+ "externs should be avoided in .c files\n" . $herecurr);
+ }
+
+ if ($paren_space =~ /\n/) {
+ WARN("FUNCTION_ARGUMENTS",
+ "arguments for function declarations should follow identifier\n" . $herecurr);
+ }
+
+ } elsif ($realfile =~ /\.c$/ && defined $stat &&
+ $stat =~ /^.\s*extern\s+/)
+ {
+ WARN("AVOID_EXTERNS",
+ "externs should be avoided in .c files\n" . $herecurr);
+ }
+
+# checks for new __setup's
+ if ($rawline =~ /\b__setup\("([^"]*)"/) {
+ my $name = $1;
+
+ if (!grep(/$name/, @setup_docs)) {
+ CHK("UNDOCUMENTED_SETUP",
+ "__setup appears un-documented -- check Documentation/kernel-parameters.txt\n" . $herecurr);
+ }
+ }
+
+# check for pointless casting of kmalloc return
+ if ($line =~ /\*\s*\)\s*[kv][czm]alloc(_node){0,1}\b/) {
+ WARN("UNNECESSARY_CASTS",
+ "unnecessary cast may hide bugs, see http://c-faq.com/malloc/mallocnocast.html\n" . $herecurr);
+ }
+
+# check for multiple semicolons
+ if ($line =~ /;\s*;\s*$/) {
+ WARN("ONE_SEMICOLON",
+ "Statements terminations use 1 semicolon\n" . $herecurr);
+ }
+
+# check for gcc specific __FUNCTION__
+ if ($line =~ /__FUNCTION__/) {
+ WARN("USE_FUNC",
+ "__func__ should be used instead of gcc specific __FUNCTION__\n" . $herecurr);
+ }
+
+# check for semaphores initialized locked
+ if ($line =~ /^.\s*sema_init.+,\W?0\W?\)/) {
+ WARN("CONSIDER_COMPLETION",
+ "consider using a completion\n" . $herecurr);
+
+ }
+# recommend kstrto* over simple_strto*
+ if ($line =~ /\bsimple_(strto.*?)\s*\(/) {
+ WARN("CONSIDER_KSTRTO",
+ "consider using kstrto* in preference to simple_$1\n" . $herecurr);
+ }
+# check for __initcall(), use device_initcall() explicitly please
+ if ($line =~ /^.\s*__initcall\s*\(/) {
+ WARN("USE_DEVICE_INITCALL",
+ "please use device_initcall() instead of __initcall()\n" . $herecurr);
+ }
+# check for various ops structs, ensure they are const.
+ my $struct_ops = qr{acpi_dock_ops|
+ address_space_operations|
+ backlight_ops|
+ block_device_operations|
+ dentry_operations|
+ dev_pm_ops|
+ dma_map_ops|
+ extent_io_ops|
+ file_lock_operations|
+ file_operations|
+ hv_ops|
+ ide_dma_ops|
+ intel_dvo_dev_ops|
+ item_operations|
+ iwl_ops|
+ kgdb_arch|
+ kgdb_io|
+ kset_uevent_ops|
+ lock_manager_operations|
+ microcode_ops|
+ mtrr_ops|
+ neigh_ops|
+ nlmsvc_binding|
+ pci_raw_ops|
+ pipe_buf_operations|
+ platform_hibernation_ops|
+ platform_suspend_ops|
+ proto_ops|
+ rpc_pipe_ops|
+ seq_operations|
+ snd_ac97_build_ops|
+ soc_pcmcia_socket_ops|
+ stacktrace_ops|
+ sysfs_ops|
+ tty_operations|
+ usb_mon_operations|
+ wd_ops}x;
+ if ($line !~ /\bconst\b/ &&
+ $line =~ /\bstruct\s+($struct_ops)\b/) {
+ WARN("CONST_STRUCT",
+ "struct $1 should normally be const\n" .
+ $herecurr);
+ }
+
+# use of NR_CPUS is usually wrong
+# ignore definitions of NR_CPUS and usage to define arrays as likely right
+ if ($line =~ /\bNR_CPUS\b/ &&
+ $line !~ /^.\s*\s*#\s*if\b.*\bNR_CPUS\b/ &&
+ $line !~ /^.\s*\s*#\s*define\b.*\bNR_CPUS\b/ &&
+ $line !~ /^.\s*$Declare\s.*\[[^\]]*NR_CPUS[^\]]*\]/ &&
+ $line !~ /\[[^\]]*\.\.\.[^\]]*NR_CPUS[^\]]*\]/ &&
+ $line !~ /\[[^\]]*NR_CPUS[^\]]*\.\.\.[^\]]*\]/)
+ {
+ WARN("NR_CPUS",
+ "usage of NR_CPUS is often wrong - consider using cpu_possible(), num_possible_cpus(), for_each_possible_cpu(), etc\n" . $herecurr);
+ }
+
+# check for %L{u,d,i} in strings
+ my $string;
+ while ($line =~ /(?:^|")([X\t]*)(?:"|$)/g) {
+ $string = substr($rawline, $-[1], $+[1] - $-[1]);
+ $string =~ s/%%/__/g;
+ if ($string =~ /(?<!%)%L[udi]/) {
+ WARN("PRINTF_L",
+ "\%Ld/%Lu are not-standard C, use %lld/%llu\n" . $herecurr);
+ last;
+ }
+ }
+
+# whine mightly about in_atomic
+ if ($line =~ /\bin_atomic\s*\(/) {
+ if ($realfile =~ m@^drivers/@) {
+ ERROR("IN_ATOMIC",
+ "do not use in_atomic in drivers\n" . $herecurr);
+ } elsif ($realfile !~ m@^kernel/@) {
+ WARN("IN_ATOMIC",
+ "use of in_atomic() is incorrect outside core kernel code\n" . $herecurr);
+ }
+ }
+
+# check for lockdep_set_novalidate_class
+ if ($line =~ /^.\s*lockdep_set_novalidate_class\s*\(/ ||
+ $line =~ /__lockdep_no_validate__\s*\)/ ) {
+ if ($realfile !~ m@^kernel/lockdep@ &&
+ $realfile !~ m@^include/linux/lockdep@ &&
+ $realfile !~ m@^drivers/base/core@) {
+ ERROR("LOCKDEP",
+ "lockdep_no_validate class is reserved for device->mutex.\n" . $herecurr);
+ }
+ }
+
+ if ($line =~ /debugfs_create_file.*S_IWUGO/ ||
+ $line =~ /DEVICE_ATTR.*S_IWUGO/ ) {
+ WARN("EXPORTED_WORLD_WRITABLE",
+ "Exporting world writable files is usually an error. Consider more restrictive permissions.\n" . $herecurr);
+ }
+
+ # Check for memset with swapped arguments
+ if ($line =~ /memset.*\,(\ |)(0x|)0(\ |0|)\);/) {
+ ERROR("MEMSET",
+ "memset size is 3rd argument, not the second.\n" . $herecurr);
+ }
+ }
+
+ # If we have no input at all, then there is nothing to report on
+ # so just keep quiet.
+ if ($#rawlines == -1) {
+ exit(0);
+ }
+
+ # In mailback mode only produce a report in the negative, for
+ # things that appear to be patches.
+ if ($mailback && ($clean == 1 || !$is_patch)) {
+ exit(0);
+ }
+
+ # This is not a patch, and we are are in 'no-patch' mode so
+ # just keep quiet.
+ if (!$chk_patch && !$is_patch) {
+ exit(0);
+ }
+
+ if (!$is_patch) {
+ ERROR("NOT_UNIFIED_DIFF",
+ "Does not appear to be a unified-diff format patch\n");
+ }
+ if ($is_patch && $chk_signoff && $signoff == 0) {
+ ERROR("MISSING_SIGN_OFF",
+ "Missing Signed-off-by: line(s)\n");
+ }
+
+ print report_dump();
+ if ($summary && !($clean == 1 && $quiet == 1)) {
+ print "$filename " if ($summary_file);
+ print "total: $cnt_error errors, $cnt_warn warnings, " .
+ (($check)? "$cnt_chk checks, " : "") .
+ "$cnt_lines lines checked\n";
+ print "\n" if ($quiet == 0);
+ }
+
+ if ($quiet == 0) {
+ # If there were whitespace errors which cleanpatch can fix
+ # then suggest that.
+ if ($rpt_cleaners) {
+ print "NOTE: whitespace errors detected, you may wish to use scripts/cleanpatch or\n";
+ print " scripts/cleanfile\n\n";
+ $rpt_cleaners = 0;
+ }
+ }
+
+ if (keys %ignore_type) {
+ print "NOTE: Ignored message types:";
+ foreach my $ignore (sort keys %ignore_type) {
+ print " $ignore";
+ }
+ print "\n";
+ print "\n" if ($quiet == 0);
+ }
+
+ if ($clean == 1 && $quiet == 0) {
+ print "$vname has no obvious style problems and is ready for submission.\n"
+ }
+ if ($clean == 0 && $quiet == 0) {
+ print << "EOM";
+$vname has style problems, please review.
+
+If any of these errors are false positives, please report
+them to the maintainer, see CHECKPATCH in MAINTAINERS.
+EOM
+ }
+
+ return $clean;
+}
diff --git a/tools/env/Makefile b/tools/env/Makefile
index 2f7a59c..28b73da 100644
--- a/tools/env/Makefile
+++ b/tools/env/Makefile
@@ -23,7 +23,7 @@
include $(TOPDIR)/config.mk
-HOSTSRCS := $(obj)crc32.c fw_env.c fw_env_main.c
+HOSTSRCS := $(SRCTREE)/lib/crc32.c fw_env.c fw_env_main.c
HEADERS := fw_env.h
# Compile for a hosted environment on the target
@@ -43,10 +43,7 @@
$(HOSTCC) $(HOSTCFLAGS_NOPED) $(HOSTLDFLAGS) -o $@ $(HOSTSRCS)
clean:
- rm -f $(obj)fw_printenv $(obj)crc32.c
-
-$(obj)crc32.c:
- ln -s $(src)../../lib/crc32.c $(obj)crc32.c
+ rm -f $(obj)fw_printenv
#########################################################################
diff --git a/tools/envcrc.c b/tools/envcrc.c
index feebbab..111d9f6 100644
--- a/tools/envcrc.c
+++ b/tools/envcrc.c
@@ -61,6 +61,7 @@
#endif /* CONFIG_ENV_IS_IN_FLASH */
#if defined(ENV_IS_EMBEDDED) && !defined(CONFIG_BUILD_ENVCRC)
+# include <environment.h>
# define CONFIG_BUILD_ENVCRC 1
#endif
@@ -77,7 +78,7 @@
#ifdef CONFIG_BUILD_ENVCRC
extern unsigned int env_size;
-extern unsigned char environment;
+extern env_t environment;
#endif /* CONFIG_BUILD_ENVCRC */
int main (int argc, char **argv)
@@ -85,7 +86,7 @@
#ifdef CONFIG_BUILD_ENVCRC
unsigned char pad = 0x00;
uint32_t crc;
- unsigned char *envptr = &environment,
+ unsigned char *envptr = (unsigned char *)&environment,
*dataptr = envptr + ENV_HEADER_SIZE;
unsigned int datasize = ENV_SIZE;
unsigned int eoe;
diff --git a/tools/mkenvimage.c b/tools/mkenvimage.c
new file mode 100644
index 0000000..9c32f4a
--- /dev/null
+++ b/tools/mkenvimage.c
@@ -0,0 +1,270 @@
+/*
+ * (C) Copyright 2011 Free Electrons
+ * David Wagner <david.wagner@free-electrons.com>
+ *
+ * Inspired from envcrc.c:
+ * (C) Copyright 2001
+ * Paolo Scaffardi, AIRVENT SAM s.p.a - RIMINI(ITALY), arsenio@tin.it
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <errno.h>
+#include <fcntl.h>
+#include <stdio.h>
+#include <stdint.h>
+#include <string.h>
+#include <unistd.h>
+#include <compiler.h>
+#include <sys/types.h>
+#include <sys/stat.h>
+
+#include <u-boot/crc.h>
+
+#define CRC_SIZE sizeof(uint32_t)
+
+static void usage(const char *exec_name)
+{
+ fprintf(stderr, "%s [-h] [-r] [-b] [-p <byte>] "
+ "-s <environment partition size> -o <output> <input file>\n"
+ "\n"
+ "This tool takes a key=value input file (same as would a "
+ "`printenv' show) and generates the corresponding environment "
+ "image, ready to be flashed.\n"
+ "\n"
+ "\tThe input file is in format:\n"
+ "\t\tkey1=value1\n"
+ "\t\tkey2=value2\n"
+ "\t\t...\n"
+ "\t-r : the environment has multiple copies in flash\n"
+ "\t-b : the target is big endian (default is little endian)\n"
+ "\t-p <byte> : fill the image with <byte> bytes instead of "
+ "0xff bytes\n"
+ "\n"
+ "If the input file is \"-\", data is read from standard input\n",
+ exec_name);
+}
+
+int main(int argc, char **argv)
+{
+ uint32_t crc, targetendian_crc;
+ const char *txt_filename = NULL, *bin_filename = NULL;
+ int txt_fd, bin_fd;
+ unsigned char *dataptr, *envptr;
+ unsigned char *filebuf = NULL;
+ unsigned int filesize = 0, envsize = 0, datasize = 0;
+ int bigendian = 0;
+ int redundant = 0;
+ unsigned char padbyte = 0xff;
+
+ int option;
+ int ret = EXIT_SUCCESS;
+
+ struct stat txt_file_stat;
+
+ int fp, ep;
+
+ /* Parse the cmdline */
+ while ((option = getopt(argc, argv, "s:o:rbp:h")) != -1) {
+ switch (option) {
+ case 's':
+ datasize = strtol(optarg, NULL, 0);
+ break;
+ case 'o':
+ bin_filename = strdup(optarg);
+ if (!bin_filename) {
+ fprintf(stderr, "Can't strdup() the output "
+ "filename\n");
+ return EXIT_FAILURE;
+ }
+ break;
+ case 'r':
+ redundant = 1;
+ break;
+ case 'b':
+ bigendian = 1;
+ break;
+ case 'p':
+ padbyte = strtol(optarg, NULL, 0);
+ break;
+ case 'h':
+ usage(argv[0]);
+ return EXIT_SUCCESS;
+ default:
+ fprintf(stderr, "Wrong option -%c\n", option);
+ usage(argv[0]);
+ return EXIT_FAILURE;
+ }
+ }
+
+ /* Check datasize and allocate the data */
+ if (datasize == 0) {
+ fprintf(stderr,
+ "Please specify the size of the envrionnment "
+ "partition.\n");
+ usage(argv[0]);
+ return EXIT_FAILURE;
+ }
+
+ dataptr = malloc(datasize * sizeof(*dataptr));
+ if (!dataptr) {
+ fprintf(stderr, "Can't alloc dataptr.\n");
+ return EXIT_FAILURE;
+ }
+
+ /*
+ * envptr points to the beginning of the actual environment (after the
+ * crc and possible `redundant' bit
+ */
+ envsize = datasize - (CRC_SIZE + redundant);
+ envptr = dataptr + CRC_SIZE + redundant;
+
+ /* Pad the environment with the padding byte */
+ memset(envptr, padbyte, envsize);
+
+ /* Open the input file ... */
+ if (optind >= argc) {
+ fprintf(stderr, "Please specify an input filename\n");
+ return EXIT_FAILURE;
+ }
+
+ txt_filename = argv[optind];
+ if (strcmp(txt_filename, "-") == 0) {
+ int readbytes = 0;
+ int readlen = sizeof(*envptr) * 2048;
+ txt_fd = STDIN_FILENO;
+
+ do {
+ filebuf = realloc(filebuf, readlen);
+ readbytes = read(txt_fd, filebuf + filesize, readlen);
+ filesize += readbytes;
+ } while (readbytes == readlen);
+
+ } else {
+ txt_fd = open(txt_filename, O_RDONLY);
+ if (txt_fd == -1) {
+ fprintf(stderr, "Can't open \"%s\": %s\n",
+ txt_filename, strerror(errno));
+ return EXIT_FAILURE;
+ }
+ /* ... and check it */
+ ret = fstat(txt_fd, &txt_file_stat);
+ if (ret == -1) {
+ fprintf(stderr, "Can't stat() on \"%s\": "
+ "%s\n", txt_filename, strerror(errno));
+ return EXIT_FAILURE;
+ }
+
+ filesize = txt_file_stat.st_size;
+ /* Read the raw input file and transform it */
+ filebuf = malloc(sizeof(*envptr) * filesize);
+ ret = read(txt_fd, filebuf, sizeof(*envptr) * filesize);
+ if (ret != sizeof(*envptr) * filesize) {
+ fprintf(stderr, "Can't read the whole input file\n");
+ return EXIT_FAILURE;
+ }
+ ret = close(txt_fd);
+ }
+ /*
+ * The right test to do is "=>" (not ">") because of the additionnal
+ * ending \0. See below.
+ */
+ if (filesize >= envsize) {
+ fprintf(stderr, "The input file is larger than the "
+ "envrionnment partition size\n");
+ return EXIT_FAILURE;
+ }
+
+ /* Replace newlines separating variables with \0 */
+ for (fp = 0, ep = 0 ; fp < filesize ; fp++) {
+ if (filebuf[fp] == '\n') {
+ if (fp == 0) {
+ /*
+ * Newline at the beggining of the file ?
+ * Ignore it.
+ */
+ continue;
+ } else if (filebuf[fp-1] == '\\') {
+ /*
+ * Embedded newline in a variable.
+ *
+ * The backslash was added to the envptr ;
+ * rewind and replace it with a newline
+ */
+ ep--;
+ envptr[ep++] = '\n';
+ } else {
+ /* End of a variable */
+ envptr[ep++] = '\0';
+ }
+ } else if (filebuf[fp] == '#') {
+ if (fp != 0 && filebuf[fp-1] == '\n') {
+ /* This line is a comment, let's skip it */
+ while (fp < txt_file_stat.st_size && fp++ &&
+ filebuf[fp] != '\n');
+ } else {
+ envptr[ep++] = filebuf[fp];
+ }
+ } else {
+ envptr[ep++] = filebuf[fp];
+ }
+ }
+ /*
+ * Make sure there is a final '\0'
+ * And do it again on the next byte to mark the end of the environment.
+ */
+ if (envptr[ep-1] != '\0') {
+ envptr[ep++] = '\0';
+ /*
+ * The text file doesn't have an ending newline. We need to
+ * check the env size again to make sure we have room for two \0
+ */
+ if (ep >= envsize) {
+ fprintf(stderr, "The environment file is too large for "
+ "the target environment storage\n");
+ return EXIT_FAILURE;
+ }
+ envptr[ep] = '\0';
+ } else {
+ envptr[ep] = '\0';
+ }
+
+ /* Computes the CRC and put it at the beginning of the data */
+ crc = crc32(0, envptr, envsize);
+ targetendian_crc = bigendian ? cpu_to_be32(crc) : cpu_to_le32(crc);
+
+ memcpy(dataptr, &targetendian_crc, sizeof(uint32_t));
+
+ bin_fd = creat(bin_filename, S_IRUSR | S_IWUSR | S_IRGRP | S_IWGRP);
+ if (bin_fd == -1) {
+ fprintf(stderr, "Can't open output file \"%s\": %s\n",
+ bin_filename, strerror(errno));
+ return EXIT_FAILURE;
+ }
+
+ if (write(bin_fd, dataptr, sizeof(*dataptr) * datasize) !=
+ sizeof(*dataptr) * datasize) {
+ fprintf(stderr, "write() failed: %s\n", strerror(errno));
+ return EXIT_FAILURE;
+ }
+
+ ret = close(bin_fd);
+
+ return ret;
+}
diff --git a/tools/mxsboot.c b/tools/mxsboot.c
new file mode 100644
index 0000000..176753d
--- /dev/null
+++ b/tools/mxsboot.c
@@ -0,0 +1,684 @@
+/*
+ * Freescale i.MX28 image generator
+ *
+ * Copyright (C) 2011 Marek Vasut <marek.vasut@gmail.com>
+ * on behalf of DENX Software Engineering GmbH
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <fcntl.h>
+#include <sys/stat.h>
+#include <sys/types.h>
+#include <unistd.h>
+
+#include "compiler.h"
+
+/*
+ * Default BCB layout.
+ *
+ * TWEAK this if you have blown any OCOTP fuses.
+ */
+#define STRIDE_PAGES 64
+#define STRIDE_COUNT 4
+
+/*
+ * Layout for 256Mb big NAND with 2048b page size, 64b OOB size and
+ * 128kb erase size.
+ *
+ * TWEAK this if you have different kind of NAND chip.
+ */
+uint32_t nand_writesize = 2048;
+uint32_t nand_oobsize = 64;
+uint32_t nand_erasesize = 128 * 1024;
+
+/*
+ * Sector on which the SigmaTel boot partition (0x53) starts.
+ */
+uint32_t sd_sector = 2048;
+
+/*
+ * Each of the U-Boot bootstreams is at maximum 1MB big.
+ *
+ * TWEAK this if, for some wild reason, you need to boot bigger image.
+ */
+#define MAX_BOOTSTREAM_SIZE (1 * 1024 * 1024)
+
+/* i.MX28 NAND controller-specific constants. DO NOT TWEAK! */
+#define MXS_NAND_DMA_DESCRIPTOR_COUNT 4
+#define MXS_NAND_CHUNK_DATA_CHUNK_SIZE 512
+#define MXS_NAND_METADATA_SIZE 10
+#define MXS_NAND_COMMAND_BUFFER_SIZE 32
+
+struct mx28_nand_fcb {
+ uint32_t checksum;
+ uint32_t fingerprint;
+ uint32_t version;
+ struct {
+ uint8_t data_setup;
+ uint8_t data_hold;
+ uint8_t address_setup;
+ uint8_t dsample_time;
+ uint8_t nand_timing_state;
+ uint8_t rea;
+ uint8_t rloh;
+ uint8_t rhoh;
+ } timing;
+ uint32_t page_data_size;
+ uint32_t total_page_size;
+ uint32_t sectors_per_block;
+ uint32_t number_of_nands; /* Ignored */
+ uint32_t total_internal_die; /* Ignored */
+ uint32_t cell_type; /* Ignored */
+ uint32_t ecc_block_n_ecc_type;
+ uint32_t ecc_block_0_size;
+ uint32_t ecc_block_n_size;
+ uint32_t ecc_block_0_ecc_type;
+ uint32_t metadata_bytes;
+ uint32_t num_ecc_blocks_per_page;
+ uint32_t ecc_block_n_ecc_level_sdk; /* Ignored */
+ uint32_t ecc_block_0_size_sdk; /* Ignored */
+ uint32_t ecc_block_n_size_sdk; /* Ignored */
+ uint32_t ecc_block_0_ecc_level_sdk; /* Ignored */
+ uint32_t num_ecc_blocks_per_page_sdk; /* Ignored */
+ uint32_t metadata_bytes_sdk; /* Ignored */
+ uint32_t erase_threshold;
+ uint32_t boot_patch;
+ uint32_t patch_sectors;
+ uint32_t firmware1_starting_sector;
+ uint32_t firmware2_starting_sector;
+ uint32_t sectors_in_firmware1;
+ uint32_t sectors_in_firmware2;
+ uint32_t dbbt_search_area_start_address;
+ uint32_t badblock_marker_byte;
+ uint32_t badblock_marker_start_bit;
+ uint32_t bb_marker_physical_offset;
+};
+
+struct mx28_nand_dbbt {
+ uint32_t checksum;
+ uint32_t fingerprint;
+ uint32_t version;
+ uint32_t number_bb;
+ uint32_t number_2k_pages_bb;
+};
+
+struct mx28_nand_bbt {
+ uint32_t nand;
+ uint32_t number_bb;
+ uint32_t badblock[510];
+};
+
+struct mx28_sd_drive_info {
+ uint32_t chip_num;
+ uint32_t drive_type;
+ uint32_t tag;
+ uint32_t first_sector_number;
+ uint32_t sector_count;
+};
+
+struct mx28_sd_config_block {
+ uint32_t signature;
+ uint32_t primary_boot_tag;
+ uint32_t secondary_boot_tag;
+ uint32_t num_copies;
+ struct mx28_sd_drive_info drv_info[1];
+};
+
+static inline uint32_t mx28_nand_ecc_size_in_bits(uint32_t ecc_strength)
+{
+ return ecc_strength * 13;
+}
+
+static inline uint32_t mx28_nand_get_ecc_strength(uint32_t page_data_size,
+ uint32_t page_oob_size)
+{
+ if (page_data_size == 2048)
+ return 8;
+
+ if (page_data_size == 4096) {
+ if (page_oob_size == 128)
+ return 8;
+
+ if (page_oob_size == 218)
+ return 16;
+ }
+
+ return 0;
+}
+
+static inline uint32_t mx28_nand_get_mark_offset(uint32_t page_data_size,
+ uint32_t ecc_strength)
+{
+ uint32_t chunk_data_size_in_bits;
+ uint32_t chunk_ecc_size_in_bits;
+ uint32_t chunk_total_size_in_bits;
+ uint32_t block_mark_chunk_number;
+ uint32_t block_mark_chunk_bit_offset;
+ uint32_t block_mark_bit_offset;
+
+ chunk_data_size_in_bits = MXS_NAND_CHUNK_DATA_CHUNK_SIZE * 8;
+ chunk_ecc_size_in_bits = mx28_nand_ecc_size_in_bits(ecc_strength);
+
+ chunk_total_size_in_bits =
+ chunk_data_size_in_bits + chunk_ecc_size_in_bits;
+
+ /* Compute the bit offset of the block mark within the physical page. */
+ block_mark_bit_offset = page_data_size * 8;
+
+ /* Subtract the metadata bits. */
+ block_mark_bit_offset -= MXS_NAND_METADATA_SIZE * 8;
+
+ /*
+ * Compute the chunk number (starting at zero) in which the block mark
+ * appears.
+ */
+ block_mark_chunk_number =
+ block_mark_bit_offset / chunk_total_size_in_bits;
+
+ /*
+ * Compute the bit offset of the block mark within its chunk, and
+ * validate it.
+ */
+ block_mark_chunk_bit_offset = block_mark_bit_offset -
+ (block_mark_chunk_number * chunk_total_size_in_bits);
+
+ if (block_mark_chunk_bit_offset > chunk_data_size_in_bits)
+ return 1;
+
+ /*
+ * Now that we know the chunk number in which the block mark appears,
+ * we can subtract all the ECC bits that appear before it.
+ */
+ block_mark_bit_offset -=
+ block_mark_chunk_number * chunk_ecc_size_in_bits;
+
+ return block_mark_bit_offset;
+}
+
+static inline uint32_t mx28_nand_mark_byte_offset(void)
+{
+ uint32_t ecc_strength;
+ ecc_strength = mx28_nand_get_ecc_strength(nand_writesize, nand_oobsize);
+ return mx28_nand_get_mark_offset(nand_writesize, ecc_strength) >> 3;
+}
+
+static inline uint32_t mx28_nand_mark_bit_offset(void)
+{
+ uint32_t ecc_strength;
+ ecc_strength = mx28_nand_get_ecc_strength(nand_writesize, nand_oobsize);
+ return mx28_nand_get_mark_offset(nand_writesize, ecc_strength) & 0x7;
+}
+
+static uint32_t mx28_nand_block_csum(uint8_t *block, uint32_t size)
+{
+ uint32_t csum = 0;
+ int i;
+
+ for (i = 0; i < size; i++)
+ csum += block[i];
+
+ return csum ^ 0xffffffff;
+}
+
+static struct mx28_nand_fcb *mx28_nand_get_fcb(uint32_t size)
+{
+ struct mx28_nand_fcb *fcb;
+ uint32_t bcb_size_bytes;
+ uint32_t stride_size_bytes;
+ uint32_t bootstream_size_pages;
+ uint32_t fw1_start_page;
+ uint32_t fw2_start_page;
+
+ fcb = malloc(nand_writesize);
+ if (!fcb) {
+ printf("MX28 NAND: Unable to allocate FCB\n");
+ return NULL;
+ }
+
+ memset(fcb, 0, nand_writesize);
+
+ fcb->fingerprint = 0x20424346;
+ fcb->version = 0x01000000;
+
+ /*
+ * FIXME: These here are default values as found in kobs-ng. We should
+ * probably retrieve the data from NAND or something.
+ */
+ fcb->timing.data_setup = 80;
+ fcb->timing.data_hold = 60;
+ fcb->timing.address_setup = 25;
+ fcb->timing.dsample_time = 6;
+
+ fcb->page_data_size = nand_writesize;
+ fcb->total_page_size = nand_writesize + nand_oobsize;
+ fcb->sectors_per_block = nand_erasesize / nand_writesize;
+
+ fcb->num_ecc_blocks_per_page = (nand_writesize / 512) - 1;
+ fcb->ecc_block_0_size = 512;
+ fcb->ecc_block_n_size = 512;
+ fcb->metadata_bytes = 10;
+
+ if (nand_writesize == 2048) {
+ fcb->ecc_block_n_ecc_type = 4;
+ fcb->ecc_block_0_ecc_type = 4;
+ } else if (nand_writesize == 4096) {
+ if (nand_oobsize == 128) {
+ fcb->ecc_block_n_ecc_type = 4;
+ fcb->ecc_block_0_ecc_type = 4;
+ } else if (nand_oobsize == 218) {
+ fcb->ecc_block_n_ecc_type = 8;
+ fcb->ecc_block_0_ecc_type = 8;
+ }
+ }
+
+ if (fcb->ecc_block_n_ecc_type == 0) {
+ printf("MX28 NAND: Unsupported NAND geometry\n");
+ goto err;
+ }
+
+ fcb->boot_patch = 0;
+ fcb->patch_sectors = 0;
+
+ fcb->badblock_marker_byte = mx28_nand_mark_byte_offset();
+ fcb->badblock_marker_start_bit = mx28_nand_mark_bit_offset();
+ fcb->bb_marker_physical_offset = nand_writesize;
+
+ stride_size_bytes = STRIDE_PAGES * nand_writesize;
+ bcb_size_bytes = stride_size_bytes * STRIDE_COUNT;
+
+ bootstream_size_pages = (size + (nand_writesize - 1)) /
+ nand_writesize;
+
+ fw1_start_page = 2 * bcb_size_bytes / nand_writesize;
+ fw2_start_page = (2 * bcb_size_bytes + MAX_BOOTSTREAM_SIZE) /
+ nand_writesize;
+
+ fcb->firmware1_starting_sector = fw1_start_page;
+ fcb->firmware2_starting_sector = fw2_start_page;
+ fcb->sectors_in_firmware1 = bootstream_size_pages;
+ fcb->sectors_in_firmware2 = bootstream_size_pages;
+
+ fcb->dbbt_search_area_start_address = STRIDE_PAGES * STRIDE_COUNT;
+
+ return fcb;
+
+err:
+ free(fcb);
+ return NULL;
+}
+
+static struct mx28_nand_dbbt *mx28_nand_get_dbbt(void)
+{
+ struct mx28_nand_dbbt *dbbt;
+
+ dbbt = malloc(nand_writesize);
+ if (!dbbt) {
+ printf("MX28 NAND: Unable to allocate DBBT\n");
+ return NULL;
+ }
+
+ memset(dbbt, 0, nand_writesize);
+
+ dbbt->fingerprint = 0x54424244;
+ dbbt->version = 0x1;
+
+ return dbbt;
+}
+
+static inline uint8_t mx28_nand_parity_13_8(const uint8_t b)
+{
+ uint32_t parity = 0, tmp;
+
+ tmp = ((b >> 6) ^ (b >> 5) ^ (b >> 3) ^ (b >> 2)) & 1;
+ parity |= tmp << 0;
+
+ tmp = ((b >> 7) ^ (b >> 5) ^ (b >> 4) ^ (b >> 2) ^ (b >> 1)) & 1;
+ parity |= tmp << 1;
+
+ tmp = ((b >> 7) ^ (b >> 6) ^ (b >> 5) ^ (b >> 1) ^ (b >> 0)) & 1;
+ parity |= tmp << 2;
+
+ tmp = ((b >> 7) ^ (b >> 4) ^ (b >> 3) ^ (b >> 0)) & 1;
+ parity |= tmp << 3;
+
+ tmp = ((b >> 6) ^ (b >> 4) ^ (b >> 3) ^
+ (b >> 2) ^ (b >> 1) ^ (b >> 0)) & 1;
+ parity |= tmp << 4;
+
+ return parity;
+}
+
+static uint8_t *mx28_nand_fcb_block(struct mx28_nand_fcb *fcb)
+{
+ uint8_t *block;
+ uint8_t *ecc;
+ int i;
+
+ block = malloc(nand_writesize + nand_oobsize);
+ if (!block) {
+ printf("MX28 NAND: Unable to allocate FCB block\n");
+ return NULL;
+ }
+
+ memset(block, 0, nand_writesize + nand_oobsize);
+
+ /* Update the FCB checksum */
+ fcb->checksum = mx28_nand_block_csum(((uint8_t *)fcb) + 4, 508);
+
+ /* Figure 12-11. in iMX28RM, rev. 1, says FCB is at offset 12 */
+ memcpy(block + 12, fcb, sizeof(struct mx28_nand_fcb));
+
+ /* ECC is at offset 12 + 512 */
+ ecc = block + 12 + 512;
+
+ /* Compute the ECC parity */
+ for (i = 0; i < sizeof(struct mx28_nand_fcb); i++)
+ ecc[i] = mx28_nand_parity_13_8(block[i + 12]);
+
+ return block;
+}
+
+static int mx28_nand_write_fcb(struct mx28_nand_fcb *fcb, char *buf)
+{
+ uint32_t offset;
+ uint8_t *fcbblock;
+ int ret = 0;
+ int i;
+
+ fcbblock = mx28_nand_fcb_block(fcb);
+ if (!fcbblock)
+ return -1;
+
+ for (i = 0; i < STRIDE_PAGES * STRIDE_COUNT; i += STRIDE_PAGES) {
+ offset = i * nand_writesize;
+ memcpy(buf + offset, fcbblock, nand_writesize + nand_oobsize);
+ }
+
+ free(fcbblock);
+ return ret;
+}
+
+static int mx28_nand_write_dbbt(struct mx28_nand_dbbt *dbbt, char *buf)
+{
+ uint32_t offset;
+ int i = STRIDE_PAGES * STRIDE_COUNT;
+
+ for (; i < 2 * STRIDE_PAGES * STRIDE_COUNT; i += STRIDE_PAGES) {
+ offset = i * nand_writesize;
+ memcpy(buf + offset, dbbt, sizeof(struct mx28_nand_dbbt));
+ }
+
+ return 0;
+}
+
+static int mx28_nand_write_firmware(struct mx28_nand_fcb *fcb, int infd,
+ char *buf)
+{
+ int ret;
+ off_t size;
+ uint32_t offset1, offset2;
+
+ size = lseek(infd, 0, SEEK_END);
+ lseek(infd, 0, SEEK_SET);
+
+ offset1 = fcb->firmware1_starting_sector * nand_writesize;
+ offset2 = fcb->firmware2_starting_sector * nand_writesize;
+
+ ret = read(infd, buf + offset1, size);
+ if (ret != size)
+ return -1;
+
+ memcpy(buf + offset2, buf + offset1, size);
+
+ return 0;
+}
+
+void usage(void)
+{
+ printf(
+ "Usage: mx28image [ops] <type> <infile> <outfile>\n"
+ "Augment BootStream file with a proper header for i.MX28 boot\n"
+ "\n"
+ " <type> type of image:\n"
+ " \"nand\" for NAND image\n"
+ " \"sd\" for SD image\n"
+ " <infile> input file, the u-boot.sb bootstream\n"
+ " <outfile> output file, the bootable image\n"
+ "\n");
+ printf(
+ "For NAND boot, these options are accepted:\n"
+ " -w <size> NAND page size\n"
+ " -o <size> NAND OOB size\n"
+ " -e <size> NAND erase size\n"
+ "\n"
+ "For SD boot, these options are accepted:\n"
+ " -p <sector> Sector where the SGTL partition starts\n"
+ );
+}
+
+static int mx28_create_nand_image(int infd, int outfd)
+{
+ struct mx28_nand_fcb *fcb;
+ struct mx28_nand_dbbt *dbbt;
+ int ret = -1;
+ char *buf;
+ int size;
+ ssize_t wr_size;
+
+ size = nand_writesize * 512 + 2 * MAX_BOOTSTREAM_SIZE;
+
+ buf = malloc(size);
+ if (!buf) {
+ printf("Can not allocate output buffer of %d bytes\n", size);
+ goto err0;
+ }
+
+ memset(buf, 0, size);
+
+ fcb = mx28_nand_get_fcb(MAX_BOOTSTREAM_SIZE);
+ if (!fcb) {
+ printf("Unable to compile FCB\n");
+ goto err1;
+ }
+
+ dbbt = mx28_nand_get_dbbt();
+ if (!dbbt) {
+ printf("Unable to compile DBBT\n");
+ goto err2;
+ }
+
+ ret = mx28_nand_write_fcb(fcb, buf);
+ if (ret) {
+ printf("Unable to write FCB to buffer\n");
+ goto err3;
+ }
+
+ ret = mx28_nand_write_dbbt(dbbt, buf);
+ if (ret) {
+ printf("Unable to write DBBT to buffer\n");
+ goto err3;
+ }
+
+ ret = mx28_nand_write_firmware(fcb, infd, buf);
+ if (ret) {
+ printf("Unable to write firmware to buffer\n");
+ goto err3;
+ }
+
+ wr_size = write(outfd, buf, size);
+ if (wr_size != size) {
+ ret = -1;
+ goto err3;
+ }
+
+ ret = 0;
+
+err3:
+ free(dbbt);
+err2:
+ free(fcb);
+err1:
+ free(buf);
+err0:
+ return ret;
+}
+
+static int mx28_create_sd_image(int infd, int outfd)
+{
+ int ret = -1;
+ uint32_t *buf;
+ int size;
+ off_t fsize;
+ ssize_t wr_size;
+ struct mx28_sd_config_block *cb;
+
+ fsize = lseek(infd, 0, SEEK_END);
+ lseek(infd, 0, SEEK_SET);
+ size = fsize + 512;
+
+ buf = malloc(size);
+ if (!buf) {
+ printf("Can not allocate output buffer of %d bytes\n", size);
+ goto err0;
+ }
+
+ ret = read(infd, (uint8_t *)buf + 512, fsize);
+ if (ret != fsize) {
+ ret = -1;
+ goto err1;
+ }
+
+ cb = (struct mx28_sd_config_block *)buf;
+
+ cb->signature = 0x00112233;
+ cb->primary_boot_tag = 0x1;
+ cb->secondary_boot_tag = 0x1;
+ cb->num_copies = 1;
+ cb->drv_info[0].chip_num = 0x0;
+ cb->drv_info[0].drive_type = 0x0;
+ cb->drv_info[0].tag = 0x1;
+ cb->drv_info[0].first_sector_number = sd_sector + 1;
+ cb->drv_info[0].sector_count = (size - 1) / 512;
+
+ wr_size = write(outfd, buf, size);
+ if (wr_size != size) {
+ ret = -1;
+ goto err1;
+ }
+
+ ret = 0;
+
+err1:
+ free(buf);
+err0:
+ return ret;
+}
+
+int parse_ops(int argc, char **argv)
+{
+ int i;
+ int tmp;
+ char *end;
+ enum param {
+ PARAM_WRITE,
+ PARAM_OOB,
+ PARAM_ERASE,
+ PARAM_PART,
+ PARAM_SD,
+ PARAM_NAND
+ };
+ int type;
+
+ for (i = 1; i < argc; i++) {
+ if (!strncmp(argv[i], "-w", 2))
+ type = PARAM_WRITE;
+ else if (!strncmp(argv[i], "-o", 2))
+ type = PARAM_OOB;
+ else if (!strncmp(argv[i], "-e", 2))
+ type = PARAM_ERASE;
+ else if (!strncmp(argv[i], "-p", 2))
+ type = PARAM_PART;
+ else /* SD/MMC */
+ break;
+
+ tmp = strtol(argv[++i], &end, 10);
+ if (tmp % 2)
+ return -1;
+ if (tmp <= 0)
+ return -1;
+
+ if (type == PARAM_WRITE)
+ nand_writesize = tmp;
+ if (type == PARAM_OOB)
+ nand_oobsize = tmp;
+ if (type == PARAM_ERASE)
+ nand_erasesize = tmp;
+ if (type == PARAM_PART)
+ sd_sector = tmp;
+ }
+
+ if (strcmp(argv[i], "sd") && strcmp(argv[i], "nand"))
+ return -1;
+
+ if (i + 3 != argc)
+ return -1;
+
+ return i;
+}
+
+int main(int argc, char **argv)
+{
+ int infd, outfd;
+ int ret = 0;
+ int offset;
+
+ offset = parse_ops(argc, argv);
+ if (offset < 0) {
+ usage();
+ ret = 1;
+ goto err1;
+ }
+
+ infd = open(argv[offset + 1], O_RDONLY);
+ if (infd < 0) {
+ printf("Input BootStream file can not be opened\n");
+ ret = 2;
+ goto err1;
+ }
+
+ outfd = open(argv[offset + 2], O_CREAT | O_TRUNC | O_WRONLY,
+ S_IRUSR | S_IWUSR);
+ if (outfd < 0) {
+ printf("Output file can not be created\n");
+ ret = 3;
+ goto err2;
+ }
+
+ if (!strcmp(argv[offset], "sd"))
+ ret = mx28_create_sd_image(infd, outfd);
+ else if (!strcmp(argv[offset], "nand"))
+ ret = mx28_create_nand_image(infd, outfd);
+
+ close(outfd);
+err2:
+ close(infd);
+err1:
+ return ret;
+}