| // SPDX-License-Identifier: GPL-2.0 |
| /* |
| * Copyright (C) 2012 Texas Instruments Incorporated - https://www.ti.com/ |
| * Copyright (C) 2018 Robert Bosch Power Tools GmbH |
| */ |
| /dts-v1/; |
| |
| #include "am33xx.dtsi" |
| #include <dt-bindings/input/input.h> |
| #include <dt-bindings/interrupt-controller/irq.h> |
| |
| / { |
| model = "Bosch AM335x Guardian"; |
| compatible = "bosch,am335x-guardian", "ti,am33xx"; |
| |
| chosen { |
| stdout-path = &uart0; |
| tick-timer = &timer2; |
| }; |
| |
| cpus { |
| cpu@0 { |
| cpu0-supply = <&dcdc2_reg>; |
| }; |
| }; |
| |
| memory@80000000 { |
| device_type = "memory"; |
| reg = <0x80000000 0x10000000>; /* 256 MB */ |
| }; |
| |
| guardian_buttons: gpio-keys { |
| pinctrl-names = "default"; |
| pinctrl-0 = <&guardian_button_pins>; |
| compatible = "gpio-keys"; |
| |
| select-button { |
| label = "guardian-select-button"; |
| linux,code = <KEY_5>; |
| gpios = <&gpio1 31 GPIO_ACTIVE_LOW>; |
| wakeup-source; |
| }; |
| |
| power-button { |
| label = "guardian-power-button"; |
| linux,code = <KEY_POWER>; |
| gpios = <&gpio2 21 GPIO_ACTIVE_LOW>; |
| wakeup-source; |
| }; |
| }; |
| |
| guardian_leds: gpio-leds { |
| pinctrl-names = "default"; |
| pinctrl-0 = <&guardian_led_pins>; |
| compatible = "gpio-leds"; |
| |
| life-led { |
| label = "guardian:life-led"; |
| gpios = <&gpio1 26 GPIO_ACTIVE_HIGH>; |
| linux,default-trigger = "heartbeat"; |
| default-state = "on"; |
| }; |
| }; |
| |
| panel { |
| compatible = "ti,tilcdc,panel"; |
| pinctrl-names = "default", "sleep"; |
| pinctrl-0 = <&lcd_pins_default &lcd_disen_pins>; |
| pinctrl-1 = <&lcd_pins_sleep>; |
| |
| display-timings { |
| 320x240 { |
| hactive = <320>; |
| vactive = <240>; |
| hback-porch = <68>; |
| hfront-porch = <20>; |
| hsync-len = <1>; |
| vback-porch = <18>; |
| vfront-porch = <4>; |
| vsync-len = <1>; |
| clock-frequency = <9000000>; |
| hsync-active = <0>; |
| vsync-active = <0>; |
| }; |
| }; |
| panel-info { |
| ac-bias = <255>; |
| ac-bias-intrpt = <0>; |
| dma-burst-sz = <16>; |
| bpp = <16>; |
| bus-width = <16>; |
| fdd = <0x80>; |
| sync-edge = <0>; |
| sync-ctrl = <1>; |
| raster-order = <0>; |
| fifo-th = <0>; |
| }; |
| |
| }; |
| |
| pwm7: pwm-7 { |
| compatible = "ti,omap-dmtimer-pwm"; |
| ti,timers = <&timer7>; |
| pinctrl-names = "default"; |
| pinctrl-0 = <&dmtimer7_pins>; |
| }; |
| |
| vmmcsd_fixed: regulator-3v3 { |
| compatible = "regulator-fixed"; |
| regulator-name = "vmmcsd_fixed"; |
| regulator-min-microvolt = <3300000>; |
| regulator-max-microvolt = <3300000>; |
| }; |
| }; |
| |
| &cppi41dma { |
| status = "okay"; |
| }; |
| |
| &elm { |
| status = "okay"; |
| }; |
| |
| &gpmc { |
| pinctrl-names = "default"; |
| pinctrl-0 = <&nandflash_pins>; |
| ranges = <0 0 0x08000000 0x1000000>; /* CS0: 16MB for NAND */ |
| status = "okay"; |
| |
| nand@0,0 { |
| compatible = "ti,omap2-nand"; |
| reg = <0 0 4>; /* CS0, offset 0, IO size 4 */ |
| interrupt-parent = <&gpmc>; |
| interrupts = <0 IRQ_TYPE_NONE>, /* fifoevent */ |
| <1 IRQ_TYPE_NONE>; /* termcount */ |
| rb-gpios = <&gpmc 0 GPIO_ACTIVE_HIGH>; /* gpmc_wait0 */ |
| ti,nand-ecc-opt = "bch16"; |
| ti,elm-id = <&elm>; |
| nand-bus-width = <8>; |
| gpmc,device-width = <1>; |
| gpmc,sync-clk-ps = <0>; |
| gpmc,cs-on-ns = <0>; |
| gpmc,cs-rd-off-ns = <30>; |
| gpmc,cs-wr-off-ns = <30>; |
| gpmc,adv-on-ns = <0>; |
| gpmc,adv-rd-off-ns = <30>; |
| gpmc,adv-wr-off-ns = <30>; |
| gpmc,we-on-ns = <0>; |
| gpmc,we-off-ns = <15>; |
| gpmc,oe-on-ns = <1>; |
| gpmc,oe-off-ns = <15>; |
| gpmc,access-ns = <30>; |
| gpmc,rd-cycle-ns = <30>; |
| gpmc,wr-cycle-ns = <30>; |
| gpmc,wait-on-read = "true"; |
| gpmc,wait-on-write = "true"; |
| gpmc,bus-turnaround-ns = <0>; |
| gpmc,cycle2cycle-delay-ns = <0>; |
| gpmc,clk-activation-ns = <0>; |
| gpmc,wait-monitoring-ns = <0>; |
| gpmc,wr-access-ns = <0>; |
| gpmc,wr-data-mux-bus-ns = <0>; |
| |
| /* |
| * MTD partition table |
| * |
| * All SPL-* partitions are sized to minimal length which can |
| * be independently programmable. For NAND flash this is equal |
| * to size of erase-block. |
| */ |
| #address-cells = <1>; |
| #size-cells = <1>; |
| |
| partition@0 { |
| label = "SPL"; |
| reg = <0x0 0x40000>; |
| }; |
| |
| partition@1 { |
| label = "SPL.backup1"; |
| reg = <0x40000 0x40000>; |
| }; |
| |
| partition@2 { |
| label = "SPL.backup2"; |
| reg = <0x80000 0x40000>; |
| }; |
| |
| partition@3 { |
| label = "SPL.backup3"; |
| reg = <0xc0000 0x40000>; |
| }; |
| |
| partition@4 { |
| label = "u-boot"; |
| reg = <0x100000 0x100000>; |
| }; |
| |
| partition@5 { |
| label = "u-boot.backup1"; |
| reg = <0x200000 0x100000>; |
| }; |
| |
| partition@6 { |
| label = "u-boot-2"; |
| reg = <0x300000 0x100000>; |
| }; |
| |
| partition@7 { |
| label = "u-boot-2.backup1"; |
| reg = <0x400000 0x100000>; |
| }; |
| |
| partition@8 { |
| label = "u-boot-env"; |
| reg = <0x500000 0x40000>; |
| }; |
| |
| partition@9 { |
| label = "u-boot-env.backup1"; |
| reg = <0x540000 0x40000>; |
| }; |
| |
| partition@10 { |
| label = "splash-screen"; |
| reg = <0x580000 0x40000>; |
| }; |
| |
| partition@11 { |
| label = "UBI"; |
| reg = <0x5c0000 0x1fa40000>; |
| }; |
| }; |
| }; |
| |
| &i2c0 { |
| pinctrl-names = "default"; |
| pinctrl-0 = <&i2c0_pins>; |
| clock-frequency = <400000>; |
| status = "okay"; |
| |
| tps: tps@24 { |
| reg = <0x24>; |
| }; |
| }; |
| |
| &lcdc { |
| blue-and-red-wiring = "crossed"; |
| status = "okay"; |
| |
| port { |
| lcdc_0: endpoint@0 { |
| remote-endpoint = <0>; |
| }; |
| }; |
| }; |
| |
| &mmc1 { |
| bus-width = <0x4>; |
| pinctrl-names = "default"; |
| pinctrl-0 = <&mmc1_pins>; |
| cd-gpios = <&gpio0 6 GPIO_ACTIVE_LOW>; |
| vmmc-supply = <&vmmcsd_fixed>; |
| status = "okay"; |
| }; |
| |
| &rtc { |
| clocks = <&clk_32768_ck>, <&clk_24mhz_clkctrl AM3_CLK_24MHZ_CLKDIV32K_CLKCTRL 0>; |
| clock-names = "ext-clk", "int-clk"; |
| system-power-controller; |
| }; |
| |
| &spi0 { |
| ti,pindir-d0-out-d1-in; |
| pinctrl-names = "default"; |
| pinctrl-0 = <&spi0_pins>; |
| status = "okay"; |
| }; |
| |
| /include/ "tps65217.dtsi" |
| |
| &tps { |
| ti,pmic-shutdown-controller; |
| interrupt-parent = <&intc>; |
| interrupts = <7>; /* NMI */ |
| |
| backlight { |
| isel = <1>; /* 1 - ISET1, 2 ISET2 */ |
| fdim = <100>; /* TPS65217_BL_FDIM_100HZ */ |
| default-brightness = <100>; |
| }; |
| |
| regulators { |
| dcdc1_reg: regulator@0 { |
| regulator-name = "vdds_dpr"; |
| regulator-always-on; |
| }; |
| |
| dcdc2_reg: regulator@1 { |
| regulator-name = "vdd_mpu"; |
| regulator-min-microvolt = <925000>; |
| regulator-max-microvolt = <1351500>; |
| regulator-boot-on; |
| regulator-always-on; |
| }; |
| |
| dcdc3_reg: regulator@2 { |
| regulator-name = "vdd_core"; |
| regulator-min-microvolt = <925000>; |
| regulator-max-microvolt = <1150000>; |
| regulator-boot-on; |
| regulator-always-on; |
| }; |
| |
| ldo1_reg: regulator@3 { |
| regulator-name = "vio,vrtc,vdds"; |
| regulator-always-on; |
| }; |
| |
| ldo2_reg: regulator@4 { |
| regulator-name = "vdd_3v3aux"; |
| regulator-always-on; |
| }; |
| |
| ldo3_reg: regulator@5 { |
| regulator-name = "vdd_1v8"; |
| regulator-min-microvolt = <1800000>; |
| regulator-max-microvolt = <1800000>; |
| regulator-always-on; |
| }; |
| |
| ldo4_reg: regulator@6 { |
| regulator-name = "vdd_3v3a"; |
| regulator-always-on; |
| }; |
| }; |
| }; |
| |
| &tscadc { |
| status = "okay"; |
| |
| adc { |
| ti,adc-channels = <0 1 2 3 4 5 6>; |
| }; |
| }; |
| |
| &uart0 { |
| pinctrl-names = "default"; |
| pinctrl-0 = <&uart0_pins>; |
| status = "okay"; |
| }; |
| |
| &uart2 { |
| pinctrl-names = "default"; |
| pinctrl-0 = <&uart2_pins>; |
| status = "okay"; |
| }; |
| |
| &usb { |
| status = "okay"; |
| }; |
| |
| &usb_ctrl_mod { |
| status = "okay"; |
| }; |
| |
| &usb0 { |
| dr_mode = "peripheral"; |
| status = "okay"; |
| }; |
| |
| &usb0_phy { |
| status = "okay"; |
| }; |
| |
| &usb1 { |
| dr_mode = "host"; |
| status = "okay"; |
| }; |
| |
| &usb1_phy { |
| status = "okay"; |
| }; |
| |
| &am33xx_pinmux { |
| pinctrl-names = "default"; |
| pinctrl-0 = <&clkout2_pin &guardian_interface_pins>; |
| |
| clkout2_pin: pinmux_clkout2_pin { |
| pinctrl-single,pins = < |
| AM33XX_PADCONF(AM335X_PIN_XDMA_EVENT_INTR1, PIN_OUTPUT_PULLDOWN, MUX_MODE3) |
| >; |
| }; |
| |
| dmtimer7_pins: pinmux_dmtimer7_pins { |
| pinctrl-single,pins = < |
| AM33XX_PADCONF(AM335X_PIN_UART0_CTSN, PIN_OUTPUT, MUX_MODE5) |
| >; |
| }; |
| |
| guardian_button_pins: pinmux_gpio_keys_pins { |
| pinctrl-single,pins = < |
| AM33XX_PADCONF(AM335X_PIN_MII1_RXD0, PIN_INPUT, MUX_MODE7) |
| AM33XX_PADCONF(AM335X_PIN_GPMC_CSN2, PIN_INPUT, MUX_MODE7) |
| >; |
| }; |
| |
| guardian_interface_pins: pinmux_guardian_interface_pins { |
| pinctrl-single,pins = < |
| AM33XX_PADCONF(AM335X_PIN_MCASP0_ACLKX, PIN_OUTPUT_PULLUP, MUX_MODE7) |
| AM33XX_PADCONF(AM335X_PIN_MCASP0_AHCLKX, PIN_OUTPUT_PULLDOWN, MUX_MODE7) |
| AM33XX_PADCONF(AM335X_PIN_MII1_TX_EN, PIN_OUTPUT_PULLDOWN, MUX_MODE7) |
| AM33XX_PADCONF(AM335X_PIN_UART1_RXD, PIN_INPUT, MUX_MODE7) |
| AM33XX_PADCONF(AM335X_PIN_UART1_TXD, PIN_INPUT, MUX_MODE7) |
| AM33XX_PADCONF(AM335X_PIN_MDC, PIN_OUTPUT_PULLUP, MUX_MODE7) |
| AM33XX_PADCONF(AM335X_PIN_MII1_CRS, PIN_OUTPUT_PULLDOWN, MUX_MODE7) |
| AM33XX_PADCONF(AM335X_PIN_RMII1_REF_CLK, PIN_OUTPUT_PULLDOWN, MUX_MODE7) |
| AM33XX_PADCONF(AM335X_PIN_MII1_TXD3, PIN_INPUT, MUX_MODE7) |
| AM33XX_PADCONF(AM335X_PIN_MII1_RX_DV, PIN_OUTPUT_PULLDOWN, MUX_MODE7) |
| >; |
| }; |
| |
| i2c0_pins: pinmux_i2c0_pins { |
| pinctrl-single,pins = < |
| AM33XX_PADCONF(AM335X_PIN_I2C0_SDA, PIN_INPUT_PULLUP, MUX_MODE0) |
| AM33XX_PADCONF(AM335X_PIN_I2C0_SCL, PIN_INPUT_PULLUP, MUX_MODE0) |
| >; |
| }; |
| |
| lcd_disen_pins: pinmux_lcd_disen_pins { |
| pinctrl-single,pins = < |
| AM33XX_PADCONF |
| (AM335X_PIN_MCASP0_FSR, PIN_OUTPUT_PULLUP | SLEWCTRL_SLOW, MUX_MODE7) |
| >; |
| }; |
| |
| lcd_pins_default: pinmux_lcd_pins_default { |
| pinctrl-single,pins = < |
| AM33XX_PADCONF(AM335X_PIN_GPMC_AD8, PIN_OUTPUT | SLEWCTRL_SLOW, MUX_MODE1) |
| AM33XX_PADCONF(AM335X_PIN_GPMC_AD9, PIN_OUTPUT | SLEWCTRL_SLOW, MUX_MODE1) |
| AM33XX_PADCONF(AM335X_PIN_GPMC_AD10, PIN_OUTPUT | SLEWCTRL_SLOW, MUX_MODE1) |
| AM33XX_PADCONF(AM335X_PIN_GPMC_AD11, PIN_OUTPUT | SLEWCTRL_SLOW, MUX_MODE1) |
| AM33XX_PADCONF(AM335X_PIN_GPMC_AD12, PIN_OUTPUT | SLEWCTRL_SLOW, MUX_MODE1) |
| AM33XX_PADCONF(AM335X_PIN_GPMC_AD13, PIN_OUTPUT | SLEWCTRL_SLOW, MUX_MODE1) |
| AM33XX_PADCONF(AM335X_PIN_GPMC_AD14, PIN_OUTPUT | SLEWCTRL_SLOW, MUX_MODE1) |
| AM33XX_PADCONF(AM335X_PIN_GPMC_AD15, PIN_OUTPUT | SLEWCTRL_SLOW, MUX_MODE1) |
| AM33XX_PADCONF(AM335X_PIN_LCD_DATA0, PIN_OUTPUT | SLEWCTRL_SLOW, MUX_MODE0) |
| AM33XX_PADCONF(AM335X_PIN_LCD_DATA1, PIN_OUTPUT | SLEWCTRL_SLOW, MUX_MODE0) |
| AM33XX_PADCONF(AM335X_PIN_LCD_DATA2, PIN_OUTPUT | SLEWCTRL_SLOW, MUX_MODE0) |
| AM33XX_PADCONF(AM335X_PIN_LCD_DATA3, PIN_OUTPUT | SLEWCTRL_SLOW, MUX_MODE0) |
| AM33XX_PADCONF(AM335X_PIN_LCD_DATA4, PIN_OUTPUT | SLEWCTRL_SLOW, MUX_MODE0) |
| AM33XX_PADCONF(AM335X_PIN_LCD_DATA5, PIN_OUTPUT | SLEWCTRL_SLOW, MUX_MODE0) |
| AM33XX_PADCONF(AM335X_PIN_LCD_DATA6, PIN_OUTPUT | SLEWCTRL_SLOW, MUX_MODE0) |
| AM33XX_PADCONF(AM335X_PIN_LCD_DATA7, PIN_OUTPUT | SLEWCTRL_SLOW, MUX_MODE0) |
| AM33XX_PADCONF(AM335X_PIN_LCD_DATA8, PIN_OUTPUT | SLEWCTRL_SLOW, MUX_MODE0) |
| AM33XX_PADCONF(AM335X_PIN_LCD_DATA9, PIN_OUTPUT | SLEWCTRL_SLOW, MUX_MODE0) |
| AM33XX_PADCONF(AM335X_PIN_LCD_DATA10, PIN_OUTPUT | SLEWCTRL_SLOW, MUX_MODE0) |
| AM33XX_PADCONF(AM335X_PIN_LCD_DATA11, PIN_OUTPUT | SLEWCTRL_SLOW, MUX_MODE0) |
| AM33XX_PADCONF(AM335X_PIN_LCD_DATA12, PIN_OUTPUT | SLEWCTRL_SLOW, MUX_MODE0) |
| AM33XX_PADCONF(AM335X_PIN_LCD_DATA13, PIN_OUTPUT | SLEWCTRL_SLOW, MUX_MODE0) |
| AM33XX_PADCONF(AM335X_PIN_LCD_DATA14, PIN_OUTPUT | SLEWCTRL_SLOW, MUX_MODE0) |
| AM33XX_PADCONF(AM335X_PIN_LCD_DATA15, PIN_OUTPUT | SLEWCTRL_SLOW, MUX_MODE0) |
| AM33XX_PADCONF(AM335X_PIN_LCD_VSYNC, PIN_OUTPUT | SLEWCTRL_SLOW, MUX_MODE0) |
| AM33XX_PADCONF(AM335X_PIN_LCD_HSYNC, PIN_OUTPUT | SLEWCTRL_SLOW, MUX_MODE0) |
| AM33XX_PADCONF(AM335X_PIN_LCD_PCLK, PIN_OUTPUT | SLEWCTRL_SLOW, MUX_MODE0) |
| AM33XX_PADCONF |
| (AM335X_PIN_LCD_AC_BIAS_EN, PIN_OUTPUT | SLEWCTRL_SLOW, MUX_MODE0) |
| >; |
| }; |
| |
| lcd_pins_sleep: pinmux_lcd_pins_sleep { |
| pinctrl-single,pins = < |
| AM33XX_PADCONF |
| (AM335X_PIN_LCD_DATA0, PULL_DISABLE | SLEWCTRL_SLOW, MUX_MODE7) |
| AM33XX_PADCONF |
| (AM335X_PIN_LCD_DATA1, PULL_DISABLE | SLEWCTRL_SLOW, MUX_MODE7) |
| AM33XX_PADCONF |
| (AM335X_PIN_LCD_DATA2, PULL_DISABLE | SLEWCTRL_SLOW, MUX_MODE7) |
| AM33XX_PADCONF |
| (AM335X_PIN_LCD_DATA3, PULL_DISABLE | SLEWCTRL_SLOW, MUX_MODE7) |
| AM33XX_PADCONF |
| (AM335X_PIN_LCD_DATA4, PULL_DISABLE | SLEWCTRL_SLOW, MUX_MODE7) |
| AM33XX_PADCONF |
| (AM335X_PIN_LCD_DATA5, PULL_DISABLE | SLEWCTRL_SLOW, MUX_MODE7) |
| AM33XX_PADCONF |
| (AM335X_PIN_LCD_DATA6, PULL_DISABLE | SLEWCTRL_SLOW, MUX_MODE7) |
| AM33XX_PADCONF |
| (AM335X_PIN_LCD_DATA7, PULL_DISABLE | SLEWCTRL_SLOW, MUX_MODE7) |
| AM33XX_PADCONF |
| (AM335X_PIN_LCD_DATA8, PULL_DISABLE | SLEWCTRL_SLOW, MUX_MODE7) |
| AM33XX_PADCONF |
| (AM335X_PIN_LCD_DATA9, PULL_DISABLE | SLEWCTRL_SLOW, MUX_MODE7) |
| AM33XX_PADCONF |
| (AM335X_PIN_LCD_DATA10, PULL_DISABLE | SLEWCTRL_SLOW, MUX_MODE7) |
| AM33XX_PADCONF |
| (AM335X_PIN_LCD_DATA11, PULL_DISABLE | SLEWCTRL_SLOW, MUX_MODE7) |
| AM33XX_PADCONF |
| (AM335X_PIN_LCD_DATA12, PULL_DISABLE | SLEWCTRL_SLOW, MUX_MODE7) |
| AM33XX_PADCONF |
| (AM335X_PIN_LCD_DATA13, PULL_DISABLE | SLEWCTRL_SLOW, MUX_MODE7) |
| AM33XX_PADCONF |
| (AM335X_PIN_LCD_DATA14, PULL_DISABLE | SLEWCTRL_SLOW, MUX_MODE7) |
| AM33XX_PADCONF |
| (AM335X_PIN_LCD_DATA15, PULL_DISABLE | SLEWCTRL_SLOW, MUX_MODE7) |
| AM33XX_PADCONF |
| (AM335X_PIN_LCD_VSYNC, PIN_INPUT_PULLDOWN | SLEWCTRL_SLOW, MUX_MODE7) |
| AM33XX_PADCONF |
| (AM335X_PIN_LCD_HSYNC, PIN_INPUT_PULLDOWN | SLEWCTRL_SLOW, MUX_MODE7) |
| AM33XX_PADCONF |
| (AM335X_PIN_LCD_PCLK, PIN_INPUT_PULLDOWN | SLEWCTRL_SLOW, MUX_MODE7) |
| AM33XX_PADCONF |
| (AM335X_PIN_LCD_AC_BIAS_EN, PIN_INPUT_PULLDOWN | SLEWCTRL_SLOW, MUX_MODE7) |
| >; |
| }; |
| |
| guardian_led_pins: pinmux_leds_pins { |
| pinctrl-single,pins = < |
| AM33XX_PADCONF(AM335X_PIN_GPMC_A10, PIN_OUTPUT, MUX_MODE7) |
| >; |
| }; |
| |
| mmc1_pins: pinmux_mmc1_pins { |
| pinctrl-single,pins = < |
| AM33XX_PADCONF(AM335X_PIN_MMC0_DAT3, PIN_INPUT_PULLUP, MUX_MODE0) |
| AM33XX_PADCONF(AM335X_PIN_MMC0_DAT2, PIN_INPUT_PULLUP, MUX_MODE0) |
| AM33XX_PADCONF(AM335X_PIN_MMC0_DAT1, PIN_INPUT_PULLUP, MUX_MODE0) |
| AM33XX_PADCONF(AM335X_PIN_MMC0_DAT0, PIN_INPUT_PULLUP, MUX_MODE0) |
| AM33XX_PADCONF(AM335X_PIN_MMC0_CLK, PIN_INPUT_PULLUP, MUX_MODE0) |
| AM33XX_PADCONF(AM335X_PIN_MMC0_CMD, PIN_INPUT_PULLUP, MUX_MODE0) |
| AM33XX_PADCONF(AM335X_PIN_SPI0_CS1, PIN_INPUT, MUX_MODE7) |
| >; |
| }; |
| |
| spi0_pins: pinmux_spi0_pins { |
| pinctrl-single,pins = < |
| AM33XX_PADCONF(AM335X_PIN_SPI0_SCLK, PIN_OUTPUT_PULLDOWN, MUX_MODE0) |
| AM33XX_PADCONF(AM335X_PIN_SPI0_D0, PIN_OUTPUT_PULLUP, MUX_MODE0) |
| AM33XX_PADCONF(AM335X_PIN_SPI0_D1, PIN_INPUT_PULLUP, MUX_MODE0) |
| AM33XX_PADCONF(AM335X_PIN_SPI0_CS0, PIN_OUTPUT_PULLUP, MUX_MODE0) |
| >; |
| }; |
| |
| uart0_pins: pinmux_uart0_pins { |
| pinctrl-single,pins = < |
| AM33XX_PADCONF(AM335X_PIN_UART0_RXD, PIN_INPUT_PULLUP, MUX_MODE0) |
| AM33XX_PADCONF(AM335X_PIN_UART0_TXD, PIN_OUTPUT_PULLDOWN, MUX_MODE0) |
| >; |
| }; |
| |
| uart2_pins: pinmux_uart2_pins { |
| pinctrl-single,pins = < |
| AM33XX_PADCONF(AM335X_PIN_MII1_TX_CLK, PIN_INPUT_PULLUP, MUX_MODE1) |
| AM33XX_PADCONF(AM335X_PIN_MII1_RX_CLK, PIN_OUTPUT_PULLDOWN, MUX_MODE1) |
| >; |
| }; |
| |
| nandflash_pins: pinmux_nandflash_pins { |
| pinctrl-single,pins = < |
| AM33XX_PADCONF(AM335X_PIN_GPMC_AD0, PIN_INPUT, MUX_MODE0) |
| AM33XX_PADCONF(AM335X_PIN_GPMC_AD1, PIN_INPUT, MUX_MODE0) |
| AM33XX_PADCONF(AM335X_PIN_GPMC_AD2, PIN_INPUT, MUX_MODE0) |
| AM33XX_PADCONF(AM335X_PIN_GPMC_AD3, PIN_INPUT, MUX_MODE0) |
| AM33XX_PADCONF(AM335X_PIN_GPMC_AD4, PIN_INPUT, MUX_MODE0) |
| AM33XX_PADCONF(AM335X_PIN_GPMC_AD5, PIN_INPUT, MUX_MODE0) |
| AM33XX_PADCONF(AM335X_PIN_GPMC_AD6, PIN_INPUT, MUX_MODE0) |
| AM33XX_PADCONF(AM335X_PIN_GPMC_AD7, PIN_INPUT, MUX_MODE0) |
| AM33XX_PADCONF(AM335X_PIN_GPMC_WAIT0, PIN_INPUT, MUX_MODE0) |
| AM33XX_PADCONF(AM335X_PIN_GPMC_WPN, PIN_OUTPUT, MUX_MODE0) |
| AM33XX_PADCONF(AM335X_PIN_GPMC_CSN0, PIN_OUTPUT, MUX_MODE0) |
| AM33XX_PADCONF(AM335X_PIN_GPMC_ADVN_ALE, PIN_OUTPUT, MUX_MODE0) |
| AM33XX_PADCONF(AM335X_PIN_GPMC_OEN_REN, PIN_OUTPUT, MUX_MODE0) |
| AM33XX_PADCONF(AM335X_PIN_GPMC_WEN, PIN_OUTPUT, MUX_MODE0) |
| AM33XX_PADCONF(AM335X_PIN_GPMC_BEN0_CLE, PIN_OUTPUT, MUX_MODE0) |
| >; |
| }; |
| }; |