arch/arm/dts/rk3568-nanopi-r5s.dts

// SPDX-License-Identifier: GPL-2.0-or-later OR MIT
/*
 * Copyright (c) 2022 FriendlyElec Computer Tech. Co., Ltd.
 * (http://www.friendlyelec.com)
 *
 * Copyright (c) 2023 Tianling Shen <cnsztl@gmail.com>
 */

/dts-v1/;
#include "rk3568-nanopi-r5s.dtsi"

/ {
	model = "FriendlyElec NanoPi R5S";
	compatible = "friendlyarm,nanopi-r5s", "rockchip,rk3568";

	aliases {
		ethernet0 = &gmac0;
	};

	gpio-leds {
		compatible = "gpio-leds";
		pinctrl-names = "default";
		pinctrl-0 = <&lan1_led_pin>, <&lan2_led_pin>, <&power_led_pin>, <&wan_led_pin>;

		led-lan1 {
			color = <LED_COLOR_ID_GREEN>;
			function = LED_FUNCTION_LAN;
			function-enumerator = <1>;
			gpios = <&gpio3 RK_PD6 GPIO_ACTIVE_HIGH>;
		};

		led-lan2 {
			color = <LED_COLOR_ID_GREEN>;
			function = LED_FUNCTION_LAN;
			function-enumerator = <2>;
			gpios = <&gpio3 RK_PD7 GPIO_ACTIVE_HIGH>;
		};

		power_led: led-power {
			color = <LED_COLOR_ID_RED>;
			function = LED_FUNCTION_POWER;
			linux,default-trigger = "heartbeat";
			gpios = <&gpio4 RK_PD2 GPIO_ACTIVE_HIGH>;
		};

		led-wan {
			color = <LED_COLOR_ID_GREEN>;
			function = LED_FUNCTION_WAN;
			gpios = <&gpio2 RK_PC1 GPIO_ACTIVE_HIGH>;
		};
	};
};

&gmac0 {
	assigned-clocks = <&cru SCLK_GMAC0_RX_TX>, <&cru SCLK_GMAC0>;
	assigned-clock-parents = <&cru SCLK_GMAC0_RGMII_SPEED>, <&cru CLK_MAC0_2TOP>;
	assigned-clock-rates = <0>, <125000000>;
	clock_in_out = "output";
	phy-handle = <&rgmii_phy0>;
	phy-mode = "rgmii";
	pinctrl-names = "default";
	pinctrl-0 = <&gmac0_miim
		     &gmac0_tx_bus2
		     &gmac0_rx_bus2
		     &gmac0_rgmii_clk
		     &gmac0_rgmii_bus>;
	snps,reset-gpio = <&gpio0 RK_PC5 GPIO_ACTIVE_LOW>;
	snps,reset-active-low;
	/* Reset time is 15ms, 50ms for rtl8211f */
	snps,reset-delays-us = <0 15000 50000>;
	tx_delay = <0x3c>;
	rx_delay = <0x2f>;
	status = "okay";
};

&mdio0 {
	rgmii_phy0: ethernet-phy@1 {
		compatible = "ethernet-phy-ieee802.3-c22";
		reg = <1>;
		pinctrl-0 = <&eth_phy0_reset_pin>;
		pinctrl-names = "default";
	};
};

&pcie2x1 {
	num-lanes = <1>;
	reset-gpios = <&gpio0 RK_PB6 GPIO_ACTIVE_HIGH>;
	status = "okay";
};

&pcie30phy {
	data-lanes = <1 2>;
	status = "okay";
};

&pcie3x1 {
	num-lanes = <1>;
	reset-gpios = <&gpio0 RK_PA0 GPIO_ACTIVE_HIGH>;
	vpcie3v3-supply = <&vcc3v3_pcie>;
	status = "okay";
};

&pcie3x2 {
	num-lanes = <1>;
	num-ib-windows = <8>;
	num-ob-windows = <8>;
	reset-gpios = <&gpio2 RK_PD6 GPIO_ACTIVE_HIGH>;
	vpcie3v3-supply = <&vcc3v3_pcie>;
	status = "okay";
};

&pinctrl {
	gmac0 {
		eth_phy0_reset_pin: eth-phy0-reset-pin {
			rockchip,pins = <0 RK_PC4 RK_FUNC_GPIO &pcfg_pull_up>;
		};
	};

	gpio-leds {
		lan1_led_pin: lan1-led-pin {
			rockchip,pins = <3 RK_PD6 RK_FUNC_GPIO &pcfg_pull_none>;
		};

		lan2_led_pin: lan2-led-pin {
			rockchip,pins = <3 RK_PD7 RK_FUNC_GPIO &pcfg_pull_none>;
		};

		power_led_pin: power-led-pin {
			rockchip,pins = <4 RK_PD2 RK_FUNC_GPIO &pcfg_pull_none>;
		};

		wan_led_pin: wan-led-pin {
			rockchip,pins = <2 RK_PC1 RK_FUNC_GPIO &pcfg_pull_none>;
		};
	};
};