| // SPDX-License-Identifier: GPL-2.0+ |
| |
| #include <dt-bindings/memory/stm32-sdram.h> |
| /{ |
| soc { |
| bootph-all; |
| |
| fmc: fmc@A0000000 { |
| compatible = "st,stm32-fmc"; |
| reg = <0xa0000000 0x1000>; |
| clocks = <&rcc 0 STM32F7_AHB3_CLOCK(FMC)>; |
| pinctrl-0 = <&fmc_pins>; |
| pinctrl-names = "default"; |
| status = "okay"; |
| bootph-all; |
| }; |
| |
| mac: ethernet@40028000 { |
| compatible = "st,stm32-dwmac"; |
| reg = <0x40028000 0x8000>; |
| reg-names = "stmmaceth"; |
| clocks = <&rcc 0 STM32F7_AHB1_CLOCK(ETHMAC)>, |
| <&rcc 0 STM32F7_AHB1_CLOCK(ETHMACTX)>, |
| <&rcc 0 STM32F7_AHB1_CLOCK(ETHMACRX)>; |
| interrupts = <61>, <62>; |
| interrupt-names = "macirq", "eth_wake_irq"; |
| snps,pbl = <8>; |
| snps,mixed-burst; |
| pinctrl-0 = <ðernet_mii>; |
| phy-mode = "rmii"; |
| phy-handle = <&phy0>; |
| |
| status = "okay"; |
| |
| mdio0 { |
| #address-cells = <1>; |
| #size-cells = <0>; |
| compatible = "snps,dwmac-mdio"; |
| phy0: ethernet-phy@0 { |
| reg = <0>; |
| }; |
| }; |
| }; |
| |
| qspi: spi@A0001000 { |
| compatible = "st,stm32f469-qspi"; |
| #address-cells = <1>; |
| #size-cells = <0>; |
| reg = <0xa0001000 0x1000>, <0x90000000 0x10000000>; |
| reg-names = "qspi", "qspi_mm"; |
| interrupts = <92>; |
| spi-max-frequency = <108000000>; |
| clocks = <&rcc 0 STM32F7_AHB3_CLOCK(QSPI)>; |
| resets = <&rcc STM32F7_AHB3_RESET(QSPI)>; |
| pinctrl-0 = <&qspi_pins>; |
| |
| status = "okay"; |
| }; |
| }; |
| }; |
| |
| &clk_hse { |
| bootph-all; |
| }; |
| |
| &gpioa { |
| bootph-all; |
| }; |
| |
| &gpiob { |
| bootph-all; |
| }; |
| |
| &gpioc { |
| bootph-all; |
| }; |
| |
| &gpiod { |
| bootph-all; |
| }; |
| |
| &gpioe { |
| bootph-all; |
| }; |
| |
| &gpiof { |
| bootph-all; |
| }; |
| |
| &gpiog { |
| bootph-all; |
| }; |
| |
| &gpioh { |
| bootph-all; |
| }; |
| |
| &gpioi { |
| bootph-all; |
| }; |
| |
| &pinctrl { |
| bootph-all; |
| |
| fmc_pins: fmc@0 { |
| bootph-all; |
| pins |
| { |
| bootph-all; |
| }; |
| }; |
| }; |
| |
| &pwrcfg { |
| bootph-all; |
| }; |
| |
| &rcc { |
| bootph-all; |
| }; |
| |
| &timers5 { |
| bootph-all; |
| }; |
| |
| &usart1 { |
| bootph-all; |
| clocks = <&rcc 0 STM32F7_APB2_CLOCK(USART1)>; |
| }; |