| // SPDX-License-Identifier: GPL-2.0+ OR X11 |
| * NXP LX2162AQDS device tree source for the SERDES block #1 - protocol 17 |
| * Some assumptions are made: |
| * * mezzanine card M8 is connected to IO SLOT1 (25g-aui for DPMAC 3,4,5,6) |
| * Copyright 2020-2021 NXP |
| #include "fsl-lx2160a-qds.dtsi" |
| phy-handle = <&inphi_phy0>; |
| phy-connection-type = "25g-aui"; |
| phy-handle = <&inphi_phy1>; |
| phy-connection-type = "25g-aui"; |
| phy-handle = <&inphi_phy2>; |
| phy-connection-type = "25g-aui"; |
| phy-handle = <&inphi_phy3>; |
| phy-connection-type = "25g-aui"; |
| inphi_phy0: ethernet-phy@0 { |
| compatible = "ethernet-phy-id0210.7440"; |
| inphi_phy1: ethernet-phy@1 { |
| compatible = "ethernet-phy-id0210.7440"; |
| inphi_phy2: ethernet-phy@2 { |
| compatible = "ethernet-phy-id0210.7440"; |
| inphi_phy3: ethernet-phy@3 { |
| compatible = "ethernet-phy-id0210.7440"; |