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wdenk03f5c552004-10-10 21:21:55 +00001/*
2 * Copyright 2004 Freescale Semiconductor.
3 * Copyright 2002,2003, Motorola Inc.
4 *
5 * See file CREDITS for list of people who contributed to this
6 * project.
7 *
8 * This program is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU General Public License as
10 * published by the Free Software Foundation; either version 2 of
11 * the License, or (at your option) any later version.
12 *
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
17 *
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
21 * MA 02111-1307 USA
22 */
23
24#include <ppc_asm.tmpl>
25#include <ppc_defs.h>
26#include <asm/cache.h>
27#include <asm/mmu.h>
28#include <config.h>
29#include <mpc85xx.h>
30
31
32/*
33 * TLB0 and TLB1 Entries
34 *
35 * Out of reset, TLB1's Entry 0 maps the highest 4K for CCSRBAR.
36 * However, CCSRBAR is then relocated to CFG_CCSRBAR right after
37 * these TLB entries are established.
38 *
39 * The TLB entries for DDR are dynamically setup in spd_sdram()
40 * and use TLB1 Entries 8 through 15 as needed according to the
41 * size of DDR memory.
42 *
43 * MAS0: tlbsel, esel, nv
44 * MAS1: valid, iprot, tid, ts, tsize
45 * MAS2: epn, sharen, x0, x1, w, i, m, g, e
46 * MAS3: rpn, u0-u3, ux, sx, uw, sw, ur, sr
47 */
48
49#define entry_start \
50 mflr r1 ; \
51 bl 0f ;
52
53#define entry_end \
540: mflr r0 ; \
55 mtlr r1 ; \
56 blr ;
57
58
59 .section .bootpg, "ax"
60 .globl tlb1_entry
61tlb1_entry:
62 entry_start
63
64 /*
65 * Number of TLB0 and TLB1 entries in the following table
66 */
67 .long 13
68
69#if (CFG_CCSRBAR_DEFAULT != CFG_CCSRBAR)
70 /*
71 * TLB0 4K Non-cacheable, guarded
72 * 0xff700000 4K Initial CCSRBAR mapping
73 *
74 * This ends up at a TLB0 Index==0 entry, and must not collide
75 * with other TLB0 Entries.
76 */
77 .long TLB1_MAS0(0, 0, 0)
78 .long TLB1_MAS1(1, 0, 0, 0, 0)
79 .long TLB1_MAS2(E500_TLB_EPN(CFG_CCSRBAR_DEFAULT), 0,0,0,0,1,0,1,0)
80 .long TLB1_MAS3(E500_TLB_RPN(CFG_CCSRBAR_DEFAULT), 0,0,0,0,0,1,0,1,0,1)
81#else
82#error("Update the number of table entries in tlb1_entry")
83#endif
84
85 /*
86 * TLB0 16K Cacheable, non-guarded
87 * 0xd001_0000 16K Temporary Global data for initialization
88 *
89 * Use four 4K TLB0 entries. These entries must be cacheable
90 * as they provide the bootstrap memory before the memory
91 * controler and real memory have been configured.
92 *
93 * These entries end up at TLB0 Indicies 0x10, 0x14, 0x18 and 0x1c,
94 * and must not collide with other TLB0 entries.
95 */
96 .long TLB1_MAS0(0, 0, 0)
97 .long TLB1_MAS1(1, 0, 0, 0, 0)
98 .long TLB1_MAS2(E500_TLB_EPN(CFG_INIT_RAM_ADDR),
99 0,0,0,0,0,0,0,0)
100 .long TLB1_MAS3(E500_TLB_RPN(CFG_INIT_RAM_ADDR),
101 0,0,0,0,0,1,0,1,0,1)
102
103 .long TLB1_MAS0(0, 0, 0)
104 .long TLB1_MAS1(1, 0, 0, 0, 0)
105 .long TLB1_MAS2(E500_TLB_EPN(CFG_INIT_RAM_ADDR + 4 * 1024),
106 0,0,0,0,0,0,0,0)
107 .long TLB1_MAS3(E500_TLB_RPN(CFG_INIT_RAM_ADDR + 4 * 1024),
108 0,0,0,0,0,1,0,1,0,1)
109
110 .long TLB1_MAS0(0, 0, 0)
111 .long TLB1_MAS1(1, 0, 0, 0, 0)
112 .long TLB1_MAS2(E500_TLB_EPN(CFG_INIT_RAM_ADDR + 8 * 1024),
113 0,0,0,0,0,0,0,0)
114 .long TLB1_MAS3(E500_TLB_RPN(CFG_INIT_RAM_ADDR + 8 * 1024),
115 0,0,0,0,0,1,0,1,0,1)
116
117 .long TLB1_MAS0(0, 0, 0)
118 .long TLB1_MAS1(1, 0, 0, 0, 0)
119 .long TLB1_MAS2(E500_TLB_EPN(CFG_INIT_RAM_ADDR + 12 * 1024),
120 0,0,0,0,0,0,0,0)
121 .long TLB1_MAS3(E500_TLB_RPN(CFG_INIT_RAM_ADDR + 12 * 1024),
122 0,0,0,0,0,1,0,1,0,1)
123
124
125 /*
126 * TLB 0: 16M Non-cacheable, guarded
127 * 0xff000000 16M FLASH
128 * Out of reset this entry is only 4K.
129 */
130 .long TLB1_MAS0(1, 0, 0)
131 .long TLB1_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_16M)
132 .long TLB1_MAS2(E500_TLB_EPN(CFG_FLASH_BASE), 0,0,0,0,1,0,1,0)
133 .long TLB1_MAS3(E500_TLB_RPN(CFG_FLASH_BASE), 0,0,0,0,0,1,0,1,0,1)
134
135 /*
136 * TLB 1: 256M Non-cacheable, guarded
137 * 0x80000000 256M PCI1 MEM First half
138 */
139 .long TLB1_MAS0(1, 1, 0)
140 .long TLB1_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_256M)
141 .long TLB1_MAS2(E500_TLB_EPN(CFG_PCI1_MEM_BASE), 0,0,0,0,1,0,1,0)
142 .long TLB1_MAS3(E500_TLB_RPN(CFG_PCI1_MEM_BASE), 0,0,0,0,0,1,0,1,0,1)
143
144 /*
145 * TLB 2: 256M Non-cacheable, guarded
146 * 0x90000000 256M PCI1 MEM Second half
147 */
148 .long TLB1_MAS0(1, 2, 0)
149 .long TLB1_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_256M)
150 .long TLB1_MAS2(E500_TLB_EPN(CFG_PCI1_MEM_BASE + 0x10000000),
151 0,0,0,0,1,0,1,0)
152 .long TLB1_MAS3(E500_TLB_RPN(CFG_PCI1_MEM_BASE + 0x10000000),
153 0,0,0,0,0,1,0,1,0,1)
154
155 /*
156 * TLB 3: 256M Non-cacheable, guarded
157 * 0xa0000000 256M PCI2 MEM First half
158 */
159 .long TLB1_MAS0(1, 3, 0)
160 .long TLB1_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_256M)
161 .long TLB1_MAS2(E500_TLB_EPN(CFG_PCI2_MEM_BASE), 0,0,0,0,1,0,1,0)
162 .long TLB1_MAS3(E500_TLB_RPN(CFG_PCI2_MEM_BASE), 0,0,0,0,0,1,0,1,0,1)
163
164 /*
165 * TLB 4: 256M Non-cacheable, guarded
166 * 0xb0000000 256M PCI2 MEM Second half
167 */
168 .long TLB1_MAS0(1, 4, 0)
169 .long TLB1_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_256M)
170 .long TLB1_MAS2(E500_TLB_EPN(CFG_PCI2_MEM_BASE + 0x10000000),
171 0,0,0,0,1,0,1,0)
172 .long TLB1_MAS3(E500_TLB_RPN(CFG_PCI2_MEM_BASE + 0x10000000),
173 0,0,0,0,0,1,0,1,0,1)
174
175 /*
176 * TLB 5: 64M Non-cacheable, guarded
177 * 0xe000_0000 1M CCSRBAR
178 * 0xe200_0000 16M PCI1 IO
179 * 0xe300_0000 16M PCI2 IO
180 */
181 .long TLB1_MAS0(1, 5, 0)
182 .long TLB1_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_64M)
183 .long TLB1_MAS2(E500_TLB_EPN(CFG_CCSRBAR), 0,0,0,0,1,0,1,0)
184 .long TLB1_MAS3(E500_TLB_RPN(CFG_CCSRBAR), 0,0,0,0,0,1,0,1,0,1)
185
186 /*
187 * TLB 6: 64M Cacheable, non-guarded
188 * 0xf000_0000 64M LBC SDRAM
189 */
190 .long TLB1_MAS0(1, 6, 0)
191 .long TLB1_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_64M)
192 .long TLB1_MAS2(E500_TLB_EPN(CFG_LBC_SDRAM_BASE), 0,0,0,0,0,0,0,0)
193 .long TLB1_MAS3(E500_TLB_RPN(CFG_LBC_SDRAM_BASE), 0,0,0,0,0,1,0,1,0,1)
194
195 /*
196 * TLB 7: 1M Non-cacheable, guarded
197 * 0xf8000000 1M CADMUS registers
198 */
199 .long TLB1_MAS0(1, 7, 0)
200 .long TLB1_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_1M)
201 .long TLB1_MAS2(E500_TLB_EPN(CADMUS_BASE_ADDR), 0,0,0,0,1,0,1,0)
202 .long TLB1_MAS3(E500_TLB_RPN(CADMUS_BASE_ADDR), 0,0,0,0,0,1,0,1,0,1)
203
204 entry_end
205
206/*
207 * LAW(Local Access Window) configuration:
208 *
209 * 0x0000_0000 0x7fff_ffff DDR 2G
210 * 0x8000_0000 0x9fff_ffff PCI1 MEM 512M
211 * 0xa000_0000 0xbfff_ffff PCI2 MEM 512M
212 * 0xe000_0000 0xe000_ffff CCSR 1M
Matthew McClintockcbfc7ce2006-06-28 10:46:13 -0500213 * 0xe200_0000 0xe20f_ffff PCI1 IO 1M
214 * 0xe210_0000 0xe21f_ffff PCI2 IO 1M
wdenk03f5c552004-10-10 21:21:55 +0000215 * 0xf000_0000 0xf7ff_ffff SDRAM 128M
216 * 0xf800_0000 0xf80f_ffff NVRAM/CADMUS (*) 1M
217 * 0xff00_0000 0xff7f_ffff FLASH (2nd bank) 8M
218 * 0xff80_0000 0xffff_ffff FLASH (boot bank) 8M
219 *
220 * Notes:
221 * CCSRBAR and L2-as-SRAM don't need a configured Local Access Window.
222 * If flash is 8M at default position (last 8M), no LAW needed.
223 *
224 * The defines below are 1-off of the actual LAWAR0 usage.
225 * So LAWAR3 define uses the LAWAR4 register in the ECM.
226 */
227
228#define LAWBAR0 0
229#define LAWAR0 ((LAWAR_TRGT_IF_DDR | (LAWAR_SIZE & LAWAR_SIZE_128M)) & ~LAWAR_EN)
230
231#define LAWBAR1 ((CFG_PCI1_MEM_BASE>>12) & 0xfffff)
232#define LAWAR1 (LAWAR_EN | LAWAR_TRGT_IF_PCI1 | (LAWAR_SIZE & LAWAR_SIZE_512M))
233
234#define LAWBAR2 ((CFG_PCI2_MEM_BASE>>12) & 0xfffff)
235#define LAWAR2 (LAWAR_EN | LAWAR_TRGT_IF_PCI2 | (LAWAR_SIZE & LAWAR_SIZE_512M))
236
Matthew McClintockcbfc7ce2006-06-28 10:46:13 -0500237#define LAWBAR3 ((CFG_PCI1_IO_PHYS>>12) & 0xfffff)
238#define LAWAR3 (LAWAR_EN | LAWAR_TRGT_IF_PCI1 | (LAWAR_SIZE & LAWAR_SIZE_1M))
wdenk03f5c552004-10-10 21:21:55 +0000239
Matthew McClintockcbfc7ce2006-06-28 10:46:13 -0500240#define LAWBAR4 ((CFG_PCI2_IO_PHYS>>12) & 0xfffff)
241#define LAWAR4 (LAWAR_EN | LAWAR_TRGT_IF_PCI2 | (LAWAR_SIZE & LAWAR_SIZE_1M))
wdenk03f5c552004-10-10 21:21:55 +0000242
243/* LBC window - maps 256M 0xf0000000 -> 0xffffffff */
244#define LAWBAR5 ((CFG_LBC_SDRAM_BASE>>12) & 0xfffff)
245#define LAWAR5 (LAWAR_EN | LAWAR_TRGT_IF_LBC | (LAWAR_SIZE & LAWAR_SIZE_256M))
246
247 .section .bootpg, "ax"
248 .globl law_entry
249
250law_entry:
251 entry_start
252 .long 6
253 .long LAWBAR0,LAWAR0,LAWBAR1,LAWAR1,LAWBAR2,LAWAR2,LAWBAR3,LAWAR3
254 .long LAWBAR4,LAWAR4,LAWBAR5,LAWAR5
255 entry_end