blob: 59ea11cd6a073587b85f3d9f132f82833dfe478c [file] [log] [blame]
Reinhard Meyera61a8192010-09-12 16:23:49 +02001/*
2 * (C) Copyright 2010
3 * Reinhard Meyer, EMK Elektronik, reinhard.meyer@emk-elektronik.de
4 * Martin Krause, Martin.Krause@tqs.de
5 * reworked original enc28j60.c
6 *
Wolfgang Denk1a459662013-07-08 09:37:19 +02007 * SPDX-License-Identifier: GPL-2.0+
Reinhard Meyera61a8192010-09-12 16:23:49 +02008 */
9
10#include <common.h>
11#include <net.h>
12#include <spi.h>
13#include <malloc.h>
14#include <netdev.h>
15#include <miiphy.h>
16#include "enc28j60.h"
17
18/*
19 * IMPORTANT: spi_claim_bus() and spi_release_bus()
20 * are called at begin and end of each of the following functions:
21 * enc_miiphy_read(), enc_miiphy_write(), enc_write_hwaddr(),
22 * enc_init(), enc_recv(), enc_send(), enc_halt()
23 * ALL other functions assume that the bus has already been claimed!
Joe Hershberger1fd92db2015-04-08 01:41:06 -050024 * Since net_process_received_packet() might call enc_send() in return, the bus
25 * must be released, net_process_received_packet() called and claimed again.
Reinhard Meyera61a8192010-09-12 16:23:49 +020026 */
27
28/*
29 * Controller memory layout.
30 * We only allow 1 frame for transmission and reserve the rest
31 * for reception to handle as many broadcast packets as possible.
32 * Also use the memory from 0x0000 for receiver buffer. See errata pt. 5
33 * 0x0000 - 0x19ff 6656 bytes receive buffer
34 * 0x1a00 - 0x1fff 1536 bytes transmit buffer =
35 * control(1)+frame(1518)+status(7)+reserve(10).
36 */
37#define ENC_RX_BUF_START 0x0000
38#define ENC_RX_BUF_END 0x19ff
39#define ENC_TX_BUF_START 0x1a00
40#define ENC_TX_BUF_END 0x1fff
41#define ENC_MAX_FRM_LEN 1518
42#define RX_RESET_COUNTER 1000
43
44/*
45 * For non data transfer functions, like phy read/write, set hwaddr, init
46 * we do not need a full, time consuming init including link ready wait.
47 * This enum helps to bring the chip through the minimum necessary inits.
48 */
49enum enc_initstate {none=0, setupdone, linkready};
50typedef struct enc_device {
51 struct eth_device *dev; /* back pointer */
52 struct spi_slave *slave;
53 int rx_reset_counter;
54 u16 next_pointer;
55 u8 bank; /* current bank in enc28j60 */
56 enum enc_initstate initstate;
57} enc_dev_t;
58
59/*
60 * enc_bset: set bits in a common register
61 * enc_bclr: clear bits in a common register
62 *
63 * making the reg parameter u8 will give a compile time warning if the
64 * functions are called with a register not accessible in all Banks
65 */
66static void enc_bset(enc_dev_t *enc, const u8 reg, const u8 data)
67{
68 u8 dout[2];
69
70 dout[0] = CMD_BFS(reg);
71 dout[1] = data;
72 spi_xfer(enc->slave, 2 * 8, dout, NULL,
73 SPI_XFER_BEGIN | SPI_XFER_END);
74}
75
76static void enc_bclr(enc_dev_t *enc, const u8 reg, const u8 data)
77{
78 u8 dout[2];
79
80 dout[0] = CMD_BFC(reg);
81 dout[1] = data;
82 spi_xfer(enc->slave, 2 * 8, dout, NULL,
83 SPI_XFER_BEGIN | SPI_XFER_END);
84}
85
86/*
87 * high byte of the register contains bank number:
88 * 0: no bank switch necessary
89 * 1: switch to bank 0
90 * 2: switch to bank 1
91 * 3: switch to bank 2
92 * 4: switch to bank 3
93 */
94static void enc_set_bank(enc_dev_t *enc, const u16 reg)
95{
96 u8 newbank = reg >> 8;
97
98 if (newbank == 0 || newbank == enc->bank)
99 return;
100 switch (newbank) {
101 case 1:
102 enc_bclr(enc, CTL_REG_ECON1,
103 ENC_ECON1_BSEL0 | ENC_ECON1_BSEL1);
104 break;
105 case 2:
106 enc_bset(enc, CTL_REG_ECON1, ENC_ECON1_BSEL0);
107 enc_bclr(enc, CTL_REG_ECON1, ENC_ECON1_BSEL1);
108 break;
109 case 3:
110 enc_bclr(enc, CTL_REG_ECON1, ENC_ECON1_BSEL0);
111 enc_bset(enc, CTL_REG_ECON1, ENC_ECON1_BSEL1);
112 break;
113 case 4:
114 enc_bset(enc, CTL_REG_ECON1,
115 ENC_ECON1_BSEL0 | ENC_ECON1_BSEL1);
116 break;
117 }
118 enc->bank = newbank;
119}
120
121/*
122 * local functions to access SPI
123 *
124 * reg: register inside ENC28J60
125 * data: 8/16 bits to write
126 * c: number of retries
127 *
128 * enc_r8: read 8 bits
129 * enc_r16: read 16 bits
130 * enc_w8: write 8 bits
131 * enc_w16: write 16 bits
132 * enc_w8_retry: write 8 bits, verify and retry
133 * enc_rbuf: read from ENC28J60 into buffer
134 * enc_wbuf: write from buffer into ENC28J60
135 */
136
137/*
138 * MAC and MII registers need a 3 byte SPI transfer to read,
139 * all other registers need a 2 byte SPI transfer.
140 */
141static int enc_reg2nbytes(const u16 reg)
142{
143 /* check if MAC or MII register */
144 return ((reg >= CTL_REG_MACON1 && reg <= CTL_REG_MIRDH) ||
145 (reg >= CTL_REG_MAADR1 && reg <= CTL_REG_MAADR4) ||
146 (reg == CTL_REG_MISTAT)) ? 3 : 2;
147}
148
149/*
150 * Read a byte register
151 */
152static u8 enc_r8(enc_dev_t *enc, const u16 reg)
153{
154 u8 dout[3];
155 u8 din[3];
156 int nbytes = enc_reg2nbytes(reg);
157
158 enc_set_bank(enc, reg);
159 dout[0] = CMD_RCR(reg);
160 spi_xfer(enc->slave, nbytes * 8, dout, din,
161 SPI_XFER_BEGIN | SPI_XFER_END);
162 return din[nbytes-1];
163}
164
165/*
166 * Read a L/H register pair and return a word.
167 * Must be called with the L register's address.
168 */
169static u16 enc_r16(enc_dev_t *enc, const u16 reg)
170{
171 u8 dout[3];
172 u8 din[3];
173 u16 result;
174 int nbytes = enc_reg2nbytes(reg);
175
176 enc_set_bank(enc, reg);
177 dout[0] = CMD_RCR(reg);
178 spi_xfer(enc->slave, nbytes * 8, dout, din,
179 SPI_XFER_BEGIN | SPI_XFER_END);
180 result = din[nbytes-1];
181 dout[0]++; /* next register */
182 spi_xfer(enc->slave, nbytes * 8, dout, din,
183 SPI_XFER_BEGIN | SPI_XFER_END);
184 result |= din[nbytes-1] << 8;
185 return result;
186}
187
188/*
189 * Write a byte register
190 */
191static void enc_w8(enc_dev_t *enc, const u16 reg, const u8 data)
192{
193 u8 dout[2];
194
195 enc_set_bank(enc, reg);
196 dout[0] = CMD_WCR(reg);
197 dout[1] = data;
198 spi_xfer(enc->slave, 2 * 8, dout, NULL,
199 SPI_XFER_BEGIN | SPI_XFER_END);
200}
201
202/*
203 * Write a L/H register pair.
204 * Must be called with the L register's address.
205 */
206static void enc_w16(enc_dev_t *enc, const u16 reg, const u16 data)
207{
208 u8 dout[2];
209
210 enc_set_bank(enc, reg);
211 dout[0] = CMD_WCR(reg);
212 dout[1] = data;
213 spi_xfer(enc->slave, 2 * 8, dout, NULL,
214 SPI_XFER_BEGIN | SPI_XFER_END);
215 dout[0]++; /* next register */
216 dout[1] = data >> 8;
217 spi_xfer(enc->slave, 2 * 8, dout, NULL,
218 SPI_XFER_BEGIN | SPI_XFER_END);
219}
220
221/*
222 * Write a byte register, verify and retry
223 */
224static void enc_w8_retry(enc_dev_t *enc, const u16 reg, const u8 data, const int c)
225{
226 u8 dout[2];
227 u8 readback;
228 int i;
229
230 enc_set_bank(enc, reg);
231 for (i = 0; i < c; i++) {
232 dout[0] = CMD_WCR(reg);
233 dout[1] = data;
234 spi_xfer(enc->slave, 2 * 8, dout, NULL,
235 SPI_XFER_BEGIN | SPI_XFER_END);
236 readback = enc_r8(enc, reg);
237 if (readback == data)
238 break;
239 /* wait 1ms */
240 udelay(1000);
241 }
242 if (i == c) {
243 printf("%s: write reg 0x%03x failed\n", enc->dev->name, reg);
244 }
245}
246
247/*
248 * Read ENC RAM into buffer
249 */
250static void enc_rbuf(enc_dev_t *enc, const u16 length, u8 *buf)
251{
252 u8 dout[1];
253
254 dout[0] = CMD_RBM;
255 spi_xfer(enc->slave, 8, dout, NULL, SPI_XFER_BEGIN);
256 spi_xfer(enc->slave, length * 8, NULL, buf, SPI_XFER_END);
257#ifdef DEBUG
258 puts("Rx:\n");
259 print_buffer(0, buf, 1, length, 0);
260#endif
261}
262
263/*
264 * Write buffer into ENC RAM
265 */
266static void enc_wbuf(enc_dev_t *enc, const u16 length, const u8 *buf, const u8 control)
267{
268 u8 dout[2];
269 dout[0] = CMD_WBM;
270 dout[1] = control;
271 spi_xfer(enc->slave, 2 * 8, dout, NULL, SPI_XFER_BEGIN);
272 spi_xfer(enc->slave, length * 8, buf, NULL, SPI_XFER_END);
273#ifdef DEBUG
274 puts("Tx:\n");
275 print_buffer(0, buf, 1, length, 0);
276#endif
277}
278
279/*
280 * Try to claim the SPI bus.
281 * Print error message on failure.
282 */
283static int enc_claim_bus(enc_dev_t *enc)
284{
285 int rc = spi_claim_bus(enc->slave);
286 if (rc)
287 printf("%s: failed to claim SPI bus\n", enc->dev->name);
288 return rc;
289}
290
291/*
292 * Release previously claimed SPI bus.
293 * This function is mainly for symmetry to enc_claim_bus().
294 * Let the toolchain decide to inline it...
295 */
296static void enc_release_bus(enc_dev_t *enc)
297{
298 spi_release_bus(enc->slave);
299}
300
301/*
302 * Read PHY register
303 */
Andy Fleming09c04c22011-03-22 22:49:13 -0500304static u16 enc_phy_read(enc_dev_t *enc, const u8 addr)
Reinhard Meyera61a8192010-09-12 16:23:49 +0200305{
306 uint64_t etime;
307 u8 status;
308
309 enc_w8(enc, CTL_REG_MIREGADR, addr);
310 enc_w8(enc, CTL_REG_MICMD, ENC_MICMD_MIIRD);
311 /* 1 second timeout - only happens on hardware problem */
312 etime = get_ticks() + get_tbclk();
313 /* poll MISTAT.BUSY bit until operation is complete */
314 do
315 {
316 status = enc_r8(enc, CTL_REG_MISTAT);
317 } while (get_ticks() <= etime && (status & ENC_MISTAT_BUSY));
318 if (status & ENC_MISTAT_BUSY) {
319 printf("%s: timeout reading phy\n", enc->dev->name);
320 return 0;
321 }
322 enc_w8(enc, CTL_REG_MICMD, 0);
323 return enc_r16(enc, CTL_REG_MIRDL);
324}
325
326/*
327 * Write PHY register
328 */
Andy Fleming09c04c22011-03-22 22:49:13 -0500329static void enc_phy_write(enc_dev_t *enc, const u8 addr, const u16 data)
Reinhard Meyera61a8192010-09-12 16:23:49 +0200330{
331 uint64_t etime;
332 u8 status;
333
334 enc_w8(enc, CTL_REG_MIREGADR, addr);
335 enc_w16(enc, CTL_REG_MIWRL, data);
336 /* 1 second timeout - only happens on hardware problem */
337 etime = get_ticks() + get_tbclk();
338 /* poll MISTAT.BUSY bit until operation is complete */
339 do
340 {
341 status = enc_r8(enc, CTL_REG_MISTAT);
342 } while (get_ticks() <= etime && (status & ENC_MISTAT_BUSY));
343 if (status & ENC_MISTAT_BUSY) {
344 printf("%s: timeout writing phy\n", enc->dev->name);
345 return;
346 }
347}
348
349/*
350 * Verify link status, wait if necessary
351 *
352 * Note: with a 10 MBit/s only PHY there is no autonegotiation possible,
353 * half/full duplex is a pure setup matter. For the time being, this driver
354 * will setup in half duplex mode only.
355 */
356static int enc_phy_link_wait(enc_dev_t *enc)
357{
358 u16 status;
359 int duplex;
360 uint64_t etime;
361
362#ifdef CONFIG_ENC_SILENTLINK
363 /* check if we have a link, then just return */
Andy Fleming09c04c22011-03-22 22:49:13 -0500364 status = enc_phy_read(enc, PHY_REG_PHSTAT1);
Reinhard Meyera61a8192010-09-12 16:23:49 +0200365 if (status & ENC_PHSTAT1_LLSTAT)
366 return 0;
367#endif
368
369 /* wait for link with 1 second timeout */
370 etime = get_ticks() + get_tbclk();
371 while (get_ticks() <= etime) {
Andy Fleming09c04c22011-03-22 22:49:13 -0500372 status = enc_phy_read(enc, PHY_REG_PHSTAT1);
Reinhard Meyera61a8192010-09-12 16:23:49 +0200373 if (status & ENC_PHSTAT1_LLSTAT) {
374 /* now we have a link */
Andy Fleming09c04c22011-03-22 22:49:13 -0500375 status = enc_phy_read(enc, PHY_REG_PHSTAT2);
Reinhard Meyera61a8192010-09-12 16:23:49 +0200376 duplex = (status & ENC_PHSTAT2_DPXSTAT) ? 1 : 0;
377 printf("%s: link up, 10Mbps %s-duplex\n",
378 enc->dev->name, duplex ? "full" : "half");
379 return 0;
380 }
381 udelay(1000);
382 }
383
384 /* timeout occured */
385 printf("%s: link down\n", enc->dev->name);
386 return 1;
387}
388
389/*
390 * This function resets the receiver only.
391 */
392static void enc_reset_rx(enc_dev_t *enc)
393{
394 u8 econ1;
395
396 econ1 = enc_r8(enc, CTL_REG_ECON1);
397 if ((econ1 & ENC_ECON1_RXRST) == 0) {
398 enc_bset(enc, CTL_REG_ECON1, ENC_ECON1_RXRST);
399 enc->rx_reset_counter = RX_RESET_COUNTER;
400 }
401}
402
403/*
404 * Reset receiver and reenable it.
405 */
406static void enc_reset_rx_call(enc_dev_t *enc)
407{
408 enc_bclr(enc, CTL_REG_ECON1, ENC_ECON1_RXRST);
409 enc_bset(enc, CTL_REG_ECON1, ENC_ECON1_RXEN);
410}
411
412/*
413 * Copy a packet from the receive ring and forward it to
414 * the protocol stack.
415 */
416static void enc_receive(enc_dev_t *enc)
417{
Joe Hershberger1fd92db2015-04-08 01:41:06 -0500418 u8 *packet = (u8 *)net_rx_packets[0];
Reinhard Meyera61a8192010-09-12 16:23:49 +0200419 u16 pkt_len;
420 u16 copy_len;
421 u16 status;
Reinhard Meyera61a8192010-09-12 16:23:49 +0200422 u8 pkt_cnt = 0;
423 u16 rxbuf_rdpt;
424 u8 hbuf[6];
425
426 enc_w16(enc, CTL_REG_ERDPTL, enc->next_pointer);
427 do {
428 enc_rbuf(enc, 6, hbuf);
429 enc->next_pointer = hbuf[0] | (hbuf[1] << 8);
430 pkt_len = hbuf[2] | (hbuf[3] << 8);
431 status = hbuf[4] | (hbuf[5] << 8);
432 debug("next_pointer=$%04x pkt_len=%u status=$%04x\n",
433 enc->next_pointer, pkt_len, status);
434 if (pkt_len <= ENC_MAX_FRM_LEN)
435 copy_len = pkt_len;
436 else
437 copy_len = 0;
438 if ((status & (1L << 7)) == 0) /* check Received Ok bit */
439 copy_len = 0;
440 /* check if next pointer is resonable */
441 if (enc->next_pointer >= ENC_TX_BUF_START)
442 copy_len = 0;
443 if (copy_len > 0) {
444 enc_rbuf(enc, copy_len, packet);
445 }
446 /* advance read pointer to next pointer */
447 enc_w16(enc, CTL_REG_ERDPTL, enc->next_pointer);
448 /* decrease packet counter */
449 enc_bset(enc, CTL_REG_ECON2, ENC_ECON2_PKTDEC);
450 /*
451 * Only odd values should be written to ERXRDPTL,
452 * see errata B4 pt.13
453 */
454 rxbuf_rdpt = enc->next_pointer - 1;
455 if ((rxbuf_rdpt < enc_r16(enc, CTL_REG_ERXSTL)) ||
456 (rxbuf_rdpt > enc_r16(enc, CTL_REG_ERXNDL))) {
457 enc_w16(enc, CTL_REG_ERXRDPTL,
458 enc_r16(enc, CTL_REG_ERXNDL));
459 } else {
460 enc_w16(enc, CTL_REG_ERXRDPTL, rxbuf_rdpt);
461 }
462 /* read pktcnt */
463 pkt_cnt = enc_r8(enc, CTL_REG_EPKTCNT);
464 if (copy_len == 0) {
Anatolij Gustschinda540662011-11-15 13:20:55 +0000465 (void)enc_r8(enc, CTL_REG_EIR);
Reinhard Meyera61a8192010-09-12 16:23:49 +0200466 enc_reset_rx(enc);
467 printf("%s: receive copy_len=0\n", enc->dev->name);
468 continue;
469 }
470 /*
Joe Hershberger1fd92db2015-04-08 01:41:06 -0500471 * Because net_process_received_packet() might call enc_send(),
472 * we need to release the SPI bus, call
473 * net_process_received_packet(), reclaim the bus.
Reinhard Meyera61a8192010-09-12 16:23:49 +0200474 */
475 enc_release_bus(enc);
Joe Hershberger1fd92db2015-04-08 01:41:06 -0500476 net_process_received_packet(packet, pkt_len);
Reinhard Meyera61a8192010-09-12 16:23:49 +0200477 if (enc_claim_bus(enc))
478 return;
Anatolij Gustschinda540662011-11-15 13:20:55 +0000479 (void)enc_r8(enc, CTL_REG_EIR);
Reinhard Meyera61a8192010-09-12 16:23:49 +0200480 } while (pkt_cnt);
481 /* Use EPKTCNT not EIR.PKTIF flag, see errata pt. 6 */
482}
483
484/*
485 * Poll for completely received packets.
486 */
487static void enc_poll(enc_dev_t *enc)
488{
489 u8 eir_reg;
Reinhard Meyera61a8192010-09-12 16:23:49 +0200490 u8 pkt_cnt;
491
492#ifdef CONFIG_USE_IRQ
493 /* clear global interrupt enable bit in enc28j60 */
494 enc_bclr(enc, CTL_REG_EIE, ENC_EIE_INTIE);
495#endif
Anatolij Gustschinda540662011-11-15 13:20:55 +0000496 (void)enc_r8(enc, CTL_REG_ESTAT);
Reinhard Meyera61a8192010-09-12 16:23:49 +0200497 eir_reg = enc_r8(enc, CTL_REG_EIR);
498 if (eir_reg & ENC_EIR_TXIF) {
499 /* clear TXIF bit in EIR */
500 enc_bclr(enc, CTL_REG_EIR, ENC_EIR_TXIF);
501 }
502 /* We have to use pktcnt and not pktif bit, see errata pt. 6 */
503 pkt_cnt = enc_r8(enc, CTL_REG_EPKTCNT);
504 if (pkt_cnt > 0) {
505 if ((eir_reg & ENC_EIR_PKTIF) == 0) {
506 debug("enc_poll: pkt cnt > 0, but pktif not set\n");
507 }
508 enc_receive(enc);
509 /*
510 * clear PKTIF bit in EIR, this should not need to be done
511 * but it seems like we get problems if we do not
512 */
513 enc_bclr(enc, CTL_REG_EIR, ENC_EIR_PKTIF);
514 }
515 if (eir_reg & ENC_EIR_RXERIF) {
516 printf("%s: rx error\n", enc->dev->name);
517 enc_bclr(enc, CTL_REG_EIR, ENC_EIR_RXERIF);
518 }
519 if (eir_reg & ENC_EIR_TXERIF) {
520 printf("%s: tx error\n", enc->dev->name);
521 enc_bclr(enc, CTL_REG_EIR, ENC_EIR_TXERIF);
522 }
523#ifdef CONFIG_USE_IRQ
524 /* set global interrupt enable bit in enc28j60 */
525 enc_bset(enc, CTL_REG_EIE, ENC_EIE_INTIE);
526#endif
527}
528
529/*
530 * Completely Reset the ENC
531 */
532static void enc_reset(enc_dev_t *enc)
533{
534 u8 dout[1];
535
536 dout[0] = CMD_SRC;
537 spi_xfer(enc->slave, 8, dout, NULL,
538 SPI_XFER_BEGIN | SPI_XFER_END);
539 /* sleep 1 ms. See errata pt. 2 */
540 udelay(1000);
541}
542
543/*
544 * Initialisation data for most of the ENC registers
545 */
546static const u16 enc_initdata[] = {
547 /*
548 * Setup the buffer space. The reset values are valid for the
549 * other pointers.
550 *
551 * We shall not write to ERXST, see errata pt. 5. Instead we
552 * have to make sure that ENC_RX_BUS_START is 0.
553 */
554 CTL_REG_ERXSTL, ENC_RX_BUF_START,
555 CTL_REG_ERXSTH, ENC_RX_BUF_START >> 8,
556 CTL_REG_ERXNDL, ENC_RX_BUF_END,
557 CTL_REG_ERXNDH, ENC_RX_BUF_END >> 8,
558 CTL_REG_ERDPTL, ENC_RX_BUF_START,
559 CTL_REG_ERDPTH, ENC_RX_BUF_START >> 8,
560 /*
561 * Set the filter to receive only good-CRC, unicast and broadcast
562 * frames.
563 * Note: some DHCP servers return their answers as broadcasts!
564 * So its unwise to remove broadcast from this. This driver
565 * might incur receiver overruns with packet loss on a broadcast
566 * flooded network.
567 */
568 CTL_REG_ERXFCON, ENC_RFR_BCEN | ENC_RFR_UCEN | ENC_RFR_CRCEN,
569
570 /* enable MAC to receive frames */
571 CTL_REG_MACON1,
572 ENC_MACON1_MARXEN | ENC_MACON1_TXPAUS | ENC_MACON1_RXPAUS,
573
574 /* configure pad, tx-crc and duplex */
575 CTL_REG_MACON3,
576 ENC_MACON3_PADCFG0 | ENC_MACON3_TXCRCEN |
577 ENC_MACON3_FRMLNEN,
578
579 /* Allow infinite deferals if the medium is continously busy */
580 CTL_REG_MACON4, ENC_MACON4_DEFER,
581
582 /* Late collisions occur beyond 63 bytes */
583 CTL_REG_MACLCON2, 63,
584
585 /*
586 * Set (low byte) Non-Back-to_Back Inter-Packet Gap.
587 * Recommended 0x12
588 */
589 CTL_REG_MAIPGL, 0x12,
590
591 /*
592 * Set (high byte) Non-Back-to_Back Inter-Packet Gap.
593 * Recommended 0x0c for half-duplex. Nothing for full-duplex
594 */
595 CTL_REG_MAIPGH, 0x0C,
596
597 /* set maximum frame length */
598 CTL_REG_MAMXFLL, ENC_MAX_FRM_LEN,
599 CTL_REG_MAMXFLH, ENC_MAX_FRM_LEN >> 8,
600
601 /*
602 * Set MAC back-to-back inter-packet gap.
603 * Recommended 0x12 for half duplex
604 * and 0x15 for full duplex.
605 */
606 CTL_REG_MABBIPG, 0x12,
607
608 /* end of table */
609 0xffff
610};
611
612/*
613 * Wait for the XTAL oscillator to become ready
614 */
615static int enc_clock_wait(enc_dev_t *enc)
616{
617 uint64_t etime;
618
619 /* one second timeout */
620 etime = get_ticks() + get_tbclk();
621
622 /*
623 * Wait for CLKRDY to become set (i.e., check that we can
624 * communicate with the ENC)
625 */
626 do
627 {
628 if (enc_r8(enc, CTL_REG_ESTAT) & ENC_ESTAT_CLKRDY)
629 return 0;
630 } while (get_ticks() <= etime);
631
632 printf("%s: timeout waiting for CLKRDY\n", enc->dev->name);
633 return -1;
634}
635
636/*
637 * Write the MAC address into the ENC
638 */
639static int enc_write_macaddr(enc_dev_t *enc)
640{
641 unsigned char *p = enc->dev->enetaddr;
642
643 enc_w8_retry(enc, CTL_REG_MAADR5, *p++, 5);
644 enc_w8_retry(enc, CTL_REG_MAADR4, *p++, 5);
645 enc_w8_retry(enc, CTL_REG_MAADR3, *p++, 5);
646 enc_w8_retry(enc, CTL_REG_MAADR2, *p++, 5);
647 enc_w8_retry(enc, CTL_REG_MAADR1, *p++, 5);
648 enc_w8_retry(enc, CTL_REG_MAADR0, *p, 5);
649 return 0;
650}
651
652/*
653 * Setup most of the ENC registers
654 */
655static int enc_setup(enc_dev_t *enc)
656{
657 u16 phid1 = 0;
658 u16 phid2 = 0;
659 const u16 *tp;
660
661 /* reset enc struct values */
662 enc->next_pointer = ENC_RX_BUF_START;
663 enc->rx_reset_counter = RX_RESET_COUNTER;
664 enc->bank = 0xff; /* invalidate current bank in enc28j60 */
665
666 /* verify PHY identification */
Andy Fleming09c04c22011-03-22 22:49:13 -0500667 phid1 = enc_phy_read(enc, PHY_REG_PHID1);
668 phid2 = enc_phy_read(enc, PHY_REG_PHID2) & ENC_PHID2_MASK;
Reinhard Meyera61a8192010-09-12 16:23:49 +0200669 if (phid1 != ENC_PHID1_VALUE || phid2 != ENC_PHID2_VALUE) {
670 printf("%s: failed to identify PHY. Found %04x:%04x\n",
671 enc->dev->name, phid1, phid2);
672 return -1;
673 }
674
675 /* now program registers */
676 for (tp = enc_initdata; *tp != 0xffff; tp += 2)
677 enc_w8_retry(enc, tp[0], tp[1], 10);
678
679 /*
680 * Prevent automatic loopback of data beeing transmitted by setting
681 * ENC_PHCON2_HDLDIS
682 */
Andy Fleming09c04c22011-03-22 22:49:13 -0500683 enc_phy_write(enc, PHY_REG_PHCON2, (1<<8));
Reinhard Meyera61a8192010-09-12 16:23:49 +0200684
685 /*
686 * LEDs configuration
687 * LEDA: LACFG = 0100 -> display link status
688 * LEDB: LBCFG = 0111 -> display TX & RX activity
689 * STRCH = 1 -> LED pulses
690 */
Andy Fleming09c04c22011-03-22 22:49:13 -0500691 enc_phy_write(enc, PHY_REG_PHLCON, 0x0472);
Reinhard Meyera61a8192010-09-12 16:23:49 +0200692
693 /* Reset PDPXMD-bit => half duplex */
Andy Fleming09c04c22011-03-22 22:49:13 -0500694 enc_phy_write(enc, PHY_REG_PHCON1, 0);
Reinhard Meyera61a8192010-09-12 16:23:49 +0200695
696#ifdef CONFIG_USE_IRQ
697 /* enable interrupts */
698 enc_bset(enc, CTL_REG_EIE, ENC_EIE_PKTIE);
699 enc_bset(enc, CTL_REG_EIE, ENC_EIE_TXIE);
700 enc_bset(enc, CTL_REG_EIE, ENC_EIE_RXERIE);
701 enc_bset(enc, CTL_REG_EIE, ENC_EIE_TXERIE);
702 enc_bset(enc, CTL_REG_EIE, ENC_EIE_INTIE);
703#endif
704
705 return 0;
706}
707
708/*
709 * Check if ENC has been initialized.
710 * If not, try to initialize it.
711 * Remember initialized state in struct.
712 */
713static int enc_initcheck(enc_dev_t *enc, const enum enc_initstate requiredstate)
714{
715 if (enc->initstate >= requiredstate)
716 return 0;
717
718 if (enc->initstate < setupdone) {
719 /* Initialize the ENC only */
720 enc_reset(enc);
721 /* if any of functions fails, skip the rest and return an error */
722 if (enc_clock_wait(enc) || enc_setup(enc) || enc_write_macaddr(enc)) {
723 return -1;
724 }
725 enc->initstate = setupdone;
726 }
727 /* if that's all we need, return here */
728 if (enc->initstate >= requiredstate)
729 return 0;
730
731 /* now wait for link ready condition */
732 if (enc_phy_link_wait(enc)) {
733 return -1;
734 }
735 enc->initstate = linkready;
736 return 0;
737}
738
739#if defined(CONFIG_CMD_MII)
740/*
741 * Read a PHY register.
742 *
743 * This function is registered with miiphy_register().
744 */
745int enc_miiphy_read(const char *devname, u8 phy_adr, u8 reg, u16 *value)
746{
747 struct eth_device *dev = eth_get_dev_by_name(devname);
748 enc_dev_t *enc;
749
750 if (!dev || phy_adr != 0)
751 return -1;
752
753 enc = dev->priv;
754 if (enc_claim_bus(enc))
755 return -1;
756 if (enc_initcheck(enc, setupdone)) {
757 enc_release_bus(enc);
758 return -1;
759 }
Andy Fleming09c04c22011-03-22 22:49:13 -0500760 *value = enc_phy_read(enc, reg);
Reinhard Meyera61a8192010-09-12 16:23:49 +0200761 enc_release_bus(enc);
762 return 0;
763}
764
765/*
766 * Write a PHY register.
767 *
768 * This function is registered with miiphy_register().
769 */
770int enc_miiphy_write(const char *devname, u8 phy_adr, u8 reg, u16 value)
771{
772 struct eth_device *dev = eth_get_dev_by_name(devname);
773 enc_dev_t *enc;
774
775 if (!dev || phy_adr != 0)
776 return -1;
777
778 enc = dev->priv;
779 if (enc_claim_bus(enc))
780 return -1;
781 if (enc_initcheck(enc, setupdone)) {
782 enc_release_bus(enc);
783 return -1;
784 }
Andy Fleming09c04c22011-03-22 22:49:13 -0500785 enc_phy_write(enc, reg, value);
Reinhard Meyera61a8192010-09-12 16:23:49 +0200786 enc_release_bus(enc);
787 return 0;
788}
789#endif
790
791/*
792 * Write hardware (MAC) address.
793 *
794 * This function entered into eth_device structure.
795 */
796static int enc_write_hwaddr(struct eth_device *dev)
797{
798 enc_dev_t *enc = dev->priv;
799
800 if (enc_claim_bus(enc))
801 return -1;
802 if (enc_initcheck(enc, setupdone)) {
803 enc_release_bus(enc);
804 return -1;
805 }
806 enc_release_bus(enc);
807 return 0;
808}
809
810/*
811 * Initialize ENC28J60 for use.
812 *
813 * This function entered into eth_device structure.
814 */
815static int enc_init(struct eth_device *dev, bd_t *bis)
816{
817 enc_dev_t *enc = dev->priv;
818
819 if (enc_claim_bus(enc))
820 return -1;
821 if (enc_initcheck(enc, linkready)) {
822 enc_release_bus(enc);
823 return -1;
824 }
825 /* enable receive */
826 enc_bset(enc, CTL_REG_ECON1, ENC_ECON1_RXEN);
827 enc_release_bus(enc);
828 return 0;
829}
830
831/*
832 * Check for received packets.
833 *
834 * This function entered into eth_device structure.
835 */
836static int enc_recv(struct eth_device *dev)
837{
838 enc_dev_t *enc = dev->priv;
839
840 if (enc_claim_bus(enc))
841 return -1;
842 if (enc_initcheck(enc, linkready)) {
843 enc_release_bus(enc);
844 return -1;
845 }
846 /* Check for dead receiver */
847 if (enc->rx_reset_counter > 0)
848 enc->rx_reset_counter--;
849 else
850 enc_reset_rx_call(enc);
851 enc_poll(enc);
852 enc_release_bus(enc);
853 return 0;
854}
855
856/*
857 * Send a packet.
858 *
859 * This function entered into eth_device structure.
860 *
861 * Should we wait here until we have a Link? Or shall we leave that to
862 * protocol retries?
863 */
864static int enc_send(
865 struct eth_device *dev,
Joe Hershbergerb58cab32012-05-21 14:45:26 +0000866 void *packet,
Reinhard Meyera61a8192010-09-12 16:23:49 +0200867 int length)
868{
869 enc_dev_t *enc = dev->priv;
870
871 if (enc_claim_bus(enc))
872 return -1;
873 if (enc_initcheck(enc, linkready)) {
874 enc_release_bus(enc);
875 return -1;
876 }
877 /* setup transmit pointers */
878 enc_w16(enc, CTL_REG_EWRPTL, ENC_TX_BUF_START);
879 enc_w16(enc, CTL_REG_ETXNDL, length + ENC_TX_BUF_START);
880 enc_w16(enc, CTL_REG_ETXSTL, ENC_TX_BUF_START);
881 /* write packet to ENC */
882 enc_wbuf(enc, length, (u8 *) packet, 0x00);
883 /*
884 * Check that the internal transmit logic has not been altered
885 * by excessive collisions. Reset transmitter if so.
886 * See Errata B4 12 and 14.
887 */
888 if (enc_r8(enc, CTL_REG_EIR) & ENC_EIR_TXERIF) {
889 enc_bset(enc, CTL_REG_ECON1, ENC_ECON1_TXRST);
890 enc_bclr(enc, CTL_REG_ECON1, ENC_ECON1_TXRST);
891 }
892 enc_bclr(enc, CTL_REG_EIR, (ENC_EIR_TXERIF | ENC_EIR_TXIF));
893 /* start transmitting */
894 enc_bset(enc, CTL_REG_ECON1, ENC_ECON1_TXRTS);
895 enc_release_bus(enc);
896 return 0;
897}
898
899/*
900 * Finish use of ENC.
901 *
902 * This function entered into eth_device structure.
903 */
904static void enc_halt(struct eth_device *dev)
905{
906 enc_dev_t *enc = dev->priv;
907
908 if (enc_claim_bus(enc))
909 return;
910 /* Just disable receiver */
911 enc_bclr(enc, CTL_REG_ECON1, ENC_ECON1_RXEN);
912 enc_release_bus(enc);
913}
914
915/*
916 * This is the only exported function.
917 *
918 * It may be called several times with different bus:cs combinations.
919 */
920int enc28j60_initialize(unsigned int bus, unsigned int cs,
921 unsigned int max_hz, unsigned int mode)
922{
923 struct eth_device *dev;
924 enc_dev_t *enc;
925
926 /* try to allocate, check and clear eth_device object */
927 dev = malloc(sizeof(*dev));
928 if (!dev) {
929 return -1;
930 }
931 memset(dev, 0, sizeof(*dev));
932
933 /* try to allocate, check and clear enc_dev_t object */
934 enc = malloc(sizeof(*enc));
935 if (!enc) {
936 free(dev);
937 return -1;
938 }
939 memset(enc, 0, sizeof(*enc));
940
941 /* try to setup the SPI slave */
942 enc->slave = spi_setup_slave(bus, cs, max_hz, mode);
943 if (!enc->slave) {
944 printf("enc28j60: invalid SPI device %i:%i\n", bus, cs);
945 free(enc);
946 free(dev);
947 return -1;
948 }
949
950 enc->dev = dev;
951 /* now fill the eth_device object */
952 dev->priv = enc;
953 dev->init = enc_init;
954 dev->halt = enc_halt;
955 dev->send = enc_send;
956 dev->recv = enc_recv;
957 dev->write_hwaddr = enc_write_hwaddr;
958 sprintf(dev->name, "enc%i.%i", bus, cs);
959 eth_register(dev);
960#if defined(CONFIG_CMD_MII)
961 miiphy_register(dev->name, enc_miiphy_read, enc_miiphy_write);
962#endif
963 return 0;
964}