wdenk | 2262cfe | 2002-11-18 00:14:45 +0000 | [diff] [blame] | 1 | /* |
| 2 | * (C) Copyright 2002 |
Albert ARIBAUD | fa82f87 | 2011-08-04 18:45:45 +0200 | [diff] [blame] | 3 | * Daniel Engström, Omicron Ceti AB, daniel@omicron.se |
wdenk | 2262cfe | 2002-11-18 00:14:45 +0000 | [diff] [blame] | 4 | * |
Wolfgang Denk | 1a45966 | 2013-07-08 09:37:19 +0200 | [diff] [blame] | 5 | * SPDX-License-Identifier: GPL-2.0+ |
wdenk | 2262cfe | 2002-11-18 00:14:45 +0000 | [diff] [blame] | 6 | */ |
| 7 | |
| 8 | #ifndef _PCI_I386_H_ |
Gabe Black | 452f50f | 2012-10-10 13:12:57 +0000 | [diff] [blame] | 9 | #define _PCI_I386_H_ |
wdenk | 2262cfe | 2002-11-18 00:14:45 +0000 | [diff] [blame] | 10 | |
Simon Glass | a219dae | 2015-03-05 12:25:31 -0700 | [diff] [blame] | 11 | #include <pci.h> |
| 12 | |
Bin Meng | 3c8ae53 | 2015-02-02 22:35:25 +0800 | [diff] [blame] | 13 | /* bus mapping constants (used for PCI core initialization) */ |
| 14 | #define PCI_REG_ADDR 0xcf8 |
| 15 | #define PCI_REG_DATA 0xcfc |
| 16 | |
| 17 | #define PCI_CFG_EN 0x80000000 |
| 18 | |
| 19 | #ifndef __ASSEMBLY__ |
| 20 | |
Graeme Russ | 83088af | 2011-11-08 02:33:15 +0000 | [diff] [blame] | 21 | #define DEFINE_PCI_DEVICE_TABLE(_table) \ |
| 22 | const struct pci_device_id _table[] |
| 23 | |
Simon Glass | d188b18 | 2014-11-12 22:42:11 -0700 | [diff] [blame] | 24 | struct pci_controller; |
| 25 | |
Graeme Russ | 1cfcf03 | 2011-11-08 02:33:22 +0000 | [diff] [blame] | 26 | void pci_setup_type1(struct pci_controller *hose); |
Simon Glass | d188b18 | 2014-11-12 22:42:11 -0700 | [diff] [blame] | 27 | |
Simon Glass | 6fb3b72 | 2014-11-12 22:42:14 -0700 | [diff] [blame] | 28 | /* |
| 29 | * Simple PCI access routines - these work from either the early PCI hose |
| 30 | * or the 'real' one, created after U-Boot has memory available |
| 31 | */ |
Simon Glass | 31f57c2 | 2015-03-05 12:25:15 -0700 | [diff] [blame] | 32 | unsigned int x86_pci_read_config8(pci_dev_t dev, unsigned where); |
| 33 | unsigned int x86_pci_read_config16(pci_dev_t dev, unsigned where); |
| 34 | unsigned int x86_pci_read_config32(pci_dev_t dev, unsigned where); |
Simon Glass | 6fb3b72 | 2014-11-12 22:42:14 -0700 | [diff] [blame] | 35 | |
Simon Glass | 31f57c2 | 2015-03-05 12:25:15 -0700 | [diff] [blame] | 36 | void x86_pci_write_config8(pci_dev_t dev, unsigned where, unsigned value); |
| 37 | void x86_pci_write_config16(pci_dev_t dev, unsigned where, unsigned value); |
| 38 | void x86_pci_write_config32(pci_dev_t dev, unsigned where, unsigned value); |
Simon Glass | 6fb3b72 | 2014-11-12 22:42:14 -0700 | [diff] [blame] | 39 | |
Simon Glass | a219dae | 2015-03-05 12:25:31 -0700 | [diff] [blame] | 40 | int pci_x86_read_config(struct udevice *bus, pci_dev_t bdf, uint offset, |
| 41 | ulong *valuep, enum pci_size_t size); |
| 42 | |
| 43 | int pci_x86_write_config(struct udevice *bus, pci_dev_t bdf, uint offset, |
| 44 | ulong value, enum pci_size_t size); |
| 45 | |
Bin Meng | e3e7fa2 | 2015-04-24 18:10:03 +0800 | [diff] [blame] | 46 | /** |
| 47 | * Assign IRQ number to a PCI device |
| 48 | * |
| 49 | * This function assigns IRQ for a PCI device. If the device does not exist |
| 50 | * or does not require interrupts then this function has no effect. |
| 51 | * |
| 52 | * @bus: PCI bus number |
| 53 | * @device: PCI device number |
Bin Meng | e3e7fa2 | 2015-04-24 18:10:03 +0800 | [diff] [blame] | 54 | * @irq: An array of IRQ numbers that are assigned to INTA through |
| 55 | * INTD of this PCI device. |
| 56 | */ |
Bin Meng | 31a2dc6 | 2015-07-15 16:23:40 +0800 | [diff] [blame] | 57 | void pci_assign_irqs(int bus, int device, u8 irq[4]); |
Bin Meng | e3e7fa2 | 2015-04-24 18:10:03 +0800 | [diff] [blame] | 58 | |
Bin Meng | 3c8ae53 | 2015-02-02 22:35:25 +0800 | [diff] [blame] | 59 | #endif /* __ASSEMBLY__ */ |
| 60 | |
| 61 | #endif /* _PCI_I386_H_ */ |