blob: 401d0afc4d0f0cd00414a75426f653e986b8d055 [file] [log] [blame]
Dave Liu24c3aca2006-12-07 21:13:15 +08001/*
2 * Copyright (C) 2006 Freescale Semiconductor, Inc.
3 *
4 * This program is free software; you can redistribute it and/or
5 * modify it under the terms of the GNU General Public License as
6 * published by the Free Software Foundation; either version 2 of
7 * the License, or (at your option) any later version.
8 *
9 * This program is distributed in the hope that it will be useful,
10 * but WITHOUT ANY WARRANTY; without even the implied warranty of
11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12 * GNU General Public License for more details.
13 *
14 * You should have received a copy of the GNU General Public License
15 * along with this program; if not, write to the Free Software
16 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
17 * MA 02111-1307 USA
18 */
19
20#ifndef __CONFIG_H
21#define __CONFIG_H
22
Dave Liu24c3aca2006-12-07 21:13:15 +080023/*
24 * High Level Configuration Options
25 */
26#define CONFIG_E300 1 /* E300 family */
27#define CONFIG_QE 1 /* Has QE */
28#define CONFIG_MPC83XX 1 /* MPC83xx family */
29#define CONFIG_MPC832X 1 /* MPC832x CPU specific */
30#define CONFIG_MPC832XEMDS 1 /* MPC832XEMDS board specific */
Tony Li14778582007-08-17 10:35:59 +080031#undef CONFIG_PQ_MDS_PIB /* POWERQUICC MDS Platform IO Board */
32#undef CONFIG_PQ_MDS_PIB_ATM /* QOC3 ATM card */
Dave Liu24c3aca2006-12-07 21:13:15 +080033
34/*
35 * System Clock Setup
36 */
37#ifdef CONFIG_PCISLAVE
38#define CONFIG_83XX_PCICLK 66000000 /* in HZ */
39#else
40#define CONFIG_83XX_CLKIN 66000000 /* in Hz */
41#endif
42
43#ifndef CONFIG_SYS_CLK_FREQ
44#define CONFIG_SYS_CLK_FREQ 66000000
45#endif
46
47/*
48 * Hardware Reset Configuration Word
49 */
50#define CFG_HRCW_LOW (\
51 HRCWL_LCL_BUS_TO_SCB_CLK_1X1 |\
52 HRCWL_DDR_TO_SCB_CLK_2X1 |\
53 HRCWL_VCO_1X2 |\
54 HRCWL_CSB_TO_CLKIN_2X1 |\
55 HRCWL_CORE_TO_CSB_2X1 |\
56 HRCWL_CE_PLL_VCO_DIV_2 |\
57 HRCWL_CE_PLL_DIV_1X1 |\
58 HRCWL_CE_TO_PLL_1X3)
59
60#ifdef CONFIG_PCISLAVE
61#define CFG_HRCW_HIGH (\
62 HRCWH_PCI_AGENT |\
63 HRCWH_PCI1_ARBITER_DISABLE |\
64 HRCWH_CORE_ENABLE |\
65 HRCWH_FROM_0XFFF00100 |\
66 HRCWH_BOOTSEQ_DISABLE |\
67 HRCWH_SW_WATCHDOG_DISABLE |\
68 HRCWH_ROM_LOC_LOCAL_16BIT |\
69 HRCWH_BIG_ENDIAN |\
70 HRCWH_LALE_NORMAL)
71#else
72#define CFG_HRCW_HIGH (\
73 HRCWH_PCI_HOST |\
74 HRCWH_PCI1_ARBITER_ENABLE |\
75 HRCWH_CORE_ENABLE |\
76 HRCWH_FROM_0X00000100 |\
77 HRCWH_BOOTSEQ_DISABLE |\
78 HRCWH_SW_WATCHDOG_DISABLE |\
79 HRCWH_ROM_LOC_LOCAL_16BIT |\
80 HRCWH_BIG_ENDIAN |\
81 HRCWH_LALE_NORMAL)
82#endif
83
84/*
85 * System IO Config
86 */
87#define CFG_SICRL 0x00000000
88
89#define CONFIG_BOARD_EARLY_INIT_F /* call board_pre_init */
Tony Li14778582007-08-17 10:35:59 +080090#define CONFIG_BOARD_EARLY_INIT_R
Dave Liu24c3aca2006-12-07 21:13:15 +080091
92/*
93 * IMMR new address
94 */
95#define CFG_IMMR 0xE0000000
96
97/*
98 * DDR Setup
99 */
100#define CFG_DDR_BASE 0x00000000 /* DDR is system memory */
101#define CFG_SDRAM_BASE CFG_DDR_BASE
102#define CFG_DDR_SDRAM_BASE CFG_DDR_BASE
103#define CFG_DDRCDR 0x73000002 /* DDR II voltage is 1.8V */
104
105#undef CONFIG_SPD_EEPROM
106#if defined(CONFIG_SPD_EEPROM)
107/* Determine DDR configuration from I2C interface
108 */
109#define SPD_EEPROM_ADDRESS 0x51 /* DDR SODIMM */
110#else
111/* Manually set up DDR parameters
112 */
113#define CFG_DDR_SIZE 128 /* MB */
114#define CFG_DDR_CS0_CONFIG 0x80840102
115#define CFG_DDR_TIMING_0 0x00220802
116#define CFG_DDR_TIMING_1 0x3935d322
117#define CFG_DDR_TIMING_2 0x0f9048ca
118#define CFG_DDR_TIMING_3 0x00000000
119#define CFG_DDR_CLK_CNTL 0x02000000
120#define CFG_DDR_MODE 0x44400232
121#define CFG_DDR_MODE2 0x8000c000
122#define CFG_DDR_INTERVAL 0x03200064
123#define CFG_DDR_CS0_BNDS 0x00000007
124#define CFG_DDR_SDRAM_CFG 0x43080000
125#define CFG_DDR_SDRAM_CFG2 0x00401000
126#endif
127
128/*
129 * Memory test
130 */
131#undef CFG_DRAM_TEST /* memory test, takes time */
132#define CFG_MEMTEST_START 0x00000000 /* memtest region */
133#define CFG_MEMTEST_END 0x00100000
134
135/*
136 * The reserved memory
137 */
138#define CFG_MONITOR_BASE TEXT_BASE /* start of monitor */
139
140#if (CFG_MONITOR_BASE < CFG_FLASH_BASE)
141#define CFG_RAMBOOT
142#else
143#undef CFG_RAMBOOT
144#endif
145
Timur Tabib2893e12007-11-05 09:34:06 -0600146/* CFG_MONITOR_LEN must be a multiple of CFG_ENV_SECT_SIZE */
Dave Liu24c3aca2006-12-07 21:13:15 +0800147#define CFG_MONITOR_LEN (256 * 1024) /* Reserve 256 kB for Mon */
148#define CFG_MALLOC_LEN (128 * 1024) /* Reserved for malloc */
149
150/*
151 * Initial RAM Base Address Setup
152 */
153#define CFG_INIT_RAM_LOCK 1
154#define CFG_INIT_RAM_ADDR 0xE6000000 /* Initial RAM address */
155#define CFG_INIT_RAM_END 0x1000 /* End of used area in RAM */
156#define CFG_GBL_DATA_SIZE 0x100 /* num bytes initial data */
157#define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
158
159/*
160 * Local Bus Configuration & Clock Setup
161 */
162#define CFG_LCRR (LCRR_DBYP | LCRR_CLKDIV_2)
163#define CFG_LBC_LBCR 0x00000000
164
165/*
166 * FLASH on the Local Bus
167 */
168#define CFG_FLASH_CFI /* use the Common Flash Interface */
Jean-Christophe PLAGNIOL-VILLARD00b18832008-08-13 01:40:42 +0200169#define CONFIG_FLASH_CFI_DRIVER /* use the CFI driver */
Dave Liu24c3aca2006-12-07 21:13:15 +0800170#define CFG_FLASH_BASE 0xFE000000 /* FLASH base address */
171#define CFG_FLASH_SIZE 16 /* FLASH size is 16M */
172
173#define CFG_LBLAWBAR0_PRELIM CFG_FLASH_BASE /* Window base at flash base */
174#define CFG_LBLAWAR0_PRELIM 0x80000018 /* 32MB window size */
175
176#define CFG_BR0_PRELIM (CFG_FLASH_BASE | /* Flash Base address */ \
177 (2 << BR_PS_SHIFT) | /* 16 bit port size */ \
178 BR_V) /* valid */
179#define CFG_OR0_PRELIM 0xfe006ff7 /* 16MB Flash size */
180
181#define CFG_MAX_FLASH_BANKS 1 /* number of banks */
182#define CFG_MAX_FLASH_SECT 128 /* sectors per device */
183
184#undef CFG_FLASH_CHECKSUM
185
186/*
187 * BCSR on the Local Bus
188 */
189#define CFG_BCSR 0xF8000000
190#define CFG_LBLAWBAR1_PRELIM CFG_BCSR /* Access window base at BCSR base */
191#define CFG_LBLAWAR1_PRELIM 0x8000000E /* Access window size 32K */
192
193#define CFG_BR1_PRELIM (CFG_BCSR|0x00000801) /* Port size=8bit, MSEL=GPCM */
194#define CFG_OR1_PRELIM 0xFFFFE9f7 /* length 32K */
195
196/*
197 * SDRAM on the Local Bus
198 */
199#undef CFG_LB_SDRAM /* The board has not SRDAM on local bus */
200
201#ifdef CFG_LB_SDRAM
202#define CFG_LBC_SDRAM_BASE 0xF0000000 /* SDRAM base address */
203#define CFG_LBC_SDRAM_SIZE 64 /* LBC SDRAM is 64MB */
204
205#define CFG_LBLAWBAR2_PRELIM CFG_LBC_SDRAM_BASE
206#define CFG_LBLAWAR2_PRELIM 0x80000019 /* 64MB */
207
208/*local bus BR2, OR2 definition for SDRAM if soldered on the EPB board */
209/*
210 * Base Register 2 and Option Register 2 configure SDRAM.
211 * The SDRAM base address, CFG_LBC_SDRAM_BASE, is 0xf0000000.
212 *
213 * For BR2, need:
214 * Base address of 0xf0000000 = BR[0:16] = 1111 0000 0000 0000 0
215 * port size = 32-bits = BR2[19:20] = 11
216 * no parity checking = BR2[21:22] = 00
217 * SDRAM for MSEL = BR2[24:26] = 011
218 * Valid = BR[31] = 1
219 *
220 * 0 4 8 12 16 20 24 28
221 * 1111 0000 0000 0000 0001 1000 0110 0001 = f0001861
222 *
223 * CFG_LBC_SDRAM_BASE should be masked and OR'ed into
224 * the top 17 bits of BR2.
225 */
226
227#define CFG_BR2_PRELIM 0xf0001861 /*Port size=32bit, MSEL=SDRAM */
228
229/*
230 * The SDRAM size in MB, CFG_LBC_SDRAM_SIZE, is 64.
231 *
232 * For OR2, need:
233 * 64MB mask for AM, OR2[0:7] = 1111 1100
234 * XAM, OR2[17:18] = 11
235 * 9 columns OR2[19-21] = 010
236 * 13 rows OR2[23-25] = 100
237 * EAD set for extra time OR[31] = 1
238 *
239 * 0 4 8 12 16 20 24 28
240 * 1111 1100 0000 0000 0110 1001 0000 0001 = fc006901
241 */
242
243#define CFG_OR2_PRELIM 0xfc006901
244
245#define CFG_LBC_LSRT 0x32000000 /* LB sdram refresh timer, about 6us */
246#define CFG_LBC_MRTPR 0x20000000 /* LB refresh timer prescal, 266MHz/32 */
247
248/*
249 * LSDMR masks
250 */
251#define CFG_LBC_LSDMR_OP_NORMAL (0 << (31 - 4))
252#define CFG_LBC_LSDMR_OP_ARFRSH (1 << (31 - 4))
253#define CFG_LBC_LSDMR_OP_SRFRSH (2 << (31 - 4))
254#define CFG_LBC_LSDMR_OP_MRW (3 << (31 - 4))
255#define CFG_LBC_LSDMR_OP_PRECH (4 << (31 - 4))
256#define CFG_LBC_LSDMR_OP_PCHALL (5 << (31 - 4))
257#define CFG_LBC_LSDMR_OP_ACTBNK (6 << (31 - 4))
258#define CFG_LBC_LSDMR_OP_RWINV (7 << (31 - 4))
259
260#define CFG_LBC_LSDMR_COMMON 0x0063b723
261
262/*
263 * SDRAM Controller configuration sequence.
264 */
265#define CFG_LBC_LSDMR_1 ( CFG_LBC_LSDMR_COMMON \
266 | CFG_LBC_LSDMR_OP_PCHALL)
267#define CFG_LBC_LSDMR_2 ( CFG_LBC_LSDMR_COMMON \
268 | CFG_LBC_LSDMR_OP_ARFRSH)
269#define CFG_LBC_LSDMR_3 ( CFG_LBC_LSDMR_COMMON \
270 | CFG_LBC_LSDMR_OP_ARFRSH)
271#define CFG_LBC_LSDMR_4 ( CFG_LBC_LSDMR_COMMON \
272 | CFG_LBC_LSDMR_OP_MRW)
273#define CFG_LBC_LSDMR_5 ( CFG_LBC_LSDMR_COMMON \
274 | CFG_LBC_LSDMR_OP_NORMAL)
275
276#endif
277
278/*
279 * Windows to access PIB via local bus
280 */
281#define CFG_LBLAWBAR3_PRELIM 0xf8008000 /* windows base 0xf8008000 */
282#define CFG_LBLAWAR3_PRELIM 0x8000000f /* windows size 64KB */
283
284/*
285 * CS2 on Local Bus, to PIB
286 */
287#define CFG_BR2_PRELIM 0xf8008801 /* CS2 base address at 0xf8008000 */
288#define CFG_OR2_PRELIM 0xffffe9f7 /* size 32KB, port size 8bit, GPCM */
289
290/*
291 * CS3 on Local Bus, to PIB
292 */
293#define CFG_BR3_PRELIM 0xf8010801 /* CS3 base address at 0xf8010000 */
294#define CFG_OR3_PRELIM 0xffffe9f7 /* size 32KB, port size 8bit, GPCM */
295
296/*
297 * Serial Port
298 */
299#define CONFIG_CONS_INDEX 1
300#undef CONFIG_SERIAL_SOFTWARE_FIFO
301#define CFG_NS16550
302#define CFG_NS16550_SERIAL
303#define CFG_NS16550_REG_SIZE 1
304#define CFG_NS16550_CLK get_bus_freq(0)
305
306#define CFG_BAUDRATE_TABLE \
307 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400,115200}
308
309#define CFG_NS16550_COM1 (CFG_IMMR+0x4500)
310#define CFG_NS16550_COM2 (CFG_IMMR+0x4600)
311
Kim Phillips22d71a72007-02-27 18:41:08 -0600312#define CONFIG_CMDLINE_EDITING 1 /* add command line history */
Dave Liu24c3aca2006-12-07 21:13:15 +0800313/* Use the HUSH parser */
314#define CFG_HUSH_PARSER
315#ifdef CFG_HUSH_PARSER
316#define CFG_PROMPT_HUSH_PS2 "> "
317#endif
318
319/* pass open firmware flat tree */
Kim Phillips35cc4e42007-08-15 22:30:39 -0500320#define CONFIG_OF_LIBFDT 1
Dave Liu24c3aca2006-12-07 21:13:15 +0800321#define CONFIG_OF_BOARD_SETUP 1
Kim Phillips5b8bc602007-12-20 14:09:22 -0600322#define CONFIG_OF_STDOUT_VIA_ALIAS 1
Dave Liu24c3aca2006-12-07 21:13:15 +0800323
324/* I2C */
325#define CONFIG_HARD_I2C /* I2C with hardware support */
326#undef CONFIG_SOFT_I2C /* I2C bit-banged */
327#define CONFIG_FSL_I2C
328#define CFG_I2C_SPEED 400000 /* I2C speed and slave address */
329#define CFG_I2C_SLAVE 0x7F
330#define CFG_I2C_NOPROBES {0x51} /* Don't probe these addrs */
331#define CFG_I2C_OFFSET 0x3000
332
333/*
334 * Config on-board RTC
335 */
336#define CONFIG_RTC_DS1374 /* use ds1374 rtc via i2c */
337#define CFG_I2C_RTC_ADDR 0x68 /* at address 0x68 */
338
339/*
340 * General PCI
341 * Addresses are mapped 1-1.
342 */
343#define CFG_PCI_MEM_BASE 0x80000000
344#define CFG_PCI_MEM_PHYS CFG_PCI_MEM_BASE
345#define CFG_PCI_MEM_SIZE 0x10000000 /* 256M */
346#define CFG_PCI_MMIO_BASE 0x90000000
347#define CFG_PCI_MMIO_PHYS CFG_PCI_MMIO_BASE
348#define CFG_PCI_MMIO_SIZE 0x10000000 /* 256M */
Scott Wooda7ba32d2008-03-24 12:44:13 -0500349#define CFG_PCI_IO_BASE 0x00000000
Dave Liu24c3aca2006-12-07 21:13:15 +0800350#define CFG_PCI_IO_PHYS 0xE0300000
351#define CFG_PCI_IO_SIZE 0x100000 /* 1M */
352
353#define CFG_PCI_SLV_MEM_LOCAL CFG_SDRAM_BASE
354#define CFG_PCI_SLV_MEM_BUS 0x00000000
355#define CFG_PCI_SLV_MEM_SIZE 0x80000000
356
357
358#ifdef CONFIG_PCI
359
360#define CONFIG_NET_MULTI
361#define CONFIG_PCI_PNP /* do pci plug-and-play */
362
363#undef CONFIG_EEPRO100
364#undef CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */
365#define CFG_PCI_SUBSYS_VENDORID 0x1957 /* Freescale */
366
367#endif /* CONFIG_PCI */
368
369
370#ifndef CONFIG_NET_MULTI
371#define CONFIG_NET_MULTI 1
372#endif
373
374/*
375 * QE UEC ethernet configuration
376 */
377#define CONFIG_UEC_ETH
Kim Phillips711a7942008-01-15 14:05:14 -0600378#define CONFIG_ETHPRIME "FSL UEC0"
Dave Liu24c3aca2006-12-07 21:13:15 +0800379
380#define CONFIG_UEC_ETH1 /* ETH3 */
381
382#ifdef CONFIG_UEC_ETH1
383#define CFG_UEC1_UCC_NUM 2 /* UCC3 */
384#define CFG_UEC1_RX_CLK QE_CLK9
385#define CFG_UEC1_TX_CLK QE_CLK10
386#define CFG_UEC1_ETH_TYPE FAST_ETH
387#define CFG_UEC1_PHY_ADDR 3
388#define CFG_UEC1_INTERFACE_MODE ENET_100_MII
389#endif
390
391#define CONFIG_UEC_ETH2 /* ETH4 */
392
393#ifdef CONFIG_UEC_ETH2
394#define CFG_UEC2_UCC_NUM 3 /* UCC4 */
395#define CFG_UEC2_RX_CLK QE_CLK7
396#define CFG_UEC2_TX_CLK QE_CLK8
397#define CFG_UEC2_ETH_TYPE FAST_ETH
398#define CFG_UEC2_PHY_ADDR 4
399#define CFG_UEC2_INTERFACE_MODE ENET_100_MII
400#endif
401
402/*
403 * Environment
404 */
405#ifndef CFG_RAMBOOT
406 #define CFG_ENV_IS_IN_FLASH 1
Timur Tabib2893e12007-11-05 09:34:06 -0600407 #define CFG_ENV_ADDR (CFG_MONITOR_BASE + CFG_MONITOR_LEN)
408 #define CFG_ENV_SECT_SIZE 0x20000
Dave Liu24c3aca2006-12-07 21:13:15 +0800409 #define CFG_ENV_SIZE 0x2000
410#else
411 #define CFG_NO_FLASH 1 /* Flash is not usable now */
412 #define CFG_ENV_IS_NOWHERE 1 /* Store ENV in memory only */
413 #define CFG_ENV_ADDR (CFG_MONITOR_BASE - 0x1000)
414 #define CFG_ENV_SIZE 0x2000
415#endif
416
417#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
418#define CFG_LOADS_BAUD_CHANGE 1 /* allow baudrate change */
419
Jon Loeliger8ea54992007-07-04 22:30:06 -0500420/*
Jon Loeliger079a1362007-07-10 10:12:10 -0500421 * BOOTP options
422 */
423#define CONFIG_BOOTP_BOOTFILESIZE
424#define CONFIG_BOOTP_BOOTPATH
425#define CONFIG_BOOTP_GATEWAY
426#define CONFIG_BOOTP_HOSTNAME
427
428
429/*
Jon Loeliger8ea54992007-07-04 22:30:06 -0500430 * Command line configuration.
431 */
432#include <config_cmd_default.h>
433
434#define CONFIG_CMD_PING
435#define CONFIG_CMD_I2C
436#define CONFIG_CMD_ASKENV
437
Dave Liu24c3aca2006-12-07 21:13:15 +0800438#if defined(CONFIG_PCI)
Jon Loeliger8ea54992007-07-04 22:30:06 -0500439 #define CONFIG_CMD_PCI
Dave Liu24c3aca2006-12-07 21:13:15 +0800440#endif
441
Jon Loeliger8ea54992007-07-04 22:30:06 -0500442#if defined(CFG_RAMBOOT)
443 #undef CONFIG_CMD_ENV
444 #undef CONFIG_CMD_LOADS
445#endif
446
Dave Liu24c3aca2006-12-07 21:13:15 +0800447
448#undef CONFIG_WATCHDOG /* watchdog disabled */
449
450/*
451 * Miscellaneous configurable options
452 */
453#define CFG_LONGHELP /* undef to save memory */
454#define CFG_LOAD_ADDR 0x2000000 /* default load address */
455#define CFG_PROMPT "=> " /* Monitor Command Prompt */
456
Jon Loeliger8ea54992007-07-04 22:30:06 -0500457#if defined(CONFIG_CMD_KGDB)
Dave Liu24c3aca2006-12-07 21:13:15 +0800458 #define CFG_CBSIZE 1024 /* Console I/O Buffer Size */
459#else
460 #define CFG_CBSIZE 256 /* Console I/O Buffer Size */
461#endif
462
463#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
464#define CFG_MAXARGS 16 /* max number of command args */
465#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */
466#define CFG_HZ 1000 /* decrementer freq: 1ms ticks */
467
468/*
469 * For booting Linux, the board info and command line data
470 * have to be in the first 8 MB of memory, since this is
471 * the maximum mapped by the Linux kernel during initialization.
472 */
473#define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
474
475/*
476 * Core HID Setup
477 */
478#define CFG_HID0_INIT 0x000000000
479#define CFG_HID0_FINAL HID0_ENABLE_MACHINE_CHECK
480#define CFG_HID2 HID2_HBE
481
482/*
Dave Liu24c3aca2006-12-07 21:13:15 +0800483 * MMU Setup
484 */
485
Becky Bruce31d82672008-05-08 19:02:12 -0500486#define CONFIG_HIGH_BATS 1 /* High BATs supported */
487
Dave Liu24c3aca2006-12-07 21:13:15 +0800488/* DDR: cache cacheable */
489#define CFG_IBAT0L (CFG_SDRAM_BASE | BATL_PP_10 | BATL_MEMCOHERENCE)
490#define CFG_IBAT0U (CFG_SDRAM_BASE | BATU_BL_256M | BATU_VS | BATU_VP)
491#define CFG_DBAT0L CFG_IBAT0L
492#define CFG_DBAT0U CFG_IBAT0U
493
494/* IMMRBAR & PCI IO: cache-inhibit and guarded */
495#define CFG_IBAT1L (CFG_IMMR | BATL_PP_10 | \
496 BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
497#define CFG_IBAT1U (CFG_IMMR | BATU_BL_4M | BATU_VS | BATU_VP)
498#define CFG_DBAT1L CFG_IBAT1L
499#define CFG_DBAT1U CFG_IBAT1U
500
501/* BCSR: cache-inhibit and guarded */
502#define CFG_IBAT2L (CFG_BCSR | BATL_PP_10 | \
503 BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
504#define CFG_IBAT2U (CFG_BCSR | BATU_BL_128K | BATU_VS | BATU_VP)
505#define CFG_DBAT2L CFG_IBAT2L
506#define CFG_DBAT2U CFG_IBAT2U
507
508/* FLASH: icache cacheable, but dcache-inhibit and guarded */
509#define CFG_IBAT3L (CFG_FLASH_BASE | BATL_PP_10 | BATL_MEMCOHERENCE)
510#define CFG_IBAT3U (CFG_FLASH_BASE | BATU_BL_32M | BATU_VS | BATU_VP)
511#define CFG_DBAT3L (CFG_FLASH_BASE | BATL_PP_10 | \
512 BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
513#define CFG_DBAT3U CFG_IBAT3U
514
515#define CFG_IBAT4L (0)
516#define CFG_IBAT4U (0)
517#define CFG_DBAT4L CFG_IBAT4L
518#define CFG_DBAT4U CFG_IBAT4U
519
520/* Stack in dcache: cacheable, no memory coherence */
521#define CFG_IBAT5L (CFG_INIT_RAM_ADDR | BATL_PP_10)
522#define CFG_IBAT5U (CFG_INIT_RAM_ADDR | BATU_BL_128K | BATU_VS | BATU_VP)
523#define CFG_DBAT5L CFG_IBAT5L
524#define CFG_DBAT5U CFG_IBAT5U
525
526#ifdef CONFIG_PCI
527/* PCI MEM space: cacheable */
528#define CFG_IBAT6L (CFG_PCI_MEM_PHYS | BATL_PP_10 | BATL_MEMCOHERENCE)
529#define CFG_IBAT6U (CFG_PCI_MEM_PHYS | BATU_BL_256M | BATU_VS | BATU_VP)
530#define CFG_DBAT6L CFG_IBAT6L
531#define CFG_DBAT6U CFG_IBAT6U
532/* PCI MMIO space: cache-inhibit and guarded */
533#define CFG_IBAT7L (CFG_PCI_MMIO_PHYS | BATL_PP_10 | \
534 BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
535#define CFG_IBAT7U (CFG_PCI_MMIO_PHYS | BATU_BL_256M | BATU_VS | BATU_VP)
536#define CFG_DBAT7L CFG_IBAT7L
537#define CFG_DBAT7U CFG_IBAT7U
538#else
539#define CFG_IBAT6L (0)
540#define CFG_IBAT6U (0)
541#define CFG_IBAT7L (0)
542#define CFG_IBAT7U (0)
543#define CFG_DBAT6L CFG_IBAT6L
544#define CFG_DBAT6U CFG_IBAT6U
545#define CFG_DBAT7L CFG_IBAT7L
546#define CFG_DBAT7U CFG_IBAT7U
547#endif
548
549/*
550 * Internal Definitions
551 *
552 * Boot Flags
553 */
554#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */
555#define BOOTFLAG_WARM 0x02 /* Software reboot */
556
Jon Loeliger8ea54992007-07-04 22:30:06 -0500557#if defined(CONFIG_CMD_KGDB)
Dave Liu24c3aca2006-12-07 21:13:15 +0800558#define CONFIG_KGDB_BAUDRATE 230400 /* speed of kgdb serial port */
559#define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */
560#endif
561
562/*
563 * Environment Configuration
564 */
565
566#define CONFIG_ENV_OVERWRITE
567
568#if defined(CONFIG_UEC_ETH)
Kim Phillips977b5752008-01-09 15:24:06 -0600569#define CONFIG_HAS_ETH0
Dave Liu24c3aca2006-12-07 21:13:15 +0800570#define CONFIG_ETHADDR 00:04:9f:ef:03:01
571#define CONFIG_HAS_ETH1
572#define CONFIG_ETH1ADDR 00:04:9f:ef:03:02
573#endif
574
575#define CONFIG_BAUDRATE 115200
576
Kim Phillipsb2115752008-04-24 14:07:38 -0500577#define CONFIG_LOADADDR 500000 /* default location for tftp and bootm */
Dave Liu24c3aca2006-12-07 21:13:15 +0800578
Wolfgang Denk53677ef2008-05-20 16:00:29 +0200579#define CONFIG_BOOTDELAY 6 /* -1 disables auto-boot */
Dave Liu24c3aca2006-12-07 21:13:15 +0800580#undef CONFIG_BOOTARGS /* the boot command will set bootargs */
581
582#define CONFIG_EXTRA_ENV_SETTINGS \
583 "netdev=eth0\0" \
584 "consoledev=ttyS0\0" \
585 "ramdiskaddr=1000000\0" \
586 "ramdiskfile=ramfs.83xx\0" \
587 "fdtaddr=400000\0" \
Kim Phillips270fe262008-03-07 12:27:31 -0600588 "fdtfile=mpc832x_mds.dtb\0" \
Dave Liu24c3aca2006-12-07 21:13:15 +0800589 ""
590
591#define CONFIG_NFSBOOTCOMMAND \
592 "setenv bootargs root=/dev/nfs rw " \
593 "nfsroot=$serverip:$rootpath " \
594 "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \
595 "console=$consoledev,$baudrate $othbootargs;" \
596 "tftp $loadaddr $bootfile;" \
597 "tftp $fdtaddr $fdtfile;" \
598 "bootm $loadaddr - $fdtaddr"
599
600#define CONFIG_RAMBOOTCOMMAND \
601 "setenv bootargs root=/dev/ram rw " \
602 "console=$consoledev,$baudrate $othbootargs;" \
603 "tftp $ramdiskaddr $ramdiskfile;" \
604 "tftp $loadaddr $bootfile;" \
605 "tftp $fdtaddr $fdtfile;" \
606 "bootm $loadaddr $ramdiskaddr $fdtaddr"
607
608
609#define CONFIG_BOOTCOMMAND CONFIG_NFSBOOTCOMMAND
610
611#endif /* __CONFIG_H */