Beniamino Galvani | bfcef28 | 2016-05-08 08:30:16 +0200 | [diff] [blame] | 1 | /* |
| 2 | * (C) Copyright 2016 Beniamino Galvani <b.galvani@gmail.com> |
| 3 | * |
| 4 | * SPDX-License-Identifier: GPL-2.0+ |
| 5 | */ |
| 6 | |
| 7 | #include <common.h> |
Simon Glass | 9d92245 | 2017-05-17 17:18:03 -0600 | [diff] [blame] | 8 | #include <dm.h> |
Beniamino Galvani | bfcef28 | 2016-05-08 08:30:16 +0200 | [diff] [blame] | 9 | #include <asm/io.h> |
| 10 | #include <asm/arch/gxbb.h> |
Beniamino Galvani | c7757d4 | 2016-05-08 08:30:17 +0200 | [diff] [blame] | 11 | #include <asm/arch/sm.h> |
Beniamino Galvani | bfcef28 | 2016-05-08 08:30:16 +0200 | [diff] [blame] | 12 | #include <phy.h> |
| 13 | |
Beniamino Galvani | c7757d4 | 2016-05-08 08:30:17 +0200 | [diff] [blame] | 14 | #define EFUSE_SN_OFFSET 20 |
| 15 | #define EFUSE_SN_SIZE 16 |
| 16 | #define EFUSE_MAC_OFFSET 52 |
| 17 | #define EFUSE_MAC_SIZE 6 |
| 18 | |
Beniamino Galvani | bfcef28 | 2016-05-08 08:30:16 +0200 | [diff] [blame] | 19 | int board_init(void) |
| 20 | { |
| 21 | return 0; |
| 22 | } |
| 23 | |
Beniamino Galvani | bfcef28 | 2016-05-08 08:30:16 +0200 | [diff] [blame] | 24 | int misc_init_r(void) |
| 25 | { |
Beniamino Galvani | c7757d4 | 2016-05-08 08:30:17 +0200 | [diff] [blame] | 26 | u8 mac_addr[EFUSE_MAC_SIZE]; |
Martin Böh | cb86d37 | 2017-06-23 13:40:00 +0000 | [diff] [blame] | 27 | char serial[EFUSE_SN_SIZE]; |
Beniamino Galvani | c7757d4 | 2016-05-08 08:30:17 +0200 | [diff] [blame] | 28 | ssize_t len; |
| 29 | |
Beniamino Galvani | bfcef28 | 2016-05-08 08:30:16 +0200 | [diff] [blame] | 30 | /* Set RGMII mode */ |
| 31 | setbits_le32(GXBB_ETH_REG_0, GXBB_ETH_REG_0_PHY_INTF | |
| 32 | GXBB_ETH_REG_0_TX_PHASE(1) | |
| 33 | GXBB_ETH_REG_0_TX_RATIO(4) | |
| 34 | GXBB_ETH_REG_0_PHY_CLK_EN | |
| 35 | GXBB_ETH_REG_0_CLK_EN); |
| 36 | |
| 37 | /* Enable power and clock gate */ |
| 38 | setbits_le32(GXBB_GCLK_MPEG_1, GXBB_GCLK_MPEG_1_ETH); |
| 39 | clrbits_le32(GXBB_MEM_PD_REG_0, GXBB_MEM_PD_REG_0_ETH_MASK); |
| 40 | |
| 41 | /* Reset PHY on GPIOZ_14 */ |
| 42 | clrbits_le32(GXBB_GPIO_EN(3), BIT(14)); |
| 43 | clrbits_le32(GXBB_GPIO_OUT(3), BIT(14)); |
| 44 | mdelay(10); |
| 45 | setbits_le32(GXBB_GPIO_OUT(3), BIT(14)); |
| 46 | |
Beniamino Galvani | c7757d4 | 2016-05-08 08:30:17 +0200 | [diff] [blame] | 47 | if (!eth_getenv_enetaddr("ethaddr", mac_addr)) { |
| 48 | len = meson_sm_read_efuse(EFUSE_MAC_OFFSET, |
| 49 | mac_addr, EFUSE_MAC_SIZE); |
| 50 | if (len == EFUSE_MAC_SIZE && is_valid_ethaddr(mac_addr)) |
Simon Glass | fd1e959 | 2017-08-03 12:22:11 -0600 | [diff] [blame] | 51 | eth_env_set_enetaddr("ethaddr", mac_addr); |
Beniamino Galvani | c7757d4 | 2016-05-08 08:30:17 +0200 | [diff] [blame] | 52 | } |
| 53 | |
Simon Glass | 00caae6 | 2017-08-03 12:22:12 -0600 | [diff] [blame^] | 54 | if (!env_get("serial#")) { |
Martin Böh | cb86d37 | 2017-06-23 13:40:00 +0000 | [diff] [blame] | 55 | len = meson_sm_read_efuse(EFUSE_SN_OFFSET, serial, |
| 56 | EFUSE_SN_SIZE); |
| 57 | if (len == EFUSE_SN_SIZE) |
Simon Glass | 382bee5 | 2017-08-03 12:22:09 -0600 | [diff] [blame] | 58 | env_set("serial#", serial); |
Martin Böh | cb86d37 | 2017-06-23 13:40:00 +0000 | [diff] [blame] | 59 | } |
| 60 | |
Beniamino Galvani | bfcef28 | 2016-05-08 08:30:16 +0200 | [diff] [blame] | 61 | return 0; |
| 62 | } |