Bartlomiej Sieka | 53d4a49 | 2007-02-09 10:45:42 +0100 | [diff] [blame] | 1 | /* |
| 2 | * (C) Copyright 2003-2007 |
| 3 | * Wolfgang Denk, DENX Software Engineering, wd@denx.de. |
| 4 | * |
| 5 | * Based on PRO Motion board config file by Andy Joseph, andy@promessdev.com |
| 6 | * |
| 7 | * See file CREDITS for list of people who contributed to this |
| 8 | * project. |
| 9 | * |
| 10 | * This program is free software; you can redistribute it and/or |
| 11 | * modify it under the terms of the GNU General Public License as |
| 12 | * published by the Free Software Foundation; either version 2 of |
| 13 | * the License, or (at your option) any later version. |
| 14 | * |
| 15 | * This program is distributed in the hope that it will be useful, |
| 16 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 17 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 18 | * GNU General Public License for more details. |
| 19 | * |
| 20 | * You should have received a copy of the GNU General Public License |
| 21 | * along with this program; if not, write to the Free Software |
| 22 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, |
| 23 | * MA 02111-1307 USA |
| 24 | */ |
| 25 | |
| 26 | #ifndef __CONFIG_H |
| 27 | #define __CONFIG_H |
| 28 | |
| 29 | |
| 30 | /* |
| 31 | * High Level Configuration Options |
| 32 | */ |
| 33 | |
| 34 | |
| 35 | /* CPU and board */ |
| 36 | #define CONFIG_MPC5xxx 1 /* This is an MPC5xxx CPU */ |
| 37 | #define CONFIG_MPC5200 1 /* More exactly a MPC5200 */ |
| 38 | #define CONFIG_MOTIONPRO 1 /* ... on Promess Motion-PRO board */ |
| 39 | |
| 40 | |
| 41 | /* |
| 42 | * Supported commands |
| 43 | */ |
| 44 | #define CONFIG_COMMANDS (CONFIG_CMD_DFL | \ |
| 45 | CFG_CMD_ASKENV | \ |
| 46 | CFG_CMD_DHCP | \ |
| 47 | CFG_CMD_REGINFO | \ |
| 48 | CFG_CMD_IMMAP | \ |
| 49 | CFG_CMD_ELF | \ |
| 50 | CFG_CMD_MII | \ |
| 51 | CFG_CMD_BEDBUG | \ |
| 52 | CFG_CMD_NET | \ |
| 53 | CFG_CMD_PING) |
| 54 | |
| 55 | /* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */ |
| 56 | #include <cmd_confdefs.h> |
| 57 | |
| 58 | |
| 59 | /* |
| 60 | * Serial console configuration |
| 61 | */ |
| 62 | #define CONFIG_PSC_CONSOLE 1 /* console is on PSC1 */ |
| 63 | #define CONFIG_NETCONSOLE 1 /* network console */ |
| 64 | #define CONFIG_BAUDRATE 115200 |
| 65 | #define CFG_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200, 230400 } |
| 66 | |
| 67 | |
| 68 | /* |
| 69 | * Ethernet configuration |
| 70 | */ |
| 71 | #define CONFIG_MPC5xxx_FEC 1 |
| 72 | #define CONFIG_PHY_ADDR 0x2 |
| 73 | #define CONFIG_PHY_TYPE 0x79c874 |
| 74 | |
| 75 | |
| 76 | /* |
| 77 | * Autobooting |
| 78 | */ |
| 79 | #define CONFIG_BOOTDELAY 2 /* autoboot after 2 seconds */ |
| 80 | #define CONFIG_AUTOBOOT_KEYED |
| 81 | #define CONFIG_AUTOBOOT_STOP_STR "\x1b\x1b" |
| 82 | #define DEBUG_BOOTKEYS 0 |
| 83 | #undef CONFIG_AUTOBOOT_DELAY_STR |
| 84 | #undef CONFIG_BOOTARGS |
| 85 | #define CONFIG_AUTOBOOT_PROMPT "Autobooting in %d seconds, " \ |
| 86 | "press \"<Esc><Esc>\" to stop\n" |
| 87 | |
| 88 | #define CONFIG_ETHADDR 00:50:C2:40:10:00 |
| 89 | #define CONFIG_OVERWRITE_ETHADDR_ONCE 1 |
| 90 | #define CONFIG_VERSION_VARIABLE 1 /* include version env variable */ |
| 91 | |
| 92 | |
| 93 | /* |
| 94 | * Default environment settings |
| 95 | */ |
| 96 | #define CONFIG_EXTRA_ENV_SETTINGS \ |
| 97 | "sdram_test=0\0" \ |
| 98 | "netdev=eth0\0" \ |
| 99 | "hostname=motionpro\0" \ |
| 100 | "netmask=255.255.0.0\0" \ |
| 101 | "ipaddr=192.168.160.22\0" \ |
| 102 | "serverip=192.168.1.1\0" \ |
| 103 | "gatewayip=192.168.1.1\0" \ |
| 104 | "kernel_addr=200000\0" \ |
| 105 | "u-boot_addr=100000\0" \ |
| 106 | "kernel_sector=20\0" \ |
| 107 | "kernel_size=1000\0" \ |
| 108 | "console=ttyS0,115200\0" \ |
| 109 | "rootpath=/opt/eldk-4.1/ppc_6xx\0" \ |
| 110 | "bootfile=/tftpboot/motionpro/uImage\0" \ |
| 111 | "u-boot=/tftpboot/motionpro/u-boot.bin\0" \ |
| 112 | "load=tftp $(u-boot_addr) $(u-boot)\0" \ |
| 113 | "update=prot off fff00000 fff3ffff; era fff00000 fff3ffff; " \ |
| 114 | "cp.b $(u-boot_addr) fff00000 $(filesize);" \ |
| 115 | "prot on fff00000 fff3ffff\0" \ |
| 116 | "ramargs=setenv bootargs root=/dev/ram rw\0" \ |
| 117 | "addip=setenv bootargs $(bootargs) console=$(console) " \ |
| 118 | "ip=$(ipaddr):$(serverip):$(gatewayip):" \ |
| 119 | "$(netmask):$(hostname):$(netdev):off panic=1\0" \ |
| 120 | "flash_nfs=run nfsargs addip;bootm $(kernel_addr)\0" \ |
| 121 | "flash_self=run ramargs addip;bootm $(kernel_addr) " \ |
| 122 | "$(ramdisk_addr)\0" \ |
| 123 | "net_nfs=tftp $(kernel_addr) $(bootfile); run nfsargs addip; " \ |
| 124 | "bootm $(kernel_addr)\0" \ |
| 125 | "nfsargs=setenv bootargs root=/dev/nfs rw " \ |
| 126 | "nfsroot=$(serverip):$(rootpath)\0" \ |
| 127 | "fstype=ext3\0" \ |
| 128 | "fatargs=setenv bootargs init=/linuxrc rw\0" \ |
| 129 | "" |
| 130 | #define CONFIG_BOOTCOMMAND "run net_nfs" |
| 131 | |
| 132 | |
| 133 | /* |
| 134 | * do board-specific init |
| 135 | */ |
| 136 | #define CONFIG_BOARD_EARLY_INIT_R 1 |
| 137 | |
| 138 | |
| 139 | /* |
| 140 | * Low level configuration |
| 141 | */ |
| 142 | |
| 143 | |
| 144 | /* |
| 145 | * Clock configuration: SYS_XTALIN = 25MHz |
| 146 | */ |
| 147 | #define CFG_MPC5XXX_CLKIN 25000000 |
| 148 | |
| 149 | |
| 150 | /* |
| 151 | * Memory map |
| 152 | */ |
| 153 | /* |
| 154 | * Warning!!! with the current BestComm Task, MBAR MUST BE set to 0xf0000000. |
| 155 | * Setting MBAR to otherwise will cause system hang when using SmartDMA such |
| 156 | * as network commands. |
| 157 | */ |
| 158 | #define CFG_MBAR 0xf0000000 |
| 159 | #define CFG_SDRAM_BASE 0x00000000 |
| 160 | |
| 161 | /* |
| 162 | * If building for running out of SDRAM, then MBAR has been set up beforehand |
| 163 | * (e.g., by the BDI). Otherwise we must specify the default boot-up value of |
| 164 | * MBAR, as given in the doccumentation. |
| 165 | */ |
| 166 | #if TEXT_BASE == 0x00100000 |
| 167 | #define CFG_DEFAULT_MBAR 0xf0000000 |
| 168 | #else /* TEXT_BASE != 0x00100000 */ |
| 169 | #define CFG_DEFAULT_MBAR 0x80000000 |
| 170 | #define CFG_LOWBOOT 1 |
| 171 | #endif /* TEXT_BASE == 0x00100000 */ |
| 172 | |
| 173 | /* Use SRAM until RAM will be available */ |
| 174 | #define CFG_INIT_RAM_ADDR MPC5XXX_SRAM |
| 175 | #define CFG_INIT_RAM_END MPC5XXX_SRAM_SIZE |
| 176 | |
| 177 | #define CFG_GBL_DATA_SIZE 128 /* size in bytes for initial data */ |
| 178 | #define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE) |
| 179 | #define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET |
| 180 | |
| 181 | #define CFG_MONITOR_BASE TEXT_BASE |
| 182 | #if (CFG_MONITOR_BASE < CFG_FLASH_BASE) |
| 183 | #define CFG_RAMBOOT 1 |
| 184 | #endif |
| 185 | |
| 186 | #define CFG_MONITOR_LEN (256 << 10) /* 256 kB for Monitor */ |
| 187 | #define CFG_MALLOC_LEN (128 << 10) /* 128 kB for malloc() */ |
| 188 | #define CFG_BOOTMAPSZ (8 << 20) /* initial mem map for Linux */ |
| 189 | |
| 190 | |
| 191 | /* |
| 192 | * Chip selects configuration |
| 193 | */ |
| 194 | /* Boot Chipselect */ |
| 195 | #define CFG_BOOTCS_START CFG_FLASH_BASE |
| 196 | #define CFG_BOOTCS_SIZE CFG_FLASH_SIZE |
| 197 | #define CFG_BOOTCS_CFG 0x03035D00 |
| 198 | |
| 199 | /* Flash memory addressing */ |
| 200 | #define CFG_CS0_START CFG_FLASH_BASE |
| 201 | #define CFG_CS0_SIZE CFG_FLASH_SIZE |
| 202 | #define CFG_CS0_CFG CFG_BOOTCS_CFG |
| 203 | |
| 204 | /* Dual Port SRAM -- Kollmorgen Drive memory addressing */ |
| 205 | #define CFG_CS1_START 0x50000000 |
| 206 | #define CFG_CS1_SIZE 0x10000 |
| 207 | #define CFG_CS1_CFG 0x05055800 |
| 208 | |
| 209 | /* Local register access */ |
| 210 | #define CFG_CS2_START 0x50010000 |
| 211 | #define CFG_CS2_SIZE 0x10000 |
| 212 | #define CFG_CS2_CFG 0x05055800 |
| 213 | |
| 214 | /* Anybus CompactCom Module memory addressing */ |
| 215 | #define CFG_CS3_START 0x50020000 |
| 216 | #define CFG_CS3_SIZE 0x10000 |
| 217 | #define CFG_CS3_CFG 0x05055800 |
| 218 | |
| 219 | /* No burst and dead cycle = 2 for all CSs */ |
| 220 | #define CFG_CS_BURST 0x00000000 |
| 221 | #define CFG_CS_DEADCYCLE 0x22222222 |
| 222 | |
| 223 | |
| 224 | /* |
| 225 | * SDRAM configuration |
| 226 | */ |
| 227 | /* 2 x MT48LC16M16A2BG-75 IT:D, CASL 2, 32 bit data bus */ |
| 228 | #define SDRAM_CONFIG1 0x52222600 |
| 229 | #define SDRAM_CONFIG2 0x88b70000 |
| 230 | #define SDRAM_CONTROL 0x50570000 |
| 231 | #define SDRAM_MODE 0x008d0000 |
| 232 | |
| 233 | |
| 234 | /* |
| 235 | * Flash configuration |
| 236 | */ |
| 237 | #define CFG_FLASH_CFI 1 /* Flash is CFI conformant */ |
| 238 | #define CFG_FLASH_CFI_DRIVER 1 |
| 239 | #define CFG_FLASH_BASE 0xff000000 |
| 240 | #define CFG_FLASH_SIZE 0x01000000 |
| 241 | #define CFG_MAX_FLASH_BANKS 1 /* max num of memory banks */ |
| 242 | #define CFG_FLASH_BANKS_LIST { CFG_FLASH_BASE } |
| 243 | #define CFG_MAX_FLASH_SECT 256 /* max num of sects on one chip */ |
| 244 | #define CONFIG_FLASH_16BIT /* Flash is 16-bit */ |
| 245 | |
| 246 | |
| 247 | /* |
| 248 | * Environment settings |
| 249 | */ |
| 250 | #define CFG_ENV_IS_IN_FLASH 1 |
| 251 | /* This has to be a multiple of the Flash sector size */ |
| 252 | #define CFG_ENV_ADDR (CFG_MONITOR_BASE + CFG_MONITOR_LEN) |
| 253 | #define CFG_ENV_SIZE 0x1000 |
| 254 | #define CFG_ENV_SECT_SIZE 0x10000 |
| 255 | |
| 256 | |
| 257 | /* |
| 258 | * Pin multiplexing configuration |
| 259 | */ |
| 260 | |
| 261 | /* PSC1: UART1 |
| 262 | * PSC2: GPIO (default) |
| 263 | * PSC3: GPIO (default) |
| 264 | * USB: 2xUART4/5 |
| 265 | * Ethernet: Ethernet 100Mbit with MD |
| 266 | * Timer: CAN2/GPIO |
| 267 | * PSC6/IRDA: GPIO (default) |
| 268 | */ |
| 269 | #define CFG_GPS_PORT_CONFIG 0x1105a004 |
| 270 | |
| 271 | |
| 272 | /* |
| 273 | * Miscellaneous configurable options |
| 274 | */ |
| 275 | #define CFG_LONGHELP /* undef to save memory */ |
| 276 | #define CFG_PROMPT "=> " /* Monitor Command Prompt */ |
| 277 | #define CFG_CBSIZE 256 /* Console I/O Buffer Size */ |
| 278 | #define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */ |
| 279 | #define CFG_MAXARGS 16 /* max number of command args */ |
| 280 | #define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */ |
| 281 | |
| 282 | #define CFG_MEMTEST_START 0x00100000 /* memtest works on */ |
| 283 | #define CFG_MEMTEST_END 0x03f00000 /* 1 ... 64 MiB in DRAM */ |
| 284 | |
| 285 | #define CFG_LOAD_ADDR 0x200000 /* default kernel load addr */ |
| 286 | |
| 287 | #define CFG_HZ 1000 /* decrementer freq: 1 ms ticks */ |
| 288 | |
| 289 | |
| 290 | /* |
| 291 | * Various low-level settings |
| 292 | */ |
| 293 | #define CFG_HID0_INIT HID0_ICE | HID0_ICFI |
| 294 | #define CFG_HID0_FINAL HID0_ICE |
| 295 | |
| 296 | #define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */ |
| 297 | #define BOOTFLAG_WARM 0x02 /* Software reboot */ |
| 298 | |
| 299 | #define CFG_CACHELINE_SIZE 32 /* For MPC5xxx CPUs */ |
| 300 | |
| 301 | |
| 302 | /* Not needed for MPC 5xxx U-Boot, but used by tools/updater */ |
| 303 | #define CFG_RESET_ADDRESS 0xfff00100 |
| 304 | |
| 305 | #endif /* __CONFIG_H */ |