blob: f189039e86c15c6a7bca26e4997e12f0102ec1c6 [file] [log] [blame]
Anton Vorontsovfab6f552008-01-09 20:57:47 +03001/*
2 * Copyright (C) 2006 Freescale Semiconductor, Inc.
3 * Dave Liu <daveliu@freescale.com>
4 *
5 * Copyright (C) 2007 Logic Product Development, Inc.
6 * Peter Barada <peterb@logicpd.com>
7 *
8 * Copyright (C) 2007 MontaVista Software, Inc.
9 * Anton Vorontsov <avorontsov@ru.mvista.com>
10 *
11 * This program is free software; you can redistribute it and/or
12 * modify it under the terms of the GNU General Public License as
13 * published by the Free Software Foundation; either version 2 of
14 * the License, or (at your option) any later version.
15 */
16
17#ifndef __CONFIG_H
18#define __CONFIG_H
19
Anton Vorontsovfab6f552008-01-09 20:57:47 +030020/*
21 * High Level Configuration Options
22 */
23#define CONFIG_E300 1 /* E300 family */
24#define CONFIG_QE 1 /* Has QE */
Peter Tyser0f898602009-05-22 17:23:24 -050025#define CONFIG_MPC83xx 1 /* MPC83xx family */
Anton Vorontsovfab6f552008-01-09 20:57:47 +030026#define CONFIG_MPC8360 1 /* MPC8360 CPU specific */
27#define CONFIG_MPC8360ERDK 1 /* MPC8360ERDK board specific */
28
Wolfgang Denk2ae18242010-10-06 09:05:45 +020029#define CONFIG_SYS_TEXT_BASE 0xFF800000
30
Anton Vorontsovfab6f552008-01-09 20:57:47 +030031/*
32 * System Clock Setup
33 */
34#ifdef CONFIG_CLKIN_33MHZ
Anton Vorontsovf700e7d2008-03-24 20:47:05 +030035#define CONFIG_83XX_CLKIN 33333333
36#define CONFIG_SYS_CLK_FREQ 33333333
Wolfgang Denk2ae18242010-10-06 09:05:45 +020037#define CONFIG_PCI_33M 1
Anton Vorontsovfab6f552008-01-09 20:57:47 +030038#define HRCWL_CSB_TO_CLKIN_MPC8360ERDK HRCWL_CSB_TO_CLKIN_10X1
39#else
40#define CONFIG_83XX_CLKIN 66000000
41#define CONFIG_SYS_CLK_FREQ 66000000
Wolfgang Denk2ae18242010-10-06 09:05:45 +020042#define CONFIG_PCI_66M 1
Anton Vorontsovfab6f552008-01-09 20:57:47 +030043#define HRCWL_CSB_TO_CLKIN_MPC8360ERDK HRCWL_CSB_TO_CLKIN_5X1
44#endif /* CONFIG_CLKIN_33MHZ */
45
46/*
47 * Hardware Reset Configuration Word
48 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020049#define CONFIG_SYS_HRCW_LOW (\
Anton Vorontsovfab6f552008-01-09 20:57:47 +030050 HRCWL_LCL_BUS_TO_SCB_CLK_1X1 |\
51 HRCWL_DDR_TO_SCB_CLK_1X1 |\
52 HRCWL_CSB_TO_CLKIN_MPC8360ERDK |\
53 HRCWL_CORE_TO_CSB_2X1 |\
54 HRCWL_CE_TO_PLL_1X15)
55
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020056#define CONFIG_SYS_HRCW_HIGH (\
Anton Vorontsovfab6f552008-01-09 20:57:47 +030057 HRCWH_PCI_HOST |\
58 HRCWH_PCI1_ARBITER_ENABLE |\
59 HRCWH_PCICKDRV_ENABLE |\
60 HRCWH_CORE_ENABLE |\
61 HRCWH_FROM_0X00000100 |\
62 HRCWH_BOOTSEQ_DISABLE |\
63 HRCWH_SW_WATCHDOG_DISABLE |\
64 HRCWH_ROM_LOC_LOCAL_16BIT |\
65 HRCWH_SECONDARY_DDR_DISABLE |\
66 HRCWH_BIG_ENDIAN |\
67 HRCWH_LALE_EARLY)
68
69/*
70 * System IO Config
71 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020072#define CONFIG_SYS_SICRH 0x00000000
73#define CONFIG_SYS_SICRL 0x40000000
Anton Vorontsovfab6f552008-01-09 20:57:47 +030074
Anton Vorontsovfab6f552008-01-09 20:57:47 +030075#define CONFIG_BOARD_EARLY_INIT_R
76
77/*
78 * IMMR new address
79 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020080#define CONFIG_SYS_IMMR 0xE0000000
Anton Vorontsovfab6f552008-01-09 20:57:47 +030081
82/*
83 * DDR Setup
84 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020085#define CONFIG_SYS_DDR_BASE 0x00000000 /* DDR is system memory */
86#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_BASE
87#define CONFIG_SYS_DDR_SDRAM_BASE CONFIG_SYS_DDR_BASE
Joe Hershberger9a986552011-10-11 23:57:17 -050088#define CONFIG_SYS_DDR_SDRAM_CLK_CNTL (DDR_SDRAM_CLK_CNTL_SS_EN \
89 | DDR_SDRAM_CLK_CNTL_CLK_ADJUST_05)
Anton Vorontsovfab6f552008-01-09 20:57:47 +030090
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020091#define CONFIG_SYS_83XX_DDR_USES_CS0
Anton Vorontsovfab6f552008-01-09 20:57:47 +030092
Anton Vorontsovd892b2d2008-03-24 20:46:57 +030093#define CONFIG_DDR_ECC /* support DDR ECC function */
94#define CONFIG_DDR_ECC_CMD /* Use DDR ECC user commands */
Anton Vorontsovfab6f552008-01-09 20:57:47 +030095
96/*
97 * DDRCDR - DDR Control Driver Register
98 */
Joe Hershberger2fef4022011-10-11 23:57:29 -050099#define CONFIG_SYS_DDRCDR_VALUE (DDRCDR_DHC_EN \
100 | DDRCDR_ODT \
101 | DDRCDR_Q_DRN)
102 /* 0x80080001 */
Anton Vorontsovfab6f552008-01-09 20:57:47 +0300103
104#undef CONFIG_SPD_EEPROM /* Do not use SPD EEPROM for DDR setup */
105
106/*
107 * Manually set up DDR parameters
108 */
109#define CONFIG_DDR_II
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200110#define CONFIG_SYS_DDR_SIZE 256 /* MB */
Joe Hershberger2fef4022011-10-11 23:57:29 -0500111#define CONFIG_SYS_DDR_CS0_BNDS 0x0000000f
Joe Hershberger9a986552011-10-11 23:57:17 -0500112#define CONFIG_SYS_DDR_CS0_CONFIG (CSCONFIG_EN \
113 | CSCONFIG_ROW_BIT_13 \
114 | CSCONFIG_COL_BIT_10 \
Joe Hershberger2fef4022011-10-11 23:57:29 -0500115 | CSCONFIG_ODT_WR_ONLY_CURRENT)
Joe Hershberger9a986552011-10-11 23:57:17 -0500116#define CONFIG_SYS_DDR_SDRAM_CFG (SDRAM_CFG_SDRAM_TYPE_DDR2 \
117 | SDRAM_CFG_ECC_EN)
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200118#define CONFIG_SYS_DDR_SDRAM_CFG2 0x00001000
Joe Hershberger9a986552011-10-11 23:57:17 -0500119#define CONFIG_SYS_DDR_CLK_CNTL (DDR_SDRAM_CLK_CNTL_CLK_ADJUST_05)
120#define CONFIG_SYS_DDR_INTERVAL ((256 << SDRAM_INTERVAL_BSTOPRE_SHIFT) \
121 | (1115 << SDRAM_INTERVAL_REFINT_SHIFT))
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200122#define CONFIG_SYS_DDR_MODE 0x47800432
123#define CONFIG_SYS_DDR_MODE2 0x8000c000
Anton Vorontsovd892b2d2008-03-24 20:46:57 +0300124
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200125#define CONFIG_SYS_DDR_TIMING_0 ((2 << TIMING_CFG0_MRS_CYC_SHIFT) | \
Anton Vorontsovd892b2d2008-03-24 20:46:57 +0300126 (9 << TIMING_CFG0_ODT_PD_EXIT_SHIFT) | \
127 (3 << TIMING_CFG0_PRE_PD_EXIT_SHIFT) | \
128 (3 << TIMING_CFG0_ACT_PD_EXIT_SHIFT) | \
129 (0 << TIMING_CFG0_WWT_SHIFT) | \
130 (0 << TIMING_CFG0_RRT_SHIFT) | \
131 (0 << TIMING_CFG0_WRT_SHIFT) | \
132 (0 << TIMING_CFG0_RWT_SHIFT))
133
Joe Hershberger9a986552011-10-11 23:57:17 -0500134#define CONFIG_SYS_DDR_TIMING_1 ((TIMING_CFG1_CASLAT_30) | \
135 (2 << TIMING_CFG1_WRTORD_SHIFT) | \
136 (2 << TIMING_CFG1_ACTTOACT_SHIFT) | \
137 (3 << TIMING_CFG1_WRREC_SHIFT) | \
Anton Vorontsovd892b2d2008-03-24 20:46:57 +0300138 (10 << TIMING_CFG1_REFREC_SHIFT) | \
Joe Hershberger9a986552011-10-11 23:57:17 -0500139 (3 << TIMING_CFG1_ACTTORW_SHIFT) | \
140 (8 << TIMING_CFG1_ACTTOPRE_SHIFT) | \
141 (3 << TIMING_CFG1_PRETOACT_SHIFT))
Anton Vorontsovd892b2d2008-03-24 20:46:57 +0300142
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200143#define CONFIG_SYS_DDR_TIMING_2 ((9 << TIMING_CFG2_FOUR_ACT_SHIFT) | \
Anton Vorontsovd892b2d2008-03-24 20:46:57 +0300144 (4 << TIMING_CFG2_CKE_PLS_SHIFT) | \
145 (2 << TIMING_CFG2_WR_DATA_DELAY_SHIFT) | \
146 (2 << TIMING_CFG2_RD_TO_PRE_SHIFT) | \
147 (2 << TIMING_CFG2_WR_LAT_DELAY_SHIFT) | \
148 (0 << TIMING_CFG2_ADD_LAT_SHIFT) | \
149 (0 << TIMING_CFG2_CPO_SHIFT))
150
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200151#define CONFIG_SYS_DDR_TIMING_3 0x00000000
Anton Vorontsovfab6f552008-01-09 20:57:47 +0300152
153/*
154 * Memory test
155 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200156#undef CONFIG_SYS_DRAM_TEST /* memory test, takes time */
157#define CONFIG_SYS_MEMTEST_START 0x00000000 /* memtest region */
158#define CONFIG_SYS_MEMTEST_END 0x00100000
Anton Vorontsovfab6f552008-01-09 20:57:47 +0300159
160/*
161 * The reserved memory
162 */
Wolfgang Denk14d0a022010-10-07 21:51:12 +0200163#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200164#define CONFIG_SYS_FLASH_BASE 0xFF800000 /* FLASH base address */
Anton Vorontsovfab6f552008-01-09 20:57:47 +0300165
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200166#if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE)
167#define CONFIG_SYS_RAMBOOT
Anton Vorontsovfab6f552008-01-09 20:57:47 +0300168#else
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200169#undef CONFIG_SYS_RAMBOOT
Anton Vorontsovfab6f552008-01-09 20:57:47 +0300170#endif
171
Joe Hershberger9a986552011-10-11 23:57:17 -0500172#define CONFIG_SYS_MONITOR_LEN (384 * 1024) /* Reserve 384 kB for Mon */
Kim Phillipsc8a90642012-06-30 18:29:20 -0500173#define CONFIG_SYS_MALLOC_LEN (256 * 1024) /* Reserved for malloc */
Anton Vorontsovfab6f552008-01-09 20:57:47 +0300174
175/*
176 * Initial RAM Base Address Setup
177 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200178#define CONFIG_SYS_INIT_RAM_LOCK 1
179#define CONFIG_SYS_INIT_RAM_ADDR 0xE6000000 /* Initial RAM address */
Wolfgang Denk553f0982010-10-26 13:32:32 +0200180#define CONFIG_SYS_INIT_RAM_SIZE 0x1000 /* Size of used area in RAM */
Joe Hershberger9a986552011-10-11 23:57:17 -0500181#define CONFIG_SYS_GBL_DATA_OFFSET \
182 (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
Anton Vorontsovfab6f552008-01-09 20:57:47 +0300183
184/*
185 * Local Bus Configuration & Clock Setup
186 */
Kim Phillipsc7190f02009-09-25 18:19:44 -0500187#define CONFIG_SYS_LCRR_DBYP LCRR_DBYP
188#define CONFIG_SYS_LCRR_CLKDIV LCRR_CLKDIV_4
Joe Hershberger9a986552011-10-11 23:57:17 -0500189#define CONFIG_SYS_LBC_LBCR 0x00000000
Anton Vorontsovfab6f552008-01-09 20:57:47 +0300190
191/*
192 * FLASH on the Local Bus
193 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200194#define CONFIG_SYS_FLASH_CFI /* use the Common Flash Interface */
Joe Hershberger9a986552011-10-11 23:57:17 -0500195#define CONFIG_FLASH_CFI_DRIVER /* use the CFI driver */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200196#define CONFIG_SYS_FLASH_SIZE 8 /* max FLASH size is 32M */
197#define CONFIG_SYS_FLASH_PROTECTION 1 /* Use intel Flash protection. */
Anton Vorontsovfab6f552008-01-09 20:57:47 +0300198
Joe Hershberger9a986552011-10-11 23:57:17 -0500199 /* Window base at flash base */
200#define CONFIG_SYS_LBLAWBAR0_PRELIM CONFIG_SYS_FLASH_BASE
Joe Hershberger7d6a0982011-10-11 23:57:30 -0500201#define CONFIG_SYS_LBLAWAR0_PRELIM (LBLAWAR_EN | LBLAWAR_32MB)
Anton Vorontsovfab6f552008-01-09 20:57:47 +0300202
Joe Hershberger9a986552011-10-11 23:57:17 -0500203#define CONFIG_SYS_BR0_PRELIM (CONFIG_SYS_FLASH_BASE \
Joe Hershberger7d6a0982011-10-11 23:57:30 -0500204 | BR_PS_16 /* 16 bit port */ \
205 | BR_MS_GPCM /* MSEL = GPCM */ \
206 | BR_V) /* valid */
207#define CONFIG_SYS_OR0_PRELIM (MEG_TO_AM(CONFIG_SYS_FLASH_SIZE) \
Joe Hershberger9a986552011-10-11 23:57:17 -0500208 | OR_UPM_XAM \
209 | OR_GPCM_CSNT \
210 | OR_GPCM_ACS_DIV2 \
211 | OR_GPCM_XACS \
212 | OR_GPCM_SCY_15 \
Joe Hershberger7d6a0982011-10-11 23:57:30 -0500213 | OR_GPCM_TRLX_SET \
214 | OR_GPCM_EHTR_SET \
Joe Hershberger9a986552011-10-11 23:57:17 -0500215 | OR_GPCM_EAD)
Anton Vorontsovfab6f552008-01-09 20:57:47 +0300216
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200217#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* number of banks */
218#define CONFIG_SYS_MAX_FLASH_SECT 256 /* max sectors per device */
Anton Vorontsovfab6f552008-01-09 20:57:47 +0300219
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200220#undef CONFIG_SYS_FLASH_CHECKSUM
Anton Vorontsovfab6f552008-01-09 20:57:47 +0300221
222/*
223 * NAND flash on the local bus
224 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200225#define CONFIG_SYS_NAND_BASE 0x60000000
Anton Vorontsov7ad95942008-03-24 20:46:51 +0300226#define CONFIG_CMD_NAND 1
227#define CONFIG_NAND_FSL_UPM 1
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200228#define CONFIG_SYS_MAX_NAND_DEVICE 1
Anton Vorontsov7ad95942008-03-24 20:46:51 +0300229#define CONFIG_MTD_NAND_VERIFY_WRITE
Anton Vorontsovfab6f552008-01-09 20:57:47 +0300230
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200231#define CONFIG_SYS_LBLAWBAR1_PRELIM CONFIG_SYS_NAND_BASE
Joe Hershberger7d6a0982011-10-11 23:57:30 -0500232/*
233 * [RFC] Comment said 4KB window; code said 256MB window; OR1 says 64MB
234 * ... What's correct?
235 */
236#define CONFIG_SYS_LBLAWAR1_PRELIM (LBLAWAR_EN | LBLAWAR_256MB)
Anton Vorontsovfab6f552008-01-09 20:57:47 +0300237
238/* Port size 8 bit, UPMA */
Joe Hershberger7d6a0982011-10-11 23:57:30 -0500239#define CONFIG_SYS_BR1_PRELIM (CONFIG_SYS_NAND_BASE \
240 | BR_PS_8 \
241 | BR_MS_UPMA \
242 | BR_V)
243 /* 0x60000881 */
244#define CONFIG_SYS_OR1_PRELIM (OR_AM_64MB | OR_UPM_EAD)
245 /* 0xFC000001 */
Anton Vorontsovfab6f552008-01-09 20:57:47 +0300246
247/*
248 * Fujitsu MB86277 (MINT) graphics controller
249 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200250#define CONFIG_SYS_VIDEO_BASE 0x70000000
Anton Vorontsovfab6f552008-01-09 20:57:47 +0300251
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200252#define CONFIG_SYS_LBLAWBAR2_PRELIM CONFIG_SYS_VIDEO_BASE
Joe Hershberger7d6a0982011-10-11 23:57:30 -0500253#define CONFIG_SYS_LBLAWAR2_PRELIM (LBLAWAR_EN | LBLAWAR_64MB)
Anton Vorontsovfab6f552008-01-09 20:57:47 +0300254
255/* Port size 32 bit, UPMB */
Joe Hershberger7d6a0982011-10-11 23:57:30 -0500256#define CONFIG_SYS_BR2_PRELIM (CONFIG_SYS_VIDEO_BASE \
257 | BR_PS_32 \
258 | BR_MS_UPMB \
259 | BR_V)
260 /* 0x000018a1 */
261#define CONFIG_SYS_OR2_PRELIM (OR_AM_64MB | OR_UPM_EAD)
262 /* 0xFC000001 */
Anton Vorontsovfab6f552008-01-09 20:57:47 +0300263
264/*
265 * Serial Port
266 */
267#define CONFIG_CONS_INDEX 1
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200268#define CONFIG_SYS_NS16550
269#define CONFIG_SYS_NS16550_SERIAL
270#define CONFIG_SYS_NS16550_REG_SIZE 1
271#define CONFIG_SYS_NS16550_CLK get_bus_freq(0)
Anton Vorontsovfab6f552008-01-09 20:57:47 +0300272
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200273#define CONFIG_SYS_BAUDRATE_TABLE \
Joe Hershberger9a986552011-10-11 23:57:17 -0500274 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 115200}
Anton Vorontsovfab6f552008-01-09 20:57:47 +0300275
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200276#define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_IMMR+0x4500)
277#define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_IMMR+0x4600)
Anton Vorontsovfab6f552008-01-09 20:57:47 +0300278
279#define CONFIG_CMDLINE_EDITING 1 /* add command line history */
Joe Hershberger9a986552011-10-11 23:57:17 -0500280#define CONFIG_AUTO_COMPLETE /* add autocompletion support */
Anton Vorontsovfab6f552008-01-09 20:57:47 +0300281/* Use the HUSH parser */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200282#define CONFIG_SYS_HUSH_PARSER
Anton Vorontsovfab6f552008-01-09 20:57:47 +0300283
284/* Pass open firmware flat tree */
285#define CONFIG_OF_LIBFDT 1
286#define CONFIG_OF_BOARD_SETUP 1
Anton Vorontsov3a0cfdd2008-03-24 20:47:02 +0300287#define CONFIG_OF_STDOUT_VIA_ALIAS
Anton Vorontsovfab6f552008-01-09 20:57:47 +0300288
289/* I2C */
Heiko Schocher00f792e2012-10-24 13:48:22 +0200290#define CONFIG_SYS_I2C
291#define CONFIG_SYS_I2C_FSL
292#define CONFIG_SYS_FSL_I2C_SPEED 400000
293#define CONFIG_SYS_FSL_I2C_SLAVE 0x7F
294#define CONFIG_SYS_FSL_I2C_OFFSET 0x3000
295#define CONFIG_SYS_FSL_I2C2_SPEED 400000
296#define CONFIG_SYS_FSL_I2C2_SLAVE 0x7F
297#define CONFIG_SYS_FSL_I2C2_OFFSET 0x3100
298#define CONFIG_SYS_I2C_NOPROBES { {0, 0x52} }
Anton Vorontsovfab6f552008-01-09 20:57:47 +0300299
300/*
301 * General PCI
302 * Addresses are mapped 1-1.
303 */
304#define CONFIG_PCI
Anton Vorontsovfab6f552008-01-09 20:57:47 +0300305
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200306#define CONFIG_SYS_PCI1_MEM_BASE 0x80000000
307#define CONFIG_SYS_PCI1_MEM_PHYS CONFIG_SYS_PCI1_MEM_BASE
308#define CONFIG_SYS_PCI1_MEM_SIZE 0x10000000 /* 256M */
309#define CONFIG_SYS_PCI1_MMIO_BASE 0x90000000
310#define CONFIG_SYS_PCI1_MMIO_PHYS CONFIG_SYS_PCI1_MMIO_BASE
311#define CONFIG_SYS_PCI1_MMIO_SIZE 0x10000000 /* 256M */
Joe Hershberger9a986552011-10-11 23:57:17 -0500312#define CONFIG_SYS_PCI1_IO_BASE 0xE0300000
313#define CONFIG_SYS_PCI1_IO_PHYS 0xE0300000
314#define CONFIG_SYS_PCI1_IO_SIZE 0x100000 /* 1M */
Anton Vorontsovfab6f552008-01-09 20:57:47 +0300315
316#ifdef CONFIG_PCI
Gabor Juhos842033e2013-05-30 07:06:12 +0000317#define CONFIG_PCI_INDIRECT_BRIDGE
Anton Vorontsovfab6f552008-01-09 20:57:47 +0300318
Anton Vorontsovfab6f552008-01-09 20:57:47 +0300319#define CONFIG_PCI_PNP /* do pci plug-and-play */
320
321#undef CONFIG_EEPRO100
322#undef CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200323#define CONFIG_SYS_PCI_SUBSYS_VENDORID 0x1957 /* Freescale */
Anton Vorontsovfab6f552008-01-09 20:57:47 +0300324
325#endif /* CONFIG_PCI */
326
Anton Vorontsovfab6f552008-01-09 20:57:47 +0300327/*
328 * QE UEC ethernet configuration
329 */
330#define CONFIG_UEC_ETH
Kim Phillips78b7a8e2010-07-26 18:34:57 -0500331#define CONFIG_ETHPRIME "UEC0"
Anton Vorontsovfab6f552008-01-09 20:57:47 +0300332
333#define CONFIG_UEC_ETH1 /* GETH1 */
334
335#ifdef CONFIG_UEC_ETH1
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200336#define CONFIG_SYS_UEC1_UCC_NUM 0 /* UCC1 */
337#define CONFIG_SYS_UEC1_RX_CLK QE_CLK_NONE
338#define CONFIG_SYS_UEC1_TX_CLK QE_CLK9
339#define CONFIG_SYS_UEC1_ETH_TYPE GIGA_ETH
340#define CONFIG_SYS_UEC1_PHY_ADDR 2
Joe Hershberger9a986552011-10-11 23:57:17 -0500341#define CONFIG_SYS_UEC1_INTERFACE_TYPE PHY_INTERFACE_MODE_RGMII_RXID
342#define CONFIG_SYS_UEC1_INTERFACE_SPEED 1000
Anton Vorontsovfab6f552008-01-09 20:57:47 +0300343#endif
344
345#define CONFIG_UEC_ETH2 /* GETH2 */
346
347#ifdef CONFIG_UEC_ETH2
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200348#define CONFIG_SYS_UEC2_UCC_NUM 1 /* UCC2 */
349#define CONFIG_SYS_UEC2_RX_CLK QE_CLK_NONE
350#define CONFIG_SYS_UEC2_TX_CLK QE_CLK4
351#define CONFIG_SYS_UEC2_ETH_TYPE GIGA_ETH
352#define CONFIG_SYS_UEC2_PHY_ADDR 4
Joe Hershberger9a986552011-10-11 23:57:17 -0500353#define CONFIG_SYS_UEC2_INTERFACE_TYPE PHY_INTERFACE_MODE_RGMII_RXID
354#define CONFIG_SYS_UEC2_INTERFACE_SPEED 1000
Anton Vorontsovfab6f552008-01-09 20:57:47 +0300355#endif
356
357/*
358 * Environment
359 */
360
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200361#ifndef CONFIG_SYS_RAMBOOT
Jean-Christophe PLAGNIOL-VILLARD5a1aceb2008-09-10 22:48:04 +0200362#define CONFIG_ENV_IS_IN_FLASH 1
Joe Hershberger9a986552011-10-11 23:57:17 -0500363#define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE + CONFIG_SYS_MONITOR_LEN)
Jean-Christophe PLAGNIOL-VILLARD0e8d1582008-09-10 22:48:06 +0200364#define CONFIG_ENV_SECT_SIZE 0x20000 /* 128K(one sector) for env */
365#define CONFIG_ENV_SIZE 0x20000
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200366#else /* CONFIG_SYS_RAMBOOT */
Joe Hershberger9a986552011-10-11 23:57:17 -0500367#define CONFIG_SYS_NO_FLASH 1 /* Flash is not usable now */
Jean-Christophe PLAGNIOL-VILLARD93f6d722008-09-10 22:48:00 +0200368#define CONFIG_ENV_IS_NOWHERE 1 /* Store ENV in memory only */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200369#define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - 0x1000)
Jean-Christophe PLAGNIOL-VILLARD0e8d1582008-09-10 22:48:06 +0200370#define CONFIG_ENV_SIZE 0x2000
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200371#endif /* CONFIG_SYS_RAMBOOT */
Anton Vorontsovfab6f552008-01-09 20:57:47 +0300372
373#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200374#define CONFIG_SYS_LOADS_BAUD_CHANGE 1 /* allow baudrate change */
Anton Vorontsovfab6f552008-01-09 20:57:47 +0300375
376/*
377 * BOOTP options
378 */
379#define CONFIG_BOOTP_BOOTFILESIZE
380#define CONFIG_BOOTP_BOOTPATH
381#define CONFIG_BOOTP_GATEWAY
382#define CONFIG_BOOTP_HOSTNAME
383
384
385/*
386 * Command line configuration.
387 */
388#include <config_cmd_default.h>
389
390#define CONFIG_CMD_PING
391#define CONFIG_CMD_I2C
392#define CONFIG_CMD_ASKENV
Anton Vorontsov3419eb62008-03-24 20:47:00 +0300393#define CONFIG_CMD_DHCP
Anton Vorontsovfab6f552008-01-09 20:57:47 +0300394
395#if defined(CONFIG_PCI)
396#define CONFIG_CMD_PCI
397#endif
398
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200399#if defined(CONFIG_SYS_RAMBOOT)
Mike Frysingerbdab39d2009-01-28 19:08:14 -0500400#undef CONFIG_CMD_SAVEENV
Anton Vorontsovfab6f552008-01-09 20:57:47 +0300401#undef CONFIG_CMD_LOADS
402#endif
403
404#undef CONFIG_WATCHDOG /* watchdog disabled */
405
406/*
407 * Miscellaneous configurable options
408 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200409#define CONFIG_SYS_LONGHELP /* undef to save memory */
410#define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */
411#define CONFIG_SYS_PROMPT "=> " /* Monitor Command Prompt */
Anton Vorontsovfab6f552008-01-09 20:57:47 +0300412
413#if defined(CONFIG_CMD_KGDB)
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200414 #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
Anton Vorontsovfab6f552008-01-09 20:57:47 +0300415#else
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200416 #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
Anton Vorontsovfab6f552008-01-09 20:57:47 +0300417#endif
418
Joe Hershberger9a986552011-10-11 23:57:17 -0500419 /* Print Buffer Size */
420#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16)
421#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
422 /* Boot Argument Buffer Size */
423#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE
424#define CONFIG_SYS_HZ 1000 /* decrementer freq: 1ms ticks */
Anton Vorontsovfab6f552008-01-09 20:57:47 +0300425
426/*
427 * For booting Linux, the board info and command line data
Ira W. Snyder9f530d52010-09-10 15:42:32 -0700428 * have to be in the first 256 MB of memory, since this is
Anton Vorontsovfab6f552008-01-09 20:57:47 +0300429 * the maximum mapped by the Linux kernel during initialization.
430 */
Joe Hershberger9a986552011-10-11 23:57:17 -0500431#define CONFIG_SYS_BOOTMAPSZ (256 << 20) /* Initial Memory map for Linux */
Anton Vorontsovfab6f552008-01-09 20:57:47 +0300432
433/*
434 * Core HID Setup
435 */
Kim Phillips1a2e2032010-04-20 19:37:54 -0500436#define CONFIG_SYS_HID0_INIT 0x000000000
437#define CONFIG_SYS_HID0_FINAL (HID0_ENABLE_MACHINE_CHECK | \
438 HID0_ENABLE_INSTRUCTION_CACHE)
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200439#define CONFIG_SYS_HID2 HID2_HBE
Anton Vorontsovfab6f552008-01-09 20:57:47 +0300440
441/*
Anton Vorontsovfab6f552008-01-09 20:57:47 +0300442 * MMU Setup
443 */
444
Becky Bruce31d82672008-05-08 19:02:12 -0500445#define CONFIG_HIGH_BATS 1 /* High BATs supported */
446
Anton Vorontsovfab6f552008-01-09 20:57:47 +0300447/* DDR: cache cacheable */
Joe Hershberger9a986552011-10-11 23:57:17 -0500448#define CONFIG_SYS_IBAT0L (CONFIG_SYS_SDRAM_BASE \
Joe Hershberger72cd4082011-10-11 23:57:28 -0500449 | BATL_PP_RW \
Joe Hershberger9a986552011-10-11 23:57:17 -0500450 | BATL_MEMCOHERENCE)
451#define CONFIG_SYS_IBAT0U (CONFIG_SYS_SDRAM_BASE \
452 | BATU_BL_256M \
453 | BATU_VS \
454 | BATU_VP)
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200455#define CONFIG_SYS_DBAT0L CONFIG_SYS_IBAT0L
456#define CONFIG_SYS_DBAT0U CONFIG_SYS_IBAT0U
Anton Vorontsovfab6f552008-01-09 20:57:47 +0300457
458/* IMMRBAR & PCI IO: cache-inhibit and guarded */
Joe Hershberger9a986552011-10-11 23:57:17 -0500459#define CONFIG_SYS_IBAT1L (CONFIG_SYS_IMMR \
Joe Hershberger72cd4082011-10-11 23:57:28 -0500460 | BATL_PP_RW \
Joe Hershberger9a986552011-10-11 23:57:17 -0500461 | BATL_CACHEINHIBIT \
462 | BATL_GUARDEDSTORAGE)
463#define CONFIG_SYS_IBAT1U (CONFIG_SYS_IMMR \
464 | BATU_BL_4M \
465 | BATU_VS \
466 | BATU_VP)
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200467#define CONFIG_SYS_DBAT1L CONFIG_SYS_IBAT1L
468#define CONFIG_SYS_DBAT1U CONFIG_SYS_IBAT1U
Anton Vorontsovfab6f552008-01-09 20:57:47 +0300469
470/* NAND: cache-inhibit and guarded */
Joe Hershberger9a986552011-10-11 23:57:17 -0500471#define CONFIG_SYS_IBAT2L (CONFIG_SYS_NAND_BASE \
Joe Hershberger72cd4082011-10-11 23:57:28 -0500472 | BATL_PP_RW \
Joe Hershberger9a986552011-10-11 23:57:17 -0500473 | BATL_CACHEINHIBIT \
474 | BATL_GUARDEDSTORAGE)
475#define CONFIG_SYS_IBAT2U (CONFIG_SYS_NAND_BASE \
476 | BATU_BL_64M \
477 | BATU_VS \
478 | BATU_VP)
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200479#define CONFIG_SYS_DBAT2L CONFIG_SYS_IBAT2L
480#define CONFIG_SYS_DBAT2U CONFIG_SYS_IBAT2U
Anton Vorontsovfab6f552008-01-09 20:57:47 +0300481
482/* FLASH: icache cacheable, but dcache-inhibit and guarded */
Joe Hershberger9a986552011-10-11 23:57:17 -0500483#define CONFIG_SYS_IBAT3L (CONFIG_SYS_FLASH_BASE \
Joe Hershberger72cd4082011-10-11 23:57:28 -0500484 | BATL_PP_RW \
Joe Hershberger9a986552011-10-11 23:57:17 -0500485 | BATL_MEMCOHERENCE)
486#define CONFIG_SYS_IBAT3U (CONFIG_SYS_FLASH_BASE \
487 | BATU_BL_32M \
488 | BATU_VS \
489 | BATU_VP)
490#define CONFIG_SYS_DBAT3L (CONFIG_SYS_FLASH_BASE \
Joe Hershberger72cd4082011-10-11 23:57:28 -0500491 | BATL_PP_RW \
Joe Hershberger9a986552011-10-11 23:57:17 -0500492 | BATL_CACHEINHIBIT \
493 | BATL_GUARDEDSTORAGE)
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200494#define CONFIG_SYS_DBAT3U CONFIG_SYS_IBAT3U
Anton Vorontsovfab6f552008-01-09 20:57:47 +0300495
496/* Stack in dcache: cacheable, no memory coherence */
Joe Hershberger9a986552011-10-11 23:57:17 -0500497#define CONFIG_SYS_IBAT4L (CONFIG_SYS_INIT_RAM_ADDR \
Joe Hershberger72cd4082011-10-11 23:57:28 -0500498 | BATL_PP_RW)
Joe Hershberger9a986552011-10-11 23:57:17 -0500499#define CONFIG_SYS_IBAT4U (CONFIG_SYS_INIT_RAM_ADDR \
500 | BATU_BL_128K \
501 | BATU_VS \
502 | BATU_VP)
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200503#define CONFIG_SYS_DBAT4L CONFIG_SYS_IBAT4L
504#define CONFIG_SYS_DBAT4U CONFIG_SYS_IBAT4U
Anton Vorontsovfab6f552008-01-09 20:57:47 +0300505
Joe Hershberger9a986552011-10-11 23:57:17 -0500506#define CONFIG_SYS_IBAT5L (CONFIG_SYS_VIDEO_BASE \
Joe Hershberger72cd4082011-10-11 23:57:28 -0500507 | BATL_PP_RW \
Joe Hershberger9a986552011-10-11 23:57:17 -0500508 | BATL_CACHEINHIBIT \
509 | BATL_GUARDEDSTORAGE)
510#define CONFIG_SYS_IBAT5U (CONFIG_SYS_VIDEO_BASE \
511 | BATU_BL_64M \
512 | BATU_VS \
513 | BATU_VP)
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200514#define CONFIG_SYS_DBAT5L CONFIG_SYS_IBAT5L
515#define CONFIG_SYS_DBAT5U CONFIG_SYS_IBAT5U
Anton Vorontsovfab6f552008-01-09 20:57:47 +0300516
517#ifdef CONFIG_PCI
518/* PCI MEM space: cacheable */
Joe Hershberger9a986552011-10-11 23:57:17 -0500519#define CONFIG_SYS_IBAT6L (CONFIG_SYS_PCI1_MEM_PHYS \
Joe Hershberger72cd4082011-10-11 23:57:28 -0500520 | BATL_PP_RW \
Joe Hershberger9a986552011-10-11 23:57:17 -0500521 | BATL_MEMCOHERENCE)
522#define CONFIG_SYS_IBAT6U (CONFIG_SYS_PCI1_MEM_PHYS \
523 | BATU_BL_256M \
524 | BATU_VS \
525 | BATU_VP)
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200526#define CONFIG_SYS_DBAT6L CONFIG_SYS_IBAT6L
527#define CONFIG_SYS_DBAT6U CONFIG_SYS_IBAT6U
Anton Vorontsovfab6f552008-01-09 20:57:47 +0300528/* PCI MMIO space: cache-inhibit and guarded */
Joe Hershberger9a986552011-10-11 23:57:17 -0500529#define CONFIG_SYS_IBAT7L (CONFIG_SYS_PCI1_MMIO_PHYS \
Joe Hershberger72cd4082011-10-11 23:57:28 -0500530 | BATL_PP_RW \
Joe Hershberger9a986552011-10-11 23:57:17 -0500531 | BATL_CACHEINHIBIT \
532 | BATL_GUARDEDSTORAGE)
533#define CONFIG_SYS_IBAT7U (CONFIG_SYS_PCI1_MMIO_PHYS \
534 | BATU_BL_256M \
535 | BATU_VS \
536 | BATU_VP)
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200537#define CONFIG_SYS_DBAT7L CONFIG_SYS_IBAT7L
538#define CONFIG_SYS_DBAT7U CONFIG_SYS_IBAT7U
Anton Vorontsovfab6f552008-01-09 20:57:47 +0300539#else /* CONFIG_PCI */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200540#define CONFIG_SYS_IBAT6L (0)
541#define CONFIG_SYS_IBAT6U (0)
542#define CONFIG_SYS_IBAT7L (0)
543#define CONFIG_SYS_IBAT7U (0)
544#define CONFIG_SYS_DBAT6L CONFIG_SYS_IBAT6L
545#define CONFIG_SYS_DBAT6U CONFIG_SYS_IBAT6U
546#define CONFIG_SYS_DBAT7L CONFIG_SYS_IBAT7L
547#define CONFIG_SYS_DBAT7U CONFIG_SYS_IBAT7U
Anton Vorontsovfab6f552008-01-09 20:57:47 +0300548#endif /* CONFIG_PCI */
549
Anton Vorontsovfab6f552008-01-09 20:57:47 +0300550#if defined(CONFIG_CMD_KGDB)
551#define CONFIG_KGDB_BAUDRATE 230400 /* speed of kgdb serial port */
552#define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */
553#endif
554
555/*
556 * Environment Configuration
557 */
558#define CONFIG_ENV_OVERWRITE
559
560#if defined(CONFIG_UEC_ETH)
561#define CONFIG_HAS_ETH0
562#define CONFIG_HAS_ETH1
563#define CONFIG_HAS_ETH2
564#define CONFIG_HAS_ETH3
Anton Vorontsovfab6f552008-01-09 20:57:47 +0300565#endif
566
567#define CONFIG_BAUDRATE 115200
568
569#define CONFIG_LOADADDR a00000
570#define CONFIG_HOSTNAME mpc8360erdk
Joe Hershbergerb3f44c22011-10-13 13:03:48 +0000571#define CONFIG_BOOTFILE "uImage"
Anton Vorontsovfab6f552008-01-09 20:57:47 +0300572
Joe Hershberger8b3637c2011-10-13 13:03:47 +0000573#define CONFIG_ROOTPATH "/nfsroot/"
Anton Vorontsovfab6f552008-01-09 20:57:47 +0300574
575#define CONFIG_BOOTDELAY 2 /* -1 disables auto-boot */
576#undef CONFIG_BOOTARGS /* the boot command will set bootargs */
577
578#define CONFIG_EXTRA_ENV_SETTINGS \
Joe Hershberger9a986552011-10-11 23:57:17 -0500579 "netdev=eth0\0" \
580 "consoledev=ttyS0\0" \
581 "loadaddr=a00000\0" \
582 "fdtaddr=900000\0" \
583 "fdtfile=mpc836x_rdk.dtb\0" \
584 "fsfile=fs\0" \
585 "ubootfile=u-boot.bin\0" \
586 "mtdparts=mtdparts=60000000.nand-flash:4096k(kernel),128k(dtb),"\
587 "-(rootfs)\0" \
588 "setbootargs=setenv bootargs console=$consoledev,$baudrate " \
589 "$mtdparts panic=1\0" \
590 "adddhcpargs=setenv bootargs $bootargs ip=on\0" \
591 "addnfsargs=setenv bootargs $bootargs ip=$ipaddr:$serverip:" \
592 "$gatewayip:$netmask:$hostname:$netdev:off " \
593 "root=/dev/nfs rw nfsroot=$serverip:$rootpath\0" \
594 "addnandargs=setenv bootargs $bootargs root=/dev/mtdblock3 " \
595 "rootfstype=jffs2 rw\0" \
596 "tftp_get_uboot=tftp 100000 $ubootfile\0" \
597 "tftp_get_kernel=tftp $loadaddr $bootfile\0" \
598 "tftp_get_dtb=tftp $fdtaddr $fdtfile\0" \
599 "tftp_get_fs=tftp c00000 $fsfile\0" \
600 "nand_erase_kernel=nand erase 0 400000\0" \
601 "nand_erase_dtb=nand erase 400000 20000\0" \
602 "nand_erase_fs=nand erase 420000 3be0000\0" \
603 "nand_write_kernel=nand write.jffs2 $loadaddr 0 400000\0" \
604 "nand_write_dtb=nand write.jffs2 $fdtaddr 400000 20000\0" \
605 "nand_write_fs=nand write.jffs2 c00000 420000 $filesize\0" \
606 "nand_read_kernel=nand read.jffs2 $loadaddr 0 400000\0" \
607 "nand_read_dtb=nand read.jffs2 $fdtaddr 400000 20000\0" \
608 "nor_reflash=protect off ff800000 ff87ffff ; " \
609 "erase ff800000 ff87ffff ; " \
610 "cp.b 100000 ff800000 $filesize\0" \
611 "nand_reflash_kernel=run tftp_get_kernel nand_erase_kernel " \
612 "nand_write_kernel\0" \
613 "nand_reflash_dtb=run tftp_get_dtb nand_erase_dtb nand_write_dtb\0"\
614 "nand_reflash_fs=run tftp_get_fs nand_erase_fs nand_write_fs\0" \
615 "nand_reflash=run nand_reflash_kernel nand_reflash_dtb " \
616 "nand_reflash_fs\0" \
617 "boot_m=bootm $loadaddr - $fdtaddr\0" \
618 "dhcpboot=dhcp ; run setbootargs adddhcpargs tftp_get_dtb boot_m\0"\
619 "nfsboot=run setbootargs addnfsargs tftp_get_kernel tftp_get_dtb "\
620 "boot_m\0" \
621 "nandboot=run setbootargs addnandargs nand_read_kernel nand_read_dtb "\
622 "boot_m\0" \
623 ""
Anton Vorontsovfab6f552008-01-09 20:57:47 +0300624
625#define CONFIG_BOOTCOMMAND "run dhcpboot"
626
627#endif /* __CONFIG_H */