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Fabian Vogt46025582016-09-26 14:26:47 +02001#include "bcm283x.dtsi"
2
3/ {
Alexander Graf409f05f2017-10-04 14:39:16 +02004 compatible = "brcm,bcm2837";
Fabian Vogt46025582016-09-26 14:26:47 +02005
6 soc {
7 ranges = <0x7e000000 0x3f000000 0x1000000>,
8 <0x40000000 0x40000000 0x00001000>;
9 dma-ranges = <0xc0000000 0x00000000 0x3f000000>;
10
Heinrich Schuchardt143256b2019-04-28 06:46:57 +020011 local_intc: local_intc@40000000 {
Fabian Vogt46025582016-09-26 14:26:47 +020012 compatible = "brcm,bcm2836-l1-intc";
13 reg = <0x40000000 0x100>;
14 interrupt-controller;
Heinrich Schuchardt143256b2019-04-28 06:46:57 +020015 #interrupt-cells = <2>;
Fabian Vogt46025582016-09-26 14:26:47 +020016 interrupt-parent = <&local_intc>;
17 };
18 };
19
Heinrich Schuchardt143256b2019-04-28 06:46:57 +020020 arm-pmu {
21 compatible = "arm,cortex-a53-pmu";
22 interrupt-parent = <&local_intc>;
23 interrupts = <9 IRQ_TYPE_LEVEL_HIGH>;
24 };
25
Fabian Vogt46025582016-09-26 14:26:47 +020026 timer {
27 compatible = "arm,armv7-timer";
28 interrupt-parent = <&local_intc>;
Heinrich Schuchardt143256b2019-04-28 06:46:57 +020029 interrupts = <0 IRQ_TYPE_LEVEL_HIGH>, // PHYS_SECURE_PPI
30 <1 IRQ_TYPE_LEVEL_HIGH>, // PHYS_NONSECURE_PPI
31 <3 IRQ_TYPE_LEVEL_HIGH>, // VIRT_PPI
32 <2 IRQ_TYPE_LEVEL_HIGH>; // HYP_PPI
Fabian Vogt46025582016-09-26 14:26:47 +020033 always-on;
34 };
35
36 cpus: cpus {
37 #address-cells = <1>;
38 #size-cells = <0>;
Alexander Graf409f05f2017-10-04 14:39:16 +020039 enable-method = "brcm,bcm2836-smp"; // for ARM 32-bit
Fabian Vogt46025582016-09-26 14:26:47 +020040
41 cpu0: cpu@0 {
42 device_type = "cpu";
43 compatible = "arm,cortex-a53";
44 reg = <0>;
45 enable-method = "spin-table";
46 cpu-release-addr = <0x0 0x000000d8>;
47 };
48
49 cpu1: cpu@1 {
50 device_type = "cpu";
51 compatible = "arm,cortex-a53";
52 reg = <1>;
53 enable-method = "spin-table";
54 cpu-release-addr = <0x0 0x000000e0>;
55 };
56
57 cpu2: cpu@2 {
58 device_type = "cpu";
59 compatible = "arm,cortex-a53";
60 reg = <2>;
61 enable-method = "spin-table";
62 cpu-release-addr = <0x0 0x000000e8>;
63 };
64
65 cpu3: cpu@3 {
66 device_type = "cpu";
67 compatible = "arm,cortex-a53";
68 reg = <3>;
69 enable-method = "spin-table";
70 cpu-release-addr = <0x0 0x000000f0>;
71 };
72 };
73};
74
75/* Make the BCM2835-style global interrupt controller be a child of the
76 * CPU-local interrupt controller.
77 */
78&intc {
79 compatible = "brcm,bcm2836-armctrl-ic";
80 reg = <0x7e00b200 0x200>;
81 interrupt-parent = <&local_intc>;
Heinrich Schuchardt143256b2019-04-28 06:46:57 +020082 interrupts = <8 IRQ_TYPE_LEVEL_HIGH>;
Fabian Vogt46025582016-09-26 14:26:47 +020083};
Alexander Graf409f05f2017-10-04 14:39:16 +020084
85&cpu_thermal {
86 coefficients = <(-538) 412000>;
87};
88
89/* enable thermal sensor with the correct compatible property set */
90&thermal {
91 compatible = "brcm,bcm2837-thermal";
92 status = "okay";
93};