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Ioana Ciornei74f04492020-04-27 15:21:14 +03001// SPDX-License-Identifier: GPL-2.0+ OR X11
2/*
3 * NXP LX2160AQDS common device tree source
4 *
5 * Copyright 2018-2019 NXP
6 *
7 */
8
9#include "fsl-lx2160a.dtsi"
10
11&dpmac17 {
12 status = "okay";
13 phy-handle = <&rgmii_phy1>;
14 phy-connection-type = "rgmii-id";
15};
16
17&dpmac18 {
18 status = "okay";
19 phy-handle = <&rgmii_phy2>;
20 phy-connection-type = "rgmii-id";
21};
22
23&emdio1 {
24 status = "okay";
25};
26
27&emdio2 {
28 status = "okay";
29};
30
31&esdhc0 {
32 status = "okay";
33};
34
35&esdhc1 {
36 status = "okay";
37};
38
39&i2c0 {
40 status = "okay";
41 u-boot,dm-pre-reloc;
42
43 fpga@66 {
44 #address-cells = <1>;
45 #size-cells = <0>;
46 compatible = "simple-mfd";
47 reg = <0x66>;
48
49 mux-mdio@54 {
50 #address-cells = <1>;
51 #size-cells = <0>;
52 compatible = "mdio-mux-i2creg";
53 reg = <0x54>;
54 #mux-control-cells = <1>;
55 mux-reg-masks = <0x54 0xf8>; // reg 0x54, bits 7:3
56 mdio-parent-bus = <&emdio1>;
57
58 mdio@00 {
59 #address-cells = <1>;
60 #size-cells = <0>;
61 reg = <0x00>;
62
63 rgmii_phy1: ethernet-phy@1 {
64 reg = <0x1>;
65 };
66 };
67 mdio@08 {
68 #address-cells = <1>;
69 #size-cells = <0>;
70 reg = <0x40>;
71
72 rgmii_phy2: ethernet-phy@2 {
73 reg = <0x2>;
74 };
75 };
76
77 emdio1_slot1: mdio@c0 { /* I/O Slot #1 */
78 reg = <0xC0>;
79 device-name = "emdio1_slot1";
80 #address-cells = <1>;
81 #size-cells = <0>;
82 };
83
84 emdio1_slot2: mdio@c8 { /* I/O Slot #2 */
85 reg = <0xC8>;
86 device-name = "emdio1_slot2";
87 #address-cells = <1>;
88 #size-cells = <0>;
89 };
90
91 emdio1_slot3: mdio@d0 { /* I/O Slot #3 */
92 reg = <0xD0>;
93 device-name = "emdio1_slot3";
94 #address-cells = <1>;
95 #size-cells = <0>;
96 };
97
98 emdio1_slot4: mdio@d8 { /* I/O Slot #4 */
99 reg = <0xD8>;
100 device-name = "emdio1_slot4";
101 #address-cells = <1>;
102 #size-cells = <0>;
103 };
104
105 emdio1_slot5: mdio@e0 { /* I/O Slot #5 */
106 reg = <0xE0>;
107 device-name = "emdio1_slot5";
108 #address-cells = <1>;
109 #size-cells = <0>;
110 };
111
112 emdio1_slot6: mdio@e8 { /* I/O Slot #6 */
113 reg = <0xE8>;
114 device-name = "emdio1_slot6";
115 #address-cells = <1>;
116 #size-cells = <0>;
117 };
118
119 emdio1_slot7: mdio@f0 { /* I/O Slot #7 */
120 reg = <0xF0>;
121 device-name = "emdio1_slot7";
122 #address-cells = <1>;
123 #size-cells = <0>;
124 };
125
126 emdio1_slot8: mdio@f8 { /* I/O Slot #8 */
127 reg = <0xF8>;
128 device-name = "emdio1_slot8";
129 #address-cells = <1>;
130 #size-cells = <0>;
131 };
132 };
133
134 };
135
136 i2c-mux@77 {
137 compatible = "nxp,pca9547";
138 reg = <0x77>;
139 #address-cells = <1>;
140 #size-cells = <0>;
141
142 i2c@3 {
143 #address-cells = <1>;
144 #size-cells = <0>;
145 reg = <0x3>;
146
147 rtc@51 {
148 compatible = "pcf2127-rtc";
149 reg = <0x51>;
150 };
151 };
152 };
153};
154
155&sata0 {
156 status = "okay";
157};
158
159&sata1 {
160 status = "okay";
161};
162
163&sata2 {
164 status = "okay";
165};
166
167&sata3 {
168 status = "okay";
169};