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wdenkdc7c9a12003-03-26 06:55:25 +00001/*
2 * Rick Bronson <rick@efn.org>
3 *
Jean-Christophe PLAGNIOL-VILLARD4a129a52008-11-30 19:36:53 +01004 * Configuration settings for the AT91RM9200DK board.
wdenkdc7c9a12003-03-26 06:55:25 +00005 *
6 * See file CREDITS for list of people who contributed to this
7 * project.
8 *
9 * This program is free software; you can redistribute it and/or
10 * modify it under the terms of the GNU General Public License as
11 * published by the Free Software Foundation; either version 2 of
12 * the License, or (at your option) any later version.
13 *
14 * This program is distributed in the hope that it will be useful,
15 * but WITHOUT ANY WARRANTY; without even the implied warranty of
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 * GNU General Public License for more details.
18 *
19 * You should have received a copy of the GNU General Public License
20 * along with this program; if not, write to the Free Software
21 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
22 * MA 02111-1307 USA
23 */
24
25#ifndef __CONFIG_H
26#define __CONFIG_H
27
28/* ARM asynchronous clock */
wdenk8b07a112004-07-10 21:45:47 +000029#define AT91C_MAIN_CLOCK 179712000 /* from 18.432 MHz crystal (18432000 / 4 * 39) */
30#define AT91C_MASTER_CLOCK 59904000 /* peripheral clock (AT91C_MASTER_CLOCK / 3) */
31/* #define AT91C_MASTER_CLOCK 44928000 */ /* peripheral clock (AT91C_MASTER_CLOCK / 4) */
wdenkdc7c9a12003-03-26 06:55:25 +000032
wdenkd9df1f42004-03-15 09:00:01 +000033#define AT91_SLOW_CLOCK 32768 /* slow clock */
34
wdenka85f9f22005-04-06 13:52:31 +000035#define CONFIG_ARM920T 1 /* This is an ARM920T Core */
36#define CONFIG_AT91RM9200 1 /* It's an Atmel AT91RM9200 SoC */
37#define CONFIG_AT91RM9200DK 1 /* on an AT91RM9200DK Board */
38#undef CONFIG_USE_IRQ /* we don't need IRQ/FIQ stuff */
39#define USE_920T_MMU 1
40
wdenk8b07a112004-07-10 21:45:47 +000041#define CONFIG_CMDLINE_TAG 1 /* enable passing of ATAGs */
wdenkdc7c9a12003-03-26 06:55:25 +000042#define CONFIG_SETUP_MEMORY_TAGS 1
wdenk8b07a112004-07-10 21:45:47 +000043#define CONFIG_INITRD_TAG 1
wdenk2abbe072003-06-16 23:50:08 +000044
wdenk8aa1a2d2005-04-04 12:44:11 +000045#ifndef CONFIG_SKIP_LOWLEVEL_INIT
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020046#define CONFIG_SYS_USE_MAIN_OSCILLATOR 1
wdenkef2807c2005-03-31 23:44:33 +000047/* flash */
Jean-Christophe PLAGNIOL-VILLARDd481c802009-01-03 17:22:25 +010048#define CONFIG_SYS_EBI_CFGR_VAL 0x00000000
49#define CONFIG_SYS_SMC_CSR0_VAL 0x00003284 /* 16bit, 2 TDF, 4 WS */
wdenkef2807c2005-03-31 23:44:33 +000050
51/* clocks */
Jean-Christophe PLAGNIOL-VILLARDd481c802009-01-03 17:22:25 +010052#define CONFIG_SYS_PLLAR_VAL 0x20263E04 /* 179.712000 MHz for PCK */
53#define CONFIG_SYS_PLLBR_VAL 0x10483E0E /* 48.054857 MHz (divider by 2 for USB) */
54#define CONFIG_SYS_MCKR_VAL 0x00000202 /* PCK/3 = MCK Master Clock = 59.904000MHz from PLLA */
wdenkef2807c2005-03-31 23:44:33 +000055
56/* sdram */
Jean-Christophe PLAGNIOL-VILLARDd481c802009-01-03 17:22:25 +010057#define CONFIG_SYS_PIOC_ASR_VAL 0xFFFF0000 /* Configure PIOC as peripheral (D16/D31) */
58#define CONFIG_SYS_PIOC_BSR_VAL 0x00000000
59#define CONFIG_SYS_PIOC_PDR_VAL 0xFFFF0000
60#define CONFIG_SYS_EBI_CSA_VAL 0x00000002 /* CS1=CONFIG_SYS_SDRAM */
61#define CONFIG_SYS_SDRC_CR_VAL 0x2188c155 /* set up the CONFIG_SYS_SDRAM */
62#define CONFIG_SYS_SDRAM 0x20000000 /* address of the CONFIG_SYS_SDRAM */
63#define CONFIG_SYS_SDRAM1 0x20000080 /* address of the CONFIG_SYS_SDRAM */
64#define CONFIG_SYS_SDRAM_VAL 0x00000000 /* value written to CONFIG_SYS_SDRAM */
65#define CONFIG_SYS_SDRC_MR_VAL 0x00000002 /* Precharge All */
66#define CONFIG_SYS_SDRC_MR_VAL1 0x00000004 /* refresh */
67#define CONFIG_SYS_SDRC_MR_VAL2 0x00000003 /* Load Mode Register */
68#define CONFIG_SYS_SDRC_MR_VAL3 0x00000000 /* Normal Mode */
69#define CONFIG_SYS_SDRC_TR_VAL 0x000002E0 /* Write refresh rate */
Jens Scharsig80523522008-11-18 10:48:46 +010070#else
71#define CONFIG_SKIP_RELOCATE_UBOOT
wdenk8aa1a2d2005-04-04 12:44:11 +000072#endif /* CONFIG_SKIP_LOWLEVEL_INIT */
wdenkdc7c9a12003-03-26 06:55:25 +000073/*
74 * Size of malloc() pool
75 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020076#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + 128*1024)
77#define CONFIG_SYS_GBL_DATA_SIZE 128 /* size in bytes reserved for initial data */
wdenka8c7c702003-12-06 19:49:23 +000078
wdenkdc7c9a12003-03-26 06:55:25 +000079#define CONFIG_BAUDRATE 115200
wdenka8c7c702003-12-06 19:49:23 +000080
wdenkdc7c9a12003-03-26 06:55:25 +000081/*
82 * Hardware drivers
83 */
84
wdenk9d5028c2004-11-21 00:06:33 +000085/* define one of these to choose the DBGU, USART0 or USART1 as console */
Jean-Christophe PLAGNIOL-VILLARDbeebd852009-03-27 23:26:43 +010086#define CONFIG_AT91RM9200_USART
wdenk4734cb72004-09-21 23:33:32 +000087#define CONFIG_DBGU
wdenk9d5028c2004-11-21 00:06:33 +000088#undef CONFIG_USART0
wdenk4734cb72004-09-21 23:33:32 +000089#undef CONFIG_USART1
90
wdenkdc7c9a12003-03-26 06:55:25 +000091#undef CONFIG_HWFLOW /* don't include RTS/CTS flow control support */
92
93#undef CONFIG_MODEM_SUPPORT /* disable modem initialization stuff */
94
wdenk8bde7f72003-06-27 21:31:46 +000095#define CONFIG_BOOTDELAY 3
wdenk8b07a112004-07-10 21:45:47 +000096/* #define CONFIG_ENV_OVERWRITE 1 */
wdenk2abbe072003-06-16 23:50:08 +000097
wdenk8bde7f72003-06-27 21:31:46 +000098
Jon Loeliger0b361c92007-07-04 22:31:42 -050099/*
Jon Loeliger80ff4f92007-07-10 09:29:01 -0500100 * BOOTP options
101 */
102#define CONFIG_BOOTP_BOOTFILESIZE
103#define CONFIG_BOOTP_BOOTPATH
104#define CONFIG_BOOTP_GATEWAY
105#define CONFIG_BOOTP_HOSTNAME
106
107
108/*
Jon Loeliger0b361c92007-07-04 22:31:42 -0500109 * Command line configuration.
110 */
111#include <config_cmd_default.h>
112
Jon Loeliger0b361c92007-07-04 22:31:42 -0500113#define CONFIG_CMD_DHCP
Wolfgang Denk3c959602008-07-31 10:12:09 +0200114#define CONFIG_CMD_MII
wdenkdc7c9a12003-03-26 06:55:25 +0000115
Wolfgang Denk3c959602008-07-31 10:12:09 +0200116#include <asm/arch/AT91RM9200.h> /* needed for port definitions */
wdenkdc7c9a12003-03-26 06:55:25 +0000117
118#define CONFIG_NR_DRAM_BANKS 1
119#define PHYS_SDRAM 0x20000000
120#define PHYS_SDRAM_SIZE 0x2000000 /* 32 megs */
121
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200122#define CONFIG_SYS_MEMTEST_START PHYS_SDRAM
123#define CONFIG_SYS_MEMTEST_END CONFIG_SYS_MEMTEST_START + PHYS_SDRAM_SIZE - 262144
wdenkdc7c9a12003-03-26 06:55:25 +0000124
125#define CONFIG_DRIVER_ETHER
wdenk8b07a112004-07-10 21:45:47 +0000126#define CONFIG_NET_RETRY_COUNT 20
wdenk074cff02004-02-24 00:16:43 +0000127#define CONFIG_AT91C_USE_RMII
wdenk2abbe072003-06-16 23:50:08 +0000128
Peter Pearsed4fc6012007-08-14 10:10:52 +0100129/* AC Characteristics */
130/* DLYBS = tCSS = 250ns min and DLYBCT = tCSH = 250ns */
131#define DATAFLASH_TCSS (0xC << 16)
132#define DATAFLASH_TCHS (0x1 << 24)
133
wdenk8b07a112004-07-10 21:45:47 +0000134#define CONFIG_HAS_DATAFLASH 1
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200135#define CONFIG_SYS_SPI_WRITE_TOUT (5*CONFIG_SYS_HZ)
136#define CONFIG_SYS_MAX_DATAFLASH_BANKS 2
137#define CONFIG_SYS_MAX_DATAFLASH_PAGES 16384
138#define CONFIG_SYS_DATAFLASH_LOGIC_ADDR_CS0 0xC0000000 /* Logical adress for CS0 */
139#define CONFIG_SYS_DATAFLASH_LOGIC_ADDR_CS3 0xD0000000 /* Logical adress for CS3 */
wdenkdc7c9a12003-03-26 06:55:25 +0000140
wdenk8b07a112004-07-10 21:45:47 +0000141#define PHYS_FLASH_1 0x10000000
142#define PHYS_FLASH_SIZE 0x200000 /* 2 megs main flash */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200143#define CONFIG_SYS_FLASH_BASE PHYS_FLASH_1
144#define CONFIG_SYS_MAX_FLASH_BANKS 1
145#define CONFIG_SYS_MAX_FLASH_SECT 256
146#define CONFIG_SYS_FLASH_ERASE_TOUT (2*CONFIG_SYS_HZ) /* Timeout for Flash Erase */
147#define CONFIG_SYS_FLASH_WRITE_TOUT (2*CONFIG_SYS_HZ) /* Timeout for Flash Write */
wdenk5779d8d2003-12-06 23:55:10 +0000148
Jean-Christophe PLAGNIOL-VILLARD057c8492008-09-10 22:47:58 +0200149#undef CONFIG_ENV_IS_IN_DATAFLASH
wdenk5779d8d2003-12-06 23:55:10 +0000150
Jean-Christophe PLAGNIOL-VILLARD057c8492008-09-10 22:47:58 +0200151#ifdef CONFIG_ENV_IS_IN_DATAFLASH
Jean-Christophe PLAGNIOL-VILLARD0e8d1582008-09-10 22:48:06 +0200152#define CONFIG_ENV_OFFSET 0x20000
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200153#define CONFIG_ENV_ADDR (CONFIG_SYS_DATAFLASH_LOGIC_ADDR_CS0 + CONFIG_ENV_OFFSET)
Jean-Christophe PLAGNIOL-VILLARD0e8d1582008-09-10 22:48:06 +0200154#define CONFIG_ENV_SIZE 0x2000 /* 0x8000 */
wdenk5779d8d2003-12-06 23:55:10 +0000155#else
Jean-Christophe PLAGNIOL-VILLARD5a1aceb2008-09-10 22:48:04 +0200156#define CONFIG_ENV_IS_IN_FLASH 1
wdenk8aa1a2d2005-04-04 12:44:11 +0000157#ifdef CONFIG_SKIP_LOWLEVEL_INIT
Jean-Christophe PLAGNIOL-VILLARD0e8d1582008-09-10 22:48:06 +0200158#define CONFIG_ENV_ADDR (PHYS_FLASH_1 + 0xe000) /* between boot.bin and u-boot.bin.gz */
159#define CONFIG_ENV_SIZE 0x2000 /* 0x8000 */
Ladislav Michl481f28b2007-12-06 22:59:16 +0100160#else
Jean-Christophe PLAGNIOL-VILLARD0e8d1582008-09-10 22:48:06 +0200161#define CONFIG_ENV_ADDR (PHYS_FLASH_1 + 0x60000) /* after u-boot.bin */
162#define CONFIG_ENV_SIZE 0x10000 /* sectors are 64K here */
wdenk8aa1a2d2005-04-04 12:44:11 +0000163#endif /* CONFIG_SKIP_LOWLEVEL_INIT */
Jean-Christophe PLAGNIOL-VILLARD057c8492008-09-10 22:47:58 +0200164#endif /* CONFIG_ENV_IS_IN_DATAFLASH */
wdenk5779d8d2003-12-06 23:55:10 +0000165
166
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200167#define CONFIG_SYS_LOAD_ADDR 0x21000000 /* default load address */
wdenkdc7c9a12003-03-26 06:55:25 +0000168
wdenk8aa1a2d2005-04-04 12:44:11 +0000169#ifdef CONFIG_SKIP_LOWLEVEL_INIT
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200170#define CONFIG_SYS_BOOT_SIZE 0x6000 /* 24 KBytes */
171#define CONFIG_SYS_U_BOOT_BASE (PHYS_FLASH_1 + 0x10000)
172#define CONFIG_SYS_U_BOOT_SIZE 0x10000 /* 64 KBytes */
Ladislav Michl481f28b2007-12-06 22:59:16 +0100173#else
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200174#define CONFIG_SYS_BOOT_SIZE 0x00 /* 0 KBytes */
175#define CONFIG_SYS_U_BOOT_BASE PHYS_FLASH_1
176#define CONFIG_SYS_U_BOOT_SIZE 0x60000 /* 384 KBytes */
wdenk8aa1a2d2005-04-04 12:44:11 +0000177#endif /* CONFIG_SKIP_LOWLEVEL_INIT */
wdenk2abbe072003-06-16 23:50:08 +0000178
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200179#define CONFIG_SYS_BAUDRATE_TABLE { 115200, 19200, 38400, 57600, 9600 }
wdenkdc7c9a12003-03-26 06:55:25 +0000180
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200181#define CONFIG_SYS_PROMPT "U-Boot> " /* Monitor Command Prompt */
182#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
183#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
184#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
wdenkdc7c9a12003-03-26 06:55:25 +0000185
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200186#define CONFIG_SYS_HZ 1000
187#define CONFIG_SYS_HZ_CLOCK AT91C_MASTER_CLOCK/2 /* AT91C_TC0_CMR is implicitly set to */
Ladislav Michl2c5260f2007-12-06 23:24:57 +0100188 /* AT91C_TC_TIMER_DIV1_CLOCK */
wdenkdc7c9a12003-03-26 06:55:25 +0000189
190#define CONFIG_STACKSIZE (32*1024) /* regular stack */
191
192#ifdef CONFIG_USE_IRQ
193#error CONFIG_USE_IRQ not supported
194#endif
195
196#endif