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Stelian Pop8e429b32008-05-08 18:52:23 +02001/*
2 * (C) Copyright 2007-2008
3 * Stelian Pop <stelian.pop@leadtechdesign.com>
4 * Lead Tech Design <www.leadtechdesign.com>
5 *
6 * Configuation settings for the AT91SAM9263EK board.
7 *
8 * See file CREDITS for list of people who contributed to this
9 * project.
10 *
11 * This program is free software; you can redistribute it and/or
12 * modify it under the terms of the GNU General Public License as
13 * published by the Free Software Foundation; either version 2 of
14 * the License, or (at your option) any later version.
15 *
16 * This program is distributed in the hope that it will be useful,
17 * but WITHOUT ANY WARRANTY; without even the implied warranty of
18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
19 * GNU General Public License for more details.
20 *
21 * You should have received a copy of the GNU General Public License
22 * along with this program; if not, write to the Free Software
23 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
24 * MA 02111-1307 USA
25 */
26
27#ifndef __CONFIG_H
28#define __CONFIG_H
29
30/* ARM asynchronous clock */
Stelian Popad229a42008-11-07 13:55:14 +010031#define AT91_MAIN_CLOCK 16367660 /* 16.367 MHz crystal */
Jean-Christophe PLAGNIOL-VILLARD6ebff362009-04-16 21:30:48 +020032#define CONFIG_SYS_HZ 1000
Stelian Pop8e429b32008-05-08 18:52:23 +020033
Stelian Pop8e429b32008-05-08 18:52:23 +020034#define CONFIG_ARM926EJS 1 /* This is an ARM926EJS Core */
35#define CONFIG_AT91SAM9263 1 /* It's an Atmel AT91SAM9263 SoC*/
36#define CONFIG_AT91SAM9263EK 1 /* on an AT91SAM9263EK Board */
Jean-Christophe PLAGNIOL-VILLARDdc39ae92009-04-16 21:30:44 +020037#define CONFIG_ARCH_CPU_INIT
Stelian Pop8e429b32008-05-08 18:52:23 +020038#undef CONFIG_USE_IRQ /* we don't need IRQ/FIQ stuff */
39
40#define CONFIG_CMDLINE_TAG 1 /* enable passing of ATAGs */
41#define CONFIG_SETUP_MEMORY_TAGS 1
42#define CONFIG_INITRD_TAG 1
43
Jean-Christophe PLAGNIOL-VILLARD1b3b7c62009-06-13 12:48:36 +020044#ifndef CONFIG_SYS_USE_BOOT_NORFLASH
Stelian Pop8e429b32008-05-08 18:52:23 +020045#define CONFIG_SKIP_LOWLEVEL_INIT
46#define CONFIG_SKIP_RELOCATE_UBOOT
Jean-Christophe PLAGNIOL-VILLARD1b3b7c62009-06-13 12:48:36 +020047#endif
Stelian Pop8e429b32008-05-08 18:52:23 +020048
49/*
50 * Hardware drivers
51 */
52#define CONFIG_ATMEL_USART 1
53#undef CONFIG_USART0
54#undef CONFIG_USART1
55#undef CONFIG_USART2
56#define CONFIG_USART3 1 /* USART 3 is DBGU */
57
Stelian Pop56a24792008-05-08 14:52:31 +020058/* LCD */
59#define CONFIG_LCD 1
60#define LCD_BPP LCD_COLOR8
61#define CONFIG_LCD_LOGO 1
62#undef LCD_TEST_PATTERN
63#define CONFIG_LCD_INFO 1
64#define CONFIG_LCD_INFO_BELOW_LOGO 1
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020065#define CONFIG_SYS_WHITE_ON_BLACK 1
Stelian Pop56a24792008-05-08 14:52:31 +020066#define CONFIG_ATMEL_LCD 1
67#define CONFIG_ATMEL_LCD_BGR555 1
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020068#define CONFIG_SYS_CONSOLE_IS_IN_ENV 1
Stelian Pop56a24792008-05-08 14:52:31 +020069
Jean-Christophe PLAGNIOL-VILLARDa484b002009-03-21 21:08:00 +010070/* LED */
71#define CONFIG_AT91_LED
72#define CONFIG_RED_LED AT91_PIN_PB7 /* this is the power led */
73#define CONFIG_GREEN_LED AT91_PIN_PB8 /* this is the user1 led */
74#define CONFIG_YELLOW_LED AT91_PIN_PC29 /* this is the user2 led */
75
Stelian Pop8e429b32008-05-08 18:52:23 +020076#define CONFIG_BOOTDELAY 3
77
Stelian Pop8e429b32008-05-08 18:52:23 +020078/*
79 * BOOTP options
80 */
81#define CONFIG_BOOTP_BOOTFILESIZE 1
82#define CONFIG_BOOTP_BOOTPATH 1
83#define CONFIG_BOOTP_GATEWAY 1
84#define CONFIG_BOOTP_HOSTNAME 1
85
86/*
87 * Command line configuration.
88 */
89#include <config_cmd_default.h>
90#undef CONFIG_CMD_BDI
Stelian Pop8e429b32008-05-08 18:52:23 +020091#undef CONFIG_CMD_FPGA
Wolfgang Denk74de7ae2009-04-01 23:34:12 +020092#undef CONFIG_CMD_IMI
Stelian Pop8e429b32008-05-08 18:52:23 +020093#undef CONFIG_CMD_IMLS
Wolfgang Denk74de7ae2009-04-01 23:34:12 +020094#undef CONFIG_CMD_LOADS
95#undef CONFIG_CMD_SOURCE
Stelian Pop8e429b32008-05-08 18:52:23 +020096
97#define CONFIG_CMD_PING 1
98#define CONFIG_CMD_DHCP 1
99#define CONFIG_CMD_NAND 1
100#define CONFIG_CMD_USB 1
101
102/* SDRAM */
103#define CONFIG_NR_DRAM_BANKS 1
104#define PHYS_SDRAM 0x20000000
105#define PHYS_SDRAM_SIZE 0x04000000 /* 64 megs */
106
107/* DataFlash */
Jean-Christophe PLAGNIOL-VILLARD4758ebd2009-03-27 23:26:44 +0100108#define CONFIG_ATMEL_DATAFLASH_SPI
Stelian Pop8e429b32008-05-08 18:52:23 +0200109#define CONFIG_HAS_DATAFLASH 1
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200110#define CONFIG_SYS_SPI_WRITE_TOUT (5*CONFIG_SYS_HZ)
111#define CONFIG_SYS_MAX_DATAFLASH_BANKS 1
112#define CONFIG_SYS_DATAFLASH_LOGIC_ADDR_CS0 0xC0000000 /* CS0 */
Stelian Pop8e429b32008-05-08 18:52:23 +0200113#define AT91_SPI_CLK 15000000
114#define DATAFLASH_TCSS (0x1a << 16)
115#define DATAFLASH_TCHS (0x1 << 24)
116
117/* NOR flash, if populated */
Jean-Christophe PLAGNIOL-VILLARD1b3b7c62009-06-13 12:48:36 +0200118#ifdef CONFIG_SYS_USE_NORFLASH
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200119#define CONFIG_SYS_FLASH_CFI 1
Jean-Christophe PLAGNIOL-VILLARD1b3b7c62009-06-13 12:48:36 +0200120#define CONFIG_FLASH_CFI_DRIVER 1
121#define PHYS_FLASH_1 0x10000000
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200122#define CONFIG_SYS_FLASH_BASE PHYS_FLASH_1
123#define CONFIG_SYS_MAX_FLASH_SECT 256
124#define CONFIG_SYS_MAX_FLASH_BANKS 1
Jean-Christophe PLAGNIOL-VILLARD1b3b7c62009-06-13 12:48:36 +0200125
126#define CONFIG_SYS_MONITOR_SEC 1:0-3
127#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE
128#define CONFIG_SYS_MONITOR_LEN (256 << 10)
129#define CONFIG_ENV_IS_IN_FLASH 1
130#define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + 0x007FE000)
131#define CONFIG_ENV_ADDR_REDUND (CONFIG_ENV_ADDR - CONFIG_ENV_SIZE)
132
133/* Address and size of Primary Environment Sector */
134#define CONFIG_ENV_SIZE 0x2000
135
136#define xstr(s) str(s)
137#define str(s) #s
138
139#define CONFIG_EXTRA_ENV_SETTINGS \
140 "monitor_base=" xstr(CONFIG_SYS_MONITOR_BASE) "\0" \
141 "update=" \
142 "protect off ${monitor_base} +${filesize};" \
143 "erase ${monitor_base} +${filesize};" \
144 "cp.b ${load_addr} ${monitor_base} ${filesize};" \
145 "protect on ${monitor_base} +${filesize}\0"
146
147#ifndef CONFIG_SKIP_LOWLEVEL_INIT
148#define MASTER_PLL_MUL 171
149#define MASTER_PLL_DIV 14
150
151/* clocks */
152#define CONFIG_SYS_MOR_VAL \
153 (AT91_PMC_MOSCEN | \
154 (255 << 8)) /* Main Oscillator Start-up Time */
155#define CONFIG_SYS_PLLAR_VAL \
156 (AT91_PMC_PLLA_WR_ERRATA | /* Bit 29 must be 1 when prog */ \
157 AT91_PMC_OUT | \
158 AT91_PMC_PLLCOUNT | /* PLL Counter */ \
159 (2 << 28) | /* PLL Clock Frequency Range */ \
160 ((MASTER_PLL_MUL - 1) << 16) | (MASTER_PLL_DIV))
161
162/* PCK/2 = MCK Master Clock from PLLA */
163#define CONFIG_SYS_MCKR1_VAL \
164 (AT91_PMC_CSS_SLOW | \
165 AT91_PMC_PRES_1 | \
166 AT91SAM9_PMC_MDIV_2 | \
167 AT91_PMC_PDIV_1)
168/* PCK/2 = MCK Master Clock from PLLA */
169#define CONFIG_SYS_MCKR2_VAL \
170 (AT91_PMC_CSS_PLLA | \
171 AT91_PMC_PRES_1 | \
172 AT91SAM9_PMC_MDIV_2 | \
173 AT91_PMC_PDIV_1)
174
175/* define PDC[31:16] as DATA[31:16] */
176#define CONFIG_SYS_PIOD_PDR_VAL1 0xFFFF0000
177/* no pull-up for D[31:16] */
178#define CONFIG_SYS_PIOD_PPUDR_VAL 0xFFFF0000
179/* EBI0_CSA, CS1 SDRAM, CS3 NAND Flash, 3.3V memories */
180#define CONFIG_SYS_MATRIX_EBI0CSA_VAL \
181 (AT91_MATRIX_EBI0_DBPUC | AT91_MATRIX_EBI0_VDDIOMSEL_3_3V | \
182 AT91_MATRIX_EBI0_CS1A_SDRAMC)
183
184/* SDRAM */
185/* SDRAMC_MR Mode register */
186#define CONFIG_SYS_SDRC_MR_VAL1 0
187/* SDRAMC_TR - Refresh Timer register */
188#define CONFIG_SYS_SDRC_TR_VAL1 0x13C
189/* SDRAMC_CR - Configuration register*/
190#define CONFIG_SYS_SDRC_CR_VAL \
191 (AT91_SDRAMC_NC_9 | \
192 AT91_SDRAMC_NR_13 | \
193 AT91_SDRAMC_NB_4 | \
194 AT91_SDRAMC_CAS_3 | \
195 AT91_SDRAMC_DBW_32 | \
196 (1 << 8) | /* Write Recovery Delay */ \
197 (7 << 12) | /* Row Cycle Delay */ \
198 (2 << 16) | /* Row Precharge Delay */ \
199 (2 << 20) | /* Row to Column Delay */ \
200 (5 << 24) | /* Active to Precharge Delay */ \
201 (1 << 28)) /* Exit Self Refresh to Active Delay */
202
203/* Memory Device Register -> SDRAM */
204#define CONFIG_SYS_SDRC_MDR_VAL AT91_SDRAMC_MD_SDRAM
205#define CONFIG_SYS_SDRC_MR_VAL2 AT91_SDRAMC_MODE_PRECHARGE
206#define CONFIG_SYS_SDRAM_VAL1 0 /* SDRAM_BASE */
207#define CONFIG_SYS_SDRC_MR_VAL3 AT91_SDRAMC_MODE_REFRESH
208#define CONFIG_SYS_SDRAM_VAL2 0 /* SDRAM_BASE */
209#define CONFIG_SYS_SDRAM_VAL3 0 /* SDRAM_BASE */
210#define CONFIG_SYS_SDRAM_VAL4 0 /* SDRAM_BASE */
211#define CONFIG_SYS_SDRAM_VAL5 0 /* SDRAM_BASE */
212#define CONFIG_SYS_SDRAM_VAL6 0 /* SDRAM_BASE */
213#define CONFIG_SYS_SDRAM_VAL7 0 /* SDRAM_BASE */
214#define CONFIG_SYS_SDRAM_VAL8 0 /* SDRAM_BASE */
215#define CONFIG_SYS_SDRAM_VAL9 0 /* SDRAM_BASE */
216#define CONFIG_SYS_SDRC_MR_VAL4 AT91_SDRAMC_MODE_LMR
217#define CONFIG_SYS_SDRAM_VAL10 0 /* SDRAM_BASE */
218#define CONFIG_SYS_SDRC_MR_VAL5 AT91_SDRAMC_MODE_NORMAL
219#define CONFIG_SYS_SDRAM_VAL11 0 /* SDRAM_BASE */
220#define CONFIG_SYS_SDRC_TR_VAL2 1200 /* SDRAM_TR */
221#define CONFIG_SYS_SDRAM_VAL12 0 /* SDRAM_BASE */
222
223/* setup SMC0, CS0 (NOR Flash) - 16-bit, 15 WS */
224#define CONFIG_SYS_SMC0_SETUP0_VAL \
225 (AT91_SMC_NWESETUP_(10) | AT91_SMC_NCS_WRSETUP_(10) | \
226 AT91_SMC_NRDSETUP_(10) | AT91_SMC_NCS_RDSETUP_(10))
227#define CONFIG_SYS_SMC0_PULSE0_VAL \
228 (AT91_SMC_NWEPULSE_(11) | AT91_SMC_NCS_WRPULSE_(11) | \
229 AT91_SMC_NRDPULSE_(11) | AT91_SMC_NCS_RDPULSE_(11))
230#define CONFIG_SYS_SMC0_CYCLE0_VAL \
231 (AT91_SMC_NWECYCLE_(22) | AT91_SMC_NRDCYCLE_(22))
232#define CONFIG_SYS_SMC0_MODE0_VAL \
233 (AT91_SMC_READMODE | AT91_SMC_WRITEMODE | \
234 AT91_SMC_DBW_16 | \
235 AT91_SMC_TDFMODE | \
236 AT91_SMC_TDF_(6))
237
238/* user reset enable */
239#define CONFIG_SYS_RSTC_RMR_VAL \
240 (AT91_RSTC_KEY | \
241 AT91_RSTC_PROCRST | \
242 AT91_RSTC_RSTTYP_WAKEUP | \
243 AT91_RSTC_RSTTYP_WATCHDOG)
244
245/* Disable Watchdog */
246#define CONFIG_SYS_WDTC_WDMR_VAL \
247 (AT91_WDT_WDIDLEHLT | AT91_WDT_WDDBGHLT | \
248 AT91_WDT_WDV | \
249 AT91_WDT_WDDIS | \
250 AT91_WDT_WDD)
251#endif
252
253#else
254#define CONFIG_SYS_NO_FLASH 1
Stelian Pop8e429b32008-05-08 18:52:23 +0200255#endif
256
257/* NAND flash */
Jean-Christophe PLAGNIOL-VILLARD74c076d2009-03-22 10:22:34 +0100258#ifdef CONFIG_CMD_NAND
259#define CONFIG_NAND_ATMEL
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200260#define CONFIG_SYS_MAX_NAND_DEVICE 1
261#define CONFIG_SYS_NAND_BASE 0x40000000
262#define CONFIG_SYS_NAND_DBW_8 1
Jean-Christophe PLAGNIOL-VILLARD74c076d2009-03-22 10:22:34 +0100263/* our ALE is AD21 */
264#define CONFIG_SYS_NAND_MASK_ALE (1 << 21)
265/* our CLE is AD22 */
266#define CONFIG_SYS_NAND_MASK_CLE (1 << 22)
267#define CONFIG_SYS_NAND_ENABLE_PIN AT91_PIN_PD15
268#define CONFIG_SYS_NAND_READY_PIN AT91_PIN_PA22
Wolfgang Denk2eb99ca2009-07-18 21:52:24 +0200269
270#define CONFIG_SYS_64BIT_VSPRINTF /* needed for nand_util.c */
Jean-Christophe PLAGNIOL-VILLARD74c076d2009-03-22 10:22:34 +0100271#endif
Stelian Pop8e429b32008-05-08 18:52:23 +0200272
273/* Ethernet */
274#define CONFIG_MACB 1
275#define CONFIG_RMII 1
276#define CONFIG_NET_MULTI 1
277#define CONFIG_NET_RETRY_COUNT 20
278#define CONFIG_RESET_PHY_R 1
279
280/* USB */
Jean-Christophe PLAGNIOL-VILLARD2b7178a2009-03-27 23:26:44 +0100281#define CONFIG_USB_ATMEL
Stelian Pop8e429b32008-05-08 18:52:23 +0200282#define CONFIG_USB_OHCI_NEW 1
Stelian Pop8e429b32008-05-08 18:52:23 +0200283#define CONFIG_DOS_PARTITION 1
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200284#define CONFIG_SYS_USB_OHCI_CPU_INIT 1
285#define CONFIG_SYS_USB_OHCI_REGS_BASE 0x00a00000 /* AT91SAM9263_UHP_BASE */
286#define CONFIG_SYS_USB_OHCI_SLOT_NAME "at91sam9263"
287#define CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS 2
Stelian Pop8e429b32008-05-08 18:52:23 +0200288#define CONFIG_USB_STORAGE 1
Stelian Pop3e0cda02008-11-09 00:14:46 +0100289#define CONFIG_CMD_FAT 1
Stelian Pop8e429b32008-05-08 18:52:23 +0200290
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200291#define CONFIG_SYS_LOAD_ADDR 0x22000000 /* load address */
Stelian Pop8e429b32008-05-08 18:52:23 +0200292
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200293#define CONFIG_SYS_MEMTEST_START PHYS_SDRAM
294#define CONFIG_SYS_MEMTEST_END 0x23e00000
Stelian Pop8e429b32008-05-08 18:52:23 +0200295
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200296#ifdef CONFIG_SYS_USE_DATAFLASH
Stelian Pop8e429b32008-05-08 18:52:23 +0200297
298/* bootstrap + u-boot + env + linux in dataflash on CS0 */
Jean-Christophe PLAGNIOL-VILLARD057c8492008-09-10 22:47:58 +0200299#define CONFIG_ENV_IS_IN_DATAFLASH 1
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200300#define CONFIG_SYS_MONITOR_BASE (CONFIG_SYS_DATAFLASH_LOGIC_ADDR_CS0 + 0x8400)
Jean-Christophe PLAGNIOL-VILLARD0e8d1582008-09-10 22:48:06 +0200301#define CONFIG_ENV_OFFSET 0x4200
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200302#define CONFIG_ENV_ADDR (CONFIG_SYS_DATAFLASH_LOGIC_ADDR_CS0 + CONFIG_ENV_OFFSET)
Jean-Christophe PLAGNIOL-VILLARD0e8d1582008-09-10 22:48:06 +0200303#define CONFIG_ENV_SIZE 0x4200
Stelian Pop8e429b32008-05-08 18:52:23 +0200304#define CONFIG_BOOTCOMMAND "cp.b 0xC0042000 0x22000000 0x210000; bootm"
305#define CONFIG_BOOTARGS "console=ttyS0,115200 " \
306 "root=/dev/mtdblock0 " \
Albin Tonnerre918319c2009-07-22 18:30:03 +0200307 "mtdparts=atmel_nand:-(root) "\
Stelian Pop8e429b32008-05-08 18:52:23 +0200308 "rw rootfstype=jffs2"
309
Jean-Christophe PLAGNIOL-VILLARD1b3b7c62009-06-13 12:48:36 +0200310#elif CONFIG_SYS_USE_NANDFLASH
Stelian Pop8e429b32008-05-08 18:52:23 +0200311
312/* bootstrap + u-boot + env + linux in nandflash */
Jean-Christophe PLAGNIOL-VILLARD51bfee12008-09-10 22:47:58 +0200313#define CONFIG_ENV_IS_IN_NAND 1
Jean-Christophe PLAGNIOL-VILLARD0e8d1582008-09-10 22:48:06 +0200314#define CONFIG_ENV_OFFSET 0x60000
315#define CONFIG_ENV_OFFSET_REDUND 0x80000
316#define CONFIG_ENV_SIZE 0x20000 /* 1 sector = 128 kB */
Stelian Pop8e429b32008-05-08 18:52:23 +0200317#define CONFIG_BOOTCOMMAND "nand read 0x22000000 0xA0000 0x200000; bootm"
318#define CONFIG_BOOTARGS "console=ttyS0,115200 " \
319 "root=/dev/mtdblock5 " \
Albin Tonnerre918319c2009-07-22 18:30:03 +0200320 "mtdparts=atmel_nand:128k(bootstrap)ro,256k(uboot)ro,128k(env1)ro,128k(env2)ro,2M(linux),-(root) " \
Stelian Pop8e429b32008-05-08 18:52:23 +0200321 "rw rootfstype=jffs2"
322
323#endif
324
325#define CONFIG_BAUDRATE 115200
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200326#define CONFIG_SYS_BAUDRATE_TABLE {115200 , 19200, 38400, 57600, 9600 }
Stelian Pop8e429b32008-05-08 18:52:23 +0200327
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200328#define CONFIG_SYS_PROMPT "U-Boot> "
329#define CONFIG_SYS_CBSIZE 256
330#define CONFIG_SYS_MAXARGS 16
331#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16)
332#define CONFIG_SYS_LONGHELP 1
Stelian Pop8e429b32008-05-08 18:52:23 +0200333#define CONFIG_CMDLINE_EDITING 1
Jean-Christophe PLAGNIOL-VILLARD03bab002009-03-30 16:51:40 +0200334#define CONFIG_AUTO_COMPLETE
335#define CONFIG_SYS_HUSH_PARSER
336#define CONFIG_SYS_PROMPT_HUSH_PS2 "> "
Stelian Pop8e429b32008-05-08 18:52:23 +0200337
Stelian Pop8e429b32008-05-08 18:52:23 +0200338/*
339 * Size of malloc() pool
340 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200341#define CONFIG_SYS_MALLOC_LEN ROUND(3 * CONFIG_ENV_SIZE + 128*1024, 0x1000)
342#define CONFIG_SYS_GBL_DATA_SIZE 128 /* 128 bytes for initial data */
Stelian Pop8e429b32008-05-08 18:52:23 +0200343
344#define CONFIG_STACKSIZE (32*1024) /* regular stack */
345
346#ifdef CONFIG_USE_IRQ
347#error CONFIG_USE_IRQ not supported
348#endif
349
350#endif