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wdenk5c952cf2004-10-10 21:27:30 +00001/*
2 * (C) Copyright 2004, Psyent Corporation <www.psyent.com>
3 * Scott McNutt <smcnutt@psyent.com>
4 *
Wolfgang Denk1a459662013-07-08 09:37:19 +02005 * SPDX-License-Identifier: GPL-2.0+
wdenk5c952cf2004-10-10 21:27:30 +00006 */
7
8/*************************************************************************
9 * Altera Nios2 Standard Peripherals
10 ************************************************************************/
11
12#ifndef __NIOS2IO_H__
13#define __NIOS2IO_H__
14
15/*------------------------------------------------------------------------
16 * UART (http://www.altera.com/literature/ds/ds_nios_uart.pdf)
17 *----------------------------------------------------------------------*/
18typedef volatile struct nios_uart_t {
19 unsigned rxdata; /* Rx data reg */
20 unsigned txdata; /* Tx data reg */
21 unsigned status; /* Status reg */
22 unsigned control; /* Control reg */
23 unsigned divisor; /* Baud rate divisor reg */
24 unsigned endofpacket; /* End-of-packet reg */
25}nios_uart_t;
26
27/* status register */
28#define NIOS_UART_PE (1 << 0) /* parity error */
29#define NIOS_UART_FE (1 << 1) /* frame error */
30#define NIOS_UART_BRK (1 << 2) /* break detect */
31#define NIOS_UART_ROE (1 << 3) /* rx overrun */
32#define NIOS_UART_TOE (1 << 4) /* tx overrun */
33#define NIOS_UART_TMT (1 << 5) /* tx empty */
34#define NIOS_UART_TRDY (1 << 6) /* tx ready */
35#define NIOS_UART_RRDY (1 << 7) /* rx ready */
36#define NIOS_UART_E (1 << 8) /* exception */
37#define NIOS_UART_DCTS (1 << 10) /* cts change */
38#define NIOS_UART_CTS (1 << 11) /* cts */
39#define NIOS_UART_EOP (1 << 12) /* eop detected */
40
41/* control register */
42#define NIOS_UART_IPE (1 << 0) /* parity error int ena*/
43#define NIOS_UART_IFE (1 << 1) /* frame error int ena */
44#define NIOS_UART_IBRK (1 << 2) /* break detect int ena */
45#define NIOS_UART_IROE (1 << 3) /* rx overrun int ena */
46#define NIOS_UART_ITOE (1 << 4) /* tx overrun int ena */
47#define NIOS_UART_ITMT (1 << 5) /* tx empty int ena */
48#define NIOS_UART_ITRDY (1 << 6) /* tx ready int ena */
49#define NIOS_UART_IRRDY (1 << 7) /* rx ready int ena */
50#define NIOS_UART_IE (1 << 8) /* exception int ena */
51#define NIOS_UART_TBRK (1 << 9) /* transmit break */
52#define NIOS_UART_IDCTS (1 << 10) /* cts change int ena */
53#define NIOS_UART_RTS (1 << 11) /* rts */
54#define NIOS_UART_IEOP (1 << 12) /* eop detected int ena */
55
56
57/*------------------------------------------------------------------------
58 * TIMER (http://www.altera.com/literature/ds/ds_nios_timer.pdf)
59 *----------------------------------------------------------------------*/
60typedef volatile struct nios_timer_t {
61 unsigned status; /* Timer status reg */
62 unsigned control; /* Timer control reg */
63 unsigned periodl; /* Timeout period low */
64 unsigned periodh; /* Timeout period high */
65 unsigned snapl; /* Snapshot low */
66 unsigned snaph; /* Snapshot high */
67}nios_timer_t;
68
69/* status register */
70#define NIOS_TIMER_TO (1 << 0) /* Timeout */
71#define NIOS_TIMER_RUN (1 << 1) /* Timer running */
72
73/* control register */
74#define NIOS_TIMER_ITO (1 << 0) /* Timeout int ena */
75#define NIOS_TIMER_CONT (1 << 1) /* Continuous mode */
76#define NIOS_TIMER_START (1 << 2) /* Start timer */
77#define NIOS_TIMER_STOP (1 << 3) /* Stop timer */
78
79
80/*------------------------------------------------------------------------
81 * PIO (http://www.altera.com/literature/ds/ds_nios_pio.pdf)
82 *----------------------------------------------------------------------*/
83typedef volatile struct nios_pio_t {
84 unsigned int data; /* Data value at each PIO in/out */
85 unsigned int direction; /* Data direct. for each PIO bit */
86 unsigned int interruptmask; /* Per-bit IRQ enable/disable */
87 unsigned int edgecapture; /* Per-bit sync. edge detect & hold */
88}nios_pio_t;
89
90/* direction register */
91#define NIOS_PIO_OUT (1) /* PIO bit is output */
92#define NIOS_PIO_IN (0) /* PIO bit is input */
93
94
95/*------------------------------------------------------------------------
96 * SPI (http://www.altera.com/literature/ds/ds_nios_spi.pdf)
97 *----------------------------------------------------------------------*/
98typedef volatile struct nios_spi_t {
99 unsigned rxdata; /* Rx data reg */
100 unsigned txdata; /* Tx data reg */
101 unsigned status; /* Status reg */
102 unsigned control; /* Control reg */
103 unsigned reserved; /* (master only) */
104 unsigned slaveselect; /* SPI slave select mask (master only) */
105}nios_spi_t;
106
107/* status register */
108#define NIOS_SPI_ROE (1 << 3) /* rx overrun */
109#define NIOS_SPI_TOE (1 << 4) /* tx overrun */
110#define NIOS_SPI_TMT (1 << 5) /* tx empty */
111#define NIOS_SPI_TRDY (1 << 6) /* tx ready */
112#define NIOS_SPI_RRDY (1 << 7) /* rx ready */
113#define NIOS_SPI_E (1 << 8) /* exception */
114
115/* control register */
116#define NIOS_SPI_IROE (1 << 3) /* rx overrun int ena */
117#define NIOS_SPI_ITOE (1 << 4) /* tx overrun int ena */
118#define NIOS_SPI_ITRDY (1 << 6) /* tx ready int ena */
119#define NIOS_SPI_IRRDY (1 << 7) /* rx ready int ena */
120#define NIOS_SPI_IE (1 << 8) /* exception int ena */
121#define NIOS_SPI_SSO (1 << 10) /* override SS_n output */
122
123/*------------------------------------------------------------------------
wdenk5c952cf2004-10-10 21:27:30 +0000124 * JTAG UART
125 *----------------------------------------------------------------------*/
126typedef volatile struct nios_jtag_t {
127 unsigned data; /* Data register */
128 unsigned control; /* Control register */
129}nios_jtag_t;
130
131/* data register */
132#define NIOS_JTAG_RVALID (1<<15) /* Read valid */
133#define NIOS_JTAG_DATA(d) ((d)&0x0ff) /* Read data */
134#define NIOS_JTAG_RAVAIL(d) ((d)>>16) /* Read space avail */
135
136/* control register */
137#define NIOS_JTAG_RE (1 << 0) /* read intr enable */
138#define NIOS_JTAG_WE (1 << 1) /* write intr enable */
139#define NIOS_JTAG_RI (1 << 8) /* read intr pending */
140#define NIOS_JTAG_WI (1 << 9) /* write intr pending*/
141#define NIOS_JTAG_AC (1 << 10) /* activity indicator */
142#define NIOS_JTAG_RRDY (1 << 12) /* read available */
Wolfgang Denk53677ef2008-05-20 16:00:29 +0200143#define NIOS_JTAG_WSPACE(d) ((d)>>16) /* Write space avail */
wdenk5c952cf2004-10-10 21:27:30 +0000144
145/*------------------------------------------------------------------------
146 * SYSTEM ID
147 *----------------------------------------------------------------------*/
148typedef volatile struct nios_sysid_t {
Wolfgang Denk53677ef2008-05-20 16:00:29 +0200149 unsigned id; /* The system build id*/
150 unsigned timestamp; /* Timestamp */
wdenk5c952cf2004-10-10 21:27:30 +0000151}nios_sysid_t;
152
153#endif /* __NIOS2IO_H__ */