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wdenk9e3f8cd2002-09-15 14:08:13 +00001/*
wdenk414eec32005-04-02 22:37:54 +00002 * (C) Copyright 2001-2005
wdenk9e3f8cd2002-09-15 14:08:13 +00003 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
4 *
5 * See file CREDITS for list of people who contributed to this
6 * project.
7 *
8 * This program is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU General Public License as
10 * published by the Free Software Foundation; either version 2 of
11 * the License, or (at your option) any later version.
12 *
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
17 *
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
21 * MA 02111-1307 USA
22 */
23
24/*
25 * board/config.h - configuration options, board specific
26 */
27
28#ifndef __CONFIG_H
29#define __CONFIG_H
30
31#include <mpc8xx_irq.h>
32
33/*
34 * High Level Configuration Options
35 * (easy to change)
36 */
37#define CONFIG_MPC860 1
38#define CONFIG_MPC860T 1
39#define CONFIG_ICU862 1
40#define CONFIG_MPC862 1
41
42#define CONFIG_8xx_CONS_SMC1 1 /* Console is on SMC1 */
43#undef CONFIG_8xx_CONS_SMC2
44#undef CONFIG_8xx_CONS_NONE
45#define CONFIG_BAUDRATE 9600
46#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
47
48#ifdef CONFIG_100MHz
49#define MPC8XX_FACT 24 /* Multiply by 24 */
50#define MPC8XX_XIN 4165000 /* 4.165 MHz in */
51#define CONFIG_8xx_GCLK_FREQ (MPC8XX_FACT * MPC8XX_XIN)
52 /* define if cant' use get_gclk_freq */
53#else
54#if 1 /* for 50MHz version of processor */
55#define MPC8XX_FACT 12 /* Multiply by 12 */
56#define MPC8XX_XIN 4000000 /* 4 MHz in */
57#define CONFIG_8xx_GCLK_FREQ 48000000 /* define if cant use get_gclk_freq */
58#else /* for 80MHz version of processor */
59#define MPC8XX_FACT 20 /* Multiply by 20 */
60#define MPC8XX_XIN 4000000 /* 4 MHz in */
61#define CONFIG_8xx_GCLK_FREQ 80000000 /* define if cant use get_gclk_freq */
62#endif
63#endif
64
wdenk9e3f8cd2002-09-15 14:08:13 +000065#if 0
66#define CONFIG_BOOTDELAY -1 /* autoboot disabled */
67#else
68#define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */
69#endif
70
71#define CONFIG_PREBOOT "echo;echo Type \"run flash_nfs\" to mount root filesystem over NFS;echo"
72
73#undef CONFIG_BOOTARGS
74#define CONFIG_BOOTCOMMAND \
75 "bootp;" \
76 "setenv bootargs root=/dev/nfs rw nfsroot=$(serverip):$(rootpath) " \
77 "ip=$(ipaddr):$(serverip):$(gatewayip):$(netmask):$(hostname)::off;" \
78 "bootm"
79
80#undef CONFIG_WATCHDOG /* watchdog disabled */
81
82#define CONFIG_STATUS_LED 1 /* Status LED enabled */
83
84#define CONFIG_BOOTP_MASK (CONFIG_BOOTP_DEFAULT | CONFIG_BOOTP_BOOTFILESIZE)
85
86#undef CONFIG_SCC1_ENET /* disable SCC1 ethernet */
87#define CONFIG_FEC_ENET 1 /* use FEC ethernet */
88#if 1
89#define CFG_DISCOVER_PHY 1
90#else
91#undef CFG_DISCOVER_PHY
92#endif
93
94#define CONFIG_MAC_PARTITION
95#define CONFIG_DOS_PARTITION
96
97/* enable I2C and select the hardware/software driver */
98#undef CONFIG_HARD_I2C /* I2C with hardware support */
99#define CONFIG_SOFT_I2C 1 /* I2C bit-banged */
100# define CFG_I2C_SPEED 50000
101# define CFG_I2C_SLAVE 0xFE
102# define CFG_I2C_EEPROM_ADDR 0x50
103# define CFG_I2C_EEPROM_ADDR_LEN 1 /* Bytes of address */
104/*
105 * Software (bit-bang) I2C driver configuration
106 */
107#define PB_SCL 0x00000020 /* PB 26 */
108#define PB_SDA 0x00000010 /* PB 27 */
109
110#define I2C_INIT (immr->im_cpm.cp_pbdir |= PB_SCL)
111#define I2C_ACTIVE (immr->im_cpm.cp_pbdir |= PB_SDA)
112#define I2C_TRISTATE (immr->im_cpm.cp_pbdir &= ~PB_SDA)
113#define I2C_READ ((immr->im_cpm.cp_pbdat & PB_SDA) != 0)
114#define I2C_SDA(bit) if(bit) immr->im_cpm.cp_pbdat |= PB_SDA; \
115 else immr->im_cpm.cp_pbdat &= ~PB_SDA
116#define I2C_SCL(bit) if(bit) immr->im_cpm.cp_pbdat |= PB_SCL; \
117 else immr->im_cpm.cp_pbdat &= ~PB_SCL
118#define I2C_DELAY udelay(5) /* 1/4 I2C clock duration */
119
120#define CFG_EEPROM_X40430 /* Use a Xicor X40430 EEPROM */
121#define CFG_EEPROM_PAGE_WRITE_BITS 4 /* 16 bytes page write mode */
122
123#define CONFIG_RTC_MPC8xx /* use internal RTC of MPC8xx */
124
125#define CONFIG_COMMANDS ( CONFIG_CMD_DFL | \
126 CFG_CMD_ASKENV | \
wdenk414eec32005-04-02 22:37:54 +0000127 CFG_CMD_DATE | \
wdenk9e3f8cd2002-09-15 14:08:13 +0000128 CFG_CMD_DHCP | \
129 CFG_CMD_EEPROM | \
130 CFG_CMD_I2C | \
131 CFG_CMD_IDE | \
wdenk414eec32005-04-02 22:37:54 +0000132 CFG_CMD_NFS | \
133 CFG_CMD_SNTP )
wdenk9e3f8cd2002-09-15 14:08:13 +0000134
135/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
136#include <cmd_confdefs.h>
137
138/*
139 * Miscellaneous configurable options
140 */
141#define CFG_LONGHELP /* undef to save memory */
142#define CFG_PROMPT "=> " /* Monitor Command Prompt */
143#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
144#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */
145#else
146#define CFG_CBSIZE 256 /* Console I/O Buffer Size */
147#endif
148#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
149#define CFG_MAXARGS 16 /* max number of command args */
150#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */
151
152#define CFG_MEMTEST_START 0x0100000 /* memtest works on */
153#define CFG_MEMTEST_END 0x0400000 /* 1 ... 4 MB in DRAM */
154
155#define CFG_LOAD_ADDR 0x00100000
156
157#define CFG_HZ 1000 /* decrementer freq: 1 ms ticks */
158
159#define CFG_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 }
160
161/*
162 * Low Level Configuration Settings
163 * (address mappings, register initial values, etc.)
164 * You should know what you are doing if you make changes here.
165 */
166/*-----------------------------------------------------------------------
167 * Internal Memory Mapped Register
168 */
169#define CFG_IMMR 0xF0000000
170#define CFG_IMMR_SIZE ((uint)(64 * 1024))
171
172/*-----------------------------------------------------------------------
173 * Definitions for initial stack pointer and data area (in DPRAM)
174 */
175#define CFG_INIT_RAM_ADDR CFG_IMMR
176#define CFG_INIT_RAM_END 0x2F00 /* End of used area in DPRAM */
177#define CFG_GBL_DATA_SIZE 64 /* size in bytes reserved for initial data */
178#define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
179#define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET
180
181/*-----------------------------------------------------------------------
182 * Start addresses for the final memory configuration
183 * (Set up by the startup code)
184 * Please note that CFG_SDRAM_BASE _must_ start at 0
185 */
186#define CFG_SDRAM_BASE 0x00000000
187#define CFG_FLASH_BASE 0x40000000
188#define CFG_FLASH_SIZE ((uint)(16 * 1024 * 1024)) /* max 16Mbyte */
189
190#define CFG_RESET_ADDRESS 0xFFF00100
191
192#if 0
193#if defined(DEBUG)
194#define CFG_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */
195#else
196#define CFG_MONITOR_LEN (192 << 10) /* Reserve 192 kB for Monitor */
197#endif
198#else
wdenkd94f92c2003-08-28 09:41:22 +0000199#define CFG_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */
wdenk9e3f8cd2002-09-15 14:08:13 +0000200#endif
201#define CFG_MONITOR_BASE TEXT_BASE
202#define CFG_MALLOC_LEN (256 << 10) /* Reserve 256 kB for malloc() */
203
204/*
205 * For booting Linux, the board info and command line data
206 * have to be in the first 8 MB of memory, since this is
207 * the maximum mapped by the Linux kernel during initialization.
208 */
209#define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
210/*-----------------------------------------------------------------------
211 * FLASH organization
212 */
213#define CFG_MAX_FLASH_BANKS 1 /* max number of memory banks */
214#define CFG_MAX_FLASH_SECT 64 /* max number of sectors on one chip */
215
216#define CFG_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */
217#define CFG_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */
218
219
220#define CFG_ENV_IS_IN_FLASH 1
221#define CFG_ENV_OFFSET 0x00F40000
222
223#define CFG_ENV_SECT_SIZE 0x40000 /* Total Size of Environment sector */
224#define CFG_ENV_SIZE 0x4000 /* Used Size of Environment Sector */
225
226/*-----------------------------------------------------------------------
227 * Cache Configuration
228 */
229#define CFG_CACHELINE_SIZE 16 /* For all MPC8xx CPUs */
230#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
231#define CFG_CACHELINE_SHIFT 4 /* log base 2 of the above value */
232#endif
233
234/*-----------------------------------------------------------------------
235 * SYPCR - System Protection Control 11-9
236 * SYPCR can only be written once after reset!
237 *-----------------------------------------------------------------------
238 * Software & Bus Monitor Timer max, Bus Monitor enable, SW Watchdog freeze
239 */
240#if defined(CONFIG_WATCHDOG)
241#define CFG_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | \
242 SYPCR_SWE | SYPCR_SWRI| SYPCR_SWP)
243#else
244#define CFG_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | SYPCR_SWP)
245#endif
246
247/*-----------------------------------------------------------------------
248 * SIUMCR - SIU Module Configuration 11-6
249 *-----------------------------------------------------------------------
250 * PCMCIA config., multi-function pin tri-state
251 */
252#define CFG_SIUMCR (SIUMCR_DBGC00 | SIUMCR_DBPC00 | SIUMCR_MLRC01)
253
254/*-----------------------------------------------------------------------
255 * TBSCR - Time Base Status and Control 11-26
256 *-----------------------------------------------------------------------
257 * Clear Reference Interrupt Status, Timebase freezing enabled
258 */
259#define CFG_TBSCR (TBSCR_REFA | TBSCR_REFB | TBSCR_TBE)
260
261/*-----------------------------------------------------------------------
262 * PISCR - Periodic Interrupt Status and Control 11-31
263 *-----------------------------------------------------------------------
264 * Clear Periodic Interrupt Status, Interrupt Timer freezing enabled
265 */
266#define CFG_PISCR (PISCR_PS | PISCR_PITF)
267
268/*-----------------------------------------------------------------------
269 * PLPRCR - PLL, Low-Power, and Reset Control Register 15-30
270 *-----------------------------------------------------------------------
271 * set the PLL, the low-power modes and the reset control (15-29)
272 */
273#define CFG_PLPRCR (((MPC8XX_FACT-1) << PLPRCR_MF_SHIFT) | \
274 PLPRCR_SPLSS | PLPRCR_TEXPS | PLPRCR_TMIST)
275
276/*-----------------------------------------------------------------------
277 * SCCR - System Clock and reset Control Register 15-27
278 *-----------------------------------------------------------------------
279 * Set clock output, timebase and RTC source and divider,
280 * power management and some other internal clocks
281 */
282#ifdef CONFIG_100MHz /* for 100 MHz, external bus is half CPU clock */
283#define SCCR_MASK 0
284#define CFG_SCCR (SCCR_TBS | SCCR_COM00 | SCCR_DFSYNC00 | \
285 SCCR_DFBRG00 | SCCR_DFNL000 | SCCR_DFNH000 | \
286 SCCR_DFLCD000 |SCCR_DFALCD00 | SCCR_EBDF01)
287#else /* up to 50 MHz we use a 1:1 clock */
288#define SCCR_MASK SCCR_EBDF11
289#define CFG_SCCR (SCCR_TBS | SCCR_COM00 | SCCR_DFSYNC00 | \
290 SCCR_DFBRG00 | SCCR_DFNL000 | SCCR_DFNH000 | \
291 SCCR_DFLCD000 |SCCR_DFALCD00 )
292#endif /* CONFIG_100MHz */
293
294/*-----------------------------------------------------------------------
295 * RCCR - RISC Controller Configuration Register 19-4
296 *-----------------------------------------------------------------------
297 */
298/* +0x09C4 => DRQP = 10 (IDMA requests have lowest priority) */
299#define CFG_RCCR 0x0020
300
301/*-----------------------------------------------------------------------
302 * PCMCIA stuff
303 *-----------------------------------------------------------------------
304 */
305#define CFG_PCMCIA_MEM_ADDR (0xE0000000)
306#define CFG_PCMCIA_MEM_SIZE ( 64 << 20 )
307#define CFG_PCMCIA_DMA_ADDR (0xE4000000)
308#define CFG_PCMCIA_DMA_SIZE ( 64 << 20 )
309#define CFG_PCMCIA_ATTRB_ADDR (0xE8000000)
310#define CFG_PCMCIA_ATTRB_SIZE ( 64 << 20 )
311#define CFG_PCMCIA_IO_ADDR (0xEC000000)
312#define CFG_PCMCIA_IO_SIZE ( 64 << 20 )
313
314/*-----------------------------------------------------------------------
315 * PCMCIA Power Switch
316 *
317 * The ICU862 uses a TPS2205 PC-Card Power-Interface Switch to
318 * control the voltages on the PCMCIA slot which is connected to Port B
319 *-----------------------------------------------------------------------
320 */
321 /* Output pins */
322#define TPS2205_VCC5 0x00008000 /* PB.16: 5V Voltage Control */
323#define TPS2205_VCC3 0x00004000 /* PB.17: 3V Voltage Control */
324#define TPS2205_VPP_PGM 0x00002000 /* PB.18: PGM Voltage Control */
325#define TPS2205_VPP_VCC 0x00001000 /* PB.19: VPP Voltage Control */
326#define TPS2205_SHDN 0x00000200 /* PB.22: Shutdown */
327#define TPS2205_OUTPUTS ( TPS2205_VCC5 | TPS2205_VCC3 | \
328 TPS2205_VPP_PGM | TPS2205_VPP_VCC | \
329 TPS2205_SHDN)
330
331 /* Input pins */
332#define TPS2205_OC 0x00000100 /* PB.23: Over-Current */
333#define TPS2205_INPUTS ( TPS2205_OC )
334
335/*-----------------------------------------------------------------------
336 * IDE/ATA stuff (Supports IDE harddisk on PCMCIA Adapter)
337 *-----------------------------------------------------------------------
338 */
339
340#define CONFIG_IDE_8xx_PCCARD 1 /* Use IDE with PC Card Adapter */
341
342#undef CONFIG_IDE_8xx_DIRECT /* Direct IDE not supported */
343#undef CONFIG_IDE_LED /* LED for ide not supported */
344#undef CONFIG_IDE_RESET /* reset for ide not supported */
345
346#define CFG_IDE_MAXBUS 1 /* max. 1 IDE bus */
347#define CFG_IDE_MAXDEVICE 1 /* max. 1 drive per IDE bus */
348
349#define CFG_ATA_IDE0_OFFSET 0x0000
350
351#define CFG_ATA_BASE_ADDR CFG_PCMCIA_MEM_ADDR
352
353/* Offset for data I/O */
354#define CFG_ATA_DATA_OFFSET (CFG_PCMCIA_MEM_SIZE + 0x320)
355
356/* Offset for normal register accesses */
357#define CFG_ATA_REG_OFFSET (2 * CFG_PCMCIA_MEM_SIZE + 0x320)
358
359/* Offset for alternate registers */
360#define CFG_ATA_ALT_OFFSET 0x0100
361
362
363 /*-----------------------------------------------------------------------
364 *
365 *-----------------------------------------------------------------------
366 *
367 */
368#define CFG_DER 0
369
370/* Because of the way the 860 starts up and assigns CS0 the
371* entire address space, we have to set the memory controller
372* differently. Normally, you write the option register
373* first, and then enable the chip select by writing the
374* base register. For CS0, you must write the base register
375* first, followed by the option register.
376*/
377
378/*
379 * Init Memory Controller:
380 *
381 * BR0 and OR0 (FLASH)
382 */
383
384#define FLASH_BASE0_PRELIM 0x40000000 /* FLASH bank #0 */
385#define FLASH_BASE1_PRELIM 0x0 /* FLASH bank #1 */
386
387#define CFG_REMAP_OR_AM 0x80000000 /* OR addr mask */
388#define CFG_PRELIM_OR_AM 0xE0000000 /* OR addr mask */
389
390/* FLASH timing: ACS = 10, TRLX = 1, CSNT = 1, SCY = 3, EHTR = 0 */
391#define CFG_OR_TIMING_FLASH (OR_CSNT_SAM | OR_ACS_DIV4 | OR_BI | OR_SCY_3_CLK | OR_TRLX)
392
393#define CFG_OR0_REMAP (CFG_REMAP_OR_AM | CFG_OR_TIMING_FLASH)
394
395#define CFG_OR0_PRELIM 0xFF000954 /* Real values for the board */
396#define CFG_BR0_PRELIM 0x40000001 /* Real values for the board */
397
398/*
399 * BR1 and OR1 (SDRAM)
400 */
401#define SDRAM_BASE1_PRELIM 0x00000000 /* SDRAM bank */
402#define SDRAM_MAX_SIZE 0x04000000 /* max 64 MB per bank */
403
404#define CFG_OR_TIMING_SDRAM 0x00000800 /* BIH is not set */
405
406#define CFG_OR1_PRELIM (CFG_PRELIM_OR_AM | CFG_OR_TIMING_SDRAM)
407#define CFG_BR1_PRELIM ((SDRAM_BASE1_PRELIM & BR_BA_MSK) | BR_MS_UPMA | BR_V)
408
409/*
410 * Memory Periodic Timer Prescaler
411 */
412
413/* periodic timer for refresh */
414#define CFG_MAMR_PTA 97 /* start with divider for 100 MHz */
415
416/* refresh rate 15.6 us (= 64 ms / 4K = 62.4 / quad bursts) for <= 128 MBit */
417#define CFG_MPTPR_2BK_4K MPTPR_PTP_DIV16 /* setting for 2 banks */
418#define CFG_MPTPR_1BK_4K MPTPR_PTP_DIV32 /* setting for 1 bank */
419
420/* refresh rate 7.8 us (= 64 ms / 8K = 31.2 / quad bursts) for 256 MBit */
421#define CFG_MPTPR_2BK_8K MPTPR_PTP_DIV8 /* setting for 2 banks */
422#define CFG_MPTPR_1BK_8K MPTPR_PTP_DIV16 /* setting for 1 bank */
423
424/*
425 * MAMR settings for SDRAM
426 */
427
428/* 8 column SDRAM */
429#define CFG_MAMR_8COL ((CFG_MAMR_PTA << MAMR_PTA_SHIFT) | MAMR_PTAE | \
430 MAMR_AMA_TYPE_0 | MAMR_DSA_1_CYCL | MAMR_G0CLA_A11 | \
431 MAMR_RLFA_1X | MAMR_WLFA_1X | MAMR_TLFA_4X)
432/* 9 column SDRAM */
433#define CFG_MAMR_9COL ((CFG_MAMR_PTA << MAMR_PTA_SHIFT) | MAMR_PTAE | \
434 MAMR_AMA_TYPE_1 | MAMR_DSA_1_CYCL | MAMR_G0CLA_A10 | \
435 MAMR_RLFA_1X | MAMR_WLFA_1X | MAMR_TLFA_4X)
436
437#define CFG_MAMR 0x13a01114
438/*
439 * Internal Definitions
440 *
441 * Boot Flags
442 */
443#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */
444#define BOOTFLAG_WARM 0x02 /* Software reboot */
445
446#ifdef CONFIG_MPC860T
447
448/* Interrupt level assignments.
449*/
450#define FEC_INTERRUPT SIU_LEVEL1 /* FEC interrupt */
451
452#endif /* CONFIG_MPC860T */
453
454
455#endif /* __CONFIG_H */