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wdenke2211742002-11-02 23:30:20 +00001/*
2 * (C) Copyright 2000
3 * Sysgo Real-Time Solutions, GmbH <www.elinos.com>
4 * Marius Groeger <mgroeger@sysgo.de>
5 *
6 * Configuation settings for the MBX8xx board.
7 *
8 * -----------------------------------------------------------------
9 * See file CREDITS for list of people who contributed to this
10 * project.
11 *
12 * This program is free software; you can redistribute it and/or
13 * modify it under the terms of the GNU General Public License as
14 * published by the Free Software Foundation; either version 2 of
15 * the License, or (at your option) any later version.
16 *
17 * This program is distributed in the hope that it will be useful,
18 * but WITHOUT ANY WARRANTY; without even the implied warranty of
19 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
20 * GNU General Public License for more details.
21 *
22 * You should have received a copy of the GNU General Public License
23 * along with this program; if not, write to the Free Software
24 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
25 * MA 02111-1307 USA
26 */
27/*
28 * Changed 2002-10-01
29 * Added PCMCIA defines mostly taken from other U-Boot boards that
30 * have PCMCIA already working. If you find any bugs, incorrect assumptions
31 * feel free to fix them yourself and submit a patch.
32 * Rod Boyce <rod_boyce@stratexnet.com.
33 */
34/*
35 * board/config.h - configuration options, board specific
36 */
37
38#ifndef __CONFIG_H
39#define __CONFIG_H
40
41/*
42 * High Level Configuration Options
43 * (easy to change)
44 */
45
46#define CONFIG_MPC860 1 /* This is a MPC860 CPU */
47#define CONFIG_MBX 1 /* ...on an MBX module */
48
49#define CONFIG_8xx_CONS_SMC1 1 /* Console is on SMC1 */
50#undef CONFIG_8xx_CONS_SMC2
51#undef CONFIG_8xx_CONS_NONE
52#define CONFIG_BAUDRATE 9600
53/* Define this to use the PCI bus */
54#undef CONFIG_USE_PCI
55
56#define CONFIG_CLOCKS_IN_MHZ 1 /* clocks passsed to Linux in MHz */
57#define CONFIG_8xx_GCLK_FREQ (50000000UL)
58#if 1
59#define CONFIG_BOOTDELAY -1 /* autoboot disabled */
60#else
61#define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */
62#endif
63#define CONFIG_BOOTCOMMAND "bootm 20000" /* autoboot command */
64
65#define CONFIG_BOOTARGS "root=/dev/nfs rw " \
66 "nfsroot=10.0.0.2:/opt/eldk/ppc_8xx " \
67 "nfsaddrs=10.0.0.99:10.0.0.2"
68
69#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
70#undef CFG_LOADS_BAUD_CHANGE /* don't allow baudrate change */
71
72#undef CONFIG_WATCHDOG /* watchdog disabled */
73
74#define CONFIG_COMMANDS ( CFG_CMD_NET | CONFIG_CMD_DFL | CFG_CMD_SDRAM | \
wdenk8bde7f72003-06-27 21:31:46 +000075 CFG_CMD_PCMCIA | CFG_CMD_IDE )
wdenke2211742002-11-02 23:30:20 +000076
77#define CONFIG_DOS_PARTITION
78
79/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
80#include <cmd_confdefs.h>
81
82/*
83 * Miscellaneous configurable options
84 */
85#define CFG_LONGHELP /* undef to save memory */
86#define CFG_PROMPT "=> " /* Monitor Command Prompt */
87#undef CFG_HUSH_PARSER /* Hush parse for U-Boot */
88#ifdef CFG_HUSH_PARSER
89#define CFG_PROMPT_HUSH_PS2 "> "
90#endif
91#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
92#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */
93#else
94#define CFG_CBSIZE 256 /* Console I/O Buffer Size */
95#endif
96#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
97#define CFG_MAXARGS 16 /* max number of command args */
98#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */
99
100#define CFG_MEMTEST_START 0x0400000 /* memtest works on */
101#define CFG_MEMTEST_END 0x0C00000 /* 4 ... 12 MB in DRAM */
102
103#define CFG_LOAD_ADDR 0x100000 /* default load address */
104
105#define CFG_HZ 1000 /* decrementer freq: 1 ms ticks */
106
107#define CFG_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 }
108
109/*
110 * Low Level Configuration Settings
111 * (address mappings, register initial values, etc.)
112 * You should know what you are doing if you make changes here.
113 */
114
115/*-----------------------------------------------------------------------
116 * Physical memory map as defined by the MBX PGM
117 */
118#define CFG_IMMR 0xFA200000 /* Internal Memory Mapped Register*/
119#define CFG_NVRAM_BASE 0xFA000000 /* NVRAM */
120#define CFG_NVRAM_OR 0xffe00000 /* w/o speed dependent flags!! */
121#define CFG_CSR_BASE 0xFA100000 /* Control/Status Registers */
122#define CFG_PCIMEM_BASE 0x80000000 /* PCI I/O and Memory Spaces */
123#define CFG_PCIMEM_OR 0xA0000108
124#define CFG_PCIBRIDGE_BASE 0xFA210000 /* PCI-Bus Bridge Registers */
125#define CFG_PCIBRIDGE_OR 0xFFFF0108
126
127/*-----------------------------------------------------------------------
128 * Definitions for initial stack pointer and data area (in DPRAM)
129 */
130#define CFG_INIT_RAM_ADDR CFG_IMMR
131#define CFG_INIT_RAM_END 0x2f00 /* End of used area in DPRAM */
132#define CFG_GBL_DATA_SIZE 64 /* size in bytes reserved for initial data */
133#define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
134#define CFG_INIT_VPD_SIZE 256 /* size in bytes reserved for vpd buffer */
135#define CFG_INIT_VPD_OFFSET (CFG_GBL_DATA_OFFSET - CFG_INIT_VPD_SIZE)
136#define CFG_INIT_SP_OFFSET (CFG_INIT_VPD_OFFSET-8)
137
138/*-----------------------------------------------------------------------
139 * Offset in DPMEM where we keep the VPD data
140 */
141#define CFG_DPRAMVPD (CFG_INIT_VPD_OFFSET - 0x2000)
142
143/*-----------------------------------------------------------------------
144 * Start addresses for the final memory configuration
145 * (Set up by the startup code)
146 * Please note that CFG_SDRAM_BASE _must_ start at 0
147 */
148#define CFG_SDRAM_BASE 0x00000000
149#define CFG_FLASH_BASE 0xfe000000
150#ifdef DEBUG
151#define CFG_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */
152#else
153#define CFG_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */
154#endif
155#undef CFG_MONITOR_BASE /* 0x200000 to run U-Boot from RAM */
156#define CFG_MONITOR_BASE CFG_FLASH_BASE
157#define CFG_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc() */
158
159/*
160 * For booting Linux, the board info and command line data
161 * have to be in the first 8 MB of memory, since this is
162 * the maximum mapped by the Linux kernel during initialization.
163 */
164#define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
165
166/*-----------------------------------------------------------------------
167 * FLASH organization
168 */
169#define CFG_MAX_FLASH_BANKS 1 /* max number of memory banks */
170#define CFG_MAX_FLASH_SECT 16 /* max number of sectors on one chip */
171
172#define CFG_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */
173#define CFG_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */
174
175/*-----------------------------------------------------------------------
176 * NVRAM Configuration
177 *
178 * Note: the MBX is special because there is already a firmware on this
179 * board: EPPC-Bug from Motorola. To avoid collisions in NVRAM Usage, we
180 * access the NVRAM at the offset 0x1000.
181 */
182#define CFG_ENV_IS_IN_NVRAM 1 /* turn on NVRAM env feature */
183#define CFG_ENV_ADDR (CFG_NVRAM_BASE + 0x1000)
184#define CFG_ENV_SIZE 0x1000
185
186/*-----------------------------------------------------------------------
187 * Cache Configuration
188 */
189#define CFG_CACHELINE_SIZE 16 /* For all MPC8xx CPUs */
190#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
191#define CFG_CACHELINE_SHIFT 4 /* log base 2 of the above value */
192#endif
193
194/*-----------------------------------------------------------------------
195 * SYPCR - System Protection Control 11-9
196 * SYPCR can only be written once after reset!
197 *-----------------------------------------------------------------------
198 * Software & Bus Monitor Timer max, Bus Monitor enable, SW Watchdog freeze
199 */
200#if defined(CONFIG_WATCHDOG)
201#define CFG_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | \
202 SYPCR_SWE | SYPCR_SWRI| SYPCR_SWP)
203#else
204#define CFG_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF)
205#endif
206
207/*-----------------------------------------------------------------------
208 * SIUMCR - SIU Module Configuration 11-6
209 *-----------------------------------------------------------------------
210 * PCMCIA config., multi-function pin tri-state
211 */
212/* #define CFG_SIUMCR (SIUMCR_DBGC11 | SIUMCR_DPC | SIUMCR_MLRC10 | SIUMCR_SEME) */
213#define CFG_SIUMCR (SIUMCR_DBGC11 | SIUMCR_DPC | SIUMCR_MLRC11 | SIUMCR_SEME | SIUMCR_BSC )
214
215/*-----------------------------------------------------------------------
216 * TBSCR - Time Base Status and Control 11-26
217 *-----------------------------------------------------------------------
218 * Clear Reference Interrupt Status, Timebase freezing enabled
219 */
220#define CFG_TBSCR (TBSCR_REFA | TBSCR_REFB | TBSCR_TBF)
221
222/*-----------------------------------------------------------------------
223 * PISCR - Periodic Interrupt Status and Control 11-31
224 *-----------------------------------------------------------------------
225 * Clear Periodic Interrupt Status, Interrupt Timer freezing enabled
226 */
227#define CFG_PISCR (PISCR_PS | PISCR_PITF | PISCR_PTE)
228
229/*-----------------------------------------------------------------------
230 * PLPRCR - PLL, Low-Power, and Reset Control Register 15-30
231 *-----------------------------------------------------------------------
232 * Reset PLL lock status sticky bit, timer expired status bit and timer
233 * interrupt status bit - leave PLL multiplication factor unchanged !
234 */
235#define CFG_PLPRCR (PLPRCR_SPLSS | PLPRCR_TEXPS | PLPRCR_TMIST)
236
237/*-----------------------------------------------------------------------
238 * SCCR - System Clock and reset Control Register 15-27
239 *-----------------------------------------------------------------------
240 * Set clock output, timebase and RTC source and divider,
241 * power management and some other internal clocks
242 */
243#define SCCR_MASK (SCCR_RTDIV | SCCR_RTSEL)
244#define CFG_SCCR SCCR_TBS
245
246/*-----------------------------------------------------------------------
247 * PCMCIA stuff
248 *-----------------------------------------------------------------------
249 *
250 */
251#define CFG_PCMCIA_MEM_ADDR (0xE0000000)
252#define CFG_PCMCIA_MEM_SIZE ( 64 << 20 )
253#define CFG_PCMCIA_DMA_ADDR (0xE4000000)
254#define CFG_PCMCIA_DMA_SIZE ( 64 << 20 )
255#define CFG_PCMCIA_ATTRB_ADDR (0xE8000000)
256#define CFG_PCMCIA_ATTRB_SIZE ( 64 << 20 )
257#define CFG_PCMCIA_IO_ADDR (0xEC000000)
258#define CFG_PCMCIA_IO_SIZE ( 64 << 20 )
259
260#define CFG_PCMCIA_INTERRUPT SIU_LEVEL6
261
262#define CONFIG_PCMCIA_SLOT_A 1
263
264
265/*-----------------------------------------------------------------------
266 * IDE/ATA stuff (Supports IDE harddisk on PCMCIA Adapter)
267 *-----------------------------------------------------------------------
268 */
269
270#define CONFIG_IDE_8xx_PCCARD 1 /* Use IDE with PC Card Adapter */
271
272#undef CONFIG_IDE_8xx_DIRECT /* Direct IDE not supported */
273#undef CONFIG_IDE_LED /* LED for ide not supported */
274#undef CONFIG_IDE_RESET /* reset for ide not supported */
275
276#define CFG_IDE_MAXBUS 1 /* max. 1 IDE bus */
277#define CFG_IDE_MAXDEVICE 1 /* max. 1 drive per IDE bus */
278
279#define CFG_ATA_IDE0_OFFSET 0x0000
280
281#define CFG_ATA_BASE_ADDR CFG_PCMCIA_MEM_ADDR
282
283/* Offset for data I/O */
284#define CFG_ATA_DATA_OFFSET (CFG_PCMCIA_MEM_SIZE + 0x320)
285
286/* Offset for normal register accesses */
287#define CFG_ATA_REG_OFFSET (2 * CFG_PCMCIA_MEM_SIZE + 0x320)
288
289/* Offset for alternate registers */
290#define CFG_ATA_ALT_OFFSET 0x0100
291
292/*-----------------------------------------------------------------------
293 * Debug Entry Mode
294 *-----------------------------------------------------------------------
295 *
296 */
297#define CFG_DER 0
298
299/*
300 * Internal Definitions
301 *
302 * Boot Flags
303 */
304#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */
305#define BOOTFLAG_WARM 0x02 /* Software reboot */
306
307#endif /* __CONFIG_H */