blob: ae4dcc2ccca9d73064c4b42957f5a00f132ff761 [file] [log] [blame]
wdenk0f8c9762002-08-19 11:57:05 +00001/*
2 * (C) Copyright 2000
3 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
4 *
5 * See file CREDITS for list of people who contributed to this
6 * project.
7 *
8 * This program is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU General Public License as
10 * published by the Free Software Foundation; either version 2 of
11 * the License, or (at your option) any later version.
12 *
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
17 *
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
21 * MA 02111-1307 USA
22 */
23
24/*
25 * board/config.h - configuration options, board specific
26 */
27
28#ifndef __CONFIG_H
29#define __CONFIG_H
30
31/*
32 * High Level Configuration Options
33 * (easy to change)
34 */
35
36#define CONFIG_MPC823 1 /* This is a MPC823 CPU */
37#define CONFIG_SPD823TS 1 /* ...on a SPD823TS board */
38
39#define CONFIG_8xx_CONS_SMC1 1 /* Console is on SMC1 */
40#undef CONFIG_8xx_CONS_SMC2
41#undef CONFIG_8xx_CONS_NONE
42#define CONFIG_BAUDRATE 115200
43#if 0
44#define CONFIG_BOOTDELAY -1 /* autoboot disabled */
45#else
46#define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */
47#endif
48
49#define CONFIG_CLOCKS_IN_MHZ 1 /* clocks passsed to Linux in MHz */
50
51#define CONFIG_BOOTCOMMAND "bootp" /* autoboot command */
52
53#define CONFIG_BOOTARGS "root=/dev/nfs rw " \
54 "nfsroot=10.0.0.2:/opt/eldk/ppc_8xx " \
55 "nfsaddrs=10.0.0.99:10.0.0.2"
56
57#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
58#undef CFG_LOADS_BAUD_CHANGE /* don't allow baudrate change */
59
60#undef CONFIG_WATCHDOG /* watchdog disabled */
61
62#define CONFIG_COMMANDS \
63((CONFIG_CMD_DFL & ~(CFG_CMD_FLASH)) | CFG_CMD_IDE) /* no Flash, but IDE */
64#define CONFIG_MAC_PARTITION
65#define CONFIG_DOS_PARTITION
66
67#define CONFIG_BOOTP_MASK (CONFIG_BOOTP_DEFAULT | CONFIG_BOOTP_BOOTFILESIZE)
68
69/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
70#include <cmd_confdefs.h>
71
72/*----------------------------------------------------------------------*/
73#define CONFIG_ETHADDR 00:D0:93:00:01:CB
74#define CONFIG_IPADDR 10.0.0.98
75#define CONFIG_SERVERIP 10.0.0.1
76#undef CONFIG_BOOTCOMMAND
wdenk3bac3512003-03-12 10:41:04 +000077#define CONFIG_BOOTCOMMAND "tftp 200000 uImage;bootm 200000"
wdenk0f8c9762002-08-19 11:57:05 +000078/*----------------------------------------------------------------------*/
79
80/*
81 * Miscellaneous configurable options
82 */
83#define CFG_LONGHELP /* undef to save memory */
84#define CFG_PROMPT "=> " /* Monitor Command Prompt */
85#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
86#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */
87#else
88#define CFG_CBSIZE 256 /* Console I/O Buffer Size */
89#endif
90#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
91#define CFG_MAXARGS 16 /* max number of command args */
92#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */
93
94#define CFG_MEMTEST_START 0x00100000 /* memtest works on */
95#define CFG_MEMTEST_END 0x00F00000 /* 1 ... 15MB in DRAM */
96
97#define CFG_LOAD_ADDR 0x00100000 /* default load address */
98
99#define CFG_PIO_MODE 0 /* IDE interface in PIO Mode 0 */
100
101#define CFG_PC_IDE_RESET ((ushort)0x0008) /* PC 12 */
102
103#define CFG_HZ 1000 /* decrementer freq: 1 ms ticks */
104
105#define CFG_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 }
106
107/*
108 * Low Level Configuration Settings
109 * (address mappings, register initial values, etc.)
110 * You should know what you are doing if you make changes here.
111 */
112/*-----------------------------------------------------------------------
113 * Internal Memory Mapped Register
114 */
115#define CFG_IMMR 0xFFF00000 /* was: 0xFF000000 */
116
117/*-----------------------------------------------------------------------
118 * Definitions for initial stack pointer and data area (in DPRAM)
119 */
120#define CFG_INIT_RAM_ADDR CFG_IMMR
121#define CFG_INIT_RAM_END 0x2F00 /* End of used area in DPRAM */
122#define CFG_GBL_DATA_SIZE 64 /* size in bytes reserved for initial data */
123#define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
124#define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET
125
126/*-----------------------------------------------------------------------
127 * Start addresses for the final memory configuration
128 * (Set up by the startup code)
129 * Please note that CFG_SDRAM_BASE _must_ start at 0
130 */
131#define CFG_SDRAM_BASE 0x00000000
132#define CFG_FLASH_BASE 0xFF000000
133#ifdef DEBUG
134#define CFG_MONITOR_LEN (512 << 10) /* Reserve 512 kB for Monitor */
135#else
136#define CFG_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */
137#endif
138#define CFG_MONITOR_BASE CFG_FLASH_BASE
139#define CFG_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc() */
140
141/*
142 * For booting Linux, the board info and command line data
143 * have to be in the first 8 MB of memory, since this is
144 * the maximum mapped by the Linux kernel during initialization.
145 */
146#define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
147/*-----------------------------------------------------------------------
148 * FLASH organization
149 */
150#define CFG_MAX_FLASH_BANKS 0 /* max number of memory banks */
151#define CFG_MAX_FLASH_SECT 0 /* max number of sectors on one chip */
152
153#define CFG_FLASH_ERASE_TOUT 0 /* Timeout for Flash Erase (in ms) */
154#define CFG_FLASH_WRITE_TOUT 0 /* Timeout for Flash Write (in ms) */
155
156#define CFG_ENV_IS_IN_FLASH 1
157#define CFG_ENV_OFFSET 0x8000 /* Offset of Environment Sector */
158#define CFG_ENV_SIZE 0x0800 /* Total Size of Environment Sector */
159/*-----------------------------------------------------------------------
160 * Cache Configuration
161 */
162#define CFG_CACHELINE_SIZE 16 /* For all MPC8xx CPUs */
163#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
164#define CFG_CACHELINE_SHIFT 4 /* log base 2 of the above value */
165#endif
166
167/*-----------------------------------------------------------------------
168 * SYPCR - System Protection Control 11-9
169 * SYPCR can only be written once after reset!
170 *-----------------------------------------------------------------------
171 * Software & Bus Monitor Timer max, Bus Monitor enable, SW Watchdog freeze
172 */
173#if defined(CONFIG_WATCHDOG)
174#define CFG_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | \
175 SYPCR_SWE | SYPCR_SWRI| SYPCR_SWP)
176#else
177#define CFG_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | SYPCR_SWP)
178#endif
179
180/*-----------------------------------------------------------------------
181 * SIUMCR - SIU Module Configuration 11-6
182 *-----------------------------------------------------------------------
183 * PCMCIA config., multi-function pin tri-state
184 */
185/* 0x00000040 */
186#define CFG_SIUMCR (SIUMCR_DBGC00 | SIUMCR_DBPC00 | SIUMCR_MLRC00 | SIUMCR_GB5E)
187
188/*-----------------------------------------------------------------------
189 * TBSCR - Time Base Status and Control 11-26
190 *-----------------------------------------------------------------------
191 * Clear Reference Interrupt Status, Timebase freezing enabled
192 */
193#define CFG_TBSCR (TBSCR_REFA | TBSCR_REFB | TBSCR_TBF)
194
195/*-----------------------------------------------------------------------
196 * PISCR - Periodic Interrupt Status and Control 11-31
197 *-----------------------------------------------------------------------
198 * Clear Periodic Interrupt Status, Interrupt Timer freezing enabled
199 */
200#define CFG_PISCR (PISCR_PS | PISCR_PITF)
201
202/*-----------------------------------------------------------------------
203 * PLPRCR - PLL, Low-Power, and Reset Control Register 15-30
204 *-----------------------------------------------------------------------
205 * Reset PLL lock status sticky bit, timer expired status bit and timer
206 * interrupt status bit, set PLL multiplication factor !
207 */
208/* 0x00b0c0c0 */
209#define CFG_PLPRCR \
210 ( (11 << PLPRCR_MF_SHIFT) | \
211 PLPRCR_SPLSS | PLPRCR_TEXPS | /*PLPRCR_TMIST|*/ \
212 /*PLPRCR_CSRC|*/ PLPRCR_LPM_NORMAL | \
213 PLPRCR_CSR | PLPRCR_LOLRE /*|PLPRCR_FIOPD*/ \
214 )
215
216/*-----------------------------------------------------------------------
217 * SCCR - System Clock and reset Control Register 15-27
218 *-----------------------------------------------------------------------
219 * Set clock output, timebase and RTC source and divider,
220 * power management and some other internal clocks
221 */
222#define SCCR_MASK SCCR_EBDF11
223/* 0x01800014 */
224#define CFG_SCCR (SCCR_COM00 | /*SCCR_TBS|*/ \
225 SCCR_RTDIV | SCCR_RTSEL | \
226 /*SCCR_CRQEN|*/ /*SCCR_PRQEN|*/ \
227 SCCR_EBDF00 | SCCR_DFSYNC00 | \
228 SCCR_DFBRG00 | SCCR_DFNL000 | \
229 SCCR_DFNH000 | SCCR_DFLCD101 | \
230 SCCR_DFALCD00)
231
232/*-----------------------------------------------------------------------
233 * RTCSC - Real-Time Clock Status and Control Register
234 *-----------------------------------------------------------------------
235 */
236/* 0x00C3 */
237#define CFG_RTCSC (RTCSC_SEC | RTCSC_ALR | RTCSC_RTF| RTCSC_RTE)
238
239
240/*-----------------------------------------------------------------------
241 * RCCR - RISC Controller Configuration Register
242 *-----------------------------------------------------------------------
243 */
244/* TIMEP=2 */
245#define CFG_RCCR 0x0200
246
247/*-----------------------------------------------------------------------
248 * RMDS - RISC Microcode Development Support Control Register
249 *-----------------------------------------------------------------------
250 */
251#define CFG_RMDS 0
252
253/*-----------------------------------------------------------------------
254 * SDSR - SDMA Status Register
255 *-----------------------------------------------------------------------
256 */
257#define CFG_SDSR ((u_char)0x83)
258
259/*-----------------------------------------------------------------------
260 * SDMR - SDMA Mask Register
261 *-----------------------------------------------------------------------
262 */
263#define CFG_SDMR ((u_char)0x00)
264
265/*-----------------------------------------------------------------------
266 *
267 * Interrupt Levels
268 *-----------------------------------------------------------------------
269 */
270#define CFG_CPM_INTERRUPT 13 /* SIU_LEVEL6 */
271
272/*-----------------------------------------------------------------------
273 * PCMCIA stuff
274 *-----------------------------------------------------------------------
275 *
276 */
277#define CFG_PCMCIA_MEM_ADDR (0xE0000000)
278#define CFG_PCMCIA_MEM_SIZE ( 64 << 20 )
279#define CFG_PCMCIA_DMA_ADDR (0xE4000000)
280#define CFG_PCMCIA_DMA_SIZE ( 64 << 20 )
281#define CFG_PCMCIA_ATTRB_ADDR (0xE8000000)
282#define CFG_PCMCIA_ATTRB_SIZE ( 64 << 20 )
283#define CFG_PCMCIA_IO_ADDR (0xEC000000)
284#define CFG_PCMCIA_IO_SIZE ( 64 << 20 )
285
286/*-----------------------------------------------------------------------
287 * IDE/ATA stuff
288 *-----------------------------------------------------------------------
289 */
290#define CONFIG_IDE_8xx_DIRECT 1 /* PCMCIA interface required */
291#define CONFIG_IDE_LED 1 /* LED for ide supported */
292#define CONFIG_IDE_RESET 1 /* reset for ide supported */
293
294#define CFG_IDE_MAXBUS 2 /* max. 2 IDE busses */
295#define CFG_IDE_MAXDEVICE (CFG_IDE_MAXBUS*2) /* max. 2 drives per IDE bus */
296
297#define CFG_ATA_BASE_ADDR 0xFE100000
298#define CFG_ATA_IDE0_OFFSET 0x0000
299#define CFG_ATA_IDE1_OFFSET 0x0C00
300
301#define CFG_ATA_DATA_OFFSET 0x0000 /* Offset for data I/O */
302#define CFG_ATA_REG_OFFSET 0x0080 /* Offset for normal register accesses */
303#define CFG_ATA_ALT_OFFSET 0x0100 /* Offset for alternate registers */
304
305/*-----------------------------------------------------------------------
306 *
307 *-----------------------------------------------------------------------
308 *
309 */
wdenk0f8c9762002-08-19 11:57:05 +0000310#define CFG_DER 0
311
312/*
313 * Init Memory Controller:
314 *
315 * BR0/1 and OR0/1 (FLASH)
316 */
317
318#define FLASH_BASE0_PRELIM 0xFF000000 /* FLASH bank #0 */
319#define FLASH_BASE1_PRELIM 0xFF080000 /* FLASH bank #1 */
320
321/* used to re-map FLASH both when starting from SRAM or FLASH:
322 * restrict access enough to keep SRAM working (if any)
323 * but not too much to meddle with FLASH accesses
324 */
325/* EPROMs are 512kb */
326#define CFG_REMAP_OR_AM 0xFFF80000 /* OR addr mask */
327#define CFG_PRELIM_OR_AM 0xFFF80000 /* OR addr mask */
328
329/* FLASH timing: ACS = 11, TRLX = 0, CSNT = 1, SCY = 5, EHTR = 1 */
330#define CFG_OR_TIMING_FLASH (/* OR_CSNT_SAM | */ OR_ACS_DIV4 | OR_BI | \
331 OR_SCY_5_CLK | OR_EHTR)
332
333#define CFG_OR0_REMAP (CFG_REMAP_OR_AM | CFG_OR_TIMING_FLASH)
334#define CFG_OR0_PRELIM (CFG_PRELIM_OR_AM | CFG_OR_TIMING_FLASH)
335/* 16 bit, bank valid */
336#define CFG_BR0_PRELIM ((FLASH_BASE0_PRELIM & BR_BA_MSK) | BR_PS_16 | BR_V )
337
338#define CFG_OR1_REMAP CFG_OR0_REMAP
339#define CFG_OR1_PRELIM CFG_OR0_PRELIM
340/* 16 bit, bank valid */
341#define CFG_BR1_PRELIM ((FLASH_BASE1_PRELIM & BR_BA_MSK) | BR_PS_16 | BR_V )
342
343/*
344 * BR2-5 and OR2-5 (SRAM/SDRAM/PER8/SHARC)
345 *
346 */
347#define SRAM_BASE 0xFE200000 /* SRAM bank */
348#define SRAM_OR_AM 0xFFE00000 /* SRAM is 2 MB */
349
350#define SDRAM_BASE3_PRELIM 0x00000000 /* SDRAM bank */
351#define SDRAM_PRELIM_OR_AM 0xF8000000 /* map max. 128 MB */
352#define SDRAM_MAX_SIZE 0x04000000 /* max 64 MB SDRAM */
353
354#define PER8_BASE 0xFE000000 /* PER8 bank */
355#define PER8_OR_AM 0xFFF00000 /* PER8 is 1 MB */
356
357#define SHARC_BASE 0xFE400000 /* SHARC bank */
358#define SHARC_OR_AM 0xFFC00000 /* SHARC is 4 MB */
359
360/* SRAM timing: Multiplexed addresses, GPL5 output to GPL5_A (don't care) */
361
362#define CFG_OR_TIMING_SRAM 0x00000D42 /* SRAM-Timing */
363#define CFG_OR2 (SRAM_OR_AM | CFG_OR_TIMING_SRAM )
364#define CFG_BR2 ((SRAM_BASE & BR_BA_MSK) | BR_PS_16 | BR_V )
365
366/* SDRAM timing: Multiplexed addresses, GPL5 output to GPL5_A (don't care) */
367
368#define CFG_OR_TIMING_SDRAM 0x00000A00 /* SDRAM-Timing */
369#define CFG_OR3_PRELIM (SDRAM_PRELIM_OR_AM | CFG_OR_TIMING_SDRAM )
370#define CFG_BR3_PRELIM ((SDRAM_BASE3_PRELIM & BR_BA_MSK) | BR_MS_UPMB | BR_V )
371
372#define CFG_OR_TIMING_PER8 0x00000F32 /* PER8-Timing */
373#define CFG_OR4 (PER8_OR_AM | CFG_OR_TIMING_PER8 )
374#define CFG_BR4 ((PER8_BASE & BR_BA_MSK) | BR_PS_8 | BR_V )
375
376#define CFG_OR_TIMING_SHARC 0x00000700 /* SHARC-Timing */
377#define CFG_OR5 (SHARC_OR_AM | CFG_OR_TIMING_SHARC )
378#define CFG_BR5 ((SHARC_BASE & BR_BA_MSK) | BR_PS_32 | BR_MS_UPMA | BR_V )
379/*
380 * Memory Periodic Timer Prescaler
381 */
382
383/* periodic timer for refresh */
wdenk2535d602003-07-17 23:16:40 +0000384#define CFG_MBMR_PTB 204
wdenk0f8c9762002-08-19 11:57:05 +0000385
386/* refresh rate 15.6 us (= 64 ms / 4K = 62.4 / quad bursts) for <= 128 MBit */
387#define CFG_MPTPR_2BK_4K MPTPR_PTP_DIV16 /* setting for 2 banks */
388#define CFG_MPTPR_1BK_4K MPTPR_PTP_DIV32 /* setting for 1 bank */
389
390/* refresh rate 7.8 us (= 64 ms / 8K = 31.2 / quad bursts) for 256 MBit */
391#define CFG_MPTPR_2BK_8K MPTPR_PTP_DIV8 /* setting for 2 banks */
392#define CFG_MPTPR_1BK_8K MPTPR_PTP_DIV16 /* setting for 1 bank */
393
394/*
395 * MBMR settings for SDRAM
396 */
397
398/* 8 column SDRAM */
wdenk2535d602003-07-17 23:16:40 +0000399#define CFG_MBMR_8COL ((CFG_MBMR_PTB << MBMR_PTB_SHIFT) | \
400 MBMR_AMB_TYPE_0 | MBMR_DSB_1_CYCL | MBMR_G0CLB_A11 | \
401 MBMR_RLFB_1X | MBMR_WLFB_1X | MBMR_TLFB_4X)
wdenk0f8c9762002-08-19 11:57:05 +0000402
403/*
404 * Internal Definitions
405 *
406 * Boot Flags
407 */
408#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */
409#define BOOTFLAG_WARM 0x02 /* Software reboot */
410
411#endif /* __CONFIG_H */