blob: 0462cad8088e9fd593ff5ba39aa9691c1a268324 [file] [log] [blame]
wdenk1f045212002-03-10 14:37:15 +00001/*
2 * (C) Copyright 2000, 2001
3 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
4 *
5 * See file CREDITS for list of people who contributed to this
6 * project.
7 *
8 * This program is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU General Public License as
10 * published by the Free Software Foundation; either version 2 of
11 * the License, or (at your option) any later version.
12 *
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
17 *
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
21 * MA 02111-1307 USA
22 */
23
24/*
25 * mpc8260.h
26 *
27 * MPC8260 specific definitions
28 */
29
30#ifndef __MPC8260_H__
31#define __MPC8260_H__
32
33/*-----------------------------------------------------------------------
34 * Exception offsets (PowerPC standard)
35 */
36#define EXC_OFF_SYS_RESET 0x0100 /* System reset */
37
38
39/*-----------------------------------------------------------------------
40 * BCR - Bus Configuration Register 4-25
41 */
42#define BCR_EBM 0x80000000 /* External Bus Mode */
43#define BCR_APD_MSK 0x70000000 /* Address Phase Delay Mask */
44#define BCR_L2C 0x08000000 /* Secondary Cache Controller */
45#define BCR_L2D_MSK 0x07000000 /* L2 Cache Hit Delay Mask */
46#define BCR_PLDP 0x00800000 /* Pipeline Maximum Depth */
47#define BCR_EAV 0x00400000 /* Enable Address Visibility */
48#define BCR_ETM 0x00080000 /* Compatibility Mode Enable */
49#define BCR_LETM 0x00040000 /* LocalBus Compatibility Mode Enable*/
50#define BCR_EPAR 0x00020000 /* Even Parity */
51#define BCR_LEPAR 0x00010000 /* Local Bus Even Parity */
52#define BCR_NPQM0 0x00008000 /* Non PowerQUICC-II Master 0 */
53#define BCR_NPQM1 0x00004000 /* Non PowerQUICC-II Master 1 */
54#define BCR_NPQM2 0x00002000 /* Non PowerQUICC-II Master 2 */
55#define BCR_EXDD 0x00000400 /* External Master Delay Disable*/
56#define BCR_ISPS 0x00000010 /* Internal Space Port Size */
57
58/*-----------------------------------------------------------------------
59 * PPC_ACR - 60x Bus Arbiter Configuration Register 4-28
60 */
61#define PPC_ACR_DBGD 0x20 /* Data Bus Grant Delay */
62#define PPC_ACR_EARB 0x10 /* External Arbitration */
63#define PPC_ACR_PRKM_MSK 0x0f /* Parking Master */
64
65#define PPC_ACR_PRKM_CPMH 0x00 /* CPM high request level */
66#define PPC_ACR_PRKM_CPMM 0x01 /* CPM middle request level */
67#define PPC_ACR_PRKM_CPML 0x02 /* CPM low request level */
68#define PPC_ACR_PRKM_CORE 0x06 /* Internal Core */
69#define PPC_ACR_PRKM_EXT1 0x07 /* External Master 1 */
70#define PPC_ACR_PRKM_EXT2 0x08 /* External Master 2 */
71#define PPC_ACR_PRKM_EXT3 0x09 /* External Master 3 */
72
73/*-----------------------------------------------------------------------
74 * PPC_ALRH/PPC_ALRL - 60x Bus Arbitration-Level Registers 4-28
75 */
76#define PPC_ALRH_PF0_MSK 0xf0000000 /* Priority Field 0 Mask */
77#define PPC_ALRH_PF1_MSK 0x0f000000 /* Priority Field 1 Mask */
78#define PPC_ALRH_PF2_MSK 0x00f00000 /* Priority Field 2 Mask */
79#define PPC_ALRH_PF3_MSK 0x000f0000 /* Priority Field 3 Mask */
80#define PPC_ALRH_PF4_MSK 0x0000f000 /* Priority Field 4 Mask */
81#define PPC_ALRH_PF5_MSK 0x00000f00 /* Priority Field 5 Mask */
82#define PPC_ALRH_PF6_MSK 0x000000f0 /* Priority Field 6 Mask */
83#define PPC_ALRH_PF7_MSK 0x0000000f /* Priority Field 7 Mask */
84#define PPC_ALRL_PF8_MSK 0xf0000000 /* Priority Field 8 Mask */
85#define PPC_ALRL_PF9_MSK 0x0f000000 /* Priority Field 9 Mask */
86#define PPC_ALRL_PF10_MSK 0x00f00000 /* Priority Field 10 Mask */
87#define PPC_ALRL_PF11_MSK 0x000f0000 /* Priority Field 11 Mask */
88#define PPC_ALRL_PF12_MSK 0x0000f000 /* Priority Field 12 Mask */
89#define PPC_ALRL_PF13_MSK 0x00000f00 /* Priority Field 13 Mask */
90#define PPC_ALRL_PF14_MSK 0x000000f0 /* Priority Field 14 Mask */
91#define PPC_ALRL_PF15_MSK 0x0000000f /* Priority Field 15 Mask */
92
93/*-----------------------------------------------------------------------
94 * LCL_ACR - Local Bus Arbiter Configuration Register 4-29
95 */
96#define LCL_ACR_DBGD 0x20 /* Data Bus Grant Delay */
97#define LCL_ACR_PRKM_MSK 0x0f /* Parking Master */
98
99#define LCL_ACR_PRKM_CPMH 0x00 /* CPM high request level */
100#define LCL_ACR_PRKM_CPMM 0x01 /* CPM middle request level */
101#define LCL_ACR_PRKM_CPML 0x02 /* CPM low request level */
102#define LCL_ACR_PRKM_HOST 0x03 /* Host Bridge */
103
104/*-----------------------------------------------------------------------
105 * LCL_ALRH/LCL_ALRL - Local Bus Arbitration Level Registers 4-30
106 */
107#define LCL_ALRH_PF0_MSK 0xf0000000 /* Priority Field 0 Mask */
108#define LCL_ALRH_PF1_MSK 0x0f000000 /* Priority Field 1 Mask */
109#define LCL_ALRH_PF2_MSK 0x00f00000 /* Priority Field 2 Mask */
110#define LCL_ALRH_PF3_MSK 0x000f0000 /* Priority Field 3 Mask */
111#define LCL_ALRH_PF4_MSK 0x0000f000 /* Priority Field 4 Mask */
112#define LCL_ALRH_PF5_MSK 0x00000f00 /* Priority Field 5 Mask */
113#define LCL_ALRH_PF6_MSK 0x000000f0 /* Priority Field 6 Mask */
114#define LCL_ALRH_PF7_MSK 0x0000000f /* Priority Field 7 Mask */
115#define LCL_ALRL_PF8_MSK 0xf0000000 /* Priority Field 8 Mask */
116#define LCL_ALRL_PF9_MSK 0x0f000000 /* Priority Field 9 Mask */
117#define LCL_ALRL_PF10_MSK 0x00f00000 /* Priority Field 10 Mask */
118#define LCL_ALRL_PF11_MSK 0x000f0000 /* Priority Field 11 Mask */
119#define LCL_ALRL_PF12_MSK 0x0000f000 /* Priority Field 12 Mask */
120#define LCL_ALRL_PF13_MSK 0x00000f00 /* Priority Field 13 Mask */
121#define LCL_ALRL_PF14_MSK 0x000000f0 /* Priority Field 14 Mask */
122#define LCL_ALRL_PF15_MSK 0x0000000f /* Priority Field 15 Mask */
123
124/*-----------------------------------------------------------------------
125 * SIUMCR - SIU Module Configuration Register 4-31
126 */
127#define SIUMCR_BBD 0x80000000 /* Bus Busy Disable */
128#define SIUMCR_ESE 0x40000000 /* External Snoop Enable */
129#define SIUMCR_PBSE 0x20000000 /* Parity Byte Select Enable */
130#define SIUMCR_CDIS 0x10000000 /* Core Disable */
131#define SIUMCR_DPPC00 0x00000000 /* Data Parity Pins Configuration*/
132#define SIUMCR_DPPC01 0x04000000 /* - " - */
133#define SIUMCR_DPPC10 0x08000000 /* - " - */
134#define SIUMCR_DPPC11 0x0c000000 /* - " - */
135#define SIUMCR_L2CPC00 0x00000000 /* L2 Cache Pins Configuration */
136#define SIUMCR_L2CPC01 0x01000000 /* - " - */
137#define SIUMCR_L2CPC10 0x02000000 /* - " - */
138#define SIUMCR_L2CPC11 0x03000000 /* - " - */
139#define SIUMCR_LBPC00 0x00000000 /* Local Bus Pins Configuration */
140#define SIUMCR_LBPC01 0x00400000 /* - " - */
141#define SIUMCR_LBPC10 0x00800000 /* - " - */
142#define SIUMCR_LBPC11 0x00c00000 /* - " - */
143#define SIUMCR_APPC00 0x00000000 /* Address Parity Pins Configuration*/
144#define SIUMCR_APPC01 0x00100000 /* - " - */
145#define SIUMCR_APPC10 0x00200000 /* - " - */
146#define SIUMCR_APPC11 0x00300000 /* - " - */
147#define SIUMCR_CS10PC00 0x00000000 /* CS10 Pin Configuration */
148#define SIUMCR_CS10PC01 0x00040000 /* - " - */
149#define SIUMCR_CS10PC10 0x00080000 /* - " - */
150#define SIUMCR_CS10PC11 0x000c0000 /* - " - */
151#define SIUMCR_BCTLC00 0x00000000 /* Buffer Control Configuration */
152#define SIUMCR_BCTLC01 0x00010000 /* - " - */
153#define SIUMCR_BCTLC10 0x00020000 /* - " - */
154#define SIUMCR_BCTLC11 0x00030000 /* - " - */
155#define SIUMCR_MMR00 0x00000000 /* Mask Masters Requests */
156#define SIUMCR_MMR01 0x00004000 /* - " - */
157#define SIUMCR_MMR10 0x00008000 /* - " - */
158#define SIUMCR_MMR11 0x0000c000 /* - " - */
159#define SIUMCR_LPBSE 0x00002000 /* LocalBus Parity Byte Select Enable*/
160
161/*-----------------------------------------------------------------------
162 * IMMR - Internal Memory Map Register 4-34
163 */
164#define IMMR_ISB_MSK 0xfffe0000 /* Internal Space base */
165#define IMMR_PARTNUM_MSK 0x0000ff00 /* Part number */
166#define IMMR_MASKNUM_MSK 0x000000ff /* Mask number */
167
168/*-----------------------------------------------------------------------
169 * SYPCR - System Protection Control Register 4-35
170 */
171#define SYPCR_SWTC 0xffff0000 /* Software Watchdog Timer Count*/
172#define SYPCR_BMT 0x0000ff00 /* Bus Monitor Timing */
173#define SYPCR_PBME 0x00000080 /* 60x Bus Monitor Enable */
174#define SYPCR_LBME 0x00000040 /* Local Bus Monitor Enable */
175#define SYPCR_SWE 0x00000004 /* Software Watchdog Enable */
176#define SYPCR_SWRI 0x00000002 /* Software Watchdog Reset/Int Select*/
177#define SYPCR_SWP 0x00000001 /* Software Watchdog Prescale */
178
179/*-----------------------------------------------------------------------
180 * TMCNTSC - Time Counter Status and Control Register 4-40
181 */
182#define TMCNTSC_SEC 0x0080 /* Once Per Second Interrupt */
183#define TMCNTSC_ALR 0x0040 /* Alarm Interrupt */
184#define TMCNTSC_SIE 0x0008 /* Second Interrupt Enable */
185#define TMCNTSC_ALE 0x0004 /* Alarm Interrupt Enable */
186#define TMCNTSC_TCF 0x0002 /* Time Counter Frequency */
187#define TMCNTSC_TCE 0x0001 /* Time Counter Enable */
188
189/*-----------------------------------------------------------------------
190 * PISCR - Periodic Interrupt Status and Control Register 4-42
191 */
192#if 0 /* already defined in asm/immap_8260.h */
193#define PISCR_PS 0x0080 /* Periodic Interrupt Status */
194#define PISCR_PIE 0x0004 /* Periodic Interrupt Enable */
195#define PISCR_PTF 0x0002 /* Periodic Timer Frequency */
196#define PISCR_PTE 0x0001 /* Periodic Timer Enable */
197#endif
198
199/*-----------------------------------------------------------------------
200 * RSR - Reset Status Register 5-4
201 */
202#define RSR_JTRS 0x00000020 /* JTAG Reset Status */
203#define RSR_CSRS 0x00000010 /* Check Stop Reset Status */
204#define RSR_SWRS 0x00000008 /* Software Watchdog Reset Status*/
205#define RSR_BMRS 0x00000004 /* Bus Monitor Reset Status */
206#define RSR_ESRS 0x00000002 /* External Soft Reset Status */
207#define RSR_EHRS 0x00000001 /* External Hard Reset Status */
208
209#define RSR_ALLBITS (RSR_JTRS|RSR_CSRS|RSR_SWRS|RSR_BMRS|RSR_ESRS|RSR_EHRS)
210
211/*-----------------------------------------------------------------------
212 * RMR - Reset Mode Register 5-5
213 */
214#define RMR_CSRE 0x00000001 /* Checkstop Reset Enable */
215
216/*-----------------------------------------------------------------------
217 * Hard Reset Configuration Word 5-8
218 */
219#define HRCW_EARB 0x80000000 /* External Arbitration */
220#define HRCW_EXMC 0x40000000 /* External Memory Controller */
221#define HRCW_CDIS 0x20000000 /* Core Disable */
222#define HRCW_EBM 0x10000000 /* External Bus Mode */
223#define HRCW_BPS00 0x00000000 /* Boot Port Size */
224#define HRCW_BPS01 0x04000000 /* - " - */
225#define HRCW_BPS10 0x08000000 /* - " - */
226#define HRCW_BPS11 0x0c000000 /* - " - */
227#define HRCW_CIP 0x02000000 /* Core Initial Prefix */
228#define HRCW_ISPS 0x01000000 /* Internal Space Port Size */
229#define HRCW_L2CPC00 0x00000000 /* L2 Cache Pins Configuration */
230#define HRCW_L2CPC01 0x00400000 /* - " - */
231#define HRCW_L2CPC10 0x00800000 /* - " - */
232#define HRCW_L2CPC11 0x00c00000 /* - " - */
233#define HRCW_DPPC00 0x00000000 /* Data Parity Pin Configuration*/
234#define HRCW_DPPC01 0x00100000 /* - " - */
235#define HRCW_DPPC10 0x00200000 /* - " - */
236#define HRCW_DPPC11 0x00300000 /* - " - */
237#define HRCW_reserved1 0x00080000 /* reserved */
238#define HRCW_ISB000 0x00000000 /* Initial Internal Space Base */
239#define HRCW_ISB001 0x00010000 /* - " - */
240#define HRCW_ISB010 0x00020000 /* - " - */
241#define HRCW_ISB011 0x00030000 /* - " - */
242#define HRCW_ISB100 0x00040000 /* - " - */
243#define HRCW_ISB101 0x00050000 /* - " - */
244#define HRCW_ISB110 0x00060000 /* - " - */
245#define HRCW_ISB111 0x00070000 /* - " - */
246#define HRCW_BMS 0x00008000 /* Boot Memory Space */
247#define HRCW_BBD 0x00004000 /* Bus Busy Disable */
248#define HRCW_MMR00 0x00000000 /* Mask Masters Requests */
249#define HRCW_MMR01 0x00001000 /* - " - */
250#define HRCW_MMR10 0x00002000 /* - " - */
251#define HRCW_MMR11 0x00003000 /* - " - */
252#define HRCW_LBPC00 0x00000000 /* Local Bus Pin Configuration */
253#define HRCW_LBPC01 0x00000400 /* - " - */
254#define HRCW_LBPC10 0x00000800 /* - " - */
255#define HRCW_LBPC11 0x00000c00 /* - " - */
256#define HRCW_APPC00 0x00000000 /* Address Parity Pin Configuration*/
257#define HRCW_APPC01 0x00000100 /* - " - */
258#define HRCW_APPC10 0x00000200 /* - " - */
259#define HRCW_APPC11 0x00000300 /* - " - */
260#define HRCW_CS10PC00 0x00000000 /* CS10 Pin Configuration */
261#define HRCW_CS10PC01 0x00000040 /* - " - */
262#define HRCW_CS10PC10 0x00000080 /* - " - */
263#define HRCW_CS10PC11 0x000000c0 /* - " - */
264#define HRCW_MODCK_H0000 0x00000000 /* High-order bits of MODCK Bus */
265#define HRCW_MODCK_H0001 0x00000001 /* - " - */
266#define HRCW_MODCK_H0010 0x00000002 /* - " - */
267#define HRCW_MODCK_H0011 0x00000003 /* - " - */
268#define HRCW_MODCK_H0100 0x00000004 /* - " - */
269#define HRCW_MODCK_H0101 0x00000005 /* - " - */
270#define HRCW_MODCK_H0110 0x00000006 /* - " - */
271#define HRCW_MODCK_H0111 0x00000007 /* - " - */
272#define HRCW_MODCK_H1000 0x00000008 /* - " - */
273#define HRCW_MODCK_H1001 0x00000009 /* - " - */
274#define HRCW_MODCK_H1010 0x0000000a /* - " - */
275#define HRCW_MODCK_H1011 0x0000000b /* - " - */
276#define HRCW_MODCK_H1100 0x0000000c /* - " - */
277#define HRCW_MODCK_H1101 0x0000000d /* - " - */
278#define HRCW_MODCK_H1110 0x0000000e /* - " - */
279#define HRCW_MODCK_H1111 0x0000000f /* - " - */
280
281/*-----------------------------------------------------------------------
282 * SCCR - System Clock Control Register 9-8
283 */
284#define SCCR_CLPD 0x00000004 /* CPM Low Power Disable */
285#define SCCR_DFBRG_MSK 0x00000003 /* Division factor of BRGCLK Mask */
286#define SCCR_DFBRG_SHIFT 0
287
288#define SCCR_DFBRG00 0x00000000 /* BRGCLK division by 4 */
289#define SCCR_DFBRG01 0x00000001 /* BRGCLK division by 16 (normal op.)*/
290#define SCCR_DFBRG10 0x00000002 /* BRGCLK division by 64 */
291#define SCCR_DFBRG11 0x00000003 /* BRGCLK division by 128 */
292
293/*-----------------------------------------------------------------------
294 * SCMR - System Clock Mode Register 9-9
295 */
296#define SCMR_CORECNF_MSK 0x1f000000 /* Core Configuration Mask */
297#define SCMR_CORECNF_SHIFT 24
298#define SCMR_BUSDF_MSK 0x00f00000 /* 60x Bus Division Factor Mask */
299#define SCMR_BUSDF_SHIFT 20
300#define SCMR_CPMDF_MSK 0x000f0000 /* CPM Division Factor Mask */
301#define SCMR_CPMDF_SHIFT 16
302#define SCMR_PLLDF 0x00001000 /* PLL Pre-divider Value */
303#define SCMR_PLLMF_MSK 0x00000fff /* PLL Multiplication Factor Mask*/
304#define SCMR_PLLMF_SHIFT 0
305
306
307/*-----------------------------------------------------------------------
308 * MxMR - Machine A/B/C Mode Registers 10-13
309 */
310#define MxMR_BSEL 0x80000000 /* Bus Select */
311#define MxMR_RFEN 0x40000000 /* Refresh Enable */
312#define MxMR_OP_MSK 0x30000000 /* Command Opcode Mask */
313#define MxMR_AMx_MSK 0x07000000 /* Addess Multiplex Size Mask */
314#define MxMR_DSx_MSK 0x00c00000 /* Disable Timer Period Mask */
315#define MxMR_G0CLx_MSK 0x00380000 /* General Line 0 Control Mask */
316#define MxMR_GPL_x4DIS 0x00040000 /* GPL_A4 Ouput Line Disable */
317#define MxMR_RLFx_MSK 0x0003c000 /* Read Loop Field Mask */
318#define MxMR_WLFx_MSK 0x00003c00 /* Write Loop Field Mask */
319#define MxMR_TLFx_MSK 0x000003c0 /* Refresh Loop Field Mask */
320#define MxMR_MAD_MSK 0x0000003f /* Machine Address Mask */
321
322#define MxMR_OP_NORM 0x00000000 /* Normal Operation */
323#define MxMR_OP_WARR 0x10000000 /* Write to Array */
324#define MxMR_OP_RARR 0x20000000 /* Read from Array */
325#define MxMR_OP_RUNP 0x30000000 /* Run Pattern */
326
327#define MxMR_AMx_TYPE_0 0x00000000 /* Addess Multiplexing Type 0 */
328#define MxMR_AMx_TYPE_1 0x01000000 /* Addess Multiplexing Type 1 */
329#define MxMR_AMx_TYPE_2 0x02000000 /* Addess Multiplexing Type 2 */
330#define MxMR_AMx_TYPE_3 0x03000000 /* Addess Multiplexing Type 3 */
331#define MxMR_AMx_TYPE_4 0x04000000 /* Addess Multiplexing Type 4 */
332#define MxMR_AMx_TYPE_5 0x05000000 /* Addess Multiplexing Type 5 */
333
334#define MxMR_DSx_1_CYCL 0x00000000 /* 1 cycle Disable Period */
335#define MxMR_DSx_2_CYCL 0x00400000 /* 2 cycle Disable Period */
336#define MxMR_DSx_3_CYCL 0x00800000 /* 3 cycle Disable Period */
337#define MxMR_DSx_4_CYCL 0x00c00000 /* 4 cycle Disable Period */
338
339#define MxMR_G0CLx_A12 0x00000000 /* General Line 0 : A12 */
340#define MxMR_G0CLx_A11 0x00080000 /* General Line 0 : A11 */
341#define MxMR_G0CLx_A10 0x00100000 /* General Line 0 : A10 */
342#define MxMR_G0CLx_A9 0x00180000 /* General Line 0 : A9 */
343#define MxMR_G0CLx_A8 0x00200000 /* General Line 0 : A8 */
344#define MxMR_G0CLx_A7 0x00280000 /* General Line 0 : A7 */
345#define MxMR_G0CLx_A6 0x00300000 /* General Line 0 : A6 */
346#define MxMR_G0CLx_A5 0x00380000 /* General Line 0 : A5 */
347
348#define MxMR_RLFx_1X 0x00004000 /* Read Loop is executed 1 time */
349#define MxMR_RLFx_2X 0x00008000 /* Read Loop is executed 2 times*/
350#define MxMR_RLFx_3X 0x0000c000 /* Read Loop is executed 3 times*/
351#define MxMR_RLFx_4X 0x00010000 /* Read Loop is executed 4 times*/
352#define MxMR_RLFx_5X 0x00014000 /* Read Loop is executed 5 times*/
353#define MxMR_RLFx_6X 0x00018000 /* Read Loop is executed 6 times*/
354#define MxMR_RLFx_7X 0x0001c000 /* Read Loop is executed 7 times*/
355#define MxMR_RLFx_8X 0x00020000 /* Read Loop is executed 8 times*/
356#define MxMR_RLFx_9X 0x00024000 /* Read Loop is executed 9 times*/
357#define MxMR_RLFx_10X 0x00028000 /* Read Loop is executed 10 times*/
358#define MxMR_RLFx_11X 0x0002c000 /* Read Loop is executed 11 times*/
359#define MxMR_RLFx_12X 0x00030000 /* Read Loop is executed 12 times*/
360#define MxMR_RLFx_13X 0x00034000 /* Read Loop is executed 13 times*/
361#define MxMR_RLFx_14X 0x00038000 /* Read Loop is executed 14 times*/
362#define MxMR_RLFx_15X 0x0003c000 /* Read Loop is executed 15 times*/
363#define MxMR_RLFx_16X 0x00000000 /* Read Loop is executed 16 times*/
364
365#define MxMR_WLFx_1X 0x00000400 /* Write Loop is executed 1 time*/
366#define MxMR_WLFx_2X 0x00000800 /* Write Loop is executed 2 times*/
367#define MxMR_WLFx_3X 0x00000c00 /* Write Loop is executed 3 times*/
368#define MxMR_WLFx_4X 0x00001000 /* Write Loop is executed 4 times*/
369#define MxMR_WLFx_5X 0x00001400 /* Write Loop is executed 5 times*/
370#define MxMR_WLFx_6X 0x00001800 /* Write Loop is executed 6 times*/
371#define MxMR_WLFx_7X 0x00001c00 /* Write Loop is executed 7 times*/
372#define MxMR_WLFx_8X 0x00002000 /* Write Loop is executed 8 times*/
373#define MxMR_WLFx_9X 0x00002400 /* Write Loop is executed 9 times*/
374#define MxMR_WLFx_10X 0x00002800 /* Write Loop is executed 10 times*/
375#define MxMR_WLFx_11X 0x00002c00 /* Write Loop is executed 11 times*/
376#define MxMR_WLFx_12X 0x00003000 /* Write Loop is executed 12 times*/
377#define MxMR_WLFx_13X 0x00003400 /* Write Loop is executed 13 times*/
378#define MxMR_WLFx_14X 0x00003800 /* Write Loop is executed 14 times*/
379#define MxMR_WLFx_15X 0x00003c00 /* Write Loop is executed 15 times*/
380#define MxMR_WLFx_16X 0x00000000 /* Write Loop is executed 16 times*/
381
382#define MxMR_TLFx_1X 0x00000040 /* Timer Loop is executed 1 time*/
383#define MxMR_TLFx_2X 0x00000080 /* Timer Loop is executed 2 times*/
384#define MxMR_TLFx_3X 0x000000c0 /* Timer Loop is executed 3 times*/
385#define MxMR_TLFx_4X 0x00000100 /* Timer Loop is executed 4 times*/
386#define MxMR_TLFx_5X 0x00000140 /* Timer Loop is executed 5 times*/
387#define MxMR_TLFx_6X 0x00000180 /* Timer Loop is executed 6 times*/
388#define MxMR_TLFx_7X 0x000001c0 /* Timer Loop is executed 7 times*/
389#define MxMR_TLFx_8X 0x00000200 /* Timer Loop is executed 8 times*/
390#define MxMR_TLFx_9X 0x00000240 /* Timer Loop is executed 9 times*/
391#define MxMR_TLFx_10X 0x00000280 /* Timer Loop is executed 10 times*/
392#define MxMR_TLFx_11X 0x000002c0 /* Timer Loop is executed 11 times*/
393#define MxMR_TLFx_12X 0x00000300 /* Timer Loop is executed 12 times*/
394#define MxMR_TLFx_13X 0x00000340 /* Timer Loop is executed 13 times*/
395#define MxMR_TLFx_14X 0x00000380 /* Timer Loop is executed 14 times*/
396#define MxMR_TLFx_15X 0x000003c0 /* Timer Loop is executed 15 times*/
397#define MxMR_TLFx_16X 0x00000000 /* Timer Loop is executed 16 times*/
398
399
400/*-----------------------------------------------------------------------
401 * BRx - Memory Controller: Base Register 10-14
402 */
403#define BRx_BA_MSK 0xffff8000 /* Base Address Mask */
404#define BRx_PS_MSK 0x00001800 /* Port Size Mask */
405#define BRx_DECC_MSK 0x00000600 /* Data Error Correct+Check Mask*/
406#define BRx_WP 0x00000100 /* Write Protect */
407#define BRx_MS_MSK 0x000000e0 /* Machine Select Mask */
408#define BRx_EMEMC 0x00000010 /* External MEMC Enable */
409#define BRx_ATOM_MSK 0x0000000c /* Atomic Operation Mask */
410#define BRx_DR 0x00000002 /* Data Pipelining */
411#define BRx_V 0x00000001 /* Bank Valid */
412
413#define BRx_PS_64 0x00000000 /* 64 bit port size (60x bus only)*/
414#define BRx_PS_8 0x00000800 /* 8 bit port size */
415#define BRx_PS_16 0x00001000 /* 16 bit port size */
416#define BRx_PS_32 0x00001800 /* 32 bit port size */
417
418#define BRx_DECC_NONE 0x00000000 /* Data Errors Checking Disabled*/
419#define BRx_DECC_NORMAL 0x00000200 /* Normal Parity Checking */
420#define BRx_DECC_RMWPC 0x00000400 /* Read-Modify-Write Parity Checking*/
421#define BRx_DECC_ECC 0x00000600 /* ECC Correction and Checking */
422
423#define BRx_MS_GPCM_P 0x00000000 /* G.P.C.M. 60x Bus Machine Select*/
424#define BRx_MS_GPCM_L 0x00000020 /* G.P.C.M. Local Bus Machine Select*/
425#define BRx_MS_SDRAM_P 0x00000040 /* SDRAM 60x Bus Machine Select */
426#define BRx_MS_SDRAM_L 0x00000060 /* SDRAM Local Bus Machine Select*/
427#define BRx_MS_UPMA 0x00000080 /* U.P.M.A Machine Select */
428#define BRx_MS_UPMB 0x000000a0 /* U.P.M.B Machine Select */
429#define BRx_MS_UPMC 0x000000c0 /* U.P.M.C Machine Select */
430
431#define BRx_ATOM_RAWA 0x00000004 /* Read-After-Write-Atomic */
432#define BRx_ATOM_WARA 0x00000008 /* Write-After-Read-Atomic */
433
434/*-----------------------------------------------------------------------
435 * ORx - Memory Controller: Option Register - SDRAM Mode 10-16
436 */
437#define ORxS_SDAM_MSK 0xfff00000 /* SDRAM Address Mask Mask */
438#define ORxS_LSDAM_MSK 0x000f8000 /* Lower SDRAM Address Mask Mask*/
439#define ORxS_BPD_MSK 0x00006000 /* Banks Per Device Mask */
440#define ORxS_ROWST_MSK 0x00001e00 /* Row Start Address Bit Mask */
441#define ORxS_NUMR_MSK 0x000001c0 /* Number of Row Addr Lines Mask*/
442#define ORxS_PMSEL 0x00000020 /* Page Mode Select */
443#define ORxS_IBID 0x00000010 /* Internal Bank Interleaving Disable*/
444
445#define ORxS_BPD_2 0x00000000 /* 2 Banks Per Device */
446#define ORxS_BPD_4 0x00002000 /* 4 Banks Per Device */
447#define ORxS_BPD_8 0x00004000 /* 8 Banks Per Device */
448
449/* ROWST values for xSDMR[PBI] = 0 */
450#define ORxS_ROWST_PBI0_A7 0x00000400 /* Row Start Address Bit is A7 */
451#define ORxS_ROWST_PBI0_A8 0x00000800 /* Row Start Address Bit is A8 */
452#define ORxS_ROWST_PBI0_A9 0x00000c00 /* Row Start Address Bit is A9 */
453#define ORxS_ROWST_PBI0_A10 0x00001000 /* Row Start Address Bit is A10 */
454#define ORxS_ROWST_PBI0_A11 0x00001400 /* Row Start Address Bit is A11 */
455#define ORxS_ROWST_PBI0_A12 0x00001800 /* Row Start Address Bit is A12 */
456#define ORxS_ROWST_PBI0_A13 0x00001c00 /* Row Start Address Bit is A13 */
457
458/* ROWST values for xSDMR[PBI] = 1 */
459#define ORxS_ROWST_PBI1_A0 0x00000000 /* Row Start Address Bit is A0 */
460#define ORxS_ROWST_PBI1_A1 0x00000200 /* Row Start Address Bit is A1 */
461#define ORxS_ROWST_PBI1_A2 0x00000400 /* Row Start Address Bit is A2 */
462#define ORxS_ROWST_PBI1_A3 0x00000600 /* Row Start Address Bit is A3 */
463#define ORxS_ROWST_PBI1_A4 0x00000800 /* Row Start Address Bit is A4 */
464#define ORxS_ROWST_PBI1_A5 0x00000a00 /* Row Start Address Bit is A5 */
465#define ORxS_ROWST_PBI1_A6 0x00000c00 /* Row Start Address Bit is A6 */
466#define ORxS_ROWST_PBI1_A7 0x00000e00 /* Row Start Address Bit is A7 */
467#define ORxS_ROWST_PBI1_A8 0x00001000 /* Row Start Address Bit is A8 */
468#define ORxS_ROWST_PBI1_A9 0x00001200 /* Row Start Address Bit is A9 */
469#define ORxS_ROWST_PBI1_A10 0x00001400 /* Row Start Address Bit is A10 */
470#define ORxS_ROWST_PBI1_A11 0x00001600 /* Row Start Address Bit is A11 */
471#define ORxS_ROWST_PBI1_A12 0x00001800 /* Row Start Address Bit is A12 */
472
473#define ORxS_NUMR_9 0x00000000 /* 9 Row Address Lines */
474#define ORxS_NUMR_10 0x00000040 /* 10 Row Address Lines */
475#define ORxS_NUMR_11 0x00000080 /* 11 Row Address Lines */
476#define ORxS_NUMR_12 0x000000c0 /* 12 Row Address Lines */
477#define ORxS_NUMR_13 0x00000100 /* 13 Row Address Lines */
478#define ORxS_NUMR_14 0x00000140 /* 14 Row Address Lines */
479#define ORxS_NUMR_15 0x00000180 /* 15 Row Address Lines */
480#define ORxS_NUMR_16 0x000001c0 /* 16 Row Address Lines */
481
482/* helper to determine the AM for a given size (SDRAM mode) */
483#define ORxS_SIZE_TO_AM(s) ((~((s) - 1)) & 0xffff8000) /* must be pow of 2 */
484
485/*-----------------------------------------------------------------------
486 * ORx - Memory Controller: Option Register - GPCM Mode 10-18
487 */
488#define ORxG_AM_MSK 0xffff8000 /* Address Mask Mask */
489#define ORxG_BCTLD 0x00001000 /* Data Buffer Control Disable */
490#define ORxG_CSNT 0x00000800 /* Chip Select Negation Time */
491#define ORxG_ACS_MSK 0x00000600 /* Address to Chip Select Setup mask*/
492#define ORxG_SCY_MSK 0x000000f0 /* Cycle Lenght in Clocks */
493#define ORxG_SETA 0x00000008 /* External Access Termination */
494#define ORxG_TRLX 0x00000004 /* Timing Relaxed */
495#define ORxG_EHTR 0x00000002 /* Extended Hold Time on Read */
496
497#define ORxG_ACS_DIV1 0x00000000 /* CS is output at the same time*/
498#define ORxG_ACS_DIV4 0x00000400 /* CS is output 1/4 a clock later*/
499#define ORxG_ACS_DIV2 0x00000600 /* CS is output 1/2 a clock later*/
500
501#define ORxG_SCY_0_CLK 0x00000000 /* 0 clock cycles wait states */
502#define ORxG_SCY_1_CLK 0x00000010 /* 1 clock cycles wait states */
503#define ORxG_SCY_2_CLK 0x00000020 /* 2 clock cycles wait states */
504#define ORxG_SCY_3_CLK 0x00000030 /* 3 clock cycles wait states */
505#define ORxG_SCY_4_CLK 0x00000040 /* 4 clock cycles wait states */
506#define ORxG_SCY_5_CLK 0x00000050 /* 5 clock cycles wait states */
507#define ORxG_SCY_6_CLK 0x00000060 /* 6 clock cycles wait states */
508#define ORxG_SCY_7_CLK 0x00000070 /* 7 clock cycles wait states */
509#define ORxG_SCY_8_CLK 0x00000080 /* 8 clock cycles wait states */
510#define ORxG_SCY_9_CLK 0x00000090 /* 9 clock cycles wait states */
511#define ORxG_SCY_10_CLK 0x000000a0 /* 10 clock cycles wait states */
512#define ORxG_SCY_11_CLK 0x000000b0 /* 11 clock cycles wait states */
513#define ORxG_SCY_12_CLK 0x000000c0 /* 12 clock cycles wait states */
514#define ORxG_SCY_13_CLK 0x000000d0 /* 13 clock cycles wait states */
515#define ORxG_SCY_14_CLK 0x000000e0 /* 14 clock cycles wait states */
516#define ORxG_SCY_15_CLK 0x000000f0 /* 15 clock cycles wait states */
517
518/*-----------------------------------------------------------------------
519 * ORx - Memory Controller: Option Register - UPM Mode 10-20
520 */
521#define ORxU_AM_MSK 0xffff8000 /* Address Mask Mask */
522#define ORxU_BCTLD 0x00001000 /* Data Buffer Control Disable */
523#define ORxU_BI 0x00000100 /* Burst Inhibit */
524#define ORxU_EHTR_MSK 0x00000006 /* Extended Hold Time on Read Mask*/
525
526#define ORxU_EHTR_NORM 0x00000000 /* Normal Timing */
527#define ORxU_EHTR_1IDLE 0x00000002 /* One Idle Clock Cycle Inserted*/
528#define ORxU_EHTR_4IDLE 0x00000004 /* Four Idle Clock Cycles Inserted*/
529#define ORxU_EHTR_8IDLE 0x00000006 /* Eight Idle Clock Cycles Inserted*/
530
531
532/* helpers to convert values into an OR address mask (GPCM mode) */
533#define P2SZ_TO_AM(s) ((~((s) - 1)) & 0xffff8000) /* must be pow of 2 */
534#define MEG_TO_AM(m) P2SZ_TO_AM((m) << 20)
535
536
537/*-----------------------------------------------------------------------
538 * PSDMR - 60x SDRAM Mode Register 10-21
539 */
540#define PSDMR_PBI 0x80000000 /* Page-based Interleaving */
541#define PSDMR_RFEN 0x40000000 /* Refresh Enable */
542#define PSDMR_OP_MSK 0x38000000 /* SDRAM Operation Mask */
543#define PSDMR_SDAM_MSK 0x07000000 /* SDRAM Address Multiplex Mask */
544#define PSDMR_BSMA_MSK 0x00e00000 /* Bank Select Muxd Addr Line Mask*/
545#define PSDMR_SDA10_MSK 0x001c0000 /* A10 Control Mask */
546#define PSDMR_RFRC_MSK 0x00038000 /* Refresh Recovery Mask */
547#define PSDMR_PRETOACT_MSK 0x00007000 /* Precharge to Activate Intvl Mask*/
548#define PSDMR_ACTTORW_MSK 0x00000e00 /* Activate to Read/Write Intvl Mask*/
549#define PSDMR_BL 0x00000100 /* Burst Length */
550#define PSDMR_LDOTOPRE_MSK 0x000000c0 /* Last Data Out to Precharge Mask*/
551#define PSDMR_WRC_MSK 0x00000030 /* Write Recovery Time Mask */
552#define PSDMR_EAMUX 0x00000008 /* External Address Multiplexing*/
553#define PSDMR_BUFCMD 0x00000004 /* SDRAM ctl lines asrtd for 2 cycles*/
554#define PSDMR_CL_MSK 0x00000003 /* CAS Latency Mask */
555
556#define PSDMR_OP_NORM 0x00000000 /* Normal Operation */
557#define PSDMR_OP_CBRR 0x08000000 /* CBR Refresh */
558#define PSDMR_OP_SELFR 0x10000000 /* Self Refresh */
559#define PSDMR_OP_MRW 0x18000000 /* Mode Register Write */
560#define PSDMR_OP_PREB 0x20000000 /* Precharge Bank */
561#define PSDMR_OP_PREA 0x28000000 /* Precharge All Banks */
562#define PSDMR_OP_ACTB 0x30000000 /* Activate Bank */
563#define PSDMR_OP_RW 0x38000000 /* Read/Write */
564
565#define PSDMR_SDAM_A13_IS_A5 0x00000000 /* SDRAM Address Multiplex A13 is A5 */
566#define PSDMR_SDAM_A14_IS_A5 0x01000000 /* SDRAM Address Multiplex A14 is A5 */
567#define PSDMR_SDAM_A15_IS_A5 0x02000000 /* SDRAM Address Multiplex A15 is A5 */
568#define PSDMR_SDAM_A16_IS_A5 0x03000000 /* SDRAM Address Multiplex A16 is A5 */
569#define PSDMR_SDAM_A17_IS_A5 0x04000000 /* SDRAM Address Multiplex A17 is A5 */
570#define PSDMR_SDAM_A18_IS_A5 0x05000000 /* SDRAM Address Multiplex A18 is A5 */
571
572#define PSDMR_BSMA_A12_A14 0x00000000 /* A12 - A14 */
573#define PSDMR_BSMA_A13_A15 0x00200000 /* A13 - A15 */
574#define PSDMR_BSMA_A14_A16 0x00400000 /* A14 - A16 */
575#define PSDMR_BSMA_A15_A17 0x00600000 /* A15 - A17 */
576#define PSDMR_BSMA_A16_A18 0x00800000 /* A16 - A18 */
577#define PSDMR_BSMA_A17_A19 0x00a00000 /* A17 - A19 */
578#define PSDMR_BSMA_A18_A20 0x00c00000 /* A18 - A20 */
579#define PSDMR_BSMA_A19_A21 0x00e00000 /* A19 - A21 */
580
581/* SDA10 values for xSDMR[PBI] = 0 */
582#define PSDMR_SDA10_PBI0_A12 0x00000000 /* "A10" Control is A12 */
583#define PSDMR_SDA10_PBI0_A11 0x00040000 /* "A10" Control is A11 */
584#define PSDMR_SDA10_PBI0_A10 0x00080000 /* "A10" Control is A10 */
585#define PSDMR_SDA10_PBI0_A9 0x000c0000 /* "A10" Control is A9 */
586#define PSDMR_SDA10_PBI0_A8 0x00100000 /* "A10" Control is A8 */
587#define PSDMR_SDA10_PBI0_A7 0x00140000 /* "A10" Control is A7 */
588#define PSDMR_SDA10_PBI0_A6 0x00180000 /* "A10" Control is A6 */
589#define PSDMR_SDA10_PBI0_A5 0x001c0000 /* "A10" Control is A5 */
590
591/* SDA10 values for xSDMR[PBI] = 1 */
592#define PSDMR_SDA10_PBI1_A10 0x00000000 /* "A10" Control is A10 */
593#define PSDMR_SDA10_PBI1_A9 0x00040000 /* "A10" Control is A9 */
594#define PSDMR_SDA10_PBI1_A8 0x00080000 /* "A10" Control is A8 */
595#define PSDMR_SDA10_PBI1_A7 0x000c0000 /* "A10" Control is A7 */
596#define PSDMR_SDA10_PBI1_A6 0x00100000 /* "A10" Control is A6 */
597#define PSDMR_SDA10_PBI1_A5 0x00140000 /* "A10" Control is A5 */
598#define PSDMR_SDA10_PBI1_A4 0x00180000 /* "A10" Control is A4 */
599#define PSDMR_SDA10_PBI1_A3 0x001c0000 /* "A10" Control is A3 */
600
601#define PSDMR_RFRC_3_CLK 0x00008000 /* 3 Clocks */
602#define PSDMR_RFRC_4_CLK 0x00010000 /* 4 Clocks */
603#define PSDMR_RFRC_5_CLK 0x00018000 /* 5 Clocks */
604#define PSDMR_RFRC_6_CLK 0x00020000 /* 6 Clocks */
605#define PSDMR_RFRC_7_CLK 0x00028000 /* 7 Clocks */
606#define PSDMR_RFRC_8_CLK 0x00030000 /* 8 Clocks */
607#define PSDMR_RFRC_16_CLK 0x00038000 /* 16 Clocks */
608
609#define PSDMR_PRETOACT_8W 0x00000000 /* 8 Clock-cycle Wait States */
610#define PSDMR_PRETOACT_1W 0x00001000 /* 1 Clock-cycle Wait States */
611#define PSDMR_PRETOACT_2W 0x00002000 /* 2 Clock-cycle Wait States */
612#define PSDMR_PRETOACT_3W 0x00003000 /* 3 Clock-cycle Wait States */
613#define PSDMR_PRETOACT_4W 0x00004000 /* 4 Clock-cycle Wait States */
614#define PSDMR_PRETOACT_5W 0x00005000 /* 5 Clock-cycle Wait States */
615#define PSDMR_PRETOACT_6W 0x00006000 /* 6 Clock-cycle Wait States */
616#define PSDMR_PRETOACT_7W 0x00007000 /* 7 Clock-cycle Wait States */
617
618#define PSDMR_ACTTORW_8W 0x00000000 /* 8 Clock-cycle Wait States */
619#define PSDMR_ACTTORW_1W 0x00000200 /* 1 Clock-cycle Wait States */
620#define PSDMR_ACTTORW_2W 0x00000400 /* 2 Clock-cycle Wait States */
621#define PSDMR_ACTTORW_3W 0x00000600 /* 3 Clock-cycle Wait States */
622#define PSDMR_ACTTORW_4W 0x00000800 /* 4 Clock-cycle Wait States */
623#define PSDMR_ACTTORW_5W 0x00000a00 /* 5 Clock-cycle Wait States */
624#define PSDMR_ACTTORW_6W 0x00000c00 /* 6 Clock-cycle Wait States */
625#define PSDMR_ACTTORW_7W 0x00000e00 /* 7 Clock-cycle Wait States */
626
627#define PSDMR_LDOTOPRE_0C 0x00000000 /* 0 Clock Cycles */
628#define PSDMR_LDOTOPRE_1C 0x00000040 /* 1 Clock Cycles */
629#define PSDMR_LDOTOPRE_2C 0x00000080 /* 2 Clock Cycles */
630
631#define PSDMR_WRC_4C 0x00000000 /* 4 Clock Cycles */
632#define PSDMR_WRC_1C 0x00000010 /* 1 Clock Cycles */
633#define PSDMR_WRC_2C 0x00000020 /* 2 Clock Cycles */
634#define PSDMR_WRC_3C 0x00000030 /* 3 Clock Cycles */
635
636#define PSDMR_CL_1 0x00000001 /* CAS Latency = 1 */
637#define PSDMR_CL_2 0x00000002 /* CAS Latency = 2 */
638#define PSDMR_CL_3 0x00000003 /* CAS Latency = 3 */
639
640/*-----------------------------------------------------------------------
641 * LSDMR - Local Bus SDRAM Mode Register 10-24
642 */
643
644/*
645 * No definitions here - the LSDMR has the same fields as the PSDMR.
646 */
647
648/*-----------------------------------------------------------------------
649 * MPTPR - Memory Refresh Timer Prescaler Register 10-32
650 * See User's Manual Errata for the changed definition (matches the
651 * 8xx now). The wrong prescaler definition causes excessive refreshes
652 * (typically "divide by 2" when "divide by 32" is intended) which will
653 * cause unnecessary memory subsystem slowdown.
654 */
655#define MPTPR_PTP_MSK 0xff00 /* Periodic Timers Prescaler Mask */
656#define MPTPR_PTP_DIV2 0x2000 /* BRGCLK divided by 2 */
657#define MPTPR_PTP_DIV4 0x1000 /* BRGCLK divided by 4 */
658#define MPTPR_PTP_DIV8 0x0800 /* BRGCLK divided by 8 */
659#define MPTPR_PTP_DIV16 0x0400 /* BRGCLK divided by 16 */
660#define MPTPR_PTP_DIV32 0x0200 /* BRGCLK divided by 32 */
661#define MPTPR_PTP_DIV64 0x0100 /* BRGCLK divided by 64 */
662
663
664/*-----------------------------------------------------------------------
665 * TGCR1/TGCR2 - Timer Global Configuration Registers 17-4
666 */
667#define TGCR1_CAS2 0x80 /* Cascade Timer 1 and 2 */
668#define TGCR1_STP2 0x20 /* Stop timer 2 */
669#define TGCR1_RST2 0x10 /* Reset timer 2 */
670#define TGCR1_GM1 0x08 /* Gate Mode for Pin 1 */
671#define TGCR1_STP1 0x02 /* Stop timer 1 */
672#define TGCR1_RST1 0x01 /* Reset timer 1 */
673#define TGCR2_CAS4 0x80 /* Cascade Timer 3 and 4 */
674#define TGCR2_STP4 0x20 /* Stop timer 4 */
675#define TGCR2_RST4 0x10 /* Reset timer 4 */
676#define TGCR2_GM2 0x08 /* Gate Mode for Pin 2 */
677#define TGCR2_STP3 0x02 /* Stop timer 3 */
678#define TGCR2_RST3 0x01 /* Reset timer 3 */
679
680
681/*-----------------------------------------------------------------------
682 * TMR1-TMR4 - Timer Mode Registers 17-6
683 */
684#define TMRx_PS_MSK 0xff00 /* Prescaler Value */
685#define TMRx_CE_MSK 0x00c0 /* Capture Edge and Enable Interrupt*/
686#define TMRx_OM 0x0020 /* Output Mode */
687#define TMRx_ORI 0x0010 /* Output Reference Interrupt Enable*/
688#define TMRx_FRR 0x0008 /* Free Run/Restart */
689#define TMRx_ICLK_MSK 0x0006 /* Timer Input Clock Source mask */
690#define TMRx_GE 0x0001 /* Gate Enable */
691
692#define TMRx_CE_INTR_DIS 0x0000 /* Disable Interrupt on capture event*/
693#define TMRx_CE_RISING 0x0040 /* Capture on Rising TINx edge only */
694#define TMRx_CE_FALLING 0x0080 /* Capture on Falling TINx edge only */
695#define TMRx_CE_ANY 0x00c0 /* Capture on any TINx edge */
696
697#define TMRx_ICLK_IN_CAS 0x0000 /* Internally cascaded input */
698#define TMRx_ICLK_IN_GEN 0x0002 /* Internal General system clock*/
699#define TMRx_ICLK_IN_GEN_DIV16 0x0004 /* Internal General system clk div 16*/
700#define TMRx_ICLK_TIN_PIN 0x0006 /* TINx pin */
701
702
703/*-----------------------------------------------------------------------
704 * CMXFCR - CMX FCC Clock Route Register 15-12
705 */
706#define CMXFCR_FC1 0x40000000 /* FCC1 connection */
707#define CMXFCR_RF1CS_MSK 0x38000000 /* Receive FCC1 Clock Source Mask */
708#define CMXFCR_TF1CS_MSK 0x07000000 /* Transmit FCC1 Clock Source Mask */
709#define CMXFCR_FC2 0x00400000 /* FCC2 connection */
710#define CMXFCR_RF2CS_MSK 0x00380000 /* Receive FCC2 Clock Source Mask */
711#define CMXFCR_TF2CS_MSK 0x00070000 /* Transmit FCC2 Clock Source Mask */
712#define CMXFCR_FC3 0x00004000 /* FCC3 connection */
713#define CMXFCR_RF3CS_MSK 0x00003800 /* Receive FCC3 Clock Source Mask */
714#define CMXFCR_TF3CS_MSK 0x00000700 /* Transmit FCC3 Clock Source Mask */
715
716#define CMXFCR_RF1CS_BRG5 0x00000000 /* Receive FCC1 Clock Source is BRG5 */
717#define CMXFCR_RF1CS_BRG6 0x08000000 /* Receive FCC1 Clock Source is BRG6 */
718#define CMXFCR_RF1CS_BRG7 0x10000000 /* Receive FCC1 Clock Source is BRG7 */
719#define CMXFCR_RF1CS_BRG8 0x18000000 /* Receive FCC1 Clock Source is BRG8 */
720#define CMXFCR_RF1CS_CLK9 0x20000000 /* Receive FCC1 Clock Source is CLK9 */
721#define CMXFCR_RF1CS_CLK10 0x28000000 /* Receive FCC1 Clock Source is CLK10 */
722#define CMXFCR_RF1CS_CLK11 0x30000000 /* Receive FCC1 Clock Source is CLK11 */
723#define CMXFCR_RF1CS_CLK12 0x38000000 /* Receive FCC1 Clock Source is CLK12 */
724
725#define CMXFCR_TF1CS_BRG5 0x00000000 /* Transmit FCC1 Clock Source is BRG5 */
726#define CMXFCR_TF1CS_BRG6 0x01000000 /* Transmit FCC1 Clock Source is BRG6 */
727#define CMXFCR_TF1CS_BRG7 0x02000000 /* Transmit FCC1 Clock Source is BRG7 */
728#define CMXFCR_TF1CS_BRG8 0x03000000 /* Transmit FCC1 Clock Source is BRG8 */
729#define CMXFCR_TF1CS_CLK9 0x04000000 /* Transmit FCC1 Clock Source is CLK9 */
730#define CMXFCR_TF1CS_CLK10 0x05000000 /* Transmit FCC1 Clock Source is CLK10 */
731#define CMXFCR_TF1CS_CLK11 0x06000000 /* Transmit FCC1 Clock Source is CLK11 */
732#define CMXFCR_TF1CS_CLK12 0x07000000 /* Transmit FCC1 Clock Source is CLK12 */
733
734#define CMXFCR_RF2CS_BRG5 0x00000000 /* Receive FCC2 Clock Source is BRG5 */
735#define CMXFCR_RF2CS_BRG6 0x00080000 /* Receive FCC2 Clock Source is BRG6 */
736#define CMXFCR_RF2CS_BRG7 0x00100000 /* Receive FCC2 Clock Source is BRG7 */
737#define CMXFCR_RF2CS_BRG8 0x00180000 /* Receive FCC2 Clock Source is BRG8 */
738#define CMXFCR_RF2CS_CLK13 0x00200000 /* Receive FCC2 Clock Source is CLK13 */
739#define CMXFCR_RF2CS_CLK14 0x00280000 /* Receive FCC2 Clock Source is CLK14 */
740#define CMXFCR_RF2CS_CLK15 0x00300000 /* Receive FCC2 Clock Source is CLK15 */
741#define CMXFCR_RF2CS_CLK16 0x00380000 /* Receive FCC2 Clock Source is CLK16 */
742
743#define CMXFCR_TF2CS_BRG5 0x00000000 /* Transmit FCC2 Clock Source is BRG5 */
744#define CMXFCR_TF2CS_BRG6 0x00010000 /* Transmit FCC2 Clock Source is BRG6 */
745#define CMXFCR_TF2CS_BRG7 0x00020000 /* Transmit FCC2 Clock Source is BRG7 */
746#define CMXFCR_TF2CS_BRG8 0x00030000 /* Transmit FCC2 Clock Source is BRG8 */
747#define CMXFCR_TF2CS_CLK13 0x00040000 /* Transmit FCC2 Clock Source is CLK13 */
748#define CMXFCR_TF2CS_CLK14 0x00050000 /* Transmit FCC2 Clock Source is CLK14 */
749#define CMXFCR_TF2CS_CLK15 0x00060000 /* Transmit FCC2 Clock Source is CLK15 */
750#define CMXFCR_TF2CS_CLK16 0x00070000 /* Transmit FCC2 Clock Source is CLK16 */
751
752#define CMXFCR_RF3CS_BRG5 0x00000000 /* Receive FCC3 Clock Source is BRG5 */
753#define CMXFCR_RF3CS_BRG6 0x00000800 /* Receive FCC3 Clock Source is BRG6 */
754#define CMXFCR_RF3CS_BRG7 0x00001000 /* Receive FCC3 Clock Source is BRG7 */
755#define CMXFCR_RF3CS_BRG8 0x00001800 /* Receive FCC3 Clock Source is BRG8 */
756#define CMXFCR_RF3CS_CLK13 0x00002000 /* Receive FCC3 Clock Source is CLK13 */
757#define CMXFCR_RF3CS_CLK14 0x00002800 /* Receive FCC3 Clock Source is CLK14 */
758#define CMXFCR_RF3CS_CLK15 0x00003000 /* Receive FCC3 Clock Source is CLK15 */
759#define CMXFCR_RF3CS_CLK16 0x00003800 /* Receive FCC3 Clock Source is CLK16 */
760
761#define CMXFCR_TF3CS_BRG5 0x00000000 /* Transmit FCC3 Clock Source is BRG5 */
762#define CMXFCR_TF3CS_BRG6 0x00000100 /* Transmit FCC3 Clock Source is BRG6 */
763#define CMXFCR_TF3CS_BRG7 0x00000200 /* Transmit FCC3 Clock Source is BRG7 */
764#define CMXFCR_TF3CS_BRG8 0x00000300 /* Transmit FCC3 Clock Source is BRG8 */
765#define CMXFCR_TF3CS_CLK13 0x00000400 /* Transmit FCC3 Clock Source is CLK13 */
766#define CMXFCR_TF3CS_CLK14 0x00000500 /* Transmit FCC3 Clock Source is CLK14 */
767#define CMXFCR_TF3CS_CLK15 0x00000600 /* Transmit FCC3 Clock Source is CLK15 */
768#define CMXFCR_TF3CS_CLK16 0x00000700 /* Transmit FCC3 Clock Source is CLK16 */
769
770/*-----------------------------------------------------------------------
771 * CMXSCR - CMX SCC Clock Route Register 15-14
772 */
773#define CMXSCR_GR1 0x80000000 /* Grant Support of SCC1 */
774#define CMXSCR_SC1 0x40000000 /* SCC1 connection */
775#define CMXSCR_RS1CS_MSK 0x38000000 /* Receive SCC1 Clock Source Mask */
776#define CMXSCR_TS1CS_MSK 0x07000000 /* Transmit SCC1 Clock Source Mask */
777#define CMXSCR_GR2 0x00800000 /* Grant Support of SCC2 */
778#define CMXSCR_SC2 0x00400000 /* SCC2 connection */
779#define CMXSCR_RS2CS_MSK 0x00380000 /* Receive SCC2 Clock Source Mask */
780#define CMXSCR_TS2CS_MSK 0x00070000 /* Transmit SCC2 Clock Source Mask */
781#define CMXSCR_GR3 0x00008000 /* Grant Support of SCC3 */
782#define CMXSCR_SC3 0x00004000 /* SCC3 connection */
783#define CMXSCR_RS3CS_MSK 0x00003800 /* Receive SCC3 Clock Source Mask */
784#define CMXSCR_TS3CS_MSK 0x00000700 /* Transmit SCC3 Clock Source Mask */
785#define CMXSCR_GR4 0x00000080 /* Grant Support of SCC4 */
786#define CMXSCR_SC4 0x00000040 /* SCC4 connection */
787#define CMXSCR_RS4CS_MSK 0x00000038 /* Receive SCC4 Clock Source Mask */
788#define CMXSCR_TS4CS_MSK 0x00000007 /* Transmit SCC4 Clock Source Mask */
789
790#define CMXSCR_RS1CS_BRG1 0x00000000 /* SCC1 Rx Clock Source is BRG1 */
791#define CMXSCR_RS1CS_BRG2 0x08000000 /* SCC1 Rx Clock Source is BRG2 */
792#define CMXSCR_RS1CS_BRG3 0x10000000 /* SCC1 Rx Clock Source is BRG3 */
793#define CMXSCR_RS1CS_BRG4 0x18000000 /* SCC1 Rx Clock Source is BRG4 */
794#define CMXSCR_RS1CS_CLK11 0x20000000 /* SCC1 Rx Clock Source is CLK11 */
795#define CMXSCR_RS1CS_CLK12 0x28000000 /* SCC1 Rx Clock Source is CLK12 */
796#define CMXSCR_RS1CS_CLK3 0x30000000 /* SCC1 Rx Clock Source is CLK3 */
797#define CMXSCR_RS1CS_CLK4 0x38000000 /* SCC1 Rx Clock Source is CLK4 */
798
799#define CMXSCR_TS1CS_BRG1 0x00000000 /* SCC1 Tx Clock Source is BRG1 */
800#define CMXSCR_TS1CS_BRG2 0x01000000 /* SCC1 Tx Clock Source is BRG2 */
801#define CMXSCR_TS1CS_BRG3 0x02000000 /* SCC1 Tx Clock Source is BRG3 */
802#define CMXSCR_TS1CS_BRG4 0x03000000 /* SCC1 Tx Clock Source is BRG4 */
803#define CMXSCR_TS1CS_CLK11 0x04000000 /* SCC1 Tx Clock Source is CLK11 */
804#define CMXSCR_TS1CS_CLK12 0x05000000 /* SCC1 Tx Clock Source is CLK12 */
805#define CMXSCR_TS1CS_CLK3 0x06000000 /* SCC1 Tx Clock Source is CLK3 */
806#define CMXSCR_TS1CS_CLK4 0x07000000 /* SCC1 Tx Clock Source is CLK4 */
807
808#define CMXSCR_RS2CS_BRG1 0x00000000 /* SCC2 Rx Clock Source is BRG1 */
809#define CMXSCR_RS2CS_BRG2 0x00080000 /* SCC2 Rx Clock Source is BRG2 */
810#define CMXSCR_RS2CS_BRG3 0x00100000 /* SCC2 Rx Clock Source is BRG3 */
811#define CMXSCR_RS2CS_BRG4 0x00180000 /* SCC2 Rx Clock Source is BRG4 */
812#define CMXSCR_RS2CS_CLK11 0x00200000 /* SCC2 Rx Clock Source is CLK11 */
813#define CMXSCR_RS2CS_CLK12 0x00280000 /* SCC2 Rx Clock Source is CLK12 */
814#define CMXSCR_RS2CS_CLK3 0x00300000 /* SCC2 Rx Clock Source is CLK3 */
815#define CMXSCR_RS2CS_CLK4 0x00380000 /* SCC2 Rx Clock Source is CLK4 */
816
817#define CMXSCR_TS2CS_BRG1 0x00000000 /* SCC2 Tx Clock Source is BRG1 */
818#define CMXSCR_TS2CS_BRG2 0x00010000 /* SCC2 Tx Clock Source is BRG2 */
819#define CMXSCR_TS2CS_BRG3 0x00020000 /* SCC2 Tx Clock Source is BRG3 */
820#define CMXSCR_TS2CS_BRG4 0x00030000 /* SCC2 Tx Clock Source is BRG4 */
821#define CMXSCR_TS2CS_CLK11 0x00040000 /* SCC2 Tx Clock Source is CLK11 */
822#define CMXSCR_TS2CS_CLK12 0x00050000 /* SCC2 Tx Clock Source is CLK12 */
823#define CMXSCR_TS2CS_CLK3 0x00060000 /* SCC2 Tx Clock Source is CLK3 */
824#define CMXSCR_TS2CS_CLK4 0x00070000 /* SCC2 Tx Clock Source is CLK4 */
825
826#define CMXSCR_RS3CS_BRG1 0x00000000 /* SCC3 Rx Clock Source is BRG1 */
827#define CMXSCR_RS3CS_BRG2 0x00000800 /* SCC3 Rx Clock Source is BRG2 */
828#define CMXSCR_RS3CS_BRG3 0x00001000 /* SCC3 Rx Clock Source is BRG3 */
829#define CMXSCR_RS3CS_BRG4 0x00001800 /* SCC3 Rx Clock Source is BRG4 */
830#define CMXSCR_RS3CS_CLK5 0x00002000 /* SCC3 Rx Clock Source is CLK5 */
831#define CMXSCR_RS3CS_CLK6 0x00002800 /* SCC3 Rx Clock Source is CLK6 */
832#define CMXSCR_RS3CS_CLK7 0x00003000 /* SCC3 Rx Clock Source is CLK7 */
833#define CMXSCR_RS3CS_CLK8 0x00003800 /* SCC3 Rx Clock Source is CLK8 */
834
835#define CMXSCR_TS3CS_BRG1 0x00000000 /* SCC3 Tx Clock Source is BRG1 */
836#define CMXSCR_TS3CS_BRG2 0x00000100 /* SCC3 Tx Clock Source is BRG2 */
837#define CMXSCR_TS3CS_BRG3 0x00000200 /* SCC3 Tx Clock Source is BRG3 */
838#define CMXSCR_TS3CS_BRG4 0x00000300 /* SCC3 Tx Clock Source is BRG4 */
839#define CMXSCR_TS3CS_CLK5 0x00000400 /* SCC3 Tx Clock Source is CLK5 */
840#define CMXSCR_TS3CS_CLK6 0x00000500 /* SCC3 Tx Clock Source is CLK6 */
841#define CMXSCR_TS3CS_CLK7 0x00000600 /* SCC3 Tx Clock Source is CLK7 */
842#define CMXSCR_TS3CS_CLK8 0x00000700 /* SCC3 Tx Clock Source is CLK8 */
843
844#define CMXSCR_RS4CS_BRG1 0x00000000 /* SCC4 Rx Clock Source is BRG1 */
845#define CMXSCR_RS4CS_BRG2 0x00000008 /* SCC4 Rx Clock Source is BRG2 */
846#define CMXSCR_RS4CS_BRG3 0x00000010 /* SCC4 Rx Clock Source is BRG3 */
847#define CMXSCR_RS4CS_BRG4 0x00000018 /* SCC4 Rx Clock Source is BRG4 */
848#define CMXSCR_RS4CS_CLK5 0x00000020 /* SCC4 Rx Clock Source is CLK5 */
849#define CMXSCR_RS4CS_CLK6 0x00000028 /* SCC4 Rx Clock Source is CLK6 */
850#define CMXSCR_RS4CS_CLK7 0x00000030 /* SCC4 Rx Clock Source is CLK7 */
851#define CMXSCR_RS4CS_CLK8 0x00000038 /* SCC4 Rx Clock Source is CLK8 */
852
853#define CMXSCR_TS4CS_BRG1 0x00000000 /* SCC4 Tx Clock Source is BRG1 */
854#define CMXSCR_TS4CS_BRG2 0x00000001 /* SCC4 Tx Clock Source is BRG2 */
855#define CMXSCR_TS4CS_BRG3 0x00000002 /* SCC4 Tx Clock Source is BRG3 */
856#define CMXSCR_TS4CS_BRG4 0x00000003 /* SCC4 Tx Clock Source is BRG4 */
857#define CMXSCR_TS4CS_CLK5 0x00000004 /* SCC4 Tx Clock Source is CLK5 */
858#define CMXSCR_TS4CS_CLK6 0x00000005 /* SCC4 Tx Clock Source is CLK6 */
859#define CMXSCR_TS4CS_CLK7 0x00000006 /* SCC4 Tx Clock Source is CLK7 */
860#define CMXSCR_TS4CS_CLK8 0x00000007 /* SCC4 Tx Clock Source is CLK8 */
861
862/*-----------------------------------------------------------------------
863 * CMXSMR - CMX SMC Clock Route Register 15-17
864 */
865#define CMXSMR_SMC1 0x80 /* SMC1 Connection */
866#define CMXSMR_SMC1CS_MSK 0x30 /* SMC1 Clock Source */
867#define CMXSMR_SMC2 0x08 /* SMC2 Connection */
868#define CMXSMR_SMC2CS_MSK 0x03 /* SMC2 Clock Source */
869
870#define CMXSMR_SMC1CS_BRG1 0x00 /* SMC1 Tx and Rx Clocks are BRG1 */
871#define CMXSMR_SMC1CS_BRG7 0x10 /* SMC1 Tx and Rx Clocks are BRG7 */
872#define CMXSMR_SMC1CS_CLK7 0x20 /* SMC1 Tx and Rx Clocks are CLK7 */
873#define CMXSMR_SMC1CS_CLK9 0x30 /* SMC1 Tx and Rx Clocks are CLK9 */
874
875#define CMXSMR_SMC2CS_BRG2 0x00 /* SMC2 Tx and Rx Clocks are BRG2 */
876#define CMXSMR_SMC2CS_BRG8 0x01 /* SMC2 Tx and Rx Clocks are BRG8 */
877#define CMXSMR_SMC2CS_CLK19 0x02 /* SMC2 Tx and Rx Clocks are CLK19 */
878#define CMXSMR_SMC2CS_CLK20 0x03 /* SMC2 Tx and Rx Clocks are CLK20 */
879
880/*-----------------------------------------------------------------------
881 * miscellaneous
882 */
883
884#define UPMA 1
885#define UPMB 2
886#define UPMC 3
887
888#if !defined(__ASSEMBLY__) && defined(CONFIG_WATCHDOG)
889extern __inline__ void
890reset_8260_watchdog(volatile immap_t *immr)
891{
892 immr->im_siu_conf.sc_swsr = 0x556c;
893 immr->im_siu_conf.sc_swsr = 0xaa39;
894}
895#endif /* !__ASSEMBLY && CONFIG_WATCHDOG */
896
897#endif /* __MPC8260_H__ */