blob: c6d20f546809a6b7b6ea968c1da05589a24ea24b [file] [log] [blame]
Peng Fan9ef89ea2021-08-07 16:00:35 +08001// SPDX-License-Identifier: GPL-2.0+
2/*
Peng Fanfdfa2142021-08-07 16:01:04 +08003 * Copyright 2020-2021 NXP
Peng Fan9ef89ea2021-08-07 16:00:35 +08004 */
Peng Fanfdfa2142021-08-07 16:01:04 +08005
6#include <common.h>
7#include <asm/io.h>
8#include <asm/arch/imx-regs.h>
9#include <asm/arch/iomux.h>
10
11static void *base = (void *)IOMUXC_BASE_ADDR;
12static void *base_mports = (void *)(0x280A1000);
13
14/*
15 * configures a single pad in the iomuxer
16 */
17void imx8ulp_iomux_setup_pad(iomux_cfg_t pad)
18{
19 u32 mux_ctrl_ofs = (pad & MUX_CTRL_OFS_MASK) >> MUX_CTRL_OFS_SHIFT;
20 u32 mux_mode = (pad & MUX_MODE_MASK) >> MUX_MODE_SHIFT;
21 u32 sel_input_ofs =
22 (pad & MUX_SEL_INPUT_OFS_MASK) >> MUX_SEL_INPUT_OFS_SHIFT;
23 u32 sel_input =
24 (pad & MUX_SEL_INPUT_MASK) >> MUX_SEL_INPUT_SHIFT;
25 u32 pad_ctrl_ofs = mux_ctrl_ofs;
26 u32 pad_ctrl = (pad & MUX_PAD_CTRL_MASK) >> MUX_PAD_CTRL_SHIFT;
27
28 if (mux_mode & IOMUX_CONFIG_MPORTS) {
29 mux_mode &= ~IOMUX_CONFIG_MPORTS;
30 base = base_mports;
31 } else {
32 base = (void *)IOMUXC_BASE_ADDR;
33 }
34
35 __raw_writel(((mux_mode << IOMUXC_PCR_MUX_ALT_SHIFT) &
36 IOMUXC_PCR_MUX_ALT_MASK), base + mux_ctrl_ofs);
37
38 if (sel_input_ofs)
39 __raw_writel((sel_input << IOMUXC_PSMI_IMUX_ALT_SHIFT), base + sel_input_ofs);
40
41 if (!(pad_ctrl & NO_PAD_CTRL))
42 __raw_writel(((mux_mode << IOMUXC_PCR_MUX_ALT_SHIFT) &
43 IOMUXC_PCR_MUX_ALT_MASK) |
44 (pad_ctrl & (~IOMUXC_PCR_MUX_ALT_MASK)),
45 base + pad_ctrl_ofs);
46}
47
48/* configures a list of pads within declared with IOMUX_PADS macro */
49void imx8ulp_iomux_setup_multiple_pads(iomux_cfg_t const *pad_list, u32 count)
50{
51 iomux_cfg_t const *p = pad_list;
52 int i;
53
54 for (i = 0; i < count; i++) {
55 imx8ulp_iomux_setup_pad(*p);
56 p++;
57 }
58}