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Tom Rini83d290c2018-05-06 17:58:06 -04001/* SPDX-License-Identifier: GPL-2.0+ */
Stelian Popd99a8ff2008-05-08 20:52:22 +02002/*
3 * (C) Copyright 2007-2008
Stelian Popc9e798d2011-11-01 00:00:39 +01004 * Stelian Pop <stelian@popies.net>
Stelian Popd99a8ff2008-05-08 20:52:22 +02005 * Lead Tech Design <www.leadtechdesign.com>
6 *
7 * Configuation settings for the AT91SAM9261EK board.
Stelian Popd99a8ff2008-05-08 20:52:22 +02008 */
9
10#ifndef __CONFIG_H
11#define __CONFIG_H
12
13/* ARM asynchronous clock */
Xu, Hongf7aea462011-07-31 22:49:00 +000014#define CONFIG_SYS_AT91_SLOW_CLOCK 32768 /* slow clock xtal */
Achim Ehrlich7c966a82010-02-24 10:29:16 +010015#define CONFIG_SYS_AT91_MAIN_CLOCK 18432000 /* 18.432 MHz crystal */
Stelian Popd99a8ff2008-05-08 20:52:22 +020016
Xu, Hongf7aea462011-07-31 22:49:00 +000017#ifdef CONFIG_AT91SAM9G10
18#define CONFIG_AT91SAM9G10EK /* It's an Atmel AT91SAM9G10 EK*/
Sedji Gaouaou5ccc2d92009-06-25 17:04:15 +020019#else
Xu, Hongf7aea462011-07-31 22:49:00 +000020#define CONFIG_AT91SAM9261EK /* It's an Atmel AT91SAM9261 EK*/
Sedji Gaouaou5ccc2d92009-06-25 17:04:15 +020021#endif
Xu, Hongf7aea462011-07-31 22:49:00 +000022
23#include <asm/hardware.h>
24
Xu, Hongf7aea462011-07-31 22:49:00 +000025#define CONFIG_CMDLINE_TAG /* enable passing of ATAGs */
26#define CONFIG_SETUP_MEMORY_TAGS
27#define CONFIG_INITRD_TAG
Stelian Popd99a8ff2008-05-08 20:52:22 +020028
29#define CONFIG_SKIP_LOWLEVEL_INIT
Stelian Popd99a8ff2008-05-08 20:52:22 +020030
Xu, Hongf7aea462011-07-31 22:49:00 +000031#define CONFIG_ATMEL_LEGACY
Xu, Hongf7aea462011-07-31 22:49:00 +000032
Stelian Popd99a8ff2008-05-08 20:52:22 +020033/*
34 * Hardware drivers
35 */
Xu, Hongf7aea462011-07-31 22:49:00 +000036
Stelian Pop820f2a92008-05-08 14:52:30 +020037/* LCD */
Stelian Pop820f2a92008-05-08 14:52:30 +020038#define LCD_BPP LCD_COLOR8
Xu, Hongf7aea462011-07-31 22:49:00 +000039#define CONFIG_LCD_LOGO
Stelian Pop820f2a92008-05-08 14:52:30 +020040#undef LCD_TEST_PATTERN
Xu, Hongf7aea462011-07-31 22:49:00 +000041#define CONFIG_LCD_INFO
42#define CONFIG_LCD_INFO_BELOW_LOGO
Xu, Hongf7aea462011-07-31 22:49:00 +000043#define CONFIG_ATMEL_LCD
Sedji Gaouaou5ccc2d92009-06-25 17:04:15 +020044#ifdef CONFIG_AT91SAM9261EK
Xu, Hongf7aea462011-07-31 22:49:00 +000045#define CONFIG_ATMEL_LCD_BGR555
Sedji Gaouaou5ccc2d92009-06-25 17:04:15 +020046#endif
Xu, Hongf7aea462011-07-31 22:49:00 +000047
Stelian Popd99a8ff2008-05-08 20:52:22 +020048/*
49 * BOOTP options
50 */
Xu, Hongf7aea462011-07-31 22:49:00 +000051#define CONFIG_BOOTP_BOOTFILESIZE
Stelian Popd99a8ff2008-05-08 20:52:22 +020052
Stelian Popd99a8ff2008-05-08 20:52:22 +020053/* SDRAM */
Xu, Hongf7aea462011-07-31 22:49:00 +000054#define CONFIG_SYS_SDRAM_BASE 0x20000000
55#define CONFIG_SYS_SDRAM_SIZE 0x04000000
56#define CONFIG_SYS_INIT_SP_ADDR \
Wenyou.Yang@microchip.com324873e2017-07-21 13:28:40 +080057 (ATMEL_BASE_SRAM + 16 * 1024 - GENERATED_GBL_DATA_SIZE)
Stelian Popd99a8ff2008-05-08 20:52:22 +020058
59/* NAND flash */
Jean-Christophe PLAGNIOL-VILLARD74c076d2009-03-22 10:22:34 +010060#ifdef CONFIG_CMD_NAND
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020061#define CONFIG_SYS_MAX_NAND_DEVICE 1
62#define CONFIG_SYS_NAND_BASE 0x40000000
Xu, Hongf7aea462011-07-31 22:49:00 +000063#define CONFIG_SYS_NAND_DBW_8
Jean-Christophe PLAGNIOL-VILLARD74c076d2009-03-22 10:22:34 +010064/* our ALE is AD22 */
65#define CONFIG_SYS_NAND_MASK_ALE (1 << 22)
66/* our CLE is AD21 */
67#define CONFIG_SYS_NAND_MASK_CLE (1 << 21)
68#define CONFIG_SYS_NAND_ENABLE_PIN AT91_PIN_PC14
69#define CONFIG_SYS_NAND_READY_PIN AT91_PIN_PC15
Wolfgang Denk2eb99ca2009-07-18 21:52:24 +020070
Jean-Christophe PLAGNIOL-VILLARD74c076d2009-03-22 10:22:34 +010071#endif
Stelian Popd99a8ff2008-05-08 20:52:22 +020072
Stelian Popd99a8ff2008-05-08 20:52:22 +020073/* Ethernet */
Xu, Hongf7aea462011-07-31 22:49:00 +000074#define CONFIG_DRIVER_DM9000
Stelian Popd99a8ff2008-05-08 20:52:22 +020075#define CONFIG_DM9000_BASE 0x30000000
76#define DM9000_IO CONFIG_DM9000_BASE
77#define DM9000_DATA (CONFIG_DM9000_BASE + 4)
Xu, Hongf7aea462011-07-31 22:49:00 +000078#define CONFIG_DM9000_USE_16BIT
79#define CONFIG_DM9000_NO_SROM
Stelian Popd99a8ff2008-05-08 20:52:22 +020080#define CONFIG_NET_RETRY_COUNT 20
Xu, Hongf7aea462011-07-31 22:49:00 +000081#define CONFIG_RESET_PHY_R
Stelian Popd99a8ff2008-05-08 20:52:22 +020082
83/* USB */
Jean-Christophe PLAGNIOL-VILLARD2b7178a2009-03-27 23:26:44 +010084#define CONFIG_USB_ATMEL
Bo Shendcd2f1a2013-10-21 16:14:00 +080085#define CONFIG_USB_ATMEL_CLK_SEL_PLLB
Xu, Hongf7aea462011-07-31 22:49:00 +000086#define CONFIG_USB_OHCI_NEW
Xu, Hongf7aea462011-07-31 22:49:00 +000087#define CONFIG_SYS_USB_OHCI_CPU_INIT
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020088#define CONFIG_SYS_USB_OHCI_REGS_BASE 0x00500000 /* AT91SAM9261_UHP_BASE */
Sedji Gaouaou5ccc2d92009-06-25 17:04:15 +020089#ifdef CONFIG_AT91SAM9G10EK
90#define CONFIG_SYS_USB_OHCI_SLOT_NAME "at91sam9g10"
91#else
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020092#define CONFIG_SYS_USB_OHCI_SLOT_NAME "at91sam9261"
Sedji Gaouaou5ccc2d92009-06-25 17:04:15 +020093#endif
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020094#define CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS 2
Stelian Popd99a8ff2008-05-08 20:52:22 +020095
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020096#define CONFIG_SYS_LOAD_ADDR 0x22000000 /* load address */
Stelian Popd99a8ff2008-05-08 20:52:22 +020097
Xu, Hongf7aea462011-07-31 22:49:00 +000098#define CONFIG_SYS_MEMTEST_START CONFIG_SYS_SDRAM_BASE
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020099#define CONFIG_SYS_MEMTEST_END 0x23e00000
Stelian Popd99a8ff2008-05-08 20:52:22 +0200100
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200101#ifdef CONFIG_SYS_USE_DATAFLASH_CS0
Stelian Popd99a8ff2008-05-08 20:52:22 +0200102
103/* bootstrap + u-boot + env + linux in dataflash on CS0 */
Wenyou.Yang@microchip.com324873e2017-07-21 13:28:40 +0800104#define CONFIG_BOOTCOMMAND "sf probe 0; " \
105 "sf read 0x22000000 0x84000 0x294000; " \
106 "bootm 0x22000000"
Stelian Popd99a8ff2008-05-08 20:52:22 +0200107
Nicolas Ferre89a7a872008-12-06 13:11:14 +0100108#elif CONFIG_SYS_USE_DATAFLASH_CS3
109
110/* bootstrap + u-boot + env + linux in dataflash on CS3 */
Wenyou.Yang@microchip.com324873e2017-07-21 13:28:40 +0800111#define CONFIG_BOOTCOMMAND "sf probe 0:3; " \
112 "sf read 0x22000000 0x84000 0x294000; " \
113 "bootm 0x22000000"
Nicolas Ferre89a7a872008-12-06 13:11:14 +0100114
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200115#else /* CONFIG_SYS_USE_NANDFLASH */
Stelian Popd99a8ff2008-05-08 20:52:22 +0200116
117/* bootstrap + u-boot + env + linux in nandflash */
Bo Shen0c58cfa2013-02-20 00:16:25 +0000118#define CONFIG_BOOTCOMMAND "nand read 0x22000000 0x200000 0x300000; bootm"
Stelian Popd99a8ff2008-05-08 20:52:22 +0200119#endif
120
Stelian Popd99a8ff2008-05-08 20:52:22 +0200121/*
122 * Size of malloc() pool
123 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200124#define CONFIG_SYS_MALLOC_LEN ROUND(3 * CONFIG_ENV_SIZE + 128*1024, 0x1000)
Stelian Popd99a8ff2008-05-08 20:52:22 +0200125
Stelian Popd99a8ff2008-05-08 20:52:22 +0200126#endif