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Tom Rini83d290c2018-05-06 17:58:06 -04001/* SPDX-License-Identifier: GPL-2.0+ */
York Sunf749db32014-06-23 15:15:56 -07002/*
Priyanka Jain89a168f2017-04-28 10:41:35 +05303 * Copyright 2017 NXP
York Sunf749db32014-06-23 15:15:56 -07004 * Copyright (C) 2014 Freescale Semiconductor
York Sunf749db32014-06-23 15:15:56 -07005 */
6
7#ifndef __LS2_COMMON_H
8#define __LS2_COMMON_H
9
York Sunf749db32014-06-23 15:15:56 -070010#define CONFIG_REMAKE_ELF
York Sunf749db32014-06-23 15:15:56 -070011#define CONFIG_GICV3
12
Bharat Bhushan08c51302017-03-22 12:06:25 +053013#include <asm/arch/stream_id_lsch3.h>
Mingkai Hu9f3183d2015-10-26 19:47:50 +080014#include <asm/arch/config.h>
Minghuan Lian31d34c62015-03-20 19:28:16 -070015
Mingkai Hu9f3183d2015-10-26 19:47:50 +080016/* Link Definitions */
Rajesh Bhagat9570df02018-12-27 04:37:59 +000017#ifdef CONFIG_TFABOOT
18#define CONFIG_SYS_INIT_SP_ADDR CONFIG_SYS_TEXT_BASE
19#else
Mingkai Hu9f3183d2015-10-26 19:47:50 +080020#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_FSL_OCRAM_BASE + 0xfff0)
Rajesh Bhagat9570df02018-12-27 04:37:59 +000021#endif
Mingkai Hu9f3183d2015-10-26 19:47:50 +080022
Bhupesh Sharma422cb082015-03-19 09:20:43 -070023/* We need architecture specific misc initializations */
Bhupesh Sharma422cb082015-03-19 09:20:43 -070024
York Sunf749db32014-06-23 15:15:56 -070025/* Link Definitions */
York Sunf749db32014-06-23 15:15:56 -070026
York Sunf749db32014-06-23 15:15:56 -070027#define CONFIG_SKIP_LOWLEVEL_INIT
York Sunf749db32014-06-23 15:15:56 -070028
York Sunf749db32014-06-23 15:15:56 -070029#ifndef CONFIG_SYS_FSL_DDR4
York Sunf749db32014-06-23 15:15:56 -070030#define CONFIG_SYS_DDR_RAW_TIMING
31#endif
York Sunf749db32014-06-23 15:15:56 -070032
33#define CONFIG_SYS_FSL_DDR_INTLV_256B /* force 256 byte interleaving */
34
Mingkai Hu9f3183d2015-10-26 19:47:50 +080035#define CONFIG_VERY_BIG_RAM
York Sunf749db32014-06-23 15:15:56 -070036#define CONFIG_SYS_DDR_SDRAM_BASE 0x80000000UL
37#define CONFIG_SYS_FSL_DDR_SDRAM_BASE_PHY 0
38#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE
39#define CONFIG_SYS_DDR_BLOCK2_BASE 0x8080000000ULL
York Sund9c68b12014-08-13 10:21:05 -070040#define CONFIG_SYS_FSL_DDR_MAIN_NUM_CTRLS 2
41
York Sun8bfa3012014-09-08 12:20:01 -070042/*
43 * SMP Definitinos
44 */
45#define CPU_RELEASE_ADDR secondary_boot_func
46
York Sund9c68b12014-08-13 10:21:05 -070047#define CONFIG_SYS_FSL_OTHER_DDR_NUM_CTRLS
Prabhakar Kushwaha44937212015-11-09 16:42:07 +053048#ifdef CONFIG_SYS_FSL_HAS_DP_DDR
York Sund9c68b12014-08-13 10:21:05 -070049#define CONFIG_SYS_DP_DDR_BASE 0x6000000000ULL
50/*
51 * DDR controller use 0 as the base address for binding.
52 * It is mapped to CONFIG_SYS_DP_DDR_BASE for core to access.
53 */
54#define CONFIG_SYS_DP_DDR_BASE_PHY 0
55#define CONFIG_DP_DDR_CTRL 2
56#define CONFIG_DP_DDR_NUM_CTRLS 1
Prabhakar Kushwaha44937212015-11-09 16:42:07 +053057#endif
York Sunf749db32014-06-23 15:15:56 -070058
59/* Generic Timer Definitions */
York Sun207774b2015-03-20 19:28:08 -070060/*
61 * This is not an accurate number. It is used in start.S. The frequency
62 * will be udpated later when get_bus_freq(0) is available.
63 */
64#define COUNTER_FREQUENCY 25000000 /* 25MHz */
York Sunf749db32014-06-23 15:15:56 -070065
66/* Size of malloc() pool */
Prabhakar Kushwahaaa66acb2015-03-19 09:20:47 -070067#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + 2048 * 1024)
York Sunf749db32014-06-23 15:15:56 -070068
69/* I2C */
Chuanhua Han654e4e72019-07-22 16:36:42 +080070#ifndef CONFIG_DM_I2C
York Sunf749db32014-06-23 15:15:56 -070071#define CONFIG_SYS_I2C
Chuanhua Han654e4e72019-07-22 16:36:42 +080072#endif
York Sunf749db32014-06-23 15:15:56 -070073
74/* Serial Port */
York Sunf749db32014-06-23 15:15:56 -070075#define CONFIG_SYS_NS16550_SERIAL
76#define CONFIG_SYS_NS16550_REG_SIZE 1
Hou Zhiqiang35642082017-01-10 16:44:16 +080077#define CONFIG_SYS_NS16550_CLK (get_serial_clock())
York Sunf749db32014-06-23 15:15:56 -070078
York Sunf749db32014-06-23 15:15:56 -070079#define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 }
80
81/* IFC */
82#define CONFIG_FSL_IFC
Prabhakar Kushwahaf3f8c562015-03-20 19:28:06 -070083
York Sunf749db32014-06-23 15:15:56 -070084/*
York Sun7288c2c2015-03-20 19:28:23 -070085 * During booting, IFC is mapped at the region of 0x30000000.
86 * But this region is limited to 256MB. To accommodate NOR, promjet
87 * and FPGA. This region is divided as below:
88 * 0x30000000 - 0x37ffffff : 128MB : NOR flash
89 * 0x38000000 - 0x3BFFFFFF : 64MB : Promjet
90 * 0x3C000000 - 0x40000000 : 64MB : FPGA etc
91 *
92 * To accommodate bigger NOR flash and other devices, we will map IFC
93 * chip selects to as below:
94 * 0x5_1000_0000..0x5_1fff_ffff Memory Hole
95 * 0x5_2000_0000..0x5_3fff_ffff IFC CSx (FPGA, NAND and others 512MB)
96 * 0x5_4000_0000..0x5_7fff_ffff ASIC or others 1GB
97 * 0x5_8000_0000..0x5_bfff_ffff IFC CS0 1GB (NOR/Promjet)
98 * 0x5_C000_0000..0x5_ffff_ffff IFC CS1 1GB (NOR/Promjet)
99 *
100 * For e.g. NOR flash at CS0 will be mapped to 0x580000000 after relocation.
York Sunf749db32014-06-23 15:15:56 -0700101 * CONFIG_SYS_FLASH_BASE has the final address (core view)
102 * CONFIG_SYS_FLASH_BASE_PHYS has the final address (IFC view)
103 * CONFIG_SYS_FLASH_BASE_PHYS_EARLY has the temporary IFC address
104 * CONFIG_SYS_TEXT_BASE is linked to 0x30000000 for booting
105 */
York Sun7288c2c2015-03-20 19:28:23 -0700106
York Sunf749db32014-06-23 15:15:56 -0700107#define CONFIG_SYS_FLASH_BASE 0x580000000ULL
108#define CONFIG_SYS_FLASH_BASE_PHYS 0x80000000
109#define CONFIG_SYS_FLASH_BASE_PHYS_EARLY 0x00000000
110
York Sun7288c2c2015-03-20 19:28:23 -0700111#define CONFIG_SYS_FLASH1_BASE_PHYS 0xC0000000
112#define CONFIG_SYS_FLASH1_BASE_PHYS_EARLY 0x8000000
113
York Sun7288c2c2015-03-20 19:28:23 -0700114#ifndef __ASSEMBLY__
115unsigned long long get_qixis_addr(void);
116#endif
117#define QIXIS_BASE get_qixis_addr()
118#define QIXIS_BASE_PHYS 0x20000000
119#define QIXIS_BASE_PHYS_EARLY 0xC000000
Yangbo Lu8b064602015-03-20 19:28:31 -0700120#define QIXIS_STAT_PRES1 0xb
121#define QIXIS_SDID_MASK 0x07
122#define QIXIS_ESDHC_NO_ADAPTER 0x7
York Sun7288c2c2015-03-20 19:28:23 -0700123
124#define CONFIG_SYS_NAND_BASE 0x530000000ULL
125#define CONFIG_SYS_NAND_BASE_PHYS 0x30000000
Prabhakar Kushwahae211c122014-07-16 09:21:12 +0530126
York Sunf749db32014-06-23 15:15:56 -0700127/* MC firmware */
York Sunf749db32014-06-23 15:15:56 -0700128/* TODO Actual DPL max length needs to be confirmed with the MC FW team */
J. German Rivera125e2bc2015-03-20 19:28:18 -0700129#define CONFIG_SYS_LS_MC_DPC_MAX_LENGTH 0x20000
130#define CONFIG_SYS_LS_MC_DRAM_DPC_OFFSET 0x00F00000
131#define CONFIG_SYS_LS_MC_DPL_MAX_LENGTH 0x20000
132#define CONFIG_SYS_LS_MC_DRAM_DPL_OFFSET 0x00F20000
York Sun3c1d2182016-04-04 11:41:26 -0700133/* For LS2085A */
J. German Riverac1000c12015-07-02 11:28:58 +0530134#define CONFIG_SYS_LS_MC_AIOP_IMG_MAX_LENGTH 0x200000
135#define CONFIG_SYS_LS_MC_DRAM_AIOP_IMG_OFFSET 0x07000000
York Sunf749db32014-06-23 15:15:56 -0700136
Bogdan Purcareata33a89912017-05-24 16:40:21 +0000137/* Define phy_reset function to boot the MC based on mcinitcmd.
138 * This happens late enough to properly fixup u-boot env MAC addresses.
139 */
140#define CONFIG_RESET_PHY_R
141
Prabhakar Kushwaha5c055082015-06-02 10:55:52 +0530142/*
143 * Carve out a DDR region which will not be used by u-boot/Linux
144 *
145 * It will be used by MC and Debug Server. The MC region must be
146 * 512MB aligned, so the min size to hide is 512MB.
147 */
York Sunb63a9502016-08-03 12:33:00 -0700148#ifdef CONFIG_FSL_MC_ENET
Meenakshi Aggarwal43ad41e2019-02-27 14:41:02 +0530149#define CONFIG_SYS_LS_MC_DRAM_BLOCK_MIN_SIZE (128UL * 1024 * 1024)
York Sunf749db32014-06-23 15:15:56 -0700150#endif
151
152/* Command line configuration */
York Sunf749db32014-06-23 15:15:56 -0700153
154/* Miscellaneous configurable options */
155#define CONFIG_SYS_LOAD_ADDR (CONFIG_SYS_DDR_SDRAM_BASE + 0x10000000)
156
157/* Physical Memory Map */
158/* fixme: these need to be checked against the board */
159#define CONFIG_CHIP_SELECTS_PER_CTRL 4
York Sunf749db32014-06-23 15:15:56 -0700160
York Sunf749db32014-06-23 15:15:56 -0700161#define CONFIG_HWCONFIG
162#define HWCONFIG_BUFFER_SIZE 128
163
Alison Wang1d3a76f2015-11-13 16:49:06 +0800164/* Allow to overwrite serial and ethaddr */
165#define CONFIG_ENV_OVERWRITE
166
York Sunf749db32014-06-23 15:15:56 -0700167/* Initial environment variables */
168#define CONFIG_EXTRA_ENV_SETTINGS \
169 "hwconfig=fsl_ddr:bank_intlv=auto\0" \
170 "loadaddr=0x80100000\0" \
171 "kernel_addr=0x100000\0" \
172 "ramdisk_addr=0x800000\0" \
173 "ramdisk_size=0x2000000\0" \
Prabhakar Kushwahaf3f8c562015-03-20 19:28:06 -0700174 "fdt_high=0xa0000000\0" \
York Sunf749db32014-06-23 15:15:56 -0700175 "initrd_high=0xffffffffffffffff\0" \
Santan Kumarf5bf23d2017-04-28 12:47:24 +0530176 "kernel_start=0x581000000\0" \
Stuart Yoder052ddd52015-01-06 13:18:57 -0800177 "kernel_load=0xa0000000\0" \
Prabhakar Kushwaha97421bd2015-07-01 16:28:22 +0530178 "kernel_size=0x2800000\0" \
Prabhakar Kushwaha16ed8562016-02-03 17:03:51 +0530179 "console=ttyAMA0,38400n8\0" \
Santan Kumarf5bf23d2017-04-28 12:47:24 +0530180 "mcinitcmd=fsl_mc start mc 0x580a00000" \
181 " 0x580e00000 \0"
York Sunf749db32014-06-23 15:15:56 -0700182
Rajesh Bhagat9570df02018-12-27 04:37:59 +0000183#ifndef CONFIG_TFABOOT
Santan Kumar1f55a932017-05-05 15:42:29 +0530184#ifdef CONFIG_SD_BOOT
185#define CONFIG_BOOTCOMMAND "mmc read 0x80200000 0x6800 0x800;"\
186 " fsl_mc apply dpl 0x80200000 &&" \
187 " mmc read $kernel_load $kernel_start" \
188 " $kernel_size && bootm $kernel_load"
189#else
Santan Kumarf5bf23d2017-04-28 12:47:24 +0530190#define CONFIG_BOOTCOMMAND "fsl_mc apply dpl 0x580d00000 &&" \
Prabhakar Kushwaha9f3e1b82016-02-03 17:04:07 +0530191 " cp.b $kernel_start $kernel_load" \
192 " $kernel_size && bootm $kernel_load"
Santan Kumar1f55a932017-05-05 15:42:29 +0530193#endif
Rajesh Bhagat9570df02018-12-27 04:37:59 +0000194#endif
York Sunf749db32014-06-23 15:15:56 -0700195
York Sunf749db32014-06-23 15:15:56 -0700196/* Monitor Command Prompt */
197#define CONFIG_SYS_CBSIZE 512 /* Console I/O Buffer Size */
York Sunf749db32014-06-23 15:15:56 -0700198#define CONFIG_SYS_MAXARGS 64 /* max command args */
199
Scott Woodb2d5ac52015-03-24 13:25:02 -0700200#define CONFIG_SPL_BSS_START_ADDR 0x80100000
201#define CONFIG_SPL_BSS_MAX_SIZE 0x00100000
Scott Woodb2d5ac52015-03-24 13:25:02 -0700202#define CONFIG_SPL_MAX_SIZE 0x16000
Scott Woodb2d5ac52015-03-24 13:25:02 -0700203#define CONFIG_SPL_STACK (CONFIG_SYS_FSL_OCRAM_BASE + 0x9ff0)
Jagdish Gediya4b5892c2018-08-23 22:53:33 +0530204#define CONFIG_SPL_TARGET "u-boot-with-spl.bin"
Scott Woodb2d5ac52015-03-24 13:25:02 -0700205
Santan Kumarfaed6bd2017-05-05 15:42:28 +0530206#ifdef CONFIG_NAND_BOOT
Scott Woodb2d5ac52015-03-24 13:25:02 -0700207#define CONFIG_SYS_NAND_U_BOOT_DST 0x80400000
208#define CONFIG_SYS_NAND_U_BOOT_START CONFIG_SYS_NAND_U_BOOT_DST
Santan Kumarfaed6bd2017-05-05 15:42:28 +0530209#endif
Scott Woodb2d5ac52015-03-24 13:25:02 -0700210#define CONFIG_SYS_SPL_MALLOC_SIZE 0x00100000
211#define CONFIG_SYS_SPL_MALLOC_START 0x80200000
York Sun63143a52017-12-18 08:24:55 -0800212#define CONFIG_SYS_MONITOR_LEN (1024 * 1024)
Scott Woodb2d5ac52015-03-24 13:25:02 -0700213
Bhupesh Sharma34cc7542015-05-28 14:54:02 +0530214#define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */
215
Simon Glass457e51c2017-05-17 08:23:10 -0600216#include <asm/arch/soc.h>
217
York Sunf749db32014-06-23 15:15:56 -0700218#endif /* __LS2_COMMON_H */