blob: b37fc2de7fb8184902037a074a8aa01b6aa28edd [file] [log] [blame]
Sekhar Nori03c396b2019-08-01 19:12:57 +05301// SPDX-License-Identifier: GPL-2.0+
2/*
3 * Copyright (C) 2018 Texas Instruments, Inc
4 */
5
6#include <common.h>
7#include <dm.h>
8#include <pci.h>
9#include <generic-phy.h>
10#include <power-domain.h>
11#include <regmap.h>
12#include <syscon.h>
13#include <asm/io.h>
14#include <asm-generic/gpio.h>
15
16DECLARE_GLOBAL_DATA_PTR;
17
18#define PCIE_VENDORID_MASK GENMASK(15, 0)
19#define PCIE_DEVICEID_SHIFT 16
20
21/* PCI DBICS registers */
22#define PCIE_CONFIG_BAR0 0x10
23#define PCIE_LINK_STATUS_REG 0x80
24#define PCIE_LINK_STATUS_SPEED_OFF 16
25#define PCIE_LINK_STATUS_SPEED_MASK (0xf << PCIE_LINK_STATUS_SPEED_OFF)
26#define PCIE_LINK_STATUS_WIDTH_OFF 20
27#define PCIE_LINK_STATUS_WIDTH_MASK (0xf << PCIE_LINK_STATUS_WIDTH_OFF)
28
29#define PCIE_LINK_CAPABILITY 0x7c
30#define PCIE_LINK_CTL_2 0xa0
31#define TARGET_LINK_SPEED_MASK 0xf
32#define LINK_SPEED_GEN_1 0x1
33#define LINK_SPEED_GEN_2 0x2
34#define LINK_SPEED_GEN_3 0x3
35
36#define PCIE_MISC_CONTROL_1_OFF 0x8bc
37#define PCIE_DBI_RO_WR_EN BIT(0)
38
39#define PLR_OFFSET 0x700
40#define PCIE_PORT_DEBUG0 (PLR_OFFSET + 0x28)
41#define PORT_LOGIC_LTSSM_STATE_MASK 0x1f
42#define PORT_LOGIC_LTSSM_STATE_L0 0x11
43
44#define PCIE_LINK_WIDTH_SPEED_CONTROL 0x80c
45#define PORT_LOGIC_SPEED_CHANGE (0x1 << 17)
46
47#define PCIE_LINK_UP_TIMEOUT_MS 100
48
49/*
50 * iATU Unroll-specific register definitions
51 * From 4.80 core version the address translation will be made by unroll.
52 * The registers are offset from atu_base
53 */
54#define PCIE_ATU_UNR_REGION_CTRL1 0x00
55#define PCIE_ATU_UNR_REGION_CTRL2 0x04
56#define PCIE_ATU_UNR_LOWER_BASE 0x08
57#define PCIE_ATU_UNR_UPPER_BASE 0x0c
58#define PCIE_ATU_UNR_LIMIT 0x10
59#define PCIE_ATU_UNR_LOWER_TARGET 0x14
60#define PCIE_ATU_UNR_UPPER_TARGET 0x18
61
62#define PCIE_ATU_REGION_INDEX1 (0x1 << 0)
63#define PCIE_ATU_REGION_INDEX0 (0x0 << 0)
64#define PCIE_ATU_TYPE_MEM (0x0 << 0)
65#define PCIE_ATU_TYPE_IO (0x2 << 0)
66#define PCIE_ATU_TYPE_CFG0 (0x4 << 0)
67#define PCIE_ATU_TYPE_CFG1 (0x5 << 0)
68#define PCIE_ATU_ENABLE (0x1 << 31)
69#define PCIE_ATU_BAR_MODE_ENABLE (0x1 << 30)
70#define PCIE_ATU_BUS(x) (((x) & 0xff) << 24)
71#define PCIE_ATU_DEV(x) (((x) & 0x1f) << 19)
72#define PCIE_ATU_FUNC(x) (((x) & 0x7) << 16)
73
74/* Register address builder */
75#define PCIE_GET_ATU_OUTB_UNR_REG_OFFSET(region) ((region) << 9)
76
77/* Offsets from App base */
78#define PCIE_CMD_STATUS 0x04
79#define LTSSM_EN_VAL BIT(0)
80
81/* Parameters for the waiting for iATU enabled routine */
82#define LINK_WAIT_MAX_IATU_RETRIES 5
83#define LINK_WAIT_IATU 10000
84
85#define AM654_PCIE_DEV_TYPE_MASK 0x3
86#define EP 0x0
87#define LEG_EP 0x1
88#define RC 0x2
89
90/**
91 * struct pcie_dw_ti - TI DW PCIe controller state
92 *
93 * @app_base: The base address of application register space
94 * @dbics_base: The base address of dbics register space
95 * @cfg_base: The base address of configuration space
96 * @atu_base: The base address of ATU space
97 * @cfg_size: The size of the configuration space which is needed
98 * as it gets written into the PCIE_ATU_LIMIT register
99 * @first_busno: This driver supports multiple PCIe controllers.
100 * first_busno stores the bus number of the PCIe root-port
101 * number which may vary depending on the PCIe setup
102 * (PEX switches etc).
103 */
104struct pcie_dw_ti {
105 void *app_base;
106 void *dbi_base;
107 void *cfg_base;
108 void *atu_base;
109 fdt_size_t cfg_size;
110 int first_busno;
111 struct udevice *dev;
112
113 /* IO and MEM PCI regions */
114 struct pci_region io;
115 struct pci_region mem;
116};
117
118enum dw_pcie_device_mode {
119 DW_PCIE_UNKNOWN_TYPE,
120 DW_PCIE_EP_TYPE,
121 DW_PCIE_LEG_EP_TYPE,
122 DW_PCIE_RC_TYPE,
123};
124
125static int pcie_dw_get_link_speed(struct pcie_dw_ti *pci)
126{
127 return (readl(pci->dbi_base + PCIE_LINK_STATUS_REG) &
128 PCIE_LINK_STATUS_SPEED_MASK) >> PCIE_LINK_STATUS_SPEED_OFF;
129}
130
131static int pcie_dw_get_link_width(struct pcie_dw_ti *pci)
132{
133 return (readl(pci->dbi_base + PCIE_LINK_STATUS_REG) &
134 PCIE_LINK_STATUS_WIDTH_MASK) >> PCIE_LINK_STATUS_WIDTH_OFF;
135}
136
137static void dw_pcie_writel_ob_unroll(struct pcie_dw_ti *pci, u32 index, u32 reg,
138 u32 val)
139{
140 u32 offset = PCIE_GET_ATU_OUTB_UNR_REG_OFFSET(index);
141 void __iomem *base = pci->atu_base;
142
143 writel(val, base + offset + reg);
144}
145
146static u32 dw_pcie_readl_ob_unroll(struct pcie_dw_ti *pci, u32 index, u32 reg)
147{
148 u32 offset = PCIE_GET_ATU_OUTB_UNR_REG_OFFSET(index);
149 void __iomem *base = pci->atu_base;
150
151 return readl(base + offset + reg);
152}
153
154/**
155 * pcie_dw_prog_outbound_atu_unroll() - Configure ATU for outbound accesses
156 *
157 * @pcie: Pointer to the PCI controller state
158 * @index: ATU region index
159 * @type: ATU accsess type
160 * @cpu_addr: the physical address for the translation entry
161 * @pci_addr: the pcie bus address for the translation entry
162 * @size: the size of the translation entry
163 */
164static void pcie_dw_prog_outbound_atu_unroll(struct pcie_dw_ti *pci, int index,
165 int type, u64 cpu_addr,
166 u64 pci_addr, u32 size)
167{
168 u32 retries, val;
169
170 debug("ATU programmed with: index: %d, type: %d, cpu addr: %8llx, pci addr: %8llx, size: %8x\n",
171 index, type, cpu_addr, pci_addr, size);
172
173 dw_pcie_writel_ob_unroll(pci, index, PCIE_ATU_UNR_LOWER_BASE,
174 lower_32_bits(cpu_addr));
175 dw_pcie_writel_ob_unroll(pci, index, PCIE_ATU_UNR_UPPER_BASE,
176 upper_32_bits(cpu_addr));
177 dw_pcie_writel_ob_unroll(pci, index, PCIE_ATU_UNR_LIMIT,
178 lower_32_bits(cpu_addr + size - 1));
179 dw_pcie_writel_ob_unroll(pci, index, PCIE_ATU_UNR_LOWER_TARGET,
180 lower_32_bits(pci_addr));
181 dw_pcie_writel_ob_unroll(pci, index, PCIE_ATU_UNR_UPPER_TARGET,
182 upper_32_bits(pci_addr));
183 dw_pcie_writel_ob_unroll(pci, index, PCIE_ATU_UNR_REGION_CTRL1,
184 type);
185 dw_pcie_writel_ob_unroll(pci, index, PCIE_ATU_UNR_REGION_CTRL2,
186 PCIE_ATU_ENABLE);
187
188 /*
189 * Make sure ATU enable takes effect before any subsequent config
190 * and I/O accesses.
191 */
192 for (retries = 0; retries < LINK_WAIT_MAX_IATU_RETRIES; retries++) {
193 val = dw_pcie_readl_ob_unroll(pci, index,
194 PCIE_ATU_UNR_REGION_CTRL2);
195 if (val & PCIE_ATU_ENABLE)
196 return;
197
198 udelay(LINK_WAIT_IATU);
199 }
200 dev_err(pci->dev, "outbound iATU is not being enabled\n");
201}
202
203/**
204 * set_cfg_address() - Configure the PCIe controller config space access
205 *
206 * @pcie: Pointer to the PCI controller state
207 * @d: PCI device to access
208 * @where: Offset in the configuration space
209 *
210 * Configures the PCIe controller to access the configuration space of
211 * a specific PCIe device and returns the address to use for this
212 * access.
213 *
214 * Return: Address that can be used to access the configation space
215 * of the requested device / offset
216 */
217static uintptr_t set_cfg_address(struct pcie_dw_ti *pcie,
218 pci_dev_t d, uint where)
219{
220 int bus = PCI_BUS(d) - pcie->first_busno;
221 uintptr_t va_address;
222 u32 atu_type;
223
224 /* Use dbi_base for own configuration read and write */
225 if (!bus) {
226 va_address = (uintptr_t)pcie->dbi_base;
227 goto out;
228 }
229
230 if (bus == 1)
231 /* For local bus, change TLP Type field to 4. */
232 atu_type = PCIE_ATU_TYPE_CFG0;
233 else
234 /* Otherwise, change TLP Type field to 5. */
235 atu_type = PCIE_ATU_TYPE_CFG1;
236
237 /*
238 * Not accessing root port configuration space?
239 * Region #0 is used for Outbound CFG space access.
240 * Direction = Outbound
241 * Region Index = 0
242 */
243 d = PCI_MASK_BUS(d);
244 d = PCI_ADD_BUS(bus, d);
245 pcie_dw_prog_outbound_atu_unroll(pcie, PCIE_ATU_REGION_INDEX1,
246 atu_type, (u64)pcie->cfg_base,
247 d << 8, pcie->cfg_size);
248
249 va_address = (uintptr_t)pcie->cfg_base;
250
251out:
252 va_address += where & ~0x3;
253
254 return va_address;
255}
256
257/**
258 * pcie_dw_addr_valid() - Check for valid bus address
259 *
260 * @d: The PCI device to access
261 * @first_busno: Bus number of the PCIe controller root complex
262 *
263 * Return 1 (true) if the PCI device can be accessed by this controller.
264 *
265 * Return: 1 on valid, 0 on invalid
266 */
267static int pcie_dw_addr_valid(pci_dev_t d, int first_busno)
268{
269 if ((PCI_BUS(d) == first_busno) && (PCI_DEV(d) > 0))
270 return 0;
271 if ((PCI_BUS(d) == first_busno + 1) && (PCI_DEV(d) > 0))
272 return 0;
273
274 return 1;
275}
276
277/**
278 * pcie_dw_ti_read_config() - Read from configuration space
279 *
280 * @bus: Pointer to the PCI bus
281 * @bdf: Identifies the PCIe device to access
282 * @offset: The offset into the device's configuration space
283 * @valuep: A pointer at which to store the read value
284 * @size: Indicates the size of access to perform
285 *
286 * Read a value of size @size from offset @offset within the configuration
287 * space of the device identified by the bus, device & function numbers in @bdf
288 * on the PCI bus @bus.
289 *
290 * Return: 0 on success
291 */
292static int pcie_dw_ti_read_config(struct udevice *bus, pci_dev_t bdf,
293 uint offset, ulong *valuep,
294 enum pci_size_t size)
295{
296 struct pcie_dw_ti *pcie = dev_get_priv(bus);
297 uintptr_t va_address;
298 ulong value;
299
300 debug("PCIE CFG read: bdf=%2x:%2x:%2x ",
301 PCI_BUS(bdf), PCI_DEV(bdf), PCI_FUNC(bdf));
302
303 if (!pcie_dw_addr_valid(bdf, pcie->first_busno)) {
304 debug("- out of range\n");
305 *valuep = pci_get_ff(size);
306 return 0;
307 }
308
309 va_address = set_cfg_address(pcie, bdf, offset);
310
311 value = readl(va_address);
312
313 debug("(addr,val)=(0x%04x, 0x%08lx)\n", offset, value);
314 *valuep = pci_conv_32_to_size(value, offset, size);
315
316 pcie_dw_prog_outbound_atu_unroll(pcie, PCIE_ATU_REGION_INDEX1,
317 PCIE_ATU_TYPE_IO, pcie->io.phys_start,
318 pcie->io.bus_start, pcie->io.size);
319
320 return 0;
321}
322
323/**
324 * pcie_dw_ti_write_config() - Write to configuration space
325 *
326 * @bus: Pointer to the PCI bus
327 * @bdf: Identifies the PCIe device to access
328 * @offset: The offset into the device's configuration space
329 * @value: The value to write
330 * @size: Indicates the size of access to perform
331 *
332 * Write the value @value of size @size from offset @offset within the
333 * configuration space of the device identified by the bus, device & function
334 * numbers in @bdf on the PCI bus @bus.
335 *
336 * Return: 0 on success
337 */
338static int pcie_dw_ti_write_config(struct udevice *bus, pci_dev_t bdf,
339 uint offset, ulong value,
340 enum pci_size_t size)
341{
342 struct pcie_dw_ti *pcie = dev_get_priv(bus);
343 uintptr_t va_address;
344 ulong old;
345
346 debug("PCIE CFG write: (b,d,f)=(%2d,%2d,%2d) ",
347 PCI_BUS(bdf), PCI_DEV(bdf), PCI_FUNC(bdf));
348 debug("(addr,val)=(0x%04x, 0x%08lx)\n", offset, value);
349
350 if (!pcie_dw_addr_valid(bdf, pcie->first_busno)) {
351 debug("- out of range\n");
352 return 0;
353 }
354
355 va_address = set_cfg_address(pcie, bdf, offset);
356
357 old = readl(va_address);
358 value = pci_conv_size_to_32(old, value, offset, size);
359 writel(value, va_address);
360
361 pcie_dw_prog_outbound_atu_unroll(pcie, PCIE_ATU_REGION_INDEX1,
362 PCIE_ATU_TYPE_IO, pcie->io.phys_start,
363 pcie->io.bus_start, pcie->io.size);
364
365 return 0;
366}
367
368static inline void dw_pcie_dbi_write_enable(struct pcie_dw_ti *pci, bool en)
369{
370 u32 val;
371
372 val = readl(pci->dbi_base + PCIE_MISC_CONTROL_1_OFF);
373 if (en)
374 val |= PCIE_DBI_RO_WR_EN;
375 else
376 val &= ~PCIE_DBI_RO_WR_EN;
377 writel(val, pci->dbi_base + PCIE_MISC_CONTROL_1_OFF);
378}
379
380/**
381 * pcie_dw_configure() - Configure link capabilities and speed
382 *
383 * @regs_base: A pointer to the PCIe controller registers
384 * @cap_speed: The capabilities and speed to configure
385 *
386 * Configure the link capabilities and speed in the PCIe root complex.
387 */
388static void pcie_dw_configure(struct pcie_dw_ti *pci, u32 cap_speed)
389{
390 u32 val;
391
392 dw_pcie_dbi_write_enable(pci, true);
393
394 val = readl(pci->dbi_base + PCIE_LINK_CAPABILITY);
395 val &= ~TARGET_LINK_SPEED_MASK;
396 val |= cap_speed;
397 writel(val, pci->dbi_base + PCIE_LINK_CAPABILITY);
398
399 val = readl(pci->dbi_base + PCIE_LINK_CTL_2);
400 val &= ~TARGET_LINK_SPEED_MASK;
401 val |= cap_speed;
402 writel(val, pci->dbi_base + PCIE_LINK_CTL_2);
403
404 dw_pcie_dbi_write_enable(pci, false);
405}
406
407/**
408 * is_link_up() - Return the link state
409 *
410 * @regs_base: A pointer to the PCIe DBICS registers
411 *
412 * Return: 1 (true) for active line and 0 (false) for no link
413 */
414static int is_link_up(struct pcie_dw_ti *pci)
415{
416 u32 val;
417
418 val = readl(pci->dbi_base + PCIE_PORT_DEBUG0);
419 val &= PORT_LOGIC_LTSSM_STATE_MASK;
420
421 return (val == PORT_LOGIC_LTSSM_STATE_L0);
422}
423
424/**
425 * wait_link_up() - Wait for the link to come up
426 *
427 * @regs_base: A pointer to the PCIe controller registers
428 *
429 * Return: 1 (true) for active line and 0 (false) for no link (timeout)
430 */
431static int wait_link_up(struct pcie_dw_ti *pci)
432{
433 unsigned long timeout;
434
435 timeout = get_timer(0) + PCIE_LINK_UP_TIMEOUT_MS;
436 while (!is_link_up(pci)) {
437 if (get_timer(0) > timeout)
438 return 0;
439 };
440
441 return 1;
442}
443
444static int pcie_dw_ti_pcie_link_up(struct pcie_dw_ti *pci, u32 cap_speed)
445{
446 u32 val;
447
448 if (is_link_up(pci)) {
449 printf("PCI Link already up before configuration!\n");
450 return 1;
451 }
452
453 /* DW pre link configurations */
454 pcie_dw_configure(pci, cap_speed);
455
456 /* Initiate link training */
457 val = readl(pci->app_base + PCIE_CMD_STATUS);
458 val |= LTSSM_EN_VAL;
459 writel(val, pci->app_base + PCIE_CMD_STATUS);
460
461 /* Check that link was established */
462 if (!wait_link_up(pci))
463 return 0;
464
465 /*
466 * Link can be established in Gen 1. still need to wait
467 * till MAC nagaotiation is completed
468 */
469 udelay(100);
470
471 return 1;
472}
473
474/**
475 * pcie_dw_setup_host() - Setup the PCIe controller for RC opertaion
476 *
477 * @pcie: Pointer to the PCI controller state
478 *
479 * Configure the host BARs of the PCIe controller root port so that
480 * PCI(e) devices may access the system memory.
481 */
482static void pcie_dw_setup_host(struct pcie_dw_ti *pci)
483{
484 u32 val;
485
486 /* setup RC BARs */
487 writel(PCI_BASE_ADDRESS_MEM_TYPE_64,
488 pci->dbi_base + PCI_BASE_ADDRESS_0);
489 writel(0x0, pci->dbi_base + PCI_BASE_ADDRESS_1);
490
491 /* setup interrupt pins */
492 dw_pcie_dbi_write_enable(pci, true);
493 val = readl(pci->dbi_base + PCI_INTERRUPT_LINE);
494 val &= 0xffff00ff;
495 val |= 0x00000100;
496 writel(val, pci->dbi_base + PCI_INTERRUPT_LINE);
497 dw_pcie_dbi_write_enable(pci, false);
498
499 /* setup bus numbers */
500 val = readl(pci->dbi_base + PCI_PRIMARY_BUS);
501 val &= 0xff000000;
502 val |= 0x00ff0100;
503 writel(val, pci->dbi_base + PCI_PRIMARY_BUS);
504
505 /* setup command register */
506 val = readl(pci->dbi_base + PCI_COMMAND);
507 val &= 0xffff0000;
508 val |= PCI_COMMAND_IO | PCI_COMMAND_MEMORY |
509 PCI_COMMAND_MASTER | PCI_COMMAND_SERR;
510 writel(val, pci->dbi_base + PCI_COMMAND);
511
512 /* Enable write permission for the DBI read-only register */
513 dw_pcie_dbi_write_enable(pci, true);
514 /* program correct class for RC */
515 writew(PCI_CLASS_BRIDGE_PCI, pci->dbi_base + PCI_CLASS_DEVICE);
516 /* Better disable write permission right after the update */
517 dw_pcie_dbi_write_enable(pci, false);
518
519 val = readl(pci->dbi_base + PCIE_LINK_WIDTH_SPEED_CONTROL);
520 val |= PORT_LOGIC_SPEED_CHANGE;
521 writel(val, pci->dbi_base + PCIE_LINK_WIDTH_SPEED_CONTROL);
522}
523
524static int pcie_am654_set_mode(struct pcie_dw_ti *pci,
525 enum dw_pcie_device_mode mode)
526{
527 struct regmap *syscon;
528 u32 val;
529 u32 mask;
530 int ret;
531
532 syscon = syscon_regmap_lookup_by_phandle(pci->dev,
533 "ti,syscon-pcie-mode");
534 if (IS_ERR(syscon))
535 return 0;
536
537 mask = AM654_PCIE_DEV_TYPE_MASK;
538
539 switch (mode) {
540 case DW_PCIE_RC_TYPE:
541 val = RC;
542 break;
543 case DW_PCIE_EP_TYPE:
544 val = EP;
545 break;
546 default:
547 dev_err(pci->dev, "INVALID device type %d\n", mode);
548 return -EINVAL;
549 }
550
551 ret = regmap_update_bits(syscon, 0, mask, val);
552 if (ret) {
553 dev_err(pci->dev, "failed to set pcie mode\n");
554 return ret;
555 }
556
557 return 0;
558}
559
560static int pcie_dw_init_id(struct pcie_dw_ti *pci)
561{
562 struct regmap *devctrl_regs;
563 unsigned int id;
564 int ret;
565
566 devctrl_regs = syscon_regmap_lookup_by_phandle(pci->dev,
567 "ti,syscon-pcie-id");
568 if (IS_ERR(devctrl_regs))
569 return PTR_ERR(devctrl_regs);
570
571 ret = regmap_read(devctrl_regs, 0, &id);
572 if (ret)
573 return ret;
574
575 dw_pcie_dbi_write_enable(pci, true);
576 writew(id & PCIE_VENDORID_MASK, pci->dbi_base + PCI_VENDOR_ID);
577 writew(id >> PCIE_DEVICEID_SHIFT, pci->dbi_base + PCI_DEVICE_ID);
578 dw_pcie_dbi_write_enable(pci, false);
579
580 return 0;
581}
582
583/**
584 * pcie_dw_ti_probe() - Probe the PCIe bus for active link
585 *
586 * @dev: A pointer to the device being operated on
587 *
588 * Probe for an active link on the PCIe bus and configure the controller
589 * to enable this port.
590 *
591 * Return: 0 on success, else -ENODEV
592 */
593static int pcie_dw_ti_probe(struct udevice *dev)
594{
595 struct pcie_dw_ti *pci = dev_get_priv(dev);
596 struct udevice *ctlr = pci_get_controller(dev);
597 struct pci_controller *hose = dev_get_uclass_priv(ctlr);
598 struct power_domain pci_pwrdmn;
599 struct phy phy0, phy1;
600 int ret;
601
602 ret = power_domain_get_by_index(dev, &pci_pwrdmn, 0);
603 if (ret) {
604 dev_err(dev, "failed to get power domain\n");
605 return ret;
606 }
607
608 ret = power_domain_on(&pci_pwrdmn);
609 if (ret) {
610 dev_err(dev, "Power domain on failed\n");
611 return ret;
612 }
613
614 ret = generic_phy_get_by_name(dev, "pcie-phy0", &phy0);
615 if (ret) {
616 dev_err(dev, "Unable to get phy0");
617 return ret;
618 }
619 generic_phy_reset(&phy0);
620 generic_phy_init(&phy0);
621 generic_phy_power_on(&phy0);
622
623 ret = generic_phy_get_by_name(dev, "pcie-phy1", &phy1);
624 if (ret) {
625 dev_err(dev, "Unable to get phy1");
626 return ret;
627 }
628 generic_phy_reset(&phy1);
629 generic_phy_init(&phy1);
630 generic_phy_power_on(&phy1);
631
632 pci->first_busno = dev->seq;
633 pci->dev = dev;
634
635 pcie_dw_setup_host(pci);
636 pcie_dw_init_id(pci);
637
638 if (device_is_compatible(dev, "ti,am654-pcie-rc"))
639 pcie_am654_set_mode(pci, DW_PCIE_RC_TYPE);
640
641 if (!pcie_dw_ti_pcie_link_up(pci, LINK_SPEED_GEN_2)) {
642 printf("PCIE-%d: Link down\n", dev->seq);
643 return -ENODEV;
644 }
645
646 printf("PCIE-%d: Link up (Gen%d-x%d, Bus%d)\n", dev->seq,
647 pcie_dw_get_link_speed(pci),
648 pcie_dw_get_link_width(pci),
649 hose->first_busno);
650
651 /* Store the IO and MEM windows settings for future use by the ATU */
652 pci->io.phys_start = hose->regions[0].phys_start; /* IO base */
653 pci->io.bus_start = hose->regions[0].bus_start; /* IO_bus_addr */
654 pci->io.size = hose->regions[0].size; /* IO size */
655
656 pci->mem.phys_start = hose->regions[1].phys_start; /* MEM base */
657 pci->mem.bus_start = hose->regions[1].bus_start; /* MEM_bus_addr */
658 pci->mem.size = hose->regions[1].size; /* MEM size */
659
660 pcie_dw_prog_outbound_atu_unroll(pci, PCIE_ATU_REGION_INDEX0,
661 PCIE_ATU_TYPE_MEM,
662 pci->mem.phys_start,
663 pci->mem.bus_start, pci->mem.size);
664
665 return 0;
666}
667
668/**
669 * pcie_dw_ti_ofdata_to_platdata() - Translate from DT to device state
670 *
671 * @dev: A pointer to the device being operated on
672 *
673 * Translate relevant data from the device tree pertaining to device @dev into
674 * state that the driver will later make use of. This state is stored in the
675 * device's private data structure.
676 *
677 * Return: 0 on success, else -EINVAL
678 */
679static int pcie_dw_ti_ofdata_to_platdata(struct udevice *dev)
680{
681 struct pcie_dw_ti *pcie = dev_get_priv(dev);
682
683 /* Get the controller base address */
684 pcie->dbi_base = (void *)dev_read_addr_name(dev, "dbics");
685 if ((fdt_addr_t)pcie->dbi_base == FDT_ADDR_T_NONE)
686 return -EINVAL;
687
688 /* Get the config space base address and size */
689 pcie->cfg_base = (void *)dev_read_addr_size_name(dev, "config",
690 &pcie->cfg_size);
691 if ((fdt_addr_t)pcie->cfg_base == FDT_ADDR_T_NONE)
692 return -EINVAL;
693
694 /* Get the iATU base address and size */
695 pcie->atu_base = (void *)dev_read_addr_name(dev, "atu");
696 if ((fdt_addr_t)pcie->atu_base == FDT_ADDR_T_NONE)
697 return -EINVAL;
698
699 /* Get the app base address and size */
700 pcie->app_base = (void *)dev_read_addr_name(dev, "app");
701 if ((fdt_addr_t)pcie->app_base == FDT_ADDR_T_NONE)
702 return -EINVAL;
703
704 return 0;
705}
706
707static const struct dm_pci_ops pcie_dw_ti_ops = {
708 .read_config = pcie_dw_ti_read_config,
709 .write_config = pcie_dw_ti_write_config,
710};
711
712static const struct udevice_id pcie_dw_ti_ids[] = {
713 { .compatible = "ti,am654-pcie-rc" },
714 { }
715};
716
717U_BOOT_DRIVER(pcie_dw_ti) = {
718 .name = "pcie_dw_ti",
719 .id = UCLASS_PCI,
720 .of_match = pcie_dw_ti_ids,
721 .ops = &pcie_dw_ti_ops,
722 .ofdata_to_platdata = pcie_dw_ti_ofdata_to_platdata,
723 .probe = pcie_dw_ti_probe,
724 .priv_auto_alloc_size = sizeof(struct pcie_dw_ti),
725};