blob: 2f0309f0ccdebbbd84c1430c3511a908faac90fd [file] [log] [blame]
Tom Rini83d290c2018-05-06 17:58:06 -04001/* SPDX-License-Identifier: GPL-2.0+ */
Ryan Mallonb8d41dd2011-06-05 07:21:22 +00002/*
3 * Bluewater Systems Snapper 9260 and 9G20 modules
4 *
5 * (C) Copyright 2011 Bluewater Systems
6 * Author: Andre Renaud <andre@bluewatersys.com>
7 * Author: Ryan Mallon <ryan@bluewatersys.com>
Ryan Mallonb8d41dd2011-06-05 07:21:22 +00008 */
9
10#ifndef __CONFIG_H
11#define __CONFIG_H
12
13/* SoC type is defined in boards.cfg */
14#include <asm/hardware.h>
Alexey Brodkin1ace4022014-02-26 17:47:58 +040015#include <linux/sizes.h>
Ryan Mallonb8d41dd2011-06-05 07:21:22 +000016
Ryan Mallonb8d41dd2011-06-05 07:21:22 +000017/* ARM asynchronous clock */
18#define CONFIG_SYS_AT91_MAIN_CLOCK 18432000 /* External Crystal, in Hz */
19#define CONFIG_SYS_AT91_SLOW_CLOCK 32768
Ryan Mallonb8d41dd2011-06-05 07:21:22 +000020
21/* CPU */
Ryan Mallonb8d41dd2011-06-05 07:21:22 +000022
Ryan Mallonb8d41dd2011-06-05 07:21:22 +000023/* SDRAM */
Ryan Mallonb8d41dd2011-06-05 07:21:22 +000024#define CONFIG_SYS_SDRAM_BASE ATMEL_BASE_CS1
25#define CONFIG_SYS_SDRAM_SIZE (64 * 1024 * 1024) /* 64MB */
26#define CONFIG_SYS_INIT_SP_ADDR (ATMEL_BASE_SRAM1 + 0x1000 - \
27 GENERATED_GBL_DATA_SIZE)
28
29/* Mem test settings */
Ryan Mallonb8d41dd2011-06-05 07:21:22 +000030
31/* NAND Flash */
Ryan Mallonb8d41dd2011-06-05 07:21:22 +000032#define CONFIG_SYS_MAX_NAND_DEVICE 1
33#define CONFIG_SYS_NAND_BASE ATMEL_BASE_CS3
34#define CONFIG_SYS_NAND_DBW_8
35#define CONFIG_SYS_NAND_MASK_ALE (1 << 21) /* AD21 */
36#define CONFIG_SYS_NAND_MASK_CLE (1 << 22) /* AD22 */
37#define CONFIG_SYS_NAND_ENABLE_PIN AT91_PIN_PC14
38#define CONFIG_SYS_NAND_READY_PIN AT91_PIN_PC13
39
40/* Ethernet */
Ryan Mallonb8d41dd2011-06-05 07:21:22 +000041#define CONFIG_TFTP_PORT
Ryan Mallonb8d41dd2011-06-05 07:21:22 +000042
43/* USB */
44#define CONFIG_USB_ATMEL
Bo Shendcd2f1a2013-10-21 16:14:00 +080045#define CONFIG_USB_ATMEL_CLK_SEL_PLLB
Ryan Mallonb8d41dd2011-06-05 07:21:22 +000046#define CONFIG_USB_OHCI_NEW
Ryan Mallonb8d41dd2011-06-05 07:21:22 +000047#define CONFIG_SYS_USB_OHCI_CPU_INIT
48#define CONFIG_SYS_USB_OHCI_REGS_BASE ATMEL_UHP_BASE
49#define CONFIG_SYS_USB_OHCI_SLOT_NAME "at91sam9260"
50#define CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS 2
Ryan Mallonb8d41dd2011-06-05 07:21:22 +000051
52/* GPIOs and IO expander */
Ryan Mallonb8d41dd2011-06-05 07:21:22 +000053#define CONFIG_PCA953X
54#define CONFIG_SYS_I2C_PCA953X_ADDR 0x28
55#define CONFIG_SYS_I2C_PCA953X_WIDTH { {0x28, 16} }
56
57/* UARTs/Serial console */
Simon Glass1a1927f2014-10-29 13:09:01 -060058#ifndef CONFIG_DM_SERIAL
Ryan Mallonb8d41dd2011-06-05 07:21:22 +000059#define CONFIG_USART_BASE ATMEL_BASE_DBGU
60#define CONFIG_USART_ID ATMEL_ID_SYS
Simon Glass1a1927f2014-10-29 13:09:01 -060061#endif
Ryan Mallonb8d41dd2011-06-05 07:21:22 +000062
63/* I2C - Bit-bashed */
Ryan Mallonb8d41dd2011-06-05 07:21:22 +000064#define CONFIG_SOFT_I2C_READ_REPEATED_START
Ryan Mallonb8d41dd2011-06-05 07:21:22 +000065#define I2C_INIT do { \
66 at91_set_gpio_output(AT91_PIN_PA23, 1); \
67 at91_set_gpio_output(AT91_PIN_PA24, 1); \
68 at91_set_pio_multi_drive(AT91_PIO_PORTA, 23, 1); \
69 at91_set_pio_multi_drive(AT91_PIO_PORTA, 24, 1); \
70 } while (0)
71#define I2C_SOFT_DECLARATIONS
72#define I2C_ACTIVE
73#define I2C_TRISTATE at91_set_gpio_input(AT91_PIN_PA23, 1);
74#define I2C_READ at91_get_gpio_value(AT91_PIN_PA23);
75#define I2C_SDA(bit) do { \
76 if (bit) { \
77 at91_set_gpio_input(AT91_PIN_PA23, 1); \
78 } else { \
79 at91_set_gpio_output(AT91_PIN_PA23, 1); \
80 at91_set_gpio_value(AT91_PIN_PA23, bit); \
81 } \
82 } while (0)
83#define I2C_SCL(bit) at91_set_pio_value(AT91_PIO_PORTA, 24, bit)
84#define I2C_DELAY udelay(2)
85
86/* Boot options */
Ryan Mallonb8d41dd2011-06-05 07:21:22 +000087
Ryan Mallonb8d41dd2011-06-05 07:21:22 +000088/* Environment settings */
Ryan Mallonb8d41dd2011-06-05 07:21:22 +000089
90/* Console settings */
Ryan Mallonb8d41dd2011-06-05 07:21:22 +000091
Ryan Mallonb8d41dd2011-06-05 07:21:22 +000092#endif /* __CONFIG_H */