blob: ffc898c58769ff586499b8f35af9695233d1c275 [file] [log] [blame]
wdenk4a9cbbe2002-08-27 09:48:53 +00001/*
2 * (C) Copyright 2000
3 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
4 *
5 * See file CREDITS for list of people who contributed to this
6 * project.
7 *
8 * This program is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU General Public License as
10 * published by the Free Software Foundation; either version 2 of
11 * the License, or (at your option) any later version.
12 *
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
17 *
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
21 * MA 02111-1307 USA
22 */
23
24#include <common.h>
25#include <commproc.h>
26#include <command.h>
wdenk281e00a2004-08-01 22:48:16 +000027#include <serial.h>
wdenkd0fb80c2003-01-11 09:48:40 +000028#include <watchdog.h>
wdenk4a9cbbe2002-08-27 09:48:53 +000029
Wolfgang Denkd87080b2006-03-31 18:32:53 +020030DECLARE_GLOBAL_DATA_PTR;
31
wdenk4a9cbbe2002-08-27 09:48:53 +000032#if !defined(CONFIG_8xx_CONS_NONE) /* No Console at all */
33
34#if defined(CONFIG_8xx_CONS_SMC1) /* Console on SMC1 */
35#define SMC_INDEX 0
wdenk4a9cbbe2002-08-27 09:48:53 +000036#define PROFF_SMC PROFF_SMC1
37#define CPM_CR_CH_SMC CPM_CR_CH_SMC1
38
39#elif defined(CONFIG_8xx_CONS_SMC2) /* Console on SMC2 */
40#define SMC_INDEX 1
wdenk4a9cbbe2002-08-27 09:48:53 +000041#define PROFF_SMC PROFF_SMC2
42#define CPM_CR_CH_SMC CPM_CR_CH_SMC2
43
wdenk281e00a2004-08-01 22:48:16 +000044#endif /* CONFIG_8xx_CONS_SMCx */
45
46#if defined(CONFIG_8xx_CONS_SCC1) /* Console on SCC1 */
wdenk4a9cbbe2002-08-27 09:48:53 +000047#define SCC_INDEX 0
48#define PROFF_SCC PROFF_SCC1
49#define CPM_CR_CH_SCC CPM_CR_CH_SCC1
50
51#elif defined(CONFIG_8xx_CONS_SCC2) /* Console on SCC2 */
wdenk4a9cbbe2002-08-27 09:48:53 +000052#define SCC_INDEX 1
53#define PROFF_SCC PROFF_SCC2
54#define CPM_CR_CH_SCC CPM_CR_CH_SCC2
55
56#elif defined(CONFIG_8xx_CONS_SCC3) /* Console on SCC3 */
wdenk4a9cbbe2002-08-27 09:48:53 +000057#define SCC_INDEX 2
58#define PROFF_SCC PROFF_SCC3
59#define CPM_CR_CH_SCC CPM_CR_CH_SCC3
60
61#elif defined(CONFIG_8xx_CONS_SCC4) /* Console on SCC4 */
wdenk4a9cbbe2002-08-27 09:48:53 +000062#define SCC_INDEX 3
63#define PROFF_SCC PROFF_SCC4
64#define CPM_CR_CH_SCC CPM_CR_CH_SCC4
65
wdenk281e00a2004-08-01 22:48:16 +000066#endif /* CONFIG_8xx_CONS_SCCx */
wdenk4a9cbbe2002-08-27 09:48:53 +000067
wdenk2535d602003-07-17 23:16:40 +000068static void serial_setdivisor(volatile cpm8xx_t *cp)
69{
wdenk75d1ea72004-01-31 20:06:54 +000070 int divisor=(gd->cpu_clk + 8*gd->baudrate)/16/gd->baudrate;
wdenk2535d602003-07-17 23:16:40 +000071
72 if(divisor/16>0x1000) {
73 /* bad divisor, assume 50Mhz clock and 9600 baud */
wdenk75d1ea72004-01-31 20:06:54 +000074 divisor=(50*1000*1000 + 8*9600)/16/9600;
wdenk2535d602003-07-17 23:16:40 +000075 }
76
wdenk3bbc8992003-12-07 22:27:15 +000077#ifdef CFG_BRGCLK_PRESCALE
78 divisor /= CFG_BRGCLK_PRESCALE;
79#endif
80
wdenk2535d602003-07-17 23:16:40 +000081 if(divisor<=0x1000) {
82 cp->cp_brgc1=((divisor-1)<<1) | CPM_BRG_EN;
83 } else {
84 cp->cp_brgc1=((divisor/16-1)<<1) | CPM_BRG_EN | CPM_BRG_DIV16;
85 }
86}
87
wdenk4a9cbbe2002-08-27 09:48:53 +000088#if (defined (CONFIG_8xx_CONS_SMC1) || defined (CONFIG_8xx_CONS_SMC2))
89
90/*
91 * Minimal serial functions needed to use one of the SMC ports
92 * as serial console interface.
93 */
94
wdenk281e00a2004-08-01 22:48:16 +000095static void smc_setbrg (void)
96{
97 volatile immap_t *im = (immap_t *)CFG_IMMR;
98 volatile cpm8xx_t *cp = &(im->im_cpm);
99
100 /* Set up the baud rate generator.
101 * See 8xx_io/commproc.c for details.
102 *
103 * Wire BRG1 to SMCx
104 */
105
106 cp->cp_simode = 0x00000000;
107
108 serial_setdivisor(cp);
109}
110
111static int smc_init (void)
wdenk4a9cbbe2002-08-27 09:48:53 +0000112{
wdenk8bde7f72003-06-27 21:31:46 +0000113 volatile immap_t *im = (immap_t *)CFG_IMMR;
wdenk4a9cbbe2002-08-27 09:48:53 +0000114 volatile smc_t *sp;
115 volatile smc_uart_t *up;
116 volatile cbd_t *tbdf, *rbdf;
117 volatile cpm8xx_t *cp = &(im->im_cpm);
118#if (!defined(CONFIG_8xx_CONS_SMC1)) && (defined(CONFIG_MPC823) || defined(CONFIG_MPC850))
119 volatile iop8xx_t *ip = (iop8xx_t *)&(im->im_ioport);
120#endif
121 uint dpaddr;
122
123 /* initialize pointers to SMC */
124
125 sp = (smc_t *) &(cp->cp_smc[SMC_INDEX]);
126 up = (smc_uart_t *) &cp->cp_dparam[PROFF_SMC];
127
128 /* Disable transmitter/receiver.
129 */
130 sp->smc_smcmr &= ~(SMCMR_REN | SMCMR_TEN);
131
132 /* Enable SDMA.
133 */
134 im->im_siu_conf.sc_sdcr = 1;
135
136 /* clear error conditions */
137#ifdef CFG_SDSR
138 im->im_sdma.sdma_sdsr = CFG_SDSR;
139#else
140 im->im_sdma.sdma_sdsr = 0x83;
141#endif
142
143 /* clear SDMA interrupt mask */
144#ifdef CFG_SDMR
145 im->im_sdma.sdma_sdmr = CFG_SDMR;
146#else
147 im->im_sdma.sdma_sdmr = 0x00;
148#endif
149
150#if defined(CONFIG_8xx_CONS_SMC1)
151 /* Use Port B for SMC1 instead of other functions.
152 */
153 cp->cp_pbpar |= 0x000000c0;
154 cp->cp_pbdir &= ~0x000000c0;
155 cp->cp_pbodr &= ~0x000000c0;
156#else /* CONFIG_8xx_CONS_SMC2 */
157# if defined(CONFIG_MPC823) || defined(CONFIG_MPC850)
158 /* Use Port A for SMC2 instead of other functions.
159 */
160 ip->iop_papar |= 0x00c0;
161 ip->iop_padir &= ~0x00c0;
162 ip->iop_paodr &= ~0x00c0;
163# else /* must be a 860 then */
164 /* Use Port B for SMC2 instead of other functions.
165 */
166 cp->cp_pbpar |= 0x00000c00;
167 cp->cp_pbdir &= ~0x00000c00;
168 cp->cp_pbodr &= ~0x00000c00;
169# endif
170#endif
171
wdenkb028f712003-12-07 21:39:28 +0000172#if defined(CONFIG_FADS) || defined(CONFIG_ADS)
wdenk4a9cbbe2002-08-27 09:48:53 +0000173 /* Enable RS232 */
174#if defined(CONFIG_8xx_CONS_SMC1)
175 *((uint *) BCSR1) &= ~BCSR1_RS232EN_1;
176#else
177 *((uint *) BCSR1) &= ~BCSR1_RS232EN_2;
178#endif
179#endif /* CONFIG_FADS */
180
181#if defined(CONFIG_RPXLITE) || defined(CONFIG_RPXCLASSIC)
182 /* Enable Monitor Port Transceiver */
183 *((uchar *) BCSR0) |= BCSR0_ENMONXCVR ;
184#endif /* CONFIG_RPXLITE */
185
186 /* Set the physical address of the host memory buffers in
187 * the buffer descriptors.
188 */
189
190#ifdef CFG_ALLOC_DPRAM
191 dpaddr = dpram_alloc_align (sizeof(cbd_t)*2 + 2, 8) ;
192#else
193 dpaddr = CPM_SERIAL_BASE ;
194#endif
195
196 /* Allocate space for two buffer descriptors in the DP ram.
197 * For now, this address seems OK, but it may have to
198 * change with newer versions of the firmware.
199 * damm: allocating space after the two buffers for rx/tx data
200 */
201
202 rbdf = (cbd_t *)&cp->cp_dpmem[dpaddr];
203 rbdf->cbd_bufaddr = (uint) (rbdf+2);
204 rbdf->cbd_sc = 0;
205 tbdf = rbdf + 1;
206 tbdf->cbd_bufaddr = ((uint) (rbdf+2)) + 1;
207 tbdf->cbd_sc = 0;
208
209 /* Set up the uart parameters in the parameter ram.
210 */
211 up->smc_rbase = dpaddr;
212 up->smc_tbase = dpaddr+sizeof(cbd_t);
213 up->smc_rfcr = SMC_EB;
214 up->smc_tfcr = SMC_EB;
215
216#if defined(CONFIG_MBX)
217 board_serial_init();
218#endif /* CONFIG_MBX */
219
220 /* Set UART mode, 8 bit, no parity, one stop.
221 * Enable receive and transmit.
222 */
223 sp->smc_smcmr = smcr_mk_clen(9) | SMCMR_SM_UART;
224
225 /* Mask all interrupts and remove anything pending.
226 */
227 sp->smc_smcm = 0;
228 sp->smc_smce = 0xff;
229
Markus Klotzbuecher81395672007-01-09 14:57:11 +0100230#ifdef CFG_SPC1920_SMC1_CLK4
231 /* clock source is PLD */
Wolfgang Denk2a8dfe02007-03-21 23:26:15 +0100232
Markus Klotzbuecher81395672007-01-09 14:57:11 +0100233 /* set freq to 19200 Baud */
234 *((volatile uchar *) CFG_SPC1920_PLD_BASE+6) = 0x3;
235 /* configure clk4 as input */
236 im->im_ioport.iop_pdpar |= 0x800;
237 im->im_ioport.iop_pddir &= ~0x800;
Wolfgang Denkf11033e2007-01-15 13:41:04 +0100238
Wolfgang Denk2a8dfe02007-03-21 23:26:15 +0100239 cp->cp_simode = ((cp->cp_simode & ~0xf000) | 0x7000);
Markus Klotzbuecherb02d0172006-07-12 08:48:24 +0200240#else
241 /* Set up the baud rate generator */
wdenk281e00a2004-08-01 22:48:16 +0000242 smc_setbrg ();
Markus Klotzbuecherb02d0172006-07-12 08:48:24 +0200243#endif
wdenk4a9cbbe2002-08-27 09:48:53 +0000244
245 /* Make the first buffer the only buffer.
246 */
247 tbdf->cbd_sc |= BD_SC_WRAP;
248 rbdf->cbd_sc |= BD_SC_EMPTY | BD_SC_WRAP;
249
250 /* Single character receive.
251 */
252 up->smc_mrblr = 1;
253 up->smc_maxidl = 0;
254
255 /* Initialize Tx/Rx parameters.
256 */
257
258 while (cp->cp_cpcr & CPM_CR_FLG) /* wait if cp is busy */
259 ;
260
261 cp->cp_cpcr = mk_cr_cmd(CPM_CR_CH_SMC, CPM_CR_INIT_TRX) | CPM_CR_FLG;
262
263 while (cp->cp_cpcr & CPM_CR_FLG) /* wait if cp is busy */
264 ;
265
266 /* Enable transmitter/receiver.
267 */
268 sp->smc_smcmr |= SMCMR_REN | SMCMR_TEN;
269
270 return (0);
271}
272
wdenk281e00a2004-08-01 22:48:16 +0000273static void
274smc_putc(const char c)
wdenk4a9cbbe2002-08-27 09:48:53 +0000275{
276 volatile cbd_t *tbdf;
277 volatile char *buf;
278 volatile smc_uart_t *up;
wdenk8bde7f72003-06-27 21:31:46 +0000279 volatile immap_t *im = (immap_t *)CFG_IMMR;
wdenk4a9cbbe2002-08-27 09:48:53 +0000280 volatile cpm8xx_t *cpmp = &(im->im_cpm);
281
wdenk4532cb62003-04-27 22:52:51 +0000282#ifdef CONFIG_MODEM_SUPPORT
wdenk4532cb62003-04-27 22:52:51 +0000283 if (gd->be_quiet)
284 return;
285#endif
286
wdenk4a9cbbe2002-08-27 09:48:53 +0000287 if (c == '\n')
wdenk281e00a2004-08-01 22:48:16 +0000288 smc_putc ('\r');
wdenk4a9cbbe2002-08-27 09:48:53 +0000289
290 up = (smc_uart_t *)&cpmp->cp_dparam[PROFF_SMC];
291
292 tbdf = (cbd_t *)&cpmp->cp_dpmem[up->smc_tbase];
293
294 /* Wait for last character to go.
295 */
296
297 buf = (char *)tbdf->cbd_bufaddr;
wdenk4a9cbbe2002-08-27 09:48:53 +0000298
299 *buf = c;
300 tbdf->cbd_datlen = 1;
301 tbdf->cbd_sc |= BD_SC_READY;
302 __asm__("eieio");
wdenkd0fb80c2003-01-11 09:48:40 +0000303
304 while (tbdf->cbd_sc & BD_SC_READY) {
305 WATCHDOG_RESET ();
wdenk4a9cbbe2002-08-27 09:48:53 +0000306 __asm__("eieio");
wdenkd0fb80c2003-01-11 09:48:40 +0000307 }
wdenk4a9cbbe2002-08-27 09:48:53 +0000308}
309
wdenk281e00a2004-08-01 22:48:16 +0000310static void
311smc_puts (const char *s)
312{
313 while (*s) {
314 smc_putc (*s++);
315 }
316}
317
318static int
319smc_getc(void)
wdenk4a9cbbe2002-08-27 09:48:53 +0000320{
321 volatile cbd_t *rbdf;
322 volatile unsigned char *buf;
323 volatile smc_uart_t *up;
wdenk8bde7f72003-06-27 21:31:46 +0000324 volatile immap_t *im = (immap_t *)CFG_IMMR;
wdenk4a9cbbe2002-08-27 09:48:53 +0000325 volatile cpm8xx_t *cpmp = &(im->im_cpm);
326 unsigned char c;
327
328 up = (smc_uart_t *)&cpmp->cp_dparam[PROFF_SMC];
329
330 rbdf = (cbd_t *)&cpmp->cp_dpmem[up->smc_rbase];
331
332 /* Wait for character to show up.
333 */
334 buf = (unsigned char *)rbdf->cbd_bufaddr;
wdenkd0fb80c2003-01-11 09:48:40 +0000335
wdenk4a9cbbe2002-08-27 09:48:53 +0000336 while (rbdf->cbd_sc & BD_SC_EMPTY)
wdenkd0fb80c2003-01-11 09:48:40 +0000337 WATCHDOG_RESET ();
338
wdenk4a9cbbe2002-08-27 09:48:53 +0000339 c = *buf;
340 rbdf->cbd_sc |= BD_SC_EMPTY;
341
342 return(c);
343}
344
wdenk281e00a2004-08-01 22:48:16 +0000345static int
346smc_tstc(void)
wdenk4a9cbbe2002-08-27 09:48:53 +0000347{
348 volatile cbd_t *rbdf;
349 volatile smc_uart_t *up;
wdenk8bde7f72003-06-27 21:31:46 +0000350 volatile immap_t *im = (immap_t *)CFG_IMMR;
wdenk4a9cbbe2002-08-27 09:48:53 +0000351 volatile cpm8xx_t *cpmp = &(im->im_cpm);
352
353 up = (smc_uart_t *)&cpmp->cp_dparam[PROFF_SMC];
354
355 rbdf = (cbd_t *)&cpmp->cp_dpmem[up->smc_rbase];
356
357 return(!(rbdf->cbd_sc & BD_SC_EMPTY));
358}
359
wdenk281e00a2004-08-01 22:48:16 +0000360struct serial_device serial_smc_device =
361{
362 "serial_smc",
363 "SMC",
364 smc_init,
365 smc_setbrg,
366 smc_getc,
367 smc_tstc,
368 smc_putc,
369 smc_puts,
370};
wdenk4a9cbbe2002-08-27 09:48:53 +0000371
wdenk281e00a2004-08-01 22:48:16 +0000372#endif /* CONFIG_8xx_CONS_SMC1 || CONFIG_8xx_CONS_SMC2 */
373
374#if defined(CONFIG_8xx_CONS_SCC1) || defined(CONFIG_8xx_CONS_SCC2) || \
375 defined(CONFIG_8xx_CONS_SCC3) || defined(CONFIG_8xx_CONS_SCC4)
376
377static void
378scc_setbrg (void)
379{
380 volatile immap_t *im = (immap_t *)CFG_IMMR;
381 volatile cpm8xx_t *cp = &(im->im_cpm);
382
383 /* Set up the baud rate generator.
384 * See 8xx_io/commproc.c for details.
385 *
386 * Wire BRG1 to SCCx
387 */
388
389 cp->cp_sicr &= ~(0x000000FF << (8 * SCC_INDEX));
390
391 serial_setdivisor(cp);
392}
393
394static int scc_init (void)
wdenk4a9cbbe2002-08-27 09:48:53 +0000395{
wdenk8bde7f72003-06-27 21:31:46 +0000396 volatile immap_t *im = (immap_t *)CFG_IMMR;
wdenk4a9cbbe2002-08-27 09:48:53 +0000397 volatile scc_t *sp;
398 volatile scc_uart_t *up;
399 volatile cbd_t *tbdf, *rbdf;
400 volatile cpm8xx_t *cp = &(im->im_cpm);
401 uint dpaddr;
402#if (SCC_INDEX != 2) || !defined(CONFIG_MPC850)
403 volatile iop8xx_t *ip = (iop8xx_t *)&(im->im_ioport);
404#endif
405
406 /* initialize pointers to SCC */
407
408 sp = (scc_t *) &(cp->cp_scc[SCC_INDEX]);
409 up = (scc_uart_t *) &cp->cp_dparam[PROFF_SCC];
410
411#if defined(CONFIG_LWMON) && defined(CONFIG_8xx_CONS_SCC2)
412 { /* Disable Ethernet, enable Serial */
413 uchar c;
414
415 c = pic_read (0x61);
416 c &= ~0x40; /* enable COM3 */
417 c |= 0x80; /* disable Ethernet */
418 pic_write (0x61, c);
419
420 /* enable RTS2 */
421 cp->cp_pbpar |= 0x2000;
422 cp->cp_pbdat |= 0x2000;
423 cp->cp_pbdir |= 0x2000;
424 }
425#endif /* CONFIG_LWMON */
426
427 /* Disable transmitter/receiver.
428 */
429 sp->scc_gsmrl &= ~(SCC_GSMRL_ENR | SCC_GSMRL_ENT);
430
431#if (SCC_INDEX == 2) && defined(CONFIG_MPC850)
432 /*
433 * The MPC850 has SCC3 on Port B
434 */
435 cp->cp_pbpar |= 0x06;
436 cp->cp_pbdir &= ~0x06;
437 cp->cp_pbodr &= ~0x06;
438
439#elif (SCC_INDEX < 2) || !defined(CONFIG_IP860)
440 /*
441 * Standard configuration for SCC's is on Part A
442 */
443 ip->iop_papar |= ((3 << (2 * SCC_INDEX)));
444 ip->iop_padir &= ~((3 << (2 * SCC_INDEX)));
445 ip->iop_paodr &= ~((3 << (2 * SCC_INDEX)));
446#else
447 /*
448 * The IP860 has SCC3 and SCC4 on Port D
449 */
450 ip->iop_pdpar |= ((3 << (2 * SCC_INDEX)));
451#endif
452
453 /* Allocate space for two buffer descriptors in the DP ram.
454 */
455
456#ifdef CFG_ALLOC_DPRAM
457 dpaddr = dpram_alloc_align (sizeof(cbd_t)*2 + 2, 8) ;
458#else
wdenk281e00a2004-08-01 22:48:16 +0000459 dpaddr = CPM_SERIAL2_BASE ;
wdenk4a9cbbe2002-08-27 09:48:53 +0000460#endif
461
462 /* Enable SDMA.
463 */
464 im->im_siu_conf.sc_sdcr = 0x0001;
465
466 /* Set the physical address of the host memory buffers in
467 * the buffer descriptors.
468 */
469
470 rbdf = (cbd_t *)&cp->cp_dpmem[dpaddr];
471 rbdf->cbd_bufaddr = (uint) (rbdf+2);
472 rbdf->cbd_sc = 0;
473 tbdf = rbdf + 1;
474 tbdf->cbd_bufaddr = ((uint) (rbdf+2)) + 1;
475 tbdf->cbd_sc = 0;
476
477 /* Set up the baud rate generator.
478 */
wdenk281e00a2004-08-01 22:48:16 +0000479 scc_setbrg ();
wdenk4a9cbbe2002-08-27 09:48:53 +0000480
481 /* Set up the uart parameters in the parameter ram.
482 */
483 up->scc_genscc.scc_rbase = dpaddr;
484 up->scc_genscc.scc_tbase = dpaddr+sizeof(cbd_t);
485
486 /* Initialize Tx/Rx parameters.
487 */
488 while (cp->cp_cpcr & CPM_CR_FLG) /* wait if cp is busy */
489 ;
490 cp->cp_cpcr = mk_cr_cmd(CPM_CR_CH_SCC, CPM_CR_INIT_TRX) | CPM_CR_FLG;
491
492 while (cp->cp_cpcr & CPM_CR_FLG) /* wait if cp is busy */
493 ;
494
495 up->scc_genscc.scc_rfcr = SCC_EB | 0x05;
496 up->scc_genscc.scc_tfcr = SCC_EB | 0x05;
497
498 up->scc_genscc.scc_mrblr = 1; /* Single character receive */
499 up->scc_maxidl = 0; /* disable max idle */
500 up->scc_brkcr = 1; /* send one break character on stop TX */
501 up->scc_parec = 0;
502 up->scc_frmec = 0;
503 up->scc_nosec = 0;
504 up->scc_brkec = 0;
505 up->scc_uaddr1 = 0;
506 up->scc_uaddr2 = 0;
507 up->scc_toseq = 0;
508 up->scc_char1 = 0x8000;
509 up->scc_char2 = 0x8000;
510 up->scc_char3 = 0x8000;
511 up->scc_char4 = 0x8000;
512 up->scc_char5 = 0x8000;
513 up->scc_char6 = 0x8000;
514 up->scc_char7 = 0x8000;
515 up->scc_char8 = 0x8000;
516 up->scc_rccm = 0xc0ff;
517
518 /* Set low latency / small fifo.
519 */
520 sp->scc_gsmrh = SCC_GSMRH_RFW;
521
522 /* Set SCC(x) clock mode to 16x
523 * See 8xx_io/commproc.c for details.
524 *
525 * Wire BRG1 to SCCn
526 */
527
528 /* Set UART mode, clock divider 16 on Tx and Rx
529 */
wdenk281e00a2004-08-01 22:48:16 +0000530 sp->scc_gsmrl &= ~0xF;
wdenk4a9cbbe2002-08-27 09:48:53 +0000531 sp->scc_gsmrl |=
532 (SCC_GSMRL_MODE_UART | SCC_GSMRL_TDCR_16 | SCC_GSMRL_RDCR_16);
533
wdenk281e00a2004-08-01 22:48:16 +0000534 sp->scc_psmr = 0;
wdenk4a9cbbe2002-08-27 09:48:53 +0000535 sp->scc_psmr |= SCU_PSMR_CL;
536
537 /* Mask all interrupts and remove anything pending.
538 */
539 sp->scc_sccm = 0;
540 sp->scc_scce = 0xffff;
541 sp->scc_dsr = 0x7e7e;
542 sp->scc_psmr = 0x3000;
543
544 /* Make the first buffer the only buffer.
545 */
546 tbdf->cbd_sc |= BD_SC_WRAP;
547 rbdf->cbd_sc |= BD_SC_EMPTY | BD_SC_WRAP;
548
549 /* Enable transmitter/receiver.
550 */
551 sp->scc_gsmrl |= (SCC_GSMRL_ENR | SCC_GSMRL_ENT);
552
553 return (0);
554}
555
wdenk281e00a2004-08-01 22:48:16 +0000556static void
557scc_putc(const char c)
wdenk4a9cbbe2002-08-27 09:48:53 +0000558{
559 volatile cbd_t *tbdf;
560 volatile char *buf;
561 volatile scc_uart_t *up;
wdenk8bde7f72003-06-27 21:31:46 +0000562 volatile immap_t *im = (immap_t *)CFG_IMMR;
wdenk4a9cbbe2002-08-27 09:48:53 +0000563 volatile cpm8xx_t *cpmp = &(im->im_cpm);
564
wdenk281e00a2004-08-01 22:48:16 +0000565#ifdef CONFIG_MODEM_SUPPORT
wdenk281e00a2004-08-01 22:48:16 +0000566 if (gd->be_quiet)
567 return;
568#endif
569
wdenk4a9cbbe2002-08-27 09:48:53 +0000570 if (c == '\n')
wdenk281e00a2004-08-01 22:48:16 +0000571 scc_putc ('\r');
wdenk4a9cbbe2002-08-27 09:48:53 +0000572
573 up = (scc_uart_t *)&cpmp->cp_dparam[PROFF_SCC];
574
575 tbdf = (cbd_t *)&cpmp->cp_dpmem[up->scc_genscc.scc_tbase];
576
577 /* Wait for last character to go.
578 */
579
580 buf = (char *)tbdf->cbd_bufaddr;
wdenk4a9cbbe2002-08-27 09:48:53 +0000581
582 *buf = c;
583 tbdf->cbd_datlen = 1;
584 tbdf->cbd_sc |= BD_SC_READY;
585 __asm__("eieio");
wdenkd0fb80c2003-01-11 09:48:40 +0000586
587 while (tbdf->cbd_sc & BD_SC_READY) {
wdenk4a9cbbe2002-08-27 09:48:53 +0000588 __asm__("eieio");
wdenkd0fb80c2003-01-11 09:48:40 +0000589 WATCHDOG_RESET ();
590 }
wdenk4a9cbbe2002-08-27 09:48:53 +0000591}
592
wdenk281e00a2004-08-01 22:48:16 +0000593static void
594scc_puts (const char *s)
595{
596 while (*s) {
597 scc_putc (*s++);
598 }
599}
600
601static int
602scc_getc(void)
wdenk4a9cbbe2002-08-27 09:48:53 +0000603{
604 volatile cbd_t *rbdf;
605 volatile unsigned char *buf;
606 volatile scc_uart_t *up;
wdenk8bde7f72003-06-27 21:31:46 +0000607 volatile immap_t *im = (immap_t *)CFG_IMMR;
wdenk4a9cbbe2002-08-27 09:48:53 +0000608 volatile cpm8xx_t *cpmp = &(im->im_cpm);
609 unsigned char c;
610
611 up = (scc_uart_t *)&cpmp->cp_dparam[PROFF_SCC];
612
613 rbdf = (cbd_t *)&cpmp->cp_dpmem[up->scc_genscc.scc_rbase];
614
615 /* Wait for character to show up.
616 */
617 buf = (unsigned char *)rbdf->cbd_bufaddr;
wdenkd0fb80c2003-01-11 09:48:40 +0000618
wdenk4a9cbbe2002-08-27 09:48:53 +0000619 while (rbdf->cbd_sc & BD_SC_EMPTY)
wdenkd0fb80c2003-01-11 09:48:40 +0000620 WATCHDOG_RESET ();
621
wdenk4a9cbbe2002-08-27 09:48:53 +0000622 c = *buf;
623 rbdf->cbd_sc |= BD_SC_EMPTY;
624
625 return(c);
626}
627
wdenk281e00a2004-08-01 22:48:16 +0000628static int
629scc_tstc(void)
wdenk4a9cbbe2002-08-27 09:48:53 +0000630{
631 volatile cbd_t *rbdf;
632 volatile scc_uart_t *up;
wdenk8bde7f72003-06-27 21:31:46 +0000633 volatile immap_t *im = (immap_t *)CFG_IMMR;
wdenk4a9cbbe2002-08-27 09:48:53 +0000634 volatile cpm8xx_t *cpmp = &(im->im_cpm);
635
636 up = (scc_uart_t *)&cpmp->cp_dparam[PROFF_SCC];
637
638 rbdf = (cbd_t *)&cpmp->cp_dpmem[up->scc_genscc.scc_rbase];
639
640 return(!(rbdf->cbd_sc & BD_SC_EMPTY));
641}
642
wdenk281e00a2004-08-01 22:48:16 +0000643struct serial_device serial_scc_device =
wdenk4a9cbbe2002-08-27 09:48:53 +0000644{
wdenk281e00a2004-08-01 22:48:16 +0000645 "serial_scc",
646 "SCC",
647 scc_init,
648 scc_setbrg,
649 scc_getc,
650 scc_tstc,
651 scc_putc,
652 scc_puts,
653};
654
655#endif /* CONFIG_8xx_CONS_SCCx */
656
657#ifdef CONFIG_MODEM_SUPPORT
658void disable_putc(void)
659{
wdenk281e00a2004-08-01 22:48:16 +0000660 gd->be_quiet = 1;
wdenk4a9cbbe2002-08-27 09:48:53 +0000661}
662
wdenk281e00a2004-08-01 22:48:16 +0000663void enable_putc(void)
664{
wdenk281e00a2004-08-01 22:48:16 +0000665 gd->be_quiet = 0;
666}
667#endif
wdenk4a9cbbe2002-08-27 09:48:53 +0000668
669#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
670
671void
672kgdb_serial_init(void)
673{
wdenk281e00a2004-08-01 22:48:16 +0000674 int i = -1;
675
676 if (strcmp(default_serial_console()->ctlr, "SMC") == 0)
677 {
wdenk4a9cbbe2002-08-27 09:48:53 +0000678#if defined(CONFIG_8xx_CONS_SMC1)
wdenk281e00a2004-08-01 22:48:16 +0000679 i = 1;
wdenk4a9cbbe2002-08-27 09:48:53 +0000680#elif defined(CONFIG_8xx_CONS_SMC2)
wdenk281e00a2004-08-01 22:48:16 +0000681 i = 2;
wdenk4a9cbbe2002-08-27 09:48:53 +0000682#endif
wdenk281e00a2004-08-01 22:48:16 +0000683 }
684 else if (strcmp(default_serial_console()->ctlr, "SMC") == 0)
685 {
686#if defined(CONFIG_8xx_CONS_SCC1)
687 i = 1;
688#elif defined(CONFIG_8xx_CONS_SCC2)
689 i = 2;
690#elif defined(CONFIG_8xx_CONS_SCC3)
691 i = 3;
692#elif defined(CONFIG_8xx_CONS_SCC4)
693 i = 4;
694#endif
695 }
696
697 if (i >= 0)
698 {
699 serial_printf("[on %s%d] ", default_serial_console()->ctlr, i);
700 }
wdenk4a9cbbe2002-08-27 09:48:53 +0000701}
702
703void
704putDebugChar (int c)
705{
706 serial_putc (c);
707}
708
709void
710putDebugStr (const char *str)
711{
712 serial_puts (str);
713}
714
715int
716getDebugChar (void)
717{
718 return serial_getc();
719}
720
721void
722kgdb_interruptible (int yes)
723{
724 return;
725}
726#endif /* CFG_CMD_KGDB */
727
728#endif /* CONFIG_8xx_CONS_NONE */