blob: 9efd88e7ec9c87df91333bd714126bafd3f4f67d [file] [log] [blame]
Mike Frysinger9171fc82008-03-30 15:46:13 -04001/*
2 * U-boot - cpu.c CPU specific functions
3 *
4 * Copyright (c) 2005-2008 Analog Devices Inc.
5 *
6 * (C) Copyright 2000-2004
7 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
8 *
9 * Licensed under the GPL-2 or later.
10 */
11
12#include <common.h>
13#include <command.h>
14#include <asm/blackfin.h>
15#include <asm/cplb.h>
16#include <asm/mach-common/bits/core.h>
Mike Frysinger9171fc82008-03-30 15:46:13 -040017#include <asm/mach-common/bits/trace.h>
18
19#include "cpu.h"
20#include "serial.h"
21
Mike Frysinger9171fc82008-03-30 15:46:13 -040022__attribute__ ((__noreturn__))
23void cpu_init_f(ulong bootflag, ulong loaded_from_ldr)
24{
25 /* Build a NOP slide over the LDR jump block. Whee! */
26 serial_early_puts("NOP Slide\n");
27 char nops[0xC];
28 memset(nops, 0x00, sizeof(nops));
29 extern char _stext_l1;
30 memcpy(&_stext_l1 - sizeof(nops), nops, sizeof(nops));
31
32 if (!loaded_from_ldr) {
33 /* Relocate sections into L1 if the LDR didn't do it -- don't
34 * check length because the linker script does the size
35 * checking at build time.
36 */
37 serial_early_puts("L1 Relocate\n");
38 extern char _stext_l1, _etext_l1, _stext_l1_lma;
39 memcpy(&_stext_l1, &_stext_l1_lma, (&_etext_l1 - &_stext_l1));
40 extern char _sdata_l1, _edata_l1, _sdata_l1_lma;
41 memcpy(&_sdata_l1, &_sdata_l1_lma, (&_edata_l1 - &_sdata_l1));
42 }
43#if defined(__ADSPBF537__) || defined(__ADSPBF536__) || defined(__ADSPBF534__)
44 /* The BF537 bootrom will reset the EBIU_AMGCTL register on us
45 * after it has finished loading the LDR. So configure it again.
46 */
47 else
48 bfin_write_EBIU_AMGCTL(CONFIG_EBIU_AMGCTL_VAL);
49#endif
50
51#ifdef CONFIG_DEBUG_DUMP
52 /* Turn on hardware trace buffer */
53 bfin_write_TBUFCTL(TBUFPWR | TBUFEN);
54#endif
55
56#ifndef CONFIG_PANIC_HANG
57 /* Reset upon a double exception rather than just hanging.
58 * Do not do bfin_read on SWRST as that will reset status bits.
59 */
60 bfin_write_SWRST(DOUBLE_FAULT);
61#endif
62
63 serial_early_puts("Board init flash\n");
64 board_init_f(bootflag);
65}
66
67int exception_init(void)
68{
69 bfin_write_EVT3(trap);
70 return 0;
71}
72
73int irq_init(void)
74{
75#ifdef SIC_IMASK0
76 bfin_write_SIC_IMASK0(0);
77 bfin_write_SIC_IMASK1(0);
78# ifdef SIC_IMASK2
79 bfin_write_SIC_IMASK2(0);
80# endif
81#elif defined(SICA_IMASK0)
82 bfin_write_SICA_IMASK0(0);
83 bfin_write_SICA_IMASK1(0);
84#else
85 bfin_write_SIC_IMASK(0);
86#endif
87 bfin_write_EVT2(evt_default); /* NMI */
88 bfin_write_EVT5(evt_default); /* hardware error */
89 bfin_write_EVT6(evt_default); /* core timer */
90 bfin_write_EVT7(evt_default);
91 bfin_write_EVT8(evt_default);
92 bfin_write_EVT9(evt_default);
93 bfin_write_EVT10(evt_default);
94 bfin_write_EVT11(evt_default);
95 bfin_write_EVT12(evt_default);
96 bfin_write_EVT13(evt_default);
97 bfin_write_EVT14(evt_default);
98 bfin_write_EVT15(evt_default);
99 bfin_write_ILAT(0);
100 CSYNC();
Mike Frysingere4337962008-08-07 15:16:56 -0400101 /* enable hardware error irq */
102 irq_flags = 0x3f;
Mike Frysinger9171fc82008-03-30 15:46:13 -0400103 local_irq_enable();
Mike Frysinger9171fc82008-03-30 15:46:13 -0400104 return 0;
105}