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Heiko Schocher03efcb02013-08-05 16:00:38 +02001; General settings that can be overwritten in the host code
2; that calls the AISGen library.
3[General]
4
5; Can be 8 or 16 - used in emifa
6busWidth=8
7
8; SPIMASTER,I2CMASTER,EMIFA,NAND,EMAC,UART,PCI,HPI,USB,MMC_SD,VLYNQ,RAW
9BootMode=UART
10
11; 8,16,24 - used for SPI,I2C
12;AddrWidth=8
13
14; NO_CRC,SECTION_CRC,SINGLE_CRC
15crcCheckType=NO_CRC
16
17; This section allows setting the PLL0 system clock with a
18; specified multiplier and divider as shown. The clock source
19; can also be chosen for internal or external.
20; |------24|------16|-------8|-------0|
21; PLL0CFG0: | CLKMODE| PLLM | PREDIV | POSTDIV|
22; PLL0CFG1: | RSVD | PLLDIV1| PLLDIV3| PLLDIV7|
23;[PLL0CONFIG]
24;PLL0CFG0 = 0x00180001
25;PLL0CFG1 = 0x00000205
26
27[PLLANDCLOCKCONFIG]
28PLL0CFG0 = 0x00180001
29PLL0CFG1 = 0x00000205
30PERIPHCLKCFG = 0x00000051
31
32; This section allows setting up the PLL1. Usually this will
33; take place as part of the EMIF3a DDR setup. The format of
34; the input args is as follows:
35; |------24|------16|-------8|-------0|
36; PLL1CFG0: | PLLM| POSTDIV| PLLDIV1| PLLDIV2|
37; PLL1CFG1: | RSVD | PLLDIV3|
38[PLL1CONFIG]
39PLL1CFG0 = 0x18010001
40PLL1CFG1 = 0x00000002
41
42; This section lets us configure the peripheral interface
43; of the current booting peripheral (I2C, SPI, or UART).
44; Use with caution. The format of the PERIPHCLKCFG field
45; is as follows:
46; SPI: |------24|------16|-------8|-------0|
47; | RSVD |PRESCALE|
48;
49; I2C: |------24|------16|-------8|-------0|
50; | RSVD |PRESCALE| CLKL | CLKH |
51;
52; UART: |------24|------16|-------8|-------0|
53; | RSVD | OSR | DLH | DLL |
54[PERIPHCLKCFG]
55PERIPHCLKCFG = 0x00000051
56
57; This section can be used to configure the PLL1 and the EMIF3a registers
58; for starting the DDR2 interface.
59; See PLL1CONFIG section for the format of the PLL1CFG fields.
60; |------24|------16|-------8|-------0|
61; PLL1CFG0: | PLL1CFG |
62; PLL1CFG1: | PLL1CFG |
63; DDRPHYC1R: | DDRPHYC1R |
64; SDCR: | SDCR |
65; SDTIMR: | SDTIMR |
66; SDTIMR2: | SDTIMR2 |
67; SDRCR: | SDRCR |
68; CLK2XSRC: | CLK2XSRC |
69[EMIF3DDR]
70PLL1CFG0 = 0x18010001
71PLL1CFG1 = 0x00000002
72DDRPHYC1R = 0x000000C2
73SDCR = 0x0017C432
74SDTIMR = 0x26922A09
75SDTIMR2 = 0x4414C722
76SDRCR = 0x00000498
77CLK2XSRC = 0x00000000
78
79; This section can be used to configure the EMIFA to use
80; CS0 as an SDRAM interface. The fields required to do this
81; are given below.
82; |------24|------16|-------8|-------0|
83; SDBCR: | SDBCR |
84; SDTIMR: | SDTIMR |
85; SDRSRPDEXIT: | SDRSRPDEXIT |
86; SDRCR: | SDRCR |
87; DIV4p5_CLK_ENABLE: | DIV4p5_CLK_ENABLE |
88;[EMIF25SDRAM]
89;SDBCR = 0x00004421
90;SDTIMR = 0x42215810
91;SDRSRPDEXIT = 0x00000009
92;SDRCR = 0x00000410
93;DIV4p5_CLK_ENABLE = 0x00000001
94
95; This section can be used to configure the async chip selects
96; of the EMIFA (CS2-CS5). The fields required to do this
97; are given below.
98; |------24|------16|-------8|-------0|
99; A1CR: | A1CR |
100; A2CR: | A2CR |
101; A3CR: | A3CR |
102; A4CR: | A4CR |
103; NANDFCR: | NANDFCR |
104;[EMIF25ASYNC]
105;A1CR = 0x00000000
106;A2CR = 0x00000000
107;A3CR = 0x00000000
108;A4CR = 0x00000000
109;NANDFCR = 0x00000000
110[EMIF25ASYNC]
111A1CR = 0x00000000
112A2CR = 0x3FFFFFFE
113A3CR = 0x00000000
114A4CR = 0x00000000
115NANDFCR = 0x00000012
116
117; This section should be used in place of PLL0CONFIG when
118; the I2C, SPI, or UART modes are being used. This ensures that
119; the system PLL and the peripheral's clocks are changed together.
120; See PLL0CONFIG section for the format of the PLL0CFG fields.
121; See PERIPHCLKCFG section for the format of the CLKCFG field.
122; |------24|------16|-------8|-------0|
123; PLL0CFG0: | PLL0CFG |
124; PLL0CFG1: | PLL0CFG |
125; PERIPHCLKCFG: | CLKCFG |
126;[PLLANDCLOCKCONFIG]
127;PLL0CFG0 = 0x00180001
128;PLL0CFG1 = 0x00000205
129;PERIPHCLKCFG = 0x00010032
130
131; This section should be used to setup the power state of modules
132; of the two PSCs. This section can be included multiple times to
133; allow the configuration of any or all of the device modules.
134; |------24|------16|-------8|-------0|
135; LPSCCFG: | PSCNUM | MODULE | PD | STATE |
136;[PSCCONFIG]
137;LPSCCFG=
138
139; This section allows setting of a single PINMUX register.
140; This section can be included multiple times to allow setting
141; as many PINMUX registers as needed.
142; |------24|------16|-------8|-------0|
143; REGNUM: | regNum |
144; MASK: | mask |
145; VALUE: | value |
146;[PINMUX]
147;REGNUM = 5
148;MASK = 0x00FF0000
149;VALUE = 0x00880000
150
151; No Params required - simply include this section for the fast boot
152; function to be called
153;[FASTBOOT]
154
155; This section allows setting up the PLL1. Usually this will
156; take place as part of the EMIF3a DDR setup. The format of
157; the input args is as follows:
158; |------24|------16|-------8|-------0|
159; PLL1CFG0: | PLLM| POSTDIV| PLLDIV1| PLLDIV2|
160; PLL1CFG1: | RSVD | PLLDIV3|
161;[PLL1CONFIG]
162;PLL1CFG0 = 0x15010001
163;PLL1CFG1 = 0x00000002
164
165; This section can be used to configure the PLL1 and the EMIF3a registers
166; for starting the DDR2 interface on ARM-boot D800K002 devices.
167; |------24|------16|-------8|-------0|
168; DDRPHYC1R: | DDRPHYC1R |
169; SDCR: | SDCR |
170; SDTIMR: | SDTIMR |
171; SDTIMR2: | SDTIMR2 |
172; SDRCR: | SDRCR |
173; CLK2XSRC: | CLK2XSRC |
174;[ARM_EMIF3DDR_PATCHFXN]
175;DDRPHYC1R = 0x000000C2
176;SDCR = 0x0017C432
177;SDTIMR = 0x26922A09
178;SDTIMR2 = 0x4414C722
179;SDRCR = 0x00000498
180;CLK2XSRC = 0x00000000
181
182; This section can be used to configure the PLL1 and the EMIF3a registers
183; for starting the DDR2 interface on DSP-boot D800K002 devices.
184; |------24|------16|-------8|-------0|
185; DDRPHYC1R: | DDRPHYC1R |
186; SDCR: | SDCR |
187; SDTIMR: | SDTIMR |
188; SDTIMR2: | SDTIMR2 |
189; SDRCR: | SDRCR |
190; CLK2XSRC: | CLK2XSRC |
191;[DSP_EMIF3DDR_PATCHFXN]
192;DDRPHYC1R = 0x000000C4
193;SDCR = 0x08134632
194;SDTIMR = 0x26922A09
195;SDTIMR2 = 0x0014C722
196;SDRCR = 0x00000492
197;CLK2XSRC = 0x00000000
198
199;[INPUTFILE]
200;FILENAME=u-boot.bin
201;LOADADDRESS=0xC1080000
202;ENTRYPOINTADDRESS=0xC1080000