blob: cb0535c151db575d6633e52883e2dc4b87978184 [file] [log] [blame]
Anton Vorontsovfab6f552008-01-09 20:57:47 +03001/*
2 * Copyright (C) 2006 Freescale Semiconductor, Inc.
3 * Dave Liu <daveliu@freescale.com>
4 *
5 * Copyright (C) 2007 Logic Product Development, Inc.
6 * Peter Barada <peterb@logicpd.com>
7 *
8 * Copyright (C) 2007 MontaVista Software, Inc.
9 * Anton Vorontsov <avorontsov@ru.mvista.com>
10 *
11 * This program is free software; you can redistribute it and/or
12 * modify it under the terms of the GNU General Public License as
13 * published by the Free Software Foundation; either version 2 of
14 * the License, or (at your option) any later version.
15 */
16
17#ifndef __CONFIG_H
18#define __CONFIG_H
19
Anton Vorontsovfab6f552008-01-09 20:57:47 +030020/*
21 * High Level Configuration Options
22 */
23#define CONFIG_E300 1 /* E300 family */
24#define CONFIG_QE 1 /* Has QE */
Peter Tyser0f898602009-05-22 17:23:24 -050025#define CONFIG_MPC83xx 1 /* MPC83xx family */
Anton Vorontsovfab6f552008-01-09 20:57:47 +030026#define CONFIG_MPC8360 1 /* MPC8360 CPU specific */
27#define CONFIG_MPC8360ERDK 1 /* MPC8360ERDK board specific */
28
29/*
30 * System Clock Setup
31 */
32#ifdef CONFIG_CLKIN_33MHZ
Anton Vorontsovf700e7d2008-03-24 20:47:05 +030033#define CONFIG_83XX_CLKIN 33333333
34#define CONFIG_SYS_CLK_FREQ 33333333
Anton Vorontsovfab6f552008-01-09 20:57:47 +030035#define PCI_33M 1
36#define HRCWL_CSB_TO_CLKIN_MPC8360ERDK HRCWL_CSB_TO_CLKIN_10X1
37#else
38#define CONFIG_83XX_CLKIN 66000000
39#define CONFIG_SYS_CLK_FREQ 66000000
40#define PCI_66M 1
41#define HRCWL_CSB_TO_CLKIN_MPC8360ERDK HRCWL_CSB_TO_CLKIN_5X1
42#endif /* CONFIG_CLKIN_33MHZ */
43
44/*
45 * Hardware Reset Configuration Word
46 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020047#define CONFIG_SYS_HRCW_LOW (\
Anton Vorontsovfab6f552008-01-09 20:57:47 +030048 HRCWL_LCL_BUS_TO_SCB_CLK_1X1 |\
49 HRCWL_DDR_TO_SCB_CLK_1X1 |\
50 HRCWL_CSB_TO_CLKIN_MPC8360ERDK |\
51 HRCWL_CORE_TO_CSB_2X1 |\
52 HRCWL_CE_TO_PLL_1X15)
53
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020054#define CONFIG_SYS_HRCW_HIGH (\
Anton Vorontsovfab6f552008-01-09 20:57:47 +030055 HRCWH_PCI_HOST |\
56 HRCWH_PCI1_ARBITER_ENABLE |\
57 HRCWH_PCICKDRV_ENABLE |\
58 HRCWH_CORE_ENABLE |\
59 HRCWH_FROM_0X00000100 |\
60 HRCWH_BOOTSEQ_DISABLE |\
61 HRCWH_SW_WATCHDOG_DISABLE |\
62 HRCWH_ROM_LOC_LOCAL_16BIT |\
63 HRCWH_SECONDARY_DDR_DISABLE |\
64 HRCWH_BIG_ENDIAN |\
65 HRCWH_LALE_EARLY)
66
67/*
68 * System IO Config
69 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020070#define CONFIG_SYS_SICRH 0x00000000
71#define CONFIG_SYS_SICRL 0x40000000
Anton Vorontsovfab6f552008-01-09 20:57:47 +030072
73#define CONFIG_BOARD_EARLY_INIT_F /* call board_pre_init */
74#define CONFIG_BOARD_EARLY_INIT_R
75
76/*
77 * IMMR new address
78 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020079#define CONFIG_SYS_IMMR 0xE0000000
Anton Vorontsovfab6f552008-01-09 20:57:47 +030080
81/*
82 * DDR Setup
83 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020084#define CONFIG_SYS_DDR_BASE 0x00000000 /* DDR is system memory */
85#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_BASE
86#define CONFIG_SYS_DDR_SDRAM_BASE CONFIG_SYS_DDR_BASE
87#define CONFIG_SYS_DDR_SDRAM_CLK_CNTL (DDR_SDRAM_CLK_CNTL_SS_EN | \
Anton Vorontsovfab6f552008-01-09 20:57:47 +030088 DDR_SDRAM_CLK_CNTL_CLK_ADJUST_05)
89
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020090#define CONFIG_SYS_83XX_DDR_USES_CS0
Anton Vorontsovfab6f552008-01-09 20:57:47 +030091
Anton Vorontsovd892b2d2008-03-24 20:46:57 +030092#define CONFIG_DDR_ECC /* support DDR ECC function */
93#define CONFIG_DDR_ECC_CMD /* Use DDR ECC user commands */
Anton Vorontsovfab6f552008-01-09 20:57:47 +030094
95/*
96 * DDRCDR - DDR Control Driver Register
97 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020098#define CONFIG_SYS_DDRCDR_VALUE 0x80080001
Anton Vorontsovfab6f552008-01-09 20:57:47 +030099
100#undef CONFIG_SPD_EEPROM /* Do not use SPD EEPROM for DDR setup */
101
102/*
103 * Manually set up DDR parameters
104 */
105#define CONFIG_DDR_II
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200106#define CONFIG_SYS_DDR_SIZE 256 /* MB */
107#define CONFIG_SYS_DDR_CS0_BNDS 0x0000000f
108#define CONFIG_SYS_DDR_CS0_CONFIG (CSCONFIG_EN | CSCONFIG_ROW_BIT_13 | \
Anton Vorontsovd892b2d2008-03-24 20:46:57 +0300109 CSCONFIG_COL_BIT_10 | CSCONFIG_ODT_WR_ACS)
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200110#define CONFIG_SYS_DDR_SDRAM_CFG (SDRAM_CFG_SDRAM_TYPE_DDR2 | SDRAM_CFG_ECC_EN)
111#define CONFIG_SYS_DDR_SDRAM_CFG2 0x00001000
112#define CONFIG_SYS_DDR_CLK_CNTL (DDR_SDRAM_CLK_CNTL_CLK_ADJUST_05)
113#define CONFIG_SYS_DDR_INTERVAL ((256 << SDRAM_INTERVAL_BSTOPRE_SHIFT) | \
Anton Vorontsovd892b2d2008-03-24 20:46:57 +0300114 (1115 << SDRAM_INTERVAL_REFINT_SHIFT))
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200115#define CONFIG_SYS_DDR_MODE 0x47800432
116#define CONFIG_SYS_DDR_MODE2 0x8000c000
Anton Vorontsovd892b2d2008-03-24 20:46:57 +0300117
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200118#define CONFIG_SYS_DDR_TIMING_0 ((2 << TIMING_CFG0_MRS_CYC_SHIFT) | \
Anton Vorontsovd892b2d2008-03-24 20:46:57 +0300119 (9 << TIMING_CFG0_ODT_PD_EXIT_SHIFT) | \
120 (3 << TIMING_CFG0_PRE_PD_EXIT_SHIFT) | \
121 (3 << TIMING_CFG0_ACT_PD_EXIT_SHIFT) | \
122 (0 << TIMING_CFG0_WWT_SHIFT) | \
123 (0 << TIMING_CFG0_RRT_SHIFT) | \
124 (0 << TIMING_CFG0_WRT_SHIFT) | \
125 (0 << TIMING_CFG0_RWT_SHIFT))
126
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200127#define CONFIG_SYS_DDR_TIMING_1 (( TIMING_CFG1_CASLAT_30) | \
Anton Vorontsovd892b2d2008-03-24 20:46:57 +0300128 ( 2 << TIMING_CFG1_WRTORD_SHIFT) | \
129 ( 2 << TIMING_CFG1_ACTTOACT_SHIFT) | \
130 ( 3 << TIMING_CFG1_WRREC_SHIFT) | \
131 (10 << TIMING_CFG1_REFREC_SHIFT) | \
132 ( 3 << TIMING_CFG1_ACTTORW_SHIFT) | \
133 ( 8 << TIMING_CFG1_ACTTOPRE_SHIFT) | \
134 ( 3 << TIMING_CFG1_PRETOACT_SHIFT))
135
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200136#define CONFIG_SYS_DDR_TIMING_2 ((9 << TIMING_CFG2_FOUR_ACT_SHIFT) | \
Anton Vorontsovd892b2d2008-03-24 20:46:57 +0300137 (4 << TIMING_CFG2_CKE_PLS_SHIFT) | \
138 (2 << TIMING_CFG2_WR_DATA_DELAY_SHIFT) | \
139 (2 << TIMING_CFG2_RD_TO_PRE_SHIFT) | \
140 (2 << TIMING_CFG2_WR_LAT_DELAY_SHIFT) | \
141 (0 << TIMING_CFG2_ADD_LAT_SHIFT) | \
142 (0 << TIMING_CFG2_CPO_SHIFT))
143
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200144#define CONFIG_SYS_DDR_TIMING_3 0x00000000
Anton Vorontsovfab6f552008-01-09 20:57:47 +0300145
146/*
147 * Memory test
148 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200149#undef CONFIG_SYS_DRAM_TEST /* memory test, takes time */
150#define CONFIG_SYS_MEMTEST_START 0x00000000 /* memtest region */
151#define CONFIG_SYS_MEMTEST_END 0x00100000
Anton Vorontsovfab6f552008-01-09 20:57:47 +0300152
153/*
154 * The reserved memory
155 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200156#define CONFIG_SYS_MONITOR_BASE TEXT_BASE /* start of monitor */
157#define CONFIG_SYS_FLASH_BASE 0xFF800000 /* FLASH base address */
Anton Vorontsovfab6f552008-01-09 20:57:47 +0300158
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200159#if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE)
160#define CONFIG_SYS_RAMBOOT
Anton Vorontsovfab6f552008-01-09 20:57:47 +0300161#else
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200162#undef CONFIG_SYS_RAMBOOT
Anton Vorontsovfab6f552008-01-09 20:57:47 +0300163#endif
164
Anatolij Gustschin8e150882009-04-23 21:29:34 +0200165#define CONFIG_SYS_MONITOR_LEN (384 * 1024) /* Reserve 384 kB for Mon */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200166#define CONFIG_SYS_MALLOC_LEN (128 * 1024) /* Reserved for malloc */
Anton Vorontsovfab6f552008-01-09 20:57:47 +0300167
168/*
169 * Initial RAM Base Address Setup
170 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200171#define CONFIG_SYS_INIT_RAM_LOCK 1
172#define CONFIG_SYS_INIT_RAM_ADDR 0xE6000000 /* Initial RAM address */
173#define CONFIG_SYS_INIT_RAM_END 0x1000 /* End of used area in RAM */
174#define CONFIG_SYS_GBL_DATA_SIZE 0x100 /* num bytes initial data */
175#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE)
Anton Vorontsovfab6f552008-01-09 20:57:47 +0300176
177/*
178 * Local Bus Configuration & Clock Setup
179 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200180#define CONFIG_SYS_LCRR (LCRR_DBYP | LCRR_CLKDIV_4)
181#define CONFIG_SYS_LBC_LBCR 0x00000000
Anton Vorontsovfab6f552008-01-09 20:57:47 +0300182
183/*
184 * FLASH on the Local Bus
185 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200186#define CONFIG_SYS_FLASH_CFI /* use the Common Flash Interface */
Jean-Christophe PLAGNIOL-VILLARD00b18832008-08-13 01:40:42 +0200187#define CONFIG_FLASH_CFI_DRIVER /* use the CFI driver */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200188#define CONFIG_SYS_FLASH_SIZE 8 /* max FLASH size is 32M */
189#define CONFIG_SYS_FLASH_PROTECTION 1 /* Use intel Flash protection. */
Anton Vorontsovfab6f552008-01-09 20:57:47 +0300190
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200191#define CONFIG_SYS_LBLAWBAR0_PRELIM CONFIG_SYS_FLASH_BASE /* Window base at flash base */
192#define CONFIG_SYS_LBLAWAR0_PRELIM 0x80000018 /* 32MB window size */
Anton Vorontsovfab6f552008-01-09 20:57:47 +0300193
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200194#define CONFIG_SYS_BR0_PRELIM (CONFIG_SYS_FLASH_BASE | /* Flash Base address */ \
Anton Vorontsovfab6f552008-01-09 20:57:47 +0300195 (2 << BR_PS_SHIFT) | /* 16 bit port size */ \
196 BR_V) /* valid */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200197#define CONFIG_SYS_OR0_PRELIM ((~(CONFIG_SYS_FLASH_SIZE - 1) << 20) | OR_UPM_XAM | \
Anton Vorontsovf9023af2008-05-29 18:14:56 +0400198 OR_GPCM_CSNT | OR_GPCM_ACS_DIV2 | \
Anton Vorontsovfab6f552008-01-09 20:57:47 +0300199 OR_GPCM_XACS | OR_GPCM_SCY_15 | \
200 OR_GPCM_TRLX | OR_GPCM_EHTR | OR_GPCM_EAD)
201
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200202#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* number of banks */
203#define CONFIG_SYS_MAX_FLASH_SECT 256 /* max sectors per device */
Anton Vorontsovfab6f552008-01-09 20:57:47 +0300204
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200205#undef CONFIG_SYS_FLASH_CHECKSUM
Anton Vorontsovfab6f552008-01-09 20:57:47 +0300206
207/*
208 * NAND flash on the local bus
209 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200210#define CONFIG_SYS_NAND_BASE 0x60000000
Anton Vorontsov7ad95942008-03-24 20:46:51 +0300211#define CONFIG_CMD_NAND 1
212#define CONFIG_NAND_FSL_UPM 1
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200213#define CONFIG_SYS_MAX_NAND_DEVICE 1
Anton Vorontsov7ad95942008-03-24 20:46:51 +0300214#define CONFIG_MTD_NAND_VERIFY_WRITE
Kim Phillipsd9ac3d52009-06-15 11:51:47 -0500215#define CONFIG_SYS_64BIT_VSPRINTF /* needed for nand_util.c */
Anton Vorontsovfab6f552008-01-09 20:57:47 +0300216
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200217#define CONFIG_SYS_LBLAWBAR1_PRELIM CONFIG_SYS_NAND_BASE
218#define CONFIG_SYS_LBLAWAR1_PRELIM 0x8000001b /* Access window size 4K */
Anton Vorontsovfab6f552008-01-09 20:57:47 +0300219
220/* Port size 8 bit, UPMA */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200221#define CONFIG_SYS_BR1_PRELIM (CONFIG_SYS_NAND_BASE | 0x00000881)
222#define CONFIG_SYS_OR1_PRELIM 0xfc000001
Anton Vorontsovfab6f552008-01-09 20:57:47 +0300223
224/*
225 * Fujitsu MB86277 (MINT) graphics controller
226 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200227#define CONFIG_SYS_VIDEO_BASE 0x70000000
Anton Vorontsovfab6f552008-01-09 20:57:47 +0300228
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200229#define CONFIG_SYS_LBLAWBAR2_PRELIM CONFIG_SYS_VIDEO_BASE
230#define CONFIG_SYS_LBLAWAR2_PRELIM 0x80000019 /* Access window size 64MB */
Anton Vorontsovfab6f552008-01-09 20:57:47 +0300231
232/* Port size 32 bit, UPMB */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200233#define CONFIG_SYS_BR2_PRELIM (CONFIG_SYS_VIDEO_BASE | 0x000018a1) /* PS=11, UPMB */
234#define CONFIG_SYS_OR2_PRELIM 0xfc000001 /* (64MB, EAD=1) */
Anton Vorontsovfab6f552008-01-09 20:57:47 +0300235
236/*
237 * Serial Port
238 */
239#define CONFIG_CONS_INDEX 1
240#undef CONFIG_SERIAL_SOFTWARE_FIFO
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200241#define CONFIG_SYS_NS16550
242#define CONFIG_SYS_NS16550_SERIAL
243#define CONFIG_SYS_NS16550_REG_SIZE 1
244#define CONFIG_SYS_NS16550_CLK get_bus_freq(0)
Anton Vorontsovfab6f552008-01-09 20:57:47 +0300245
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200246#define CONFIG_SYS_BAUDRATE_TABLE \
Anton Vorontsovfab6f552008-01-09 20:57:47 +0300247 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 115200,}
248
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200249#define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_IMMR+0x4500)
250#define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_IMMR+0x4600)
Anton Vorontsovfab6f552008-01-09 20:57:47 +0300251
252#define CONFIG_CMDLINE_EDITING 1 /* add command line history */
253/* Use the HUSH parser */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200254#define CONFIG_SYS_HUSH_PARSER
255#ifdef CONFIG_SYS_HUSH_PARSER
256#define CONFIG_SYS_PROMPT_HUSH_PS2 "> "
Anton Vorontsovfab6f552008-01-09 20:57:47 +0300257#endif
258
259/* Pass open firmware flat tree */
260#define CONFIG_OF_LIBFDT 1
261#define CONFIG_OF_BOARD_SETUP 1
Anton Vorontsov3a0cfdd2008-03-24 20:47:02 +0300262#define CONFIG_OF_STDOUT_VIA_ALIAS
Anton Vorontsovfab6f552008-01-09 20:57:47 +0300263
264/* I2C */
265#define CONFIG_HARD_I2C /* I2C with hardware support */
266#undef CONFIG_SOFT_I2C /* I2C bit-banged */
267#define CONFIG_FSL_I2C
268#define CONFIG_I2C_MULTI_BUS
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200269#define CONFIG_SYS_I2C_SPEED 400000 /* I2C speed and slave address */
270#define CONFIG_SYS_I2C_SLAVE 0x7F
271#define CONFIG_SYS_I2C_NOPROBES {{0x52}} /* Don't probe these addrs */
272#define CONFIG_SYS_I2C_OFFSET 0x3000
273#define CONFIG_SYS_I2C2_OFFSET 0x3100
Anton Vorontsovfab6f552008-01-09 20:57:47 +0300274
275/*
276 * General PCI
277 * Addresses are mapped 1-1.
278 */
279#define CONFIG_PCI
Anton Vorontsovfab6f552008-01-09 20:57:47 +0300280
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200281#define CONFIG_SYS_PCI1_MEM_BASE 0x80000000
282#define CONFIG_SYS_PCI1_MEM_PHYS CONFIG_SYS_PCI1_MEM_BASE
283#define CONFIG_SYS_PCI1_MEM_SIZE 0x10000000 /* 256M */
284#define CONFIG_SYS_PCI1_MMIO_BASE 0x90000000
285#define CONFIG_SYS_PCI1_MMIO_PHYS CONFIG_SYS_PCI1_MMIO_BASE
286#define CONFIG_SYS_PCI1_MMIO_SIZE 0x10000000 /* 256M */
287#define CONFIG_SYS_PCI1_IO_BASE 0xE0300000
288#define CONFIG_SYS_PCI1_IO_PHYS 0xE0300000
289#define CONFIG_SYS_PCI1_IO_SIZE 0x100000 /* 1M */
Anton Vorontsovfab6f552008-01-09 20:57:47 +0300290
291#ifdef CONFIG_PCI
292
293#define CONFIG_NET_MULTI
294#define CONFIG_PCI_PNP /* do pci plug-and-play */
295
296#undef CONFIG_EEPRO100
297#undef CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200298#define CONFIG_SYS_PCI_SUBSYS_VENDORID 0x1957 /* Freescale */
Anton Vorontsovfab6f552008-01-09 20:57:47 +0300299
300#endif /* CONFIG_PCI */
301
302
303#ifndef CONFIG_NET_MULTI
304#define CONFIG_NET_MULTI 1
305#endif
306
307/*
308 * QE UEC ethernet configuration
309 */
310#define CONFIG_UEC_ETH
Kim Phillips711a7942008-01-15 14:05:14 -0600311#define CONFIG_ETHPRIME "FSL UEC0"
Anton Vorontsovfab6f552008-01-09 20:57:47 +0300312
313#define CONFIG_UEC_ETH1 /* GETH1 */
314
315#ifdef CONFIG_UEC_ETH1
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200316#define CONFIG_SYS_UEC1_UCC_NUM 0 /* UCC1 */
317#define CONFIG_SYS_UEC1_RX_CLK QE_CLK_NONE
318#define CONFIG_SYS_UEC1_TX_CLK QE_CLK9
319#define CONFIG_SYS_UEC1_ETH_TYPE GIGA_ETH
320#define CONFIG_SYS_UEC1_PHY_ADDR 2
321#define CONFIG_SYS_UEC1_INTERFACE_MODE ENET_1000_RGMII_RXID
Anton Vorontsovfab6f552008-01-09 20:57:47 +0300322#endif
323
324#define CONFIG_UEC_ETH2 /* GETH2 */
325
326#ifdef CONFIG_UEC_ETH2
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200327#define CONFIG_SYS_UEC2_UCC_NUM 1 /* UCC2 */
328#define CONFIG_SYS_UEC2_RX_CLK QE_CLK_NONE
329#define CONFIG_SYS_UEC2_TX_CLK QE_CLK4
330#define CONFIG_SYS_UEC2_ETH_TYPE GIGA_ETH
331#define CONFIG_SYS_UEC2_PHY_ADDR 4
332#define CONFIG_SYS_UEC2_INTERFACE_MODE ENET_1000_RGMII_RXID
Anton Vorontsovfab6f552008-01-09 20:57:47 +0300333#endif
334
335/*
336 * Environment
337 */
338
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200339#ifndef CONFIG_SYS_RAMBOOT
Jean-Christophe PLAGNIOL-VILLARD5a1aceb2008-09-10 22:48:04 +0200340#define CONFIG_ENV_IS_IN_FLASH 1
Anatolij Gustschin8e150882009-04-23 21:29:34 +0200341#define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE + CONFIG_SYS_MONITOR_LEN)
Jean-Christophe PLAGNIOL-VILLARD0e8d1582008-09-10 22:48:06 +0200342#define CONFIG_ENV_SECT_SIZE 0x20000 /* 128K(one sector) for env */
343#define CONFIG_ENV_SIZE 0x20000
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200344#else /* CONFIG_SYS_RAMBOOT */
345#define CONFIG_SYS_NO_FLASH 1 /* Flash is not usable now */
Jean-Christophe PLAGNIOL-VILLARD93f6d722008-09-10 22:48:00 +0200346#define CONFIG_ENV_IS_NOWHERE 1 /* Store ENV in memory only */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200347#define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - 0x1000)
Jean-Christophe PLAGNIOL-VILLARD0e8d1582008-09-10 22:48:06 +0200348#define CONFIG_ENV_SIZE 0x2000
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200349#endif /* CONFIG_SYS_RAMBOOT */
Anton Vorontsovfab6f552008-01-09 20:57:47 +0300350
351#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200352#define CONFIG_SYS_LOADS_BAUD_CHANGE 1 /* allow baudrate change */
Anton Vorontsovfab6f552008-01-09 20:57:47 +0300353
354/*
355 * BOOTP options
356 */
357#define CONFIG_BOOTP_BOOTFILESIZE
358#define CONFIG_BOOTP_BOOTPATH
359#define CONFIG_BOOTP_GATEWAY
360#define CONFIG_BOOTP_HOSTNAME
361
362
363/*
364 * Command line configuration.
365 */
366#include <config_cmd_default.h>
367
368#define CONFIG_CMD_PING
369#define CONFIG_CMD_I2C
370#define CONFIG_CMD_ASKENV
Anton Vorontsov3419eb62008-03-24 20:47:00 +0300371#define CONFIG_CMD_DHCP
Anton Vorontsovfab6f552008-01-09 20:57:47 +0300372
373#if defined(CONFIG_PCI)
374#define CONFIG_CMD_PCI
375#endif
376
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200377#if defined(CONFIG_SYS_RAMBOOT)
Mike Frysingerbdab39d2009-01-28 19:08:14 -0500378#undef CONFIG_CMD_SAVEENV
Anton Vorontsovfab6f552008-01-09 20:57:47 +0300379#undef CONFIG_CMD_LOADS
380#endif
381
382#undef CONFIG_WATCHDOG /* watchdog disabled */
383
384/*
385 * Miscellaneous configurable options
386 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200387#define CONFIG_SYS_LONGHELP /* undef to save memory */
388#define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */
389#define CONFIG_SYS_PROMPT "=> " /* Monitor Command Prompt */
Anton Vorontsovfab6f552008-01-09 20:57:47 +0300390
391#if defined(CONFIG_CMD_KGDB)
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200392 #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
Anton Vorontsovfab6f552008-01-09 20:57:47 +0300393#else
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200394 #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
Anton Vorontsovfab6f552008-01-09 20:57:47 +0300395#endif
396
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200397#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
398#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
399#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */
400#define CONFIG_SYS_HZ 1000 /* decrementer freq: 1ms ticks */
Anton Vorontsovfab6f552008-01-09 20:57:47 +0300401
402/*
403 * For booting Linux, the board info and command line data
404 * have to be in the first 8 MB of memory, since this is
405 * the maximum mapped by the Linux kernel during initialization.
406 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200407#define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
Anton Vorontsovfab6f552008-01-09 20:57:47 +0300408
409/*
410 * Core HID Setup
411 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200412#define CONFIG_SYS_HID0_INIT 0x000000000
413#define CONFIG_SYS_HID0_FINAL HID0_ENABLE_MACHINE_CHECK
414#define CONFIG_SYS_HID2 HID2_HBE
Anton Vorontsovfab6f552008-01-09 20:57:47 +0300415
416/*
Anton Vorontsovfab6f552008-01-09 20:57:47 +0300417 * MMU Setup
418 */
419
Becky Bruce31d82672008-05-08 19:02:12 -0500420#define CONFIG_HIGH_BATS 1 /* High BATs supported */
421
Anton Vorontsovfab6f552008-01-09 20:57:47 +0300422/* DDR: cache cacheable */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200423#define CONFIG_SYS_IBAT0L (CONFIG_SYS_SDRAM_BASE | BATL_PP_10 | BATL_MEMCOHERENCE)
424#define CONFIG_SYS_IBAT0U (CONFIG_SYS_SDRAM_BASE | BATU_BL_256M | BATU_VS | BATU_VP)
425#define CONFIG_SYS_DBAT0L CONFIG_SYS_IBAT0L
426#define CONFIG_SYS_DBAT0U CONFIG_SYS_IBAT0U
Anton Vorontsovfab6f552008-01-09 20:57:47 +0300427
428/* IMMRBAR & PCI IO: cache-inhibit and guarded */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200429#define CONFIG_SYS_IBAT1L (CONFIG_SYS_IMMR | BATL_PP_10 | \
Anton Vorontsovfab6f552008-01-09 20:57:47 +0300430 BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200431#define CONFIG_SYS_IBAT1U (CONFIG_SYS_IMMR | BATU_BL_4M | BATU_VS | BATU_VP)
432#define CONFIG_SYS_DBAT1L CONFIG_SYS_IBAT1L
433#define CONFIG_SYS_DBAT1U CONFIG_SYS_IBAT1U
Anton Vorontsovfab6f552008-01-09 20:57:47 +0300434
435/* NAND: cache-inhibit and guarded */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200436#define CONFIG_SYS_IBAT2L (CONFIG_SYS_NAND_BASE | BATL_PP_10 | BATL_CACHEINHIBIT |\
Anton Vorontsovfab6f552008-01-09 20:57:47 +0300437 BATL_GUARDEDSTORAGE)
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200438#define CONFIG_SYS_IBAT2U (CONFIG_SYS_NAND_BASE | BATU_BL_64M | BATU_VS | BATU_VP)
439#define CONFIG_SYS_DBAT2L CONFIG_SYS_IBAT2L
440#define CONFIG_SYS_DBAT2U CONFIG_SYS_IBAT2U
Anton Vorontsovfab6f552008-01-09 20:57:47 +0300441
442/* FLASH: icache cacheable, but dcache-inhibit and guarded */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200443#define CONFIG_SYS_IBAT3L (CONFIG_SYS_FLASH_BASE | BATL_PP_10 | BATL_MEMCOHERENCE)
444#define CONFIG_SYS_IBAT3U (CONFIG_SYS_FLASH_BASE | BATU_BL_32M | BATU_VS | BATU_VP)
445#define CONFIG_SYS_DBAT3L (CONFIG_SYS_FLASH_BASE | BATL_PP_10 | \
Anton Vorontsovfab6f552008-01-09 20:57:47 +0300446 BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200447#define CONFIG_SYS_DBAT3U CONFIG_SYS_IBAT3U
Anton Vorontsovfab6f552008-01-09 20:57:47 +0300448
449/* Stack in dcache: cacheable, no memory coherence */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200450#define CONFIG_SYS_IBAT4L (CONFIG_SYS_INIT_RAM_ADDR | BATL_PP_10)
451#define CONFIG_SYS_IBAT4U (CONFIG_SYS_INIT_RAM_ADDR | BATU_BL_128K | BATU_VS | BATU_VP)
452#define CONFIG_SYS_DBAT4L CONFIG_SYS_IBAT4L
453#define CONFIG_SYS_DBAT4U CONFIG_SYS_IBAT4U
Anton Vorontsovfab6f552008-01-09 20:57:47 +0300454
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200455#define CONFIG_SYS_IBAT5L (CONFIG_SYS_VIDEO_BASE | BATL_PP_10 | BATL_CACHEINHIBIT | \
Anton Vorontsovfab6f552008-01-09 20:57:47 +0300456 BATL_GUARDEDSTORAGE)
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200457#define CONFIG_SYS_IBAT5U (CONFIG_SYS_VIDEO_BASE | BATU_BL_64M | BATU_VS | BATU_VP)
458#define CONFIG_SYS_DBAT5L CONFIG_SYS_IBAT5L
459#define CONFIG_SYS_DBAT5U CONFIG_SYS_IBAT5U
Anton Vorontsovfab6f552008-01-09 20:57:47 +0300460
461#ifdef CONFIG_PCI
462/* PCI MEM space: cacheable */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200463#define CONFIG_SYS_IBAT6L (CONFIG_SYS_PCI1_MEM_PHYS | BATL_PP_10 | BATL_MEMCOHERENCE)
464#define CONFIG_SYS_IBAT6U (CONFIG_SYS_PCI1_MEM_PHYS | BATU_BL_256M | BATU_VS | BATU_VP)
465#define CONFIG_SYS_DBAT6L CONFIG_SYS_IBAT6L
466#define CONFIG_SYS_DBAT6U CONFIG_SYS_IBAT6U
Anton Vorontsovfab6f552008-01-09 20:57:47 +0300467/* PCI MMIO space: cache-inhibit and guarded */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200468#define CONFIG_SYS_IBAT7L (CONFIG_SYS_PCI1_MMIO_PHYS | BATL_PP_10 | \
Anton Vorontsovfab6f552008-01-09 20:57:47 +0300469 BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200470#define CONFIG_SYS_IBAT7U (CONFIG_SYS_PCI1_MMIO_PHYS | BATU_BL_256M | BATU_VS | BATU_VP)
471#define CONFIG_SYS_DBAT7L CONFIG_SYS_IBAT7L
472#define CONFIG_SYS_DBAT7U CONFIG_SYS_IBAT7U
Anton Vorontsovfab6f552008-01-09 20:57:47 +0300473#else /* CONFIG_PCI */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200474#define CONFIG_SYS_IBAT6L (0)
475#define CONFIG_SYS_IBAT6U (0)
476#define CONFIG_SYS_IBAT7L (0)
477#define CONFIG_SYS_IBAT7U (0)
478#define CONFIG_SYS_DBAT6L CONFIG_SYS_IBAT6L
479#define CONFIG_SYS_DBAT6U CONFIG_SYS_IBAT6U
480#define CONFIG_SYS_DBAT7L CONFIG_SYS_IBAT7L
481#define CONFIG_SYS_DBAT7U CONFIG_SYS_IBAT7U
Anton Vorontsovfab6f552008-01-09 20:57:47 +0300482#endif /* CONFIG_PCI */
483
484/*
485 * Internal Definitions
486 *
487 * Boot Flags
488 */
489#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */
490#define BOOTFLAG_WARM 0x02 /* Software reboot */
491
492#if defined(CONFIG_CMD_KGDB)
493#define CONFIG_KGDB_BAUDRATE 230400 /* speed of kgdb serial port */
494#define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */
495#endif
496
497/*
498 * Environment Configuration
499 */
500#define CONFIG_ENV_OVERWRITE
501
502#if defined(CONFIG_UEC_ETH)
503#define CONFIG_HAS_ETH0
504#define CONFIG_HAS_ETH1
505#define CONFIG_HAS_ETH2
506#define CONFIG_HAS_ETH3
507#define CONFIG_ETHADDR 00:04:9f:ef:01:01
508#define CONFIG_ETH1ADDR 00:04:9f:ef:01:02
509#define CONFIG_ETH2ADDR 00:04:9f:ef:01:03
510#define CONFIG_ETH3ADDR 00:04:9f:ef:01:04
511#endif
512
513#define CONFIG_BAUDRATE 115200
514
515#define CONFIG_LOADADDR a00000
516#define CONFIG_HOSTNAME mpc8360erdk
517#define CONFIG_BOOTFILE uImage
518
519#define CONFIG_IPADDR 10.0.0.99
520#define CONFIG_SERVERIP 10.0.0.2
521#define CONFIG_GATEWAYIP 10.0.0.2
522#define CONFIG_NETMASK 255.255.255.0
523#define CONFIG_ROOTPATH /nfsroot/
524
525#define CONFIG_BOOTDELAY 2 /* -1 disables auto-boot */
526#undef CONFIG_BOOTARGS /* the boot command will set bootargs */
527
528#define CONFIG_EXTRA_ENV_SETTINGS \
529 "netdev=eth0\0"\
530 "consoledev=ttyS0\0"\
531 "loadaddr=a00000\0"\
532 "fdtaddr=900000\0"\
Kim Phillipscc861f72009-08-26 21:25:46 -0500533 "fdtfile=mpc836x_rdk.dtb\0"\
Anton Vorontsovfab6f552008-01-09 20:57:47 +0300534 "fsfile=fs\0"\
535 "ubootfile=u-boot.bin\0"\
Anton Vorontsov7ad95942008-03-24 20:46:51 +0300536 "mtdparts=mtdparts=60000000.nand-flash:4096k(kernel),128k(dtb),-(rootfs)\0"\
Anton Vorontsovfab6f552008-01-09 20:57:47 +0300537 "setbootargs=setenv bootargs console=$consoledev,$baudrate "\
Wolfgang Denk53677ef2008-05-20 16:00:29 +0200538 "$mtdparts panic=1\0"\
Anton Vorontsovfab6f552008-01-09 20:57:47 +0300539 "adddhcpargs=setenv bootargs $bootargs ip=on\0"\
540 "addnfsargs=setenv bootargs $bootargs ip=$ipaddr:$serverip:"\
Wolfgang Denk53677ef2008-05-20 16:00:29 +0200541 "$gatewayip:$netmask:$hostname:$netdev:off "\
542 "root=/dev/nfs rw nfsroot=$serverip:$rootpath\0"\
Anton Vorontsov7ad95942008-03-24 20:46:51 +0300543 "addnandargs=setenv bootargs $bootargs root=/dev/mtdblock3 "\
544 "rootfstype=jffs2 rw\0"\
Anton Vorontsovfab6f552008-01-09 20:57:47 +0300545 "tftp_get_uboot=tftp 100000 $ubootfile\0"\
546 "tftp_get_kernel=tftp $loadaddr $bootfile\0"\
547 "tftp_get_dtb=tftp $fdtaddr $fdtfile\0"\
548 "tftp_get_fs=tftp c00000 $fsfile\0"\
Anton Vorontsov7ad95942008-03-24 20:46:51 +0300549 "nand_erase_kernel=nand erase 0 400000\0"\
550 "nand_erase_dtb=nand erase 400000 20000\0"\
551 "nand_erase_fs=nand erase 420000 3be0000\0"\
552 "nand_write_kernel=nand write.jffs2 $loadaddr 0 400000\0"\
553 "nand_write_dtb=nand write.jffs2 $fdtaddr 400000 20000\0"\
554 "nand_write_fs=nand write.jffs2 c00000 420000 $filesize\0"\
555 "nand_read_kernel=nand read.jffs2 $loadaddr 0 400000\0"\
556 "nand_read_dtb=nand read.jffs2 $fdtaddr 400000 20000\0"\
Anton Vorontsovfab6f552008-01-09 20:57:47 +0300557 "nor_reflash=protect off ff800000 ff87ffff ; erase ff800000 ff87ffff ; "\
Wolfgang Denk53677ef2008-05-20 16:00:29 +0200558 "cp.b 100000 ff800000 $filesize\0"\
Anton Vorontsov7ad95942008-03-24 20:46:51 +0300559 "nand_reflash_kernel=run tftp_get_kernel nand_erase_kernel "\
560 "nand_write_kernel\0"\
561 "nand_reflash_dtb=run tftp_get_dtb nand_erase_dtb nand_write_dtb\0"\
562 "nand_reflash_fs=run tftp_get_fs nand_erase_fs nand_write_fs\0"\
563 "nand_reflash=run nand_reflash_kernel nand_reflash_dtb "\
564 "nand_reflash_fs\0"\
Anton Vorontsovfab6f552008-01-09 20:57:47 +0300565 "boot_m=bootm $loadaddr - $fdtaddr\0"\
Anton Vorontsov3419eb62008-03-24 20:47:00 +0300566 "dhcpboot=dhcp ; run setbootargs adddhcpargs tftp_get_dtb boot_m\0"\
Anton Vorontsovfab6f552008-01-09 20:57:47 +0300567 "nfsboot=run setbootargs addnfsargs tftp_get_kernel tftp_get_dtb "\
Anton Vorontsov3419eb62008-03-24 20:47:00 +0300568 "boot_m\0"\
Anton Vorontsov7ad95942008-03-24 20:46:51 +0300569 "nandboot=run setbootargs addnandargs nand_read_kernel nand_read_dtb "\
570 "boot_m\0"\
Anton Vorontsovfab6f552008-01-09 20:57:47 +0300571 ""
572
573#define CONFIG_BOOTCOMMAND "run dhcpboot"
574
575#endif /* __CONFIG_H */