blob: 80334bd607e9cdf5a290af107ff9b5b529c60899 [file] [log] [blame]
Andre Schwarzc005b932008-06-10 09:13:16 +02001/*
2 * Copyright (C) Matrix Vision GmbH 2008
3 *
4 * Matrix Vision mvBlueLYNX-M7 configuration file
5 * based on Freescale's MPC8349ITX.
6 *
7 * See file CREDITS for list of people who contributed to this
8 * project.
9 *
10 * This program is free software; you can redistribute it and/or
11 * modify it under the terms of the GNU General Public License as
12 * published by the Free Software Foundation; either version 2 of
13 * the License, or (at your option) any later version.
14 *
15 * This program is distributed in the hope that it will be useful,
16 * but WITHOUT ANY WARRANTY; without even the implied warranty of
17 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
18 * GNU General Public License for more details.
19 *
20 * You should have received a copy of the GNU General Public License
21 * along with this program; if not, write to the Free Software
22 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
23 * MA 02111-1307 USA
24 */
25
26
27#ifndef __CONFIG_H
28#define __CONFIG_H
29
Andre Schwarz5ed546f2008-07-02 18:54:08 +020030#include <version.h>
Andre Schwarzc005b932008-06-10 09:13:16 +020031
32/*
33 * High Level Configuration Options
34 */
35#define CONFIG_E300 1
Peter Tyser0f898602009-05-22 17:23:24 -050036#define CONFIG_MPC83xx 1
Peter Tyser2c7920a2009-05-22 17:23:25 -050037#define CONFIG_MPC834x 1
Andre Schwarzc005b932008-06-10 09:13:16 +020038#define CONFIG_MPC8343 1
39
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020040#define CONFIG_SYS_IMMR 0xE0000000
Andre Schwarzc005b932008-06-10 09:13:16 +020041
42#define CONFIG_PCI
Andre Schwarzc005b932008-06-10 09:13:16 +020043#define CONFIG_PCI_SKIP_HOST_BRIDGE
44#define CONFIG_HARD_I2C
45#define CONFIG_TSEC_ENET
46#define CONFIG_MPC8XXX_SPI
47#define CONFIG_HARD_SPI
48#define MVBLM7_MMC_CS 0x04000000
André Schwarz28887d82009-08-27 14:48:35 +020049#define CONFIG_MISC_INIT_R
Andre Schwarzc005b932008-06-10 09:13:16 +020050
51/* I2C */
Andre Schwarzc005b932008-06-10 09:13:16 +020052#define CONFIG_FSL_I2C
53#define CONFIG_I2C_MULTI_BUS
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020054#define CONFIG_SYS_I2C_OFFSET 0x3000
55#define CONFIG_SYS_I2C2_OFFSET 0x3100
Andre Schwarzc005b932008-06-10 09:13:16 +020056
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020057#define CONFIG_SYS_I2C_SPEED 100000
58#define CONFIG_SYS_I2C_SLAVE 0x7F
Andre Schwarzc005b932008-06-10 09:13:16 +020059
60/*
61 * DDR Setup
62 */
André Schwarz28887d82009-08-27 14:48:35 +020063#undef CONFIG_SPD_EEPROM
64
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020065#define CONFIG_SYS_DDR_BASE 0x00000000
66#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_BASE
67#define CONFIG_SYS_DDR_SDRAM_BASE CONFIG_SYS_DDR_BASE
68#define CONFIG_SYS_83XX_DDR_USES_CS0 1
69#define CONFIG_SYS_MEMTEST_START (60<<20)
70#define CONFIG_SYS_MEMTEST_END (70<<20)
André Schwarz28887d82009-08-27 14:48:35 +020071#define CONFIG_VERY_BIG_RAM
Andre Schwarzc005b932008-06-10 09:13:16 +020072
André Schwarz28887d82009-08-27 14:48:35 +020073#define CONFIG_SYS_DDRCDR 0x22000001
74#define CONFIG_SYS_DDR_SDRAM_CLK_CNTL DDR_SDRAM_CLK_CNTL_CLK_ADJUST_05
Andre Schwarzc005b932008-06-10 09:13:16 +020075
André Schwarz28887d82009-08-27 14:48:35 +020076#define CONFIG_SYS_DDR_SIZE 512
Andre Schwarzc005b932008-06-10 09:13:16 +020077
André Schwarz28887d82009-08-27 14:48:35 +020078#define CONFIG_SYS_DDR_CS0_CONFIG 0x80014202
Andre Schwarzc005b932008-06-10 09:13:16 +020079
André Schwarz28887d82009-08-27 14:48:35 +020080#define CONFIG_SYS_DDR_CS0_BNDS 0x0000003f
Andre Schwarzc005b932008-06-10 09:13:16 +020081
André Schwarz28887d82009-08-27 14:48:35 +020082#define CONFIG_SYS_DDR_TIMING_0 0x00260802
83#define CONFIG_SYS_DDR_TIMING_1 0x3837c322
84#define CONFIG_SYS_DDR_TIMING_2 0x0f9848c6
85#define CONFIG_SYS_DDR_TIMING_3 0x00000000
Andre Schwarzc005b932008-06-10 09:13:16 +020086
André Schwarz28887d82009-08-27 14:48:35 +020087#define CONFIG_SYS_DDR_SDRAM_CFG 0x43080008
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020088#define CONFIG_SYS_DDR_SDRAM_CFG2 0x00401000
André Schwarz28887d82009-08-27 14:48:35 +020089#define CONFIG_SYS_DDR_INTERVAL 0x02000100
Andre Schwarzc005b932008-06-10 09:13:16 +020090
André Schwarz28887d82009-08-27 14:48:35 +020091#define CONFIG_SYS_DDR_MODE 0x04040242
92#define CONFIG_SYS_DDR_MODE2 0x00800000
Andre Schwarzc005b932008-06-10 09:13:16 +020093
94/* Flash */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020095#define CONFIG_SYS_FLASH_CFI
Jean-Christophe PLAGNIOL-VILLARD00b18832008-08-13 01:40:42 +020096#define CONFIG_FLASH_CFI_DRIVER
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020097#define CONFIG_SYS_FLASH_CFI_WIDTH FLASH_CFI_16BIT
Andre Schwarzc005b932008-06-10 09:13:16 +020098
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020099#define CONFIG_SYS_FLASH_BASE 0xFF800000
100#define CONFIG_SYS_FLASH_SIZE 8
101#define CONFIG_SYS_FLASH_SIZE_SHIFT 3
102#define CONFIG_SYS_FLASH_EMPTY_INFO
103#define CONFIG_SYS_FLASH_ERASE_TOUT 60000
104#define CONFIG_SYS_FLASH_WRITE_TOUT 500
105#define CONFIG_SYS_MAX_FLASH_BANKS 1
106#define CONFIG_SYS_MAX_FLASH_SECT 256
Andre Schwarzc005b932008-06-10 09:13:16 +0200107
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200108#define CONFIG_SYS_BR0_PRELIM (CONFIG_SYS_FLASH_BASE | BR_PS_16 | BR_V)
109#define CONFIG_SYS_OR0_PRELIM ((~(CONFIG_SYS_FLASH_SIZE - 1) << 20) | OR_UPM_XAM | \
Kim Phillips2329fe12008-06-10 13:25:24 -0500110 OR_GPCM_CSNT | OR_GPCM_ACS_DIV2 | OR_GPCM_XACS|\
Andre Schwarzc005b932008-06-10 09:13:16 +0200111 OR_GPCM_SCY_15 | OR_GPCM_TRLX | OR_GPCM_EHTR | \
112 OR_GPCM_EAD)
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200113#define CONFIG_SYS_LBLAWBAR0_PRELIM CONFIG_SYS_FLASH_BASE
114#define CONFIG_SYS_LBLAWAR0_PRELIM (LBLAWAR_EN | (0x13 + CONFIG_SYS_FLASH_SIZE_SHIFT))
Andre Schwarzc005b932008-06-10 09:13:16 +0200115
116/*
117 * U-Boot memory configuration
118 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200119#define CONFIG_SYS_MONITOR_BASE TEXT_BASE
120#undef CONFIG_SYS_RAMBOOT
Andre Schwarzc005b932008-06-10 09:13:16 +0200121
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200122#define CONFIG_SYS_INIT_RAM_LOCK
123#define CONFIG_SYS_INIT_RAM_ADDR 0xFD000000 /* Initial RAM address */
124#define CONFIG_SYS_INIT_RAM_END 0x1000 /* End of used area in RAM*/
Andre Schwarzc005b932008-06-10 09:13:16 +0200125
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200126#define CONFIG_SYS_GBL_DATA_SIZE 0x100 /* num bytes initial data */
127#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE)
128#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
Andre Schwarzc005b932008-06-10 09:13:16 +0200129
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200130/* CONFIG_SYS_MONITOR_LEN must be a multiple of CONFIG_ENV_SECT_SIZE */
131#define CONFIG_SYS_MONITOR_LEN (512 * 1024)
132#define CONFIG_SYS_MALLOC_LEN (512 * 1024)
Andre Schwarzc005b932008-06-10 09:13:16 +0200133
134/*
135 * Local Bus LCRR and LBCR regs
136 * LCRR: DLL bypass, Clock divider is 4
137 * External Local Bus rate is
138 * CLKIN * HRCWL_CSB_TO_CLKIN / HRCWL_LCL_BUS_TO_SCB_CLK / LCRR_CLKDIV
139 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200140#define CONFIG_SYS_LCRR (LCRR_DBYP | LCRR_CLKDIV_4)
141#define CONFIG_SYS_LBC_LBCR 0x00000000
Andre Schwarzc005b932008-06-10 09:13:16 +0200142
143/* LB sdram refresh timer, about 6us */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200144#define CONFIG_SYS_LBC_LSRT 0x32000000
Andre Schwarzc005b932008-06-10 09:13:16 +0200145/* LB refresh timer prescal, 266MHz/32*/
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200146#define CONFIG_SYS_LBC_MRTPR 0x20000000
Andre Schwarzc005b932008-06-10 09:13:16 +0200147
148/*
149 * Serial Port
150 */
151#define CONFIG_CONS_INDEX 1
152#undef CONFIG_SERIAL_SOFTWARE_FIFO
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200153#define CONFIG_SYS_NS16550
154#define CONFIG_SYS_NS16550_SERIAL
155#define CONFIG_SYS_NS16550_REG_SIZE 1
156#define CONFIG_SYS_NS16550_CLK get_bus_freq(0)
Andre Schwarzc005b932008-06-10 09:13:16 +0200157
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200158#define CONFIG_SYS_BAUDRATE_TABLE \
Andre Schwarzc005b932008-06-10 09:13:16 +0200159 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 115200}
160
161#define CONFIG_CONSOLE ttyS0
162#define CONFIG_BAUDRATE 115200
163
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200164#define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_IMMR + 0x4500)
165#define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_IMMR + 0x4600)
Andre Schwarzc005b932008-06-10 09:13:16 +0200166
167/* pass open firmware flat tree */
168#define CONFIG_OF_LIBFDT 1
169#define CONFIG_OF_BOARD_SETUP 1
170#define CONFIG_OF_STDOUT_VIA_ALIAS 1
171#define MV_DTB_NAME "mvblm7.dtb"
172
173/*
174 * PCI
175 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200176#define CONFIG_SYS_PCI1_MEM_BASE 0x80000000
177#define CONFIG_SYS_PCI1_MEM_PHYS CONFIG_SYS_PCI1_MEM_BASE
178#define CONFIG_SYS_PCI1_MEM_SIZE 0x10000000
179#define CONFIG_SYS_PCI1_MMIO_BASE (CONFIG_SYS_PCI1_MEM_BASE + CONFIG_SYS_PCI1_MEM_SIZE)
180#define CONFIG_SYS_PCI1_MMIO_PHYS CONFIG_SYS_PCI1_MMIO_BASE
181#define CONFIG_SYS_PCI1_MMIO_SIZE 0x10000000
182#define CONFIG_SYS_PCI1_IO_BASE 0x00000000
183#define CONFIG_SYS_PCI1_IO_PHYS 0xE2000000
184#define CONFIG_SYS_PCI1_IO_SIZE 0x01000000
Andre Schwarzc005b932008-06-10 09:13:16 +0200185
Andre Schwarzc005b932008-06-10 09:13:16 +0200186#define CONFIG_NET_MULTI 1
187#define CONFIG_NET_RETRY_COUNT 3
188
189#define PCI_66M
190#define CONFIG_83XX_CLKIN 66666667
191#define CONFIG_PCI_PNP
192#define CONFIG_PCI_SCAN_SHOW
193
194/* TSEC */
195#define CONFIG_GMII
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200196#define CONFIG_SYS_VSC8601_SKEWFIX
197#define CONFIG_SYS_VSC8601_SKEW_TX 3
198#define CONFIG_SYS_VSC8601_SKEW_RX 3
Andre Schwarzc005b932008-06-10 09:13:16 +0200199
200#define CONFIG_TSEC1
201#define CONFIG_TSEC2
202
203#define CONFIG_HAS_ETH0
204#define CONFIG_TSEC1_NAME "TSEC0"
205#define CONFIG_FEC1_PHY_NORXERR
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200206#define CONFIG_SYS_TSEC1_OFFSET 0x24000
207#define CONFIG_SYS_TSEC1 (CONFIG_SYS_IMMR+CONFIG_SYS_TSEC1_OFFSET)
Andre Schwarzc005b932008-06-10 09:13:16 +0200208#define TSEC1_PHY_ADDR 0x10
209#define TSEC1_PHYIDX 0
210#define TSEC1_FLAGS (TSEC_GIGABIT|TSEC_REDUCED)
211
212#define CONFIG_HAS_ETH1
213#define CONFIG_TSEC2_NAME "TSEC1"
214#define CONFIG_FEC2_PHY_NORXERR
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200215#define CONFIG_SYS_TSEC2_OFFSET 0x25000
216#define CONFIG_SYS_TSEC2 (CONFIG_SYS_IMMR+CONFIG_SYS_TSEC2_OFFSET)
Andre Schwarzc005b932008-06-10 09:13:16 +0200217#define TSEC2_PHY_ADDR 0x11
218#define TSEC2_PHYIDX 0
219#define TSEC2_FLAGS (TSEC_GIGABIT|TSEC_REDUCED)
220
221#define CONFIG_ETHPRIME "TSEC0"
222
223#define CONFIG_BOOTP_VENDOREX
224#define CONFIG_BOOTP_SUBNETMASK
225#define CONFIG_BOOTP_GATEWAY
226#define CONFIG_BOOTP_DNS
227#define CONFIG_BOOTP_DNS2
228#define CONFIG_BOOTP_HOSTNAME
229#define CONFIG_BOOTP_BOOTFILESIZE
230#define CONFIG_BOOTP_BOOTPATH
231#define CONFIG_BOOTP_NTPSERVER
232#define CONFIG_BOOTP_RANDOM_DELAY
233#define CONFIG_BOOTP_SEND_HOSTNAME
234
235/* USB */
236#define CONFIG_HAS_FSL_DR_USB
237
238/*
239 * Environment
240 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200241#undef CONFIG_SYS_FLASH_PROTECTION
Andre Schwarzc005b932008-06-10 09:13:16 +0200242#define CONFIG_ENV_OVERWRITE
243
Jean-Christophe PLAGNIOL-VILLARD5a1aceb2008-09-10 22:48:04 +0200244#define CONFIG_ENV_IS_IN_FLASH 1
Jean-Christophe PLAGNIOL-VILLARD0e8d1582008-09-10 22:48:06 +0200245#define CONFIG_ENV_ADDR 0xFF800000
246#define CONFIG_ENV_SIZE 0x2000
247#define CONFIG_ENV_SECT_SIZE 0x2000
248#define CONFIG_ENV_ADDR_REDUND (CONFIG_ENV_ADDR+CONFIG_ENV_SIZE)
249#define CONFIG_ENV_SIZE_REDUND CONFIG_ENV_SIZE
Andre Schwarzc005b932008-06-10 09:13:16 +0200250
Wolfgang Denke093a242008-06-28 23:34:37 +0200251#define CONFIG_LOADS_ECHO
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200252#define CONFIG_SYS_LOADS_BAUD_CHANGE
Andre Schwarzc005b932008-06-10 09:13:16 +0200253
254/*
255 * Command line configuration.
256 */
257#include <config_cmd_default.h>
258
259#define CONFIG_CMD_CACHE
260#define CONFIG_CMD_IRQ
261#define CONFIG_CMD_NET
262#define CONFIG_CMD_MII
263#define CONFIG_CMD_PING
264#define CONFIG_CMD_DHCP
265#define CONFIG_CMD_SDRAM
266#define CONFIG_CMD_PCI
267#define CONFIG_CMD_I2C
268#define CONFIG_CMD_FPGA
269
270#undef CONFIG_WATCHDOG
271
272/*
273 * Miscellaneous configurable options
274 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200275#define CONFIG_SYS_LONGHELP
Andre Schwarzc005b932008-06-10 09:13:16 +0200276#define CONFIG_CMDLINE_EDITING
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200277#define CONFIG_SYS_HUSH_PARSER
278#define CONFIG_SYS_PROMPT_HUSH_PS2 "> "
Andre Schwarzc005b932008-06-10 09:13:16 +0200279
280/* default load address */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200281#define CONFIG_SYS_LOAD_ADDR 0x2000000
Andre Schwarzc005b932008-06-10 09:13:16 +0200282/* default location for tftp and bootm */
283#define CONFIG_LOADADDR 0x200000
284
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200285#define CONFIG_SYS_PROMPT "mvBL-M7> "
286#define CONFIG_SYS_CBSIZE 256
Andre Schwarzc005b932008-06-10 09:13:16 +0200287
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200288#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16)
289#define CONFIG_SYS_MAXARGS 16
290#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE
291#define CONFIG_SYS_HZ 1000
Andre Schwarzc005b932008-06-10 09:13:16 +0200292
293/*
294 * For booting Linux, the board info and command line data
295 * have to be in the first 8 MB of memory, since this is
296 * the maximum mapped by the Linux kernel during initialization.
297 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200298#define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux*/
Andre Schwarzc005b932008-06-10 09:13:16 +0200299
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200300#define CONFIG_SYS_HRCW_LOW 0x0
301#define CONFIG_SYS_HRCW_HIGH 0x0
Andre Schwarzc005b932008-06-10 09:13:16 +0200302
303/*
304 * System performance
305 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200306#define CONFIG_SYS_ACR_PIPE_DEP 3 /* Arbiter pipeline depth (0-3) */
307#define CONFIG_SYS_ACR_RPTCNT 3 /* Arbiter repeat count (0-7) */
308#define CONFIG_SYS_SPCR_TSEC1EP 3 /* TSEC1 emergency priority (0-3) */
309#define CONFIG_SYS_SPCR_TSEC2EP 3 /* TSEC2 emergency priority (0-3) */
Andre Schwarzc005b932008-06-10 09:13:16 +0200310
311/* clocking */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200312#define CONFIG_SYS_SCCR_ENCCM 0
313#define CONFIG_SYS_SCCR_USBMPHCM 0
314#define CONFIG_SYS_SCCR_USBDRCM 2
315#define CONFIG_SYS_SCCR_TSEC1CM 1
316#define CONFIG_SYS_SCCR_TSEC2CM 1
Andre Schwarzc005b932008-06-10 09:13:16 +0200317
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200318#define CONFIG_SYS_SICRH 0x1fff8003
319#define CONFIG_SYS_SICRL (SICRL_LDP_A | SICRL_USB1 | SICRL_USB0)
Andre Schwarzc005b932008-06-10 09:13:16 +0200320
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200321#define CONFIG_SYS_HID0_INIT 0x000000000
322#define CONFIG_SYS_HID0_FINAL CONFIG_SYS_HID0_INIT
Andre Schwarzc005b932008-06-10 09:13:16 +0200323
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200324#define CONFIG_SYS_HID2 HID2_HBE
Andre Schwarz5ed546f2008-07-02 18:54:08 +0200325#define CONFIG_HIGH_BATS 1
Andre Schwarzc005b932008-06-10 09:13:16 +0200326
327/* DDR */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200328#define CONFIG_SYS_IBAT0L (CONFIG_SYS_SDRAM_BASE | BATL_PP_10 | BATL_MEMCOHERENCE)
329#define CONFIG_SYS_IBAT0U (CONFIG_SYS_SDRAM_BASE | BATU_BL_256M | BATU_VS | BATU_VP)
Andre Schwarzc005b932008-06-10 09:13:16 +0200330
331/* PCI */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200332#define CONFIG_SYS_IBAT1L (CONFIG_SYS_PCI1_MEM_BASE | BATL_PP_10 | BATL_MEMCOHERENCE)
333#define CONFIG_SYS_IBAT1U (CONFIG_SYS_PCI1_MEM_BASE | BATU_BL_256M | BATU_VS | BATU_VP)
334#define CONFIG_SYS_IBAT2L (CONFIG_SYS_PCI1_MMIO_BASE | BATL_PP_10 | BATL_CACHEINHIBIT |\
Andre Schwarzc005b932008-06-10 09:13:16 +0200335 BATL_GUARDEDSTORAGE)
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200336#define CONFIG_SYS_IBAT2U (CONFIG_SYS_PCI1_MMIO_BASE | BATU_BL_256M | BATU_VS | BATU_VP)
Andre Schwarzc005b932008-06-10 09:13:16 +0200337
338/* no PCI2 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200339#define CONFIG_SYS_IBAT3L 0
340#define CONFIG_SYS_IBAT3U 0
341#define CONFIG_SYS_IBAT4L 0
342#define CONFIG_SYS_IBAT4U 0
Andre Schwarzc005b932008-06-10 09:13:16 +0200343
344/* IMMRBAR @ 0xE0000000, PCI IO @ 0xE2000000 & BCSR @ 0xE2400000 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200345#define CONFIG_SYS_IBAT5L (CONFIG_SYS_IMMR | BATL_PP_10 | BATL_CACHEINHIBIT | \
Andre Schwarzc005b932008-06-10 09:13:16 +0200346 BATL_GUARDEDSTORAGE)
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200347#define CONFIG_SYS_IBAT5U (CONFIG_SYS_IMMR | BATU_BL_256M | BATU_VS | BATU_VP)
Andre Schwarzc005b932008-06-10 09:13:16 +0200348
349/* stack in DCACHE 0xFDF00000 & FLASH @ 0xFF800000 */
Scott Woodc1230982009-03-31 17:49:36 -0500350#define CONFIG_SYS_IBAT6L (0xF0000000 | BATL_PP_10 | BATL_MEMCOHERENCE | \
351 BATL_GUARDEDSTORAGE)
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200352#define CONFIG_SYS_IBAT6U (0xF0000000 | BATU_BL_256M | BATU_VS | BATU_VP)
353#define CONFIG_SYS_IBAT7L 0
354#define CONFIG_SYS_IBAT7U 0
Andre Schwarzc005b932008-06-10 09:13:16 +0200355
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200356#define CONFIG_SYS_DBAT0L CONFIG_SYS_IBAT0L
357#define CONFIG_SYS_DBAT0U CONFIG_SYS_IBAT0U
358#define CONFIG_SYS_DBAT1L CONFIG_SYS_IBAT1L
359#define CONFIG_SYS_DBAT1U CONFIG_SYS_IBAT1U
360#define CONFIG_SYS_DBAT2L CONFIG_SYS_IBAT2L
361#define CONFIG_SYS_DBAT2U CONFIG_SYS_IBAT2U
362#define CONFIG_SYS_DBAT3L CONFIG_SYS_IBAT3L
363#define CONFIG_SYS_DBAT3U CONFIG_SYS_IBAT3U
364#define CONFIG_SYS_DBAT4L CONFIG_SYS_IBAT4L
365#define CONFIG_SYS_DBAT4U CONFIG_SYS_IBAT4U
366#define CONFIG_SYS_DBAT5L CONFIG_SYS_IBAT5L
367#define CONFIG_SYS_DBAT5U CONFIG_SYS_IBAT5U
368#define CONFIG_SYS_DBAT6L CONFIG_SYS_IBAT6L
369#define CONFIG_SYS_DBAT6U CONFIG_SYS_IBAT6U
370#define CONFIG_SYS_DBAT7L CONFIG_SYS_IBAT7L
371#define CONFIG_SYS_DBAT7U CONFIG_SYS_IBAT7U
Andre Schwarzc005b932008-06-10 09:13:16 +0200372
373/*
374 * Internal Definitions
375 *
376 * Boot Flags
377 */
378#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */
379#define BOOTFLAG_WARM 0x02 /* Software reboot */
380
381
382/*
383 * Environment Configuration
384 */
385#define CONFIG_ENV_OVERWRITE
386
387#define CONFIG_NETDEV eth0
388
389/* Default path and filenames */
390#define CONFIG_BOOTDELAY 5
391#define CONFIG_AUTOBOOT_KEYED
392#define CONFIG_AUTOBOOT_STOP_STR "s"
393#define CONFIG_ZERO_BOOTDELAY_CHECK
394#define CONFIG_RESET_TO_RETRY 1000
395
Andre Schwarz1a9eeb72008-08-20 11:11:52 +0200396#define MV_CI mvBL-M7
397#define MV_VCI mvBL-M7
André Schwarz28887d82009-08-27 14:48:35 +0200398#define MV_FPGA_DATA 0xfff40000
399#define MV_FPGA_SIZE 0
Andre Schwarz1a9eeb72008-08-20 11:11:52 +0200400#define MV_KERNEL_ADDR 0xff810000
401#define MV_INITRD_ADDR 0xffb00000
Wolfgang Denk74de7ae2009-04-01 23:34:12 +0200402#define MV_SOURCE_ADDR 0xff804000
403#define MV_SOURCE_ADDR2 0xff806000
Andre Schwarz1a9eeb72008-08-20 11:11:52 +0200404#define MV_DTB_ADDR 0xff808000
405#define MV_INITRD_LENGTH 0x00400000
Andre Schwarzc005b932008-06-10 09:13:16 +0200406
407#define CONFIG_SHOW_BOOT_PROGRESS 1
408
Andre Schwarz1a9eeb72008-08-20 11:11:52 +0200409#define MV_KERNEL_ADDR_RAM 0x00100000
410#define MV_DTB_ADDR_RAM 0x00600000
411#define MV_INITRD_ADDR_RAM 0x01000000
Andre Schwarzc005b932008-06-10 09:13:16 +0200412
413#define CONFIG_BOOTCOMMAND "if imi ${autoscr_addr}; \
Wolfgang Denk74de7ae2009-04-01 23:34:12 +0200414 then source ${autoscr_addr}; \
415 else source ${autoscr_addr2}; \
Andre Schwarzc005b932008-06-10 09:13:16 +0200416 fi;"
417#define CONFIG_BOOTARGS "root=/dev/ram ro rootfstype=squashfs"
418
419#define CONFIG_EXTRA_ENV_SETTINGS \
420 "console_nr=0\0" \
Andre Schwarz1a9eeb72008-08-20 11:11:52 +0200421 "baudrate=" MK_STR(CONFIG_BAUDRATE) "\0" \
Andre Schwarzc005b932008-06-10 09:13:16 +0200422 "stdin=serial\0" \
423 "stdout=serial\0" \
424 "stderr=serial\0" \
425 "fpga=0\0" \
Andre Schwarz1a9eeb72008-08-20 11:11:52 +0200426 "fpgadata=" MK_STR(MV_FPGA_DATA) "\0" \
427 "fpgadatasize=" MK_STR(MV_FPGA_SIZE) "\0" \
Wolfgang Denk74de7ae2009-04-01 23:34:12 +0200428 "autoscr_addr=" MK_STR(MV_SOURCE_ADDR) "\0" \
429 "autoscr_addr2=" MK_STR(MV_SOURCE_ADDR2) "\0" \
Andre Schwarz1a9eeb72008-08-20 11:11:52 +0200430 "mv_kernel_addr=" MK_STR(MV_KERNEL_ADDR) "\0" \
431 "mv_kernel_addr_ram=" MK_STR(MV_KERNEL_ADDR_RAM) "\0" \
432 "mv_initrd_addr=" MK_STR(MV_INITRD_ADDR) "\0" \
433 "mv_initrd_addr_ram=" MK_STR(MV_INITRD_ADDR_RAM) "\0" \
434 "mv_initrd_length=" MK_STR(MV_INITRD_LENGTH) "\0" \
435 "mv_dtb_addr=" MK_STR(MV_DTB_ADDR) "\0" \
436 "mv_dtb_addr_ram=" MK_STR(MV_DTB_ADDR_RAM) "\0" \
437 "dtb_name=" MK_STR(MV_DTB_NAME) "\0" \
Andre Schwarz5ed546f2008-07-02 18:54:08 +0200438 "mv_version=" U_BOOT_VERSION "\0" \
Andre Schwarz1a9eeb72008-08-20 11:11:52 +0200439 "dhcp_client_id=" MK_STR(MV_CI) "\0" \
440 "dhcp_vendor-class-identifier=" MK_STR(MV_VCI) "\0" \
Andre Schwarzc005b932008-06-10 09:13:16 +0200441 "netretry=no\0" \
442 "use_static_ipaddr=no\0" \
443 "static_ipaddr=192.168.90.10\0" \
444 "static_netmask=255.255.255.0\0" \
445 "static_gateway=0.0.0.0\0" \
André Schwarz28887d82009-08-27 14:48:35 +0200446 "initrd_name=uInitrd.mvBL-M7-rfs\0" \
Andre Schwarzc005b932008-06-10 09:13:16 +0200447 "zcip=no\0" \
448 "netboot=yes\0" \
449 "mvtest=Ff\0" \
450 "tried_bootfromflash=no\0" \
451 "tried_bootfromnet=no\0" \
452 "bootfile=mvblm72625.boot\0" \
453 "use_dhcp=yes\0" \
454 "gev_start=yes\0" \
455 "mvbcdma_debug=0\0" \
456 "mvbcia_debug=0\0" \
457 "propdev_debug=0\0" \
458 "gevss_debug=0\0" \
459 "watchdog=0\0" \
460 "usb_dr_mode=host\0" \
Andre Schwarz1a9eeb72008-08-20 11:11:52 +0200461 "sensor_cnt=2\0" \
Andre Schwarzc005b932008-06-10 09:13:16 +0200462 ""
463
464#define CONFIG_FPGA_COUNT 1
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200465#define CONFIG_FPGA CONFIG_SYS_ALTERA_CYCLON2
Andre Schwarzc005b932008-06-10 09:13:16 +0200466#define CONFIG_FPGA_ALTERA
467#define CONFIG_FPGA_CYCLON2
468
469#endif