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wdenke2211742002-11-02 23:30:20 +00001/*
2 * (C) Copyright 2001
3 * Erik Theisen, Wave 7 Optics, etheisen@mindspring.com
4 *
5 * See file CREDITS for list of people who contributed to this
6 * project.
7 *
8 * This program is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU General Public License as
10 * published by the Free Software Foundation; either version 2 of
11 * the License, or (at your option) any later version.
12 *
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
17 *
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
21 * MA 02111-1307 USA
22 */
23
24/*
25 * board/config.h - configuration options, board specific
26 */
27
28#ifndef __CONFIG_H
29#define __CONFIG_H
30
31/*
32 * High Level Configuration Options
33 * (easy to change)
34 */
35
36#define CONFIG_405GP 1 /* This is a PPC405GP CPU */
37#define CONFIG_4xx 1 /* ...member of PPC405 family */
38#define CONFIG_W7O 1 /* ...on a Wave 7 Optics board */
39#define CONFIG_W7OLMG 1 /* ...specifically an LMG */
40
wdenkc837dcb2004-01-20 23:12:12 +000041#define CONFIG_BOARD_EARLY_INIT_F 1 /* Call board_early_init_f */
42#define CONFIG_MISC_INIT_F 1 /* and misc_init_f() */
wdenke2211742002-11-02 23:30:20 +000043
44#define CONFIG_SYS_CLK_FREQ 33333333 /* external frequency to pll */
45
46#define CONFIG_BAUDRATE 9600
47#define CONFIG_BOOTDELAY 3 /* autoboot after 3 seconds */
48
49#if 1
50#define CONFIG_BOOTCOMMAND "bootvx" /* VxWorks boot command */
51#else
52#define CONFIG_BOOTCOMMAND "bootp" /* autoboot command */
53#endif
54
55#undef CONFIG_BOOTARGS
56
57#define CONFIG_LOADADDR F0080000
58
59#define CONFIG_ETHADDR 00:06:0D:00:00:00 /* Default, overridden at boot */
60#define CONFIG_OVERWRITE_ETHADDR_ONCE
61#define CONFIG_IPADDR 192.168.1.1
62#define CONFIG_NETMASK 255.255.255.0
63#define CONFIG_SERVERIP 192.168.1.2
64
65#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020066#undef CONFIG_SYS_LOADS_BAUD_CHANGE /* disallow baudrate change */
wdenke2211742002-11-02 23:30:20 +000067
Ben Warren96e21f82008-10-27 23:50:15 -070068#define CONFIG_PPC4xx_EMAC
wdenke2211742002-11-02 23:30:20 +000069#define CONFIG_MII 1 /* MII PHY management */
70#define CONFIG_PHY_ADDR 0 /* PHY address */
Ben Warren18cc7af2009-04-28 16:50:53 -070071#define CONFIG_NET_MULTI
wdenke2211742002-11-02 23:30:20 +000072
73#define CONFIG_RTC_M48T35A 1 /* ST Electronics M48 timekeeper */
74#define CONFIG_DTT_LM75 1 /* ON Semi's LM75 */
75#define CONFIG_DTT_SENSORS {2, 4} /* Sensor addresses */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020076#define CONFIG_SYS_DTT_MAX_TEMP 70
77#define CONFIG_SYS_DTT_LOW_TEMP -30
78#define CONFIG_SYS_DTT_HYSTERESIS 3
wdenke2211742002-11-02 23:30:20 +000079
wdenke2211742002-11-02 23:30:20 +000080
Jon Loeligera5562902007-07-08 15:31:57 -050081/*
Jon Loeligera1aa0bb2007-07-10 09:22:23 -050082 * BOOTP options
83 */
84#define CONFIG_BOOTP_BOOTFILESIZE
85#define CONFIG_BOOTP_BOOTPATH
86#define CONFIG_BOOTP_GATEWAY
87#define CONFIG_BOOTP_HOSTNAME
88
89
90/*
Jon Loeligera5562902007-07-08 15:31:57 -050091 * Command line configuration.
92 */
93#include <config_cmd_default.h>
94
95#define CONFIG_CMD_PCI
96#define CONFIG_CMD_IRQ
97#define CONFIG_CMD_ASKENV
98#define CONFIG_CMD_DHCP
99#define CONFIG_CMD_BEDBUG
100#define CONFIG_CMD_DATE
101#define CONFIG_CMD_I2C
102#define CONFIG_CMD_EEPROM
103#define CONFIG_CMD_ELF
104#define CONFIG_CMD_BSP
105#define CONFIG_CMD_REGINFO
106#define CONFIG_CMD_DTT
107
wdenke2211742002-11-02 23:30:20 +0000108
109#undef CONFIG_WATCHDOG /* watchdog disabled */
110#define CONFIG_HW_WATCHDOG /* HW Watchdog, board specific */
111
112#define CONFIG_SPD_EEPROM /* SPD EEPROM for SDRAM param. */
wdenkdb2f721f2003-03-06 00:58:30 +0000113#define CONFIG_SPDDRAM_SILENT /* No output if spd fails */
wdenke2211742002-11-02 23:30:20 +0000114/*
115 * Miscellaneous configurable options
116 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200117#define CONFIG_SYS_LONGHELP /* undef to save memory */
118#define CONFIG_SYS_PROMPT "Wave7Optics> " /* Monitor Command Prompt */
119#undef CONFIG_SYS_HUSH_PARSER /* No hush parse for U-Boot */
120#ifdef CONFIG_SYS_HUSH_PARSER
121#define CONFIG_SYS_PROMPT_HUSH_PS2 "> "
wdenke2211742002-11-02 23:30:20 +0000122#endif
Jon Loeligera5562902007-07-08 15:31:57 -0500123#if defined(CONFIG_CMD_KGDB)
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200124#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
wdenke2211742002-11-02 23:30:20 +0000125#else
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200126#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
wdenke2211742002-11-02 23:30:20 +0000127#endif
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200128#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
129#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
130#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */
wdenke2211742002-11-02 23:30:20 +0000131
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200132#define CONFIG_SYS_MEMTEST_START 0x0400000 /* memtest works on */
133#define CONFIG_SYS_MEMTEST_END 0x0C00000 /* 4 ... 12 MB in DRAM */
wdenke2211742002-11-02 23:30:20 +0000134
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200135#undef CONFIG_SYS_EXT_SERIAL_CLOCK /* external serial clock */
136#define CONFIG_SYS_405_UART_ERRATA_59 /* 405GP/CR Rev. D silicon */
137#define CONFIG_SYS_BASE_BAUD 384000
wdenke2211742002-11-02 23:30:20 +0000138
139
140/* The following table includes the supported baudrates */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200141#define CONFIG_SYS_BAUDRATE_TABLE {9600}
wdenke2211742002-11-02 23:30:20 +0000142
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200143#define CONFIG_SYS_LOAD_ADDR 0x100000 /* default load address */
144#define CONFIG_SYS_EXTBDINFO 1 /* use extended board_info (bd_t) */
wdenke2211742002-11-02 23:30:20 +0000145
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200146#define CONFIG_SYS_HZ 1000 /* decrementer freq: 1 ms ticks */
wdenke2211742002-11-02 23:30:20 +0000147
148/*-----------------------------------------------------------------------
149 * PCI stuff
150 *-----------------------------------------------------------------------
151 */
152#define PCI_HOST_ADAPTER 0 /* configure as pci adapter */
153#define PCI_HOST_FORCE 1 /* configure as pci host */
154#define PCI_HOST_AUTO 2 /* detected via arbiter enable */
155
156#define CONFIG_PCI /* include pci support */
157#define CONFIG_PCI_HOST PCI_HOST_AUTO /* select pci host function */
158#define CONFIG_PCI_PNP /* pci plug-and-play */
159/* resource configuration */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200160#define CONFIG_SYS_PCI_SUBSYS_VENDORID 0x1014 /* PCI Vendor ID: IBM */
161#define CONFIG_SYS_PCI_SUBSYS_DEVICEID 0x0156 /* PCI Device ID: 405GP */
162#define CONFIG_SYS_PCI_PTM1LA 0x00000000 /* point to sdram */
163#define CONFIG_SYS_PCI_PTM1MS 0x80000001 /* 2GB, enable hard-wired to 1 */
164#define CONFIG_SYS_PCI_PTM1PCI 0x00000000 /* Host: use this pci address */
165#define CONFIG_SYS_PCI_PTM2LA 0x00000000 /* disabled */
166#define CONFIG_SYS_PCI_PTM2MS 0x00000000 /* disabled */
167#define CONFIG_SYS_PCI_PTM2PCI 0x00000000 /* Host: use this pci address */
wdenke2211742002-11-02 23:30:20 +0000168
169/*-----------------------------------------------------------------------
170 * Set up values for external bus controller
171 * used by cpu_init.c
172 *-----------------------------------------------------------------------
173 */
174 /* use PerWE instead of PCI_INT ( these functions share a pin ) */
175#define CONFIG_USE_PERWE 1
176
177/* use on chip memory ( OCM ) for temperary stack until sdram is tested */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200178#define CONFIG_SYS_TEMP_STACK_OCM 1
wdenke2211742002-11-02 23:30:20 +0000179
180/* bank 0 is boot flash */
181/* BME=0,TWT=6,CSN=1,OEN=1,WBN=0,WBF=0,TH=2,RE=0,SOR=0,BEM=1,PEN=0 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200182#define CONFIG_SYS_W7O_EBC_PB0AP 0x03050440
wdenke2211742002-11-02 23:30:20 +0000183/* BAS=0xFFE,BS=0x1(2MB),BU=0x3(R/W),BW=0x0(8 bits) */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200184#define CONFIG_SYS_W7O_EBC_PB0CR 0xFFE38000
wdenke2211742002-11-02 23:30:20 +0000185
186/* bank 1 is main flash */
187/* BME=0,TWT=9,CSN=1,OEN=1,WBN=0,WBF=0,TH=1,RE=0,SOR=0,BEM=1,PEN=0 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200188#define CONFIG_SYS_EBC_PB1AP 0x04850240
wdenke2211742002-11-02 23:30:20 +0000189/* BAS=0xF00,BS=0x7(128MB),BU=0x3(R/W),BW=0x10(32 bits) */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200190#define CONFIG_SYS_EBC_PB1CR 0xF00FC000
wdenke2211742002-11-02 23:30:20 +0000191
192/* bank 2 is RTC/NVRAM */
193/* BME=0,TWT=6,CSN=0,OEN=0,WBN=0,WBF=0,TH=2,RE=0,SOR=0,BEM=1,PEN=0 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200194#define CONFIG_SYS_EBC_PB2AP 0x03000440
wdenke2211742002-11-02 23:30:20 +0000195/* BAS=0xFC0,BS=0x0(1MB),BU=0x3(R/W),BW=0x0(8 bits) */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200196#define CONFIG_SYS_EBC_PB2CR 0xFC018000
wdenke2211742002-11-02 23:30:20 +0000197
198/* bank 3 is FPGA 0 */
199/* BME=0,TWT=4,CSN=0,OEN=0,WBN=0,WBF=0,TH=2,RE=0,SOR=0,BEM=0,PEN=0 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200200#define CONFIG_SYS_EBC_PB3AP 0x02000400
wdenke2211742002-11-02 23:30:20 +0000201/* BAS=0xFD0,BS=0x0(1MB),BU=0x3(R/W),BW=0x1(16 bits) */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200202#define CONFIG_SYS_EBC_PB3CR 0xFD01A000
wdenke2211742002-11-02 23:30:20 +0000203
204/* bank 4 is SAM 8 bit range */
205/* BME=,TWT=,CSN=,OEN=,WBN=,WBF=,TH=,RE=,SOR=,BEM=,PEN= */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200206#define CONFIG_SYS_EBC_PB4AP 0x02840380
wdenke2211742002-11-02 23:30:20 +0000207/* BAS=,BS=,BU=0x3(R/W),BW=0x0(8 bits) */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200208#define CONFIG_SYS_EBC_PB4CR 0xFE878000
wdenke2211742002-11-02 23:30:20 +0000209
210/* bank 5 is SAM 16 bit range */
211/* BME=0,TWT=10,CSN=2,OEN=0,WBN=0,WBF=0,TH=6,RE=1,SOR=1,BEM=0,PEN=0 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200212#define CONFIG_SYS_EBC_PB5AP 0x05040d80
wdenke2211742002-11-02 23:30:20 +0000213/* BAS=,BS=,BU=0x3(R/W),BW=0x1(16 bits) */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200214#define CONFIG_SYS_EBC_PB5CR 0xFD87A000
wdenke2211742002-11-02 23:30:20 +0000215
216/* bank 6 is unused */
Stefan Roesed1c3b272009-09-09 16:25:29 +0200217/* PB6AP = 0 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200218#define CONFIG_SYS_EBC_PB6AP 0x00000000
Stefan Roesed1c3b272009-09-09 16:25:29 +0200219/* PB6CR = 0 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200220#define CONFIG_SYS_EBC_PB6CR 0x00000000
wdenke2211742002-11-02 23:30:20 +0000221
222/* bank 7 is LED register */
223/* BME=0,TWT=6,CSN=1,OEN=1,WBN=0,WBF=0,TH=2,RE=0,SOR=0,BEM=1,PEN=0 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200224#define CONFIG_SYS_W7O_EBC_PB7AP 0x03050440
wdenke2211742002-11-02 23:30:20 +0000225/* BAS=0xFE0,BS=0x0(1MB),BU=0x3(R/W),BW=0x2(32 bits) */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200226#define CONFIG_SYS_W7O_EBC_PB7CR 0xFE01C000
wdenke2211742002-11-02 23:30:20 +0000227
228/*-----------------------------------------------------------------------
229 * Start addresses for the final memory configuration
230 * (Set up by the startup code)
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200231 * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
wdenke2211742002-11-02 23:30:20 +0000232 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200233#define CONFIG_SYS_SDRAM_BASE 0x00000000
234#define CONFIG_SYS_FLASH_BASE 0xFFFC0000
235#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE
236#define CONFIG_SYS_MONITOR_LEN (256 * 1024) /* Reserve 196 kB for Monitor */
237#define CONFIG_SYS_MALLOC_LEN (128 * 1024) /* Reserve 128 kB for malloc() */
wdenke2211742002-11-02 23:30:20 +0000238
239/*
240 * For booting Linux, the board info and command line data
241 * have to be in the first 8 MB of memory, since this is
242 * the maximum mapped by the Linux kernel during initialization.
243 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200244#define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
wdenke2211742002-11-02 23:30:20 +0000245/*-----------------------------------------------------------------------
246 * FLASH organization
247 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200248#define CONFIG_SYS_MAX_FLASH_BANKS 2 /* max number of memory banks */
249#define CONFIG_SYS_MAX_FLASH_SECT 256 /* max number of sec on 1 chip */
wdenke2211742002-11-02 23:30:20 +0000250
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200251#define CONFIG_SYS_FLASH_ERASE_TOUT 120000 /* Timeout, Flash Erase, in ms */
252#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Timeout, Flash Write, in ms */
253#define CONFIG_SYS_FLASH_PROTECTION 1 /* Use real Flash protection */
wdenke2211742002-11-02 23:30:20 +0000254
255#if 1 /* Use NVRAM for environment variables */
256/*-----------------------------------------------------------------------
257 * NVRAM organization
258 */
Jean-Christophe PLAGNIOL-VILLARD9314cee2008-09-10 22:47:59 +0200259#define CONFIG_ENV_IS_IN_NVRAM 1 /* use NVRAM for env vars */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200260#define CONFIG_SYS_NVRAM_BASE_ADDR 0xfc000000 /* NVRAM base address */
261#define CONFIG_SYS_NVRAM_SIZE (32*1024) /* NVRAM size */
Jean-Christophe PLAGNIOL-VILLARD0e8d1582008-09-10 22:48:06 +0200262#define CONFIG_ENV_SIZE 0x1000 /* Size of Environment vars */
263/*define CONFIG_ENV_ADDR \
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200264 (CONFIG_SYS_NVRAM_BASE_ADDR+CONFIG_SYS_NVRAM_SIZE-CONFIG_ENV_SIZE) Env */
265#define CONFIG_ENV_ADDR CONFIG_SYS_NVRAM_BASE_ADDR
wdenke2211742002-11-02 23:30:20 +0000266
267#else /* Use Boot Flash for environment variables */
268/*-----------------------------------------------------------------------
269 * Flash EEPROM for environment
270 */
Jean-Christophe PLAGNIOL-VILLARD5a1aceb2008-09-10 22:48:04 +0200271#define CONFIG_ENV_IS_IN_FLASH 1
Jean-Christophe PLAGNIOL-VILLARD0e8d1582008-09-10 22:48:06 +0200272#define CONFIG_ENV_OFFSET 0x00040000 /* Offset of Environment Sector */
273#define CONFIG_ENV_SIZE 0x10000 /* Total Size of env. sector */
wdenke2211742002-11-02 23:30:20 +0000274
Jean-Christophe PLAGNIOL-VILLARD0e8d1582008-09-10 22:48:06 +0200275#define CONFIG_ENV_SECT_SIZE 0x10000 /* see README - env sec tot sze */
wdenke2211742002-11-02 23:30:20 +0000276#endif
277
278/*-----------------------------------------------------------------------
279 * I2C EEPROM (ATMEL 24C04N)
280 */
281#define CONFIG_HARD_I2C 1 /* Hardware assisted I2C */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200282#define CONFIG_SYS_I2C_SPEED 400000 /* I2C speed and slave address */
283#define CONFIG_SYS_I2C_SLAVE 0x7F
wdenke2211742002-11-02 23:30:20 +0000284
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200285#define CONFIG_SYS_I2C_EEPROM_ADDR 0x50 /* EEPROM ATMEL 24C04N */
286#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 /* Bytes of address */
287#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 3
288#define CONFIG_SYS_I2C_MULTI_EEPROMS
wdenke2211742002-11-02 23:30:20 +0000289/*-----------------------------------------------------------------------
290 * Definitions for Serial Presence Detect EEPROM address
291 * (to get SDRAM settings)
292 */
293#define SPD_EEPROM_ADDRESS 0x50 /* XXX conflicting address!!! XXX */
294
wdenke2211742002-11-02 23:30:20 +0000295/*
296 * Init Memory Controller:
297 */
298#define FLASH_BASE0_PRELIM 0xFFE00000 /* FLASH bank #0 */
299#define FLASH_BASE1_PRELIM 0xF0000000 /* FLASH bank #1 */
300
301/* On Chip Memory location */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200302#define CONFIG_SYS_OCM_DATA_ADDR 0xF8000000
303#define CONFIG_SYS_OCM_DATA_SIZE 0x1000
wdenke2211742002-11-02 23:30:20 +0000304
305/*-----------------------------------------------------------------------
306 * Definitions for initial stack pointer and data area (in RAM)
307 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200308#define CONFIG_SYS_INIT_RAM_ADDR CONFIG_SYS_OCM_DATA_ADDR /* inside of SDRAM */
309#define CONFIG_SYS_INIT_RAM_END CONFIG_SYS_OCM_DATA_SIZE /* End of used area in RAM */
310#define CONFIG_SYS_GBL_DATA_SIZE 64 /* size in bytes reserved for initial data */
311#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE)
312#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
wdenke2211742002-11-02 23:30:20 +0000313
314
315/*
316 * Internal Definitions
317 *
318 * Boot Flags
319 */
320#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */
321#define BOOTFLAG_WARM 0x02 /* Software reboot */
322
Jon Loeligera5562902007-07-08 15:31:57 -0500323#if defined(CONFIG_CMD_KGDB)
wdenke2211742002-11-02 23:30:20 +0000324#define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */
325#define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */
326#endif
327
328/*
329 * FPGA(s) configuration
330 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200331#define CONFIG_SYS_FPGA_IMAGE_LEN 0x80000 /* 512KB FPGA image */
wdenke2211742002-11-02 23:30:20 +0000332#define CONFIG_NUM_FPGAS 1 /* Number of FPGAs on board */
333#define CONFIG_MAX_FPGAS 6 /* Maximum number of FPGAs */
334#define CONFIG_FPGAS_BASE 0xFD000000L /* Base address of FPGAs */
335#define CONFIG_FPGAS_BANK_SIZE 0x00100000L /* FPGAs' mmap bank size */
336
337#endif /* __CONFIG_H */