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Ilko Ilievf0a2c7b2009-04-16 21:30:48 +02001/*
2 * (C) Copyright 2007-2008
3 * Stelian Pop <stelian.pop@leadtechdesign.com>
4 * Lead Tech Design <www.leadtechdesign.com>
5 * Ilko Iliev <www.ronetix.at>
6 *
7 * Configuation settings for the RONETIX PM9263 board.
8 *
9 * See file CREDITS for list of people who contributed to this
10 * project.
11 *
12 * This program is free software; you can redistribute it and/or
13 * modify it under the terms of the GNU General Public License as
14 * published by the Free Software Foundation; either version 2 of
15 * the License, or (at your option) any later version.
16 *
17 * This program is distributed in the hope that it will be useful,
18 * but WITHOUT ANY WARRANTY; without even the implied warranty of
19 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
20 * GNU General Public License for more details.
21 *
22 * You should have received a copy of the GNU General Public License
23 * along with this program; if not, write to the Free Software
24 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
25 * MA 02111-1307 USA
26 */
27
28#ifndef __CONFIG_H
29#define __CONFIG_H
30
31/* ARM asynchronous clock */
Jean-Christophe PLAGNIOL-VILLARDb2403582009-05-31 14:53:18 +020032#define CONFIG_DISPLAY_CPUINFO
Ilko Ilievf0a2c7b2009-04-16 21:30:48 +020033#define CONFIG_DISPLAY_BOARDINFO
34
Jean-Christophe PLAGNIOL-VILLARD01550a22009-06-12 21:20:38 +020035#define MASTER_PLL_DIV 6
36#define MASTER_PLL_MUL 65
Ilko Ilievf0a2c7b2009-04-16 21:30:48 +020037#define MAIN_PLL_DIV 2 /* 2 or 4 */
38#define AT91_MAIN_CLOCK 18432000
39
Jean-Christophe PLAGNIOL-VILLARD6ebff362009-04-16 21:30:48 +020040#define CONFIG_SYS_HZ 1000
Ilko Ilievf0a2c7b2009-04-16 21:30:48 +020041
42#define CONFIG_ARM926EJS 1 /* This is an ARM926EJS Core */
43#define CONFIG_AT91SAM9263 1 /* It's an Atmel AT91SAM9263 SoC*/
44#define CONFIG_PM9263 1 /* on a Ronetix PM9263 Board */
45#define CONFIG_ARCH_CPU_INIT
46#undef CONFIG_USE_IRQ /* we don't need IRQ/FIQ stuff */
47
48/* clocks */
Jean-Christophe PLAGNIOL-VILLARD01550a22009-06-12 21:20:38 +020049#define CONFIG_SYS_MOR_VAL \
50 (AT91_PMC_MOSCEN | \
51 (255 << 8)) /* Main Oscillator Start-up Time */
52#define CONFIG_SYS_PLLAR_VAL \
53 (AT91_PMC_PLLA_WR_ERRATA | /* Bit 29 must be 1 when prog */ \
54 AT91_PMC_OUT | \
55 AT91_PMC_PLLCOUNT | /* PLL Counter */ \
56 (2 << 28) | /* PLL Clock Frequency Range */ \
57 ((MASTER_PLL_MUL - 1) << 16) | (MASTER_PLL_DIV))
Ilko Ilievf0a2c7b2009-04-16 21:30:48 +020058
59#if (MAIN_PLL_DIV == 2)
60/* PCK/2 = MCK Master Clock from PLLA */
Jean-Christophe PLAGNIOL-VILLARD01550a22009-06-12 21:20:38 +020061#define CONFIG_SYS_MCKR1_VAL \
62 (AT91_PMC_CSS_SLOW | \
63 AT91_PMC_PRES_1 | \
64 AT91SAM9_PMC_MDIV_2 | \
65 AT91_PMC_PDIV_1)
Ilko Ilievf0a2c7b2009-04-16 21:30:48 +020066/* PCK/2 = MCK Master Clock from PLLA */
Jean-Christophe PLAGNIOL-VILLARD01550a22009-06-12 21:20:38 +020067#define CONFIG_SYS_MCKR2_VAL \
68 (AT91_PMC_CSS_PLLA | \
69 AT91_PMC_PRES_1 | \
70 AT91SAM9_PMC_MDIV_2 | \
71 AT91_PMC_PDIV_1)
Ilko Ilievf0a2c7b2009-04-16 21:30:48 +020072#else
73/* PCK/4 = MCK Master Clock from PLLA */
Jean-Christophe PLAGNIOL-VILLARD01550a22009-06-12 21:20:38 +020074#define CONFIG_SYS_MCKR1_VAL \
75 (AT91_PMC_CSS_SLOW | \
76 AT91_PMC_PRES_1 | \
77 AT91RM9200_PMC_MDIV_3 | \
78 AT91_PMC_PDIV_1)
Ilko Ilievf0a2c7b2009-04-16 21:30:48 +020079/* PCK/4 = MCK Master Clock from PLLA */
Jean-Christophe PLAGNIOL-VILLARD01550a22009-06-12 21:20:38 +020080#define CONFIG_SYS_MCKR2_VAL \
81 (AT91_PMC_CSS_PLLA | \
82 AT91_PMC_PRES_1 | \
83 AT91RM9200_PMC_MDIV_3 | \
84 AT91_PMC_PDIV_1)
Ilko Ilievf0a2c7b2009-04-16 21:30:48 +020085#endif
86/* define PDC[31:16] as DATA[31:16] */
87#define CONFIG_SYS_PIOD_PDR_VAL1 0xFFFF0000
88/* no pull-up for D[31:16] */
89#define CONFIG_SYS_PIOD_PPUDR_VAL 0xFFFF0000
90/* EBI0_CSA, CS1 SDRAM, CS3 NAND Flash, 3.3V memories */
Jean-Christophe PLAGNIOL-VILLARD01550a22009-06-12 21:20:38 +020091#define CONFIG_SYS_MATRIX_EBI0CSA_VAL \
92 (AT91_MATRIX_EBI0_DBPUC | AT91_MATRIX_EBI0_VDDIOMSEL_3_3V | \
93 AT91_MATRIX_EBI0_CS1A_SDRAMC)
Ilko Ilievf0a2c7b2009-04-16 21:30:48 +020094
95/* SDRAM */
96/* SDRAMC_MR Mode register */
97#define CONFIG_SYS_SDRC_MR_VAL1 0
98/* SDRAMC_TR - Refresh Timer register */
Jean-Christophe PLAGNIOL-VILLARD01550a22009-06-12 21:20:38 +020099#define CONFIG_SYS_SDRC_TR_VAL1 0x3AA
100/* SDRAMC_CR - Configuration register*/
101#define CONFIG_SYS_SDRC_CR_VAL \
102 (AT91_SDRAMC_NC_9 | \
103 AT91_SDRAMC_NR_13 | \
104 AT91_SDRAMC_NB_4 | \
105 AT91_SDRAMC_CAS_2 | \
106 AT91_SDRAMC_DBW_32 | \
107 (2 << 8) | /* tWR - Write Recovery Delay */ \
108 (7 << 12) | /* tRC - Row Cycle Delay */ \
109 (2 << 16) | /* tRP - Row Precharge Delay */ \
110 (2 << 20) | /* tRCD - Row to Column Delay */ \
111 (5 << 24) | /* tRAS - Active to Precharge Delay */ \
112 (8 << 28)) /* tXSR - Exit Self Refresh to Active Delay */
113
Ilko Ilievf0a2c7b2009-04-16 21:30:48 +0200114/* Memory Device Register -> SDRAM */
Jean-Christophe PLAGNIOL-VILLARD01550a22009-06-12 21:20:38 +0200115#define CONFIG_SYS_SDRC_MDR_VAL AT91_SDRAMC_MD_SDRAM
116#define CONFIG_SYS_SDRC_MR_VAL2 AT91_SDRAMC_MODE_PRECHARGE
Ilko Ilievf0a2c7b2009-04-16 21:30:48 +0200117#define CONFIG_SYS_SDRAM_VAL1 0 /* SDRAM_BASE */
Jean-Christophe PLAGNIOL-VILLARD01550a22009-06-12 21:20:38 +0200118#define CONFIG_SYS_SDRC_MR_VAL3 AT91_SDRAMC_MODE_REFRESH
Ilko Ilievf0a2c7b2009-04-16 21:30:48 +0200119#define CONFIG_SYS_SDRAM_VAL2 0 /* SDRAM_BASE */
120#define CONFIG_SYS_SDRAM_VAL3 0 /* SDRAM_BASE */
121#define CONFIG_SYS_SDRAM_VAL4 0 /* SDRAM_BASE */
122#define CONFIG_SYS_SDRAM_VAL5 0 /* SDRAM_BASE */
123#define CONFIG_SYS_SDRAM_VAL6 0 /* SDRAM_BASE */
124#define CONFIG_SYS_SDRAM_VAL7 0 /* SDRAM_BASE */
125#define CONFIG_SYS_SDRAM_VAL8 0 /* SDRAM_BASE */
126#define CONFIG_SYS_SDRAM_VAL9 0 /* SDRAM_BASE */
Jean-Christophe PLAGNIOL-VILLARD01550a22009-06-12 21:20:38 +0200127#define CONFIG_SYS_SDRC_MR_VAL4 AT91_SDRAMC_MODE_LMR
Ilko Ilievf0a2c7b2009-04-16 21:30:48 +0200128#define CONFIG_SYS_SDRAM_VAL10 0 /* SDRAM_BASE */
Jean-Christophe PLAGNIOL-VILLARD01550a22009-06-12 21:20:38 +0200129#define CONFIG_SYS_SDRC_MR_VAL5 AT91_SDRAMC_MODE_NORMAL
Ilko Ilievf0a2c7b2009-04-16 21:30:48 +0200130#define CONFIG_SYS_SDRAM_VAL11 0 /* SDRAM_BASE */
131#define CONFIG_SYS_SDRC_TR_VAL2 1200 /* SDRAM_TR */
132#define CONFIG_SYS_SDRAM_VAL12 0 /* SDRAM_BASE */
133
134/* setup SMC0, CS0 (NOR Flash) - 16-bit, 15 WS */
Jean-Christophe PLAGNIOL-VILLARD01550a22009-06-12 21:20:38 +0200135#define CONFIG_SYS_SMC0_SETUP0_VAL \
136 (AT91_SMC_NWESETUP_(10) | AT91_SMC_NCS_WRSETUP_(10) | \
137 AT91_SMC_NRDSETUP_(10) | AT91_SMC_NCS_RDSETUP_(10))
138#define CONFIG_SYS_SMC0_PULSE0_VAL \
139 (AT91_SMC_NWEPULSE_(11) | AT91_SMC_NCS_WRPULSE_(11) | \
140 AT91_SMC_NRDPULSE_(11) | AT91_SMC_NCS_RDPULSE_(11))
141#define CONFIG_SYS_SMC0_CYCLE0_VAL \
142 (AT91_SMC_NWECYCLE_(22) | AT91_SMC_NRDCYCLE_(22))
143#define CONFIG_SYS_SMC0_MODE0_VAL \
144 (AT91_SMC_READMODE | AT91_SMC_WRITEMODE | \
145 AT91_SMC_DBW_16 | \
146 AT91_SMC_TDFMODE | \
147 AT91_SMC_TDF_(6))
Ilko Ilievf0a2c7b2009-04-16 21:30:48 +0200148
Jean-Christophe PLAGNIOL-VILLARD01550a22009-06-12 21:20:38 +0200149/* user reset enable */
150#define CONFIG_SYS_RSTC_RMR_VAL \
151 (AT91_RSTC_KEY | \
152 AT91_RSTC_PROCRST | \
153 AT91_RSTC_RSTTYP_WAKEUP | \
154 AT91_RSTC_RSTTYP_WATCHDOG)
Ilko Ilievf0a2c7b2009-04-16 21:30:48 +0200155
Jean-Christophe PLAGNIOL-VILLARD01550a22009-06-12 21:20:38 +0200156/* Disable Watchdog */
157#define CONFIG_SYS_WDTC_WDMR_VAL \
158 (AT91_WDT_WDIDLEHLT | AT91_WDT_WDDBGHLT | \
159 AT91_WDT_WDV | \
160 AT91_WDT_WDDIS | \
161 AT91_WDT_WDD)
Ilko Ilievf0a2c7b2009-04-16 21:30:48 +0200162
163#define CONFIG_CMDLINE_TAG 1 /* enable passing of ATAGs */
164#define CONFIG_SETUP_MEMORY_TAGS 1
165#define CONFIG_INITRD_TAG 1
166
167#undef CONFIG_SKIP_LOWLEVEL_INIT
168#undef CONFIG_SKIP_RELOCATE_UBOOT
169#define CONFIG_USER_LOWLEVEL_INIT 1
170
171/*
172 * Hardware drivers
173 */
174#define CONFIG_ATMEL_USART 1
175#undef CONFIG_USART0
176#undef CONFIG_USART1
177#undef CONFIG_USART2
178#define CONFIG_USART3 1 /* USART 3 is DBGU */
179
180/* LCD */
181#define CONFIG_LCD 1
182#define LCD_BPP LCD_COLOR8
183#define CONFIG_LCD_LOGO 1
184#undef LCD_TEST_PATTERN
185#define CONFIG_LCD_INFO 1
186#define CONFIG_LCD_INFO_BELOW_LOGO 1
187#define CONFIG_SYS_WHITE_ON_BLACK 1
188#define CONFIG_ATMEL_LCD 1
189#define CONFIG_ATMEL_LCD_BGR555 1
190#define CONFIG_SYS_CONSOLE_IS_IN_ENV 1
191
192#define CONFIG_LCD_IN_PSRAM 1
193
194/* LED */
195#define CONFIG_AT91_LED
196#define CONFIG_RED_LED AT91_PIN_PB7 /* this is the power led */
197#define CONFIG_GREEN_LED AT91_PIN_PB8 /* this is the user1 led */
198
199#define CONFIG_BOOTDELAY 3
200
201/*
202 * BOOTP options
203 */
204#define CONFIG_BOOTP_BOOTFILESIZE 1
205#define CONFIG_BOOTP_BOOTPATH 1
206#define CONFIG_BOOTP_GATEWAY 1
207#define CONFIG_BOOTP_HOSTNAME 1
208
209/*
210 * Command line configuration.
211 */
212#include <config_cmd_default.h>
213#undef CONFIG_CMD_BDI
214#undef CONFIG_CMD_IMI
215#undef CONFIG_CMD_AUTOSCRIPT
216#undef CONFIG_CMD_FPGA
217#undef CONFIG_CMD_LOADS
218#undef CONFIG_CMD_IMLS
219
220#define CONFIG_CMD_PING 1
221#define CONFIG_CMD_DHCP 1
222#define CONFIG_CMD_NAND 1
223#define CONFIG_CMD_USB 1
224
225/* SDRAM */
226#define CONFIG_NR_DRAM_BANKS 1
227#define PHYS_SDRAM 0x20000000
228#define PHYS_SDRAM_SIZE 0x04000000 /* 64 megs */
229
230/* DataFlash */
231#define CONFIG_ATMEL_DATAFLASH_SPI
232#define CONFIG_HAS_DATAFLASH 1
233#define CONFIG_SYS_SPI_WRITE_TOUT (5 * CONFIG_SYS_HZ)
234#define CONFIG_SYS_MAX_DATAFLASH_BANKS 1
235#define CONFIG_SYS_DATAFLASH_LOGIC_ADDR_CS0 0xC0000000 /* CS0 */
236#define AT91_SPI_CLK 15000000
237#define DATAFLASH_TCSS (0x1a << 16)
238#define DATAFLASH_TCHS (0x1 << 24)
239
240/* NOR flash, if populated */
241#define CONFIG_SYS_FLASH_CFI 1
242#define CONFIG_FLASH_CFI_DRIVER 1
243#define PHYS_FLASH_1 0x10000000
244#define CONFIG_SYS_FLASH_BASE PHYS_FLASH_1
245#define CONFIG_SYS_MAX_FLASH_SECT 256
246#define CONFIG_SYS_MAX_FLASH_BANKS 1
247
248/* NAND flash */
249#ifdef CONFIG_CMD_NAND
250#define CONFIG_NAND_ATMEL
251#define CONFIG_SYS_NAND_MAX_CHIPS 1
252#define CONFIG_SYS_MAX_NAND_DEVICE 1
253#define CONFIG_SYS_NAND_BASE 0x40000000
254#define CONFIG_SYS_NAND_DBW_8 1
255/* our ALE is AD21 */
256#define CONFIG_SYS_NAND_MASK_ALE (1 << 21)
257/* our CLE is AD22 */
258#define CONFIG_SYS_NAND_MASK_CLE (1 << 22)
259#define CONFIG_SYS_NAND_ENABLE_PIN AT91_PIN_PD15
260#define CONFIG_SYS_NAND_READY_PIN AT91_PIN_PB30
Wolfgang Denk2eb99ca2009-07-18 21:52:24 +0200261
262#define CONFIG_SYS_64BIT_VSPRINTF /* needed for nand_util.c */
Ilko Ilievf0a2c7b2009-04-16 21:30:48 +0200263#endif
264
265#define CONFIG_CMD_JFFS2 1
266#define CONFIG_JFFS2_CMDLINE 1
267#define CONFIG_JFFS2_NAND 1
268#define CONFIG_JFFS2_DEV "nand0" /* NAND device jffs2 lives on */
269#define CONFIG_JFFS2_PART_OFFSET 0 /* start of jffs2 partition */
270#define CONFIG_JFFS2_PART_SIZE (256 * 1024 * 1024) /* partition size*/
271
272/* PSRAM */
273#define PHYS_PSRAM 0x70000000
274#define PHYS_PSRAM_SIZE 0x00400000 /* 4MB */
275
276/* Ethernet */
277#define CONFIG_MACB 1
278#define CONFIG_RMII 1
279#define CONFIG_NET_MULTI 1
280#define CONFIG_NET_RETRY_COUNT 20
281#define CONFIG_RESET_PHY_R 1
282
283/* USB */
284#define CONFIG_USB_ATMEL
285#define CONFIG_USB_OHCI_NEW 1
286#define CONFIG_DOS_PARTITION 1
287#define CONFIG_SYS_USB_OHCI_CPU_INIT 1
288#define CONFIG_SYS_USB_OHCI_REGS_BASE 0x00a00000 /* AT91SAM9263_UHP_BASE */
289#define CONFIG_SYS_USB_OHCI_SLOT_NAME "at91sam9263"
290#define CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS 2
291#define CONFIG_USB_STORAGE 1
292
293#define CONFIG_SYS_LOAD_ADDR 0x22000000 /* load address */
294
295#define CONFIG_SYS_MEMTEST_START PHYS_SDRAM
296#define CONFIG_SYS_MEMTEST_END 0x23e00000
297
298#define CONFIG_SYS_USE_FLASH 1
299#undef CONFIG_SYS_USE_DATAFLASH
300#undef CONFIG_SYS_USE_NANDFLASH
301
302#ifdef CONFIG_SYS_USE_DATAFLASH
303
304/* bootstrap + u-boot + env + linux in dataflash on CS0 */
305#define CONFIG_ENV_IS_IN_DATAFLASH
306#define CFG_MONITOR_BASE (CFG_DATAFLASH_LOGIC_ADDR_CS0 + 0x8400)
307#define CONFIG_ENV_OFFSET 0x4200
308#define CONFIG_ENV_ADDR (CFG_DATAFLASH_LOGIC_ADDR_CS0 + CONFIG_ENV_OFFSET)
309#define CONFIG_ENV_SIZE 0x4200
310#define CONFIG_BOOTCOMMAND "cp.b 0xC0042000 0x22000000 0x210000; bootm"
311#define CONFIG_BOOTARGS "console=ttyS0,115200 " \
312 "root=/dev/mtdblock0 " \
Albin Tonnerre918319c2009-07-22 18:30:03 +0200313 "mtdparts=atmel_nand:-(root) "\
Ilko Ilievf0a2c7b2009-04-16 21:30:48 +0200314 "rw rootfstype=jffs2"
315
316#elif defined(CONFIG_SYS_USE_NANDFLASH) /* CFG_USE_NANDFLASH */
317
318/* bootstrap + u-boot + env + linux in nandflash */
319#define CONFIG_ENV_IS_IN_NAND
320#define CONFIG_ENV_OFFSET 0x60000
321#define CONFIG_ENV_OFFSET_REDUND 0x80000
322#define CONFIG_ENV_SIZE 0x20000 /* 1 sector = 128 kB */
323#define CONFIG_BOOTCOMMAND "nand read 0x22000000 0xA0000 0x200000; bootm"
324#define CONFIG_BOOTARGS "console=ttyS0,115200 " \
325 "root=/dev/mtdblock5 " \
Albin Tonnerre918319c2009-07-22 18:30:03 +0200326 "mtdparts=atmel_nand:" \
Ilko Ilievf0a2c7b2009-04-16 21:30:48 +0200327 "128k(bootstrap)ro," \
328 "256k(uboot)ro," \
329 "128k(env1)ro," \
330 "128k(env2)ro," \
331 "2M(linux)," \
332 "-(root) " \
333 "rw rootfstype=jffs2"
334
335#elif defined(CONFIG_SYS_USE_FLASH) /* CFG_USE_FLASH */
336
337#define CONFIG_ENV_IS_IN_FLASH 1
338#define CONFIG_ENV_OFFSET 0x40000
339#define CONFIG_ENV_SECT_SIZE 0x10000
340#define CONFIG_ENV_SIZE 0x10000
341#define CONFIG_ENV_OVERWRITE 1
342
343/* JFFS Partition offset set */
344#define CONFIG_SYS_JFFS2_FIRST_BANK 0
345#define CONFIG_SYS_JFFS2_NUM_BANKS 1
346
347/* 512k reserved for u-boot */
348#define CONFIG_SYS_JFFS2_FIRST_SECTOR 11
349
350#define CONFIG_BOOTCOMMAND "run flashboot"
351#define CONFIG_ROOTPATH /ronetix/rootfs
352#define CONFIG_AUTOBOOT_PROMPT "autoboot in %d seconds\n"
353
354#define CONFIG_CON_ROT "fbcon=rotate:3 "
355#define CONFIG_BOOTARGS "root=/dev/mtdblock4 rootfstype=jffs2 "\
356 CONFIG_CON_ROT
357
358#define MTDIDS_DEFAULT "nor0=physmap-flash.0,nand0=nand"
359#define MTDPARTS_DEFAULT \
360 "mtdparts=physmap-flash.0:" \
361 "256k(u-boot)ro," \
362 "64k(u-boot-env)ro," \
363 "1408k(kernel)," \
364 "-(rootfs);" \
365 "nand:-(nand)"
366
367#define CONFIG_EXTRA_ENV_SETTINGS \
368 "mtdids=" MTDIDS_DEFAULT "\0" \
369 "mtdparts=" MTDPARTS_DEFAULT "\0" \
370 "partition=nand0,0\0" \
371 "ramargs=setenv bootargs $(bootargs) $(mtdparts)\0" \
372 "nfsargs=setenv bootargs root=/dev/nfs rw " \
373 CONFIG_CON_ROT \
374 "nfsroot=$(serverip):$(rootpath) $(mtdparts)\0" \
375 "addip=setenv bootargs $(bootargs) " \
376 "ip=$(ipaddr):$(serverip):$(gatewayip):$(netmask)"\
377 ":$(hostname):eth0:off\0" \
378 "ramboot=tftpboot 0x22000000 vmImage;" \
379 "run ramargs;run addip;bootm 22000000\0" \
380 "nfsboot=tftpboot 0x22000000 vmImage;" \
381 "run nfsargs;run addip;bootm 22000000\0" \
382 "flashboot=run ramargs;run addip;bootm 0x10050000\0" \
383 ""
384
385#else
386#error "Undefined memory device"
387#endif
388
389#define CONFIG_BAUDRATE 115200
390#define CONFIG_SYS_BAUDRATE_TABLE {115200 , 19200, 38400, 57600, 9600 }
391
392#define CONFIG_SYS_PROMPT "u-boot-pm9263> "
393#define CONFIG_SYS_CBSIZE 256
394#define CONFIG_SYS_MAXARGS 16
395#define CONFIG_SYS_PBSIZE \
396 (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16)
397#define CONFIG_SYS_LONGHELP 1
398#define CONFIG_CMDLINE_EDITING 1
399
Ilko Ilievf0a2c7b2009-04-16 21:30:48 +0200400/*
401 * Size of malloc() pool
402 */
403#define CONFIG_SYS_MALLOC_LEN ROUND(3 * CONFIG_ENV_SIZE + 128 * 1024, 0x1000)
404#define CONFIG_SYS_GBL_DATA_SIZE 128 /* 128 bytes for initial data */
405
406#define CONFIG_STACKSIZE (32 * 1024) /* regular stack */
407
408#ifdef CONFIG_USE_IRQ
409#error CONFIG_USE_IRQ not supported
410#endif
411
412#endif