board/ea/mx7ulp_com/imximage.cfg

/*
 * Copyright (C) 2016 Freescale Semiconductor, Inc.
 *
 * SPDX-License-Identifier:	GPL-2.0+
 *
 * Refer docs/README.imxmage for more details about how-to configure
 * and create imximage boot image
 *
 * The syntax is taken as close as possible with the kwbimage
 */

#define __ASSEMBLY__
#include <config.h>

/* image version */

IMAGE_VERSION 2

/*
 * Boot Device : one of
 * spi/sd/nand/onenand, qspi/nor
 */

BOOT_FROM	sd

#ifdef CONFIG_USE_IMXIMG_PLUGIN
/*PLUGIN    plugin-binary-file    IRAM_FREE_START_ADDR*/
PLUGIN	board/freescale/mx7ulp_evk/plugin.bin 0x2F020000
#else

#ifdef CONFIG_SECURE_BOOT
CSF CONFIG_CSF_SIZE
#endif
/*
 * Device Configuration Data (DCD)
 *
 * Each entry must have the format:
 * Addr-type           Address        Value
 *
 * where:
 *	Addr-type register length (1,2 or 4 bytes)
 *	Address	  absolute address of the register
 *	value	  value to be stored in the register
 */
DATA 4   0x403f00dc 0x00000000
DATA 4   0x403e0040 0x01000020
DATA 4   0x403e0500 0x01000000
DATA 4   0x403e050c 0x80808080
DATA 4   0x403e0508 0x00160002
DATA 4   0x403E0510 0x00000001
DATA 4   0x403E0514 0x00000014
DATA 4   0x403e0500 0x00000001
CHECK_BITS_SET 4 0x403e0500 0x01000000
/*
 * Default PFD0 divide is 27, which generates:
 * PFD0 Freq = A7 APLL (528MHz) * 18 / 27 = 352MHz
 *
 * i.MX7ULP COM board can not run DDR at 352MHz, so
 * use a divider of 30 (0x1E), which gives:
 *
 * PFD0 Freq = A7 APLL (528MHz) * 18 / 30 = 316.8MHz
 */
DATA 4   0x403e050c 0x8080801E
CHECK_BITS_SET 4 0x403e050c 0x00000040
DATA 4   0x403E0030 0x00000001
DATA 4   0x403e0040 0x11000020
DATA 4   0x403f00dc 0x42000000

DATA 4   0x40B300AC 0x40000000

DATA 4   0x40AD0128 0x00040000
DATA 4   0x40AD00F8 0x00000000
DATA 4   0x40AD00D8 0x00000180
DATA 4   0x40AD0104 0x00000180
DATA 4   0x40AD0108 0x00000180
DATA 4   0x40AD0124 0x00010000
DATA 4   0x40AD0080 0x0000018C
DATA 4   0x40AD0084 0x0000018C
DATA 4   0x40AD0088 0x0000018C
DATA 4   0x40AD008C 0x0000018C

DATA 4   0x40AD0120 0x00010000
DATA 4   0x40AD010C 0x00000180
DATA 4   0x40AD0110 0x00000180
DATA 4   0x40AD0114 0x00000180
DATA 4   0x40AD0118 0x00000180
DATA 4   0x40AD0090 0x00000180
DATA 4   0x40AD0094 0x00000180
DATA 4   0x40AD0098 0x00000180
DATA 4   0x40AD009C 0x00000180

DATA 4   0x40AD00E0 0x00040000
DATA 4   0x40AD00E4 0x00040000

DATA 4   0x40AB001C 0x00008000
DATA 4   0x40AB085C 0x0D3900A0
DATA 4   0x40AB0800 0xA1390003
DATA 4   0x40AB0890 0x00400000
DATA 4   0x40AB081C 0x33333333
DATA 4   0x40AB0820 0x33333333
DATA 4   0x40AB0824 0x33333333
DATA 4   0x40AB0828 0x33333333
DATA 4   0x40AB08C0 0x24922492
DATA 4   0x40AB0848 0x3A3E3838
DATA 4   0x40AB0850 0x28282C2A
DATA 4   0x40AB083C 0x20000000
DATA 4   0x40AB0840 0x00000000
DATA 4   0x40AB08B8 0x00000800
DATA 4   0x40AB000C 0x292C40F5
DATA 4   0x40AB0004 0x00020064
DATA 4   0x40AB0010 0xB6AD0A83
DATA 4   0x40AB0014 0x00C70093
DATA 4   0x40AB0018 0x00211708
DATA 4   0x40AB002C 0x0F9F26D2
DATA 4   0x40AB0030 0x009F0E10
DATA 4   0x40AB0038 0x00130556
DATA 4   0x40AB0008 0x12272000
DATA 4   0x40AB0040 0x0000003F
DATA 4   0x40AB0000 0xC3110000
DATA 4   0x40AB001C 0x00008010
DATA 4   0x40AB001C 0x00008018
DATA 4   0x40AB001C 0x003F8030
DATA 4   0x40AB001C 0xFF0A8030
DATA 4   0x40AB001C 0x82018030
DATA 4   0x40AB001C 0x06028030
DATA 4   0x40AB001C 0x01038030
DATA 4   0x40AB001C 0x003F8038
DATA 4   0x40AB001C 0xFF0A8038
DATA 4   0x40AB001C 0x82018038
DATA 4   0x40AB001C 0x06028038
DATA 4   0x40AB001C 0x01038038
DATA 4   0x40AB083C 0xA0000000
DATA 4   0x40AB083C 0xA0000000
DATA 4   0x40AB0020 0x00001800
DATA 4   0x40AB0800 0xA1310003
DATA 4   0x40AB001C 0x00000000
#endif