blob: 6903b3614659661ea3ac9b51542e8cb9a438e3d5 [file] [log] [blame]
Wolfgang Grandeggercd12f612009-10-23 12:03:16 +02001/*
2 * (C) Copyright 2006
3 * MicroSys GmbH
4 *
5 * (C) Copyright 2009
6 * Wolfgang Grandegger, DENX Software Engineering, wg@denx.de.
7 *
8 * See file CREDITS for list of people who contributed to this
9 * project.
10 *
11 * This program is free software; you can redistribute it and/or
12 * modify it under the terms of the GNU General Public License as
13 * published by the Free Software Foundation; either version 2 of
14 * the License, or (at your option) any later version.
15 *
16 * This program is distributed in the hope that it will be useful,
17 * but WITHOUT ANY WARRANTY; without even the implied warranty of
18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
19 * GNU General Public License for more details.
20 *
21 * You should have received a copy of the GNU General Public License
22 * along with this program; if not, write to the Free Software
23 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
24 * MA 02111-1307 USA
25 */
26
27#ifndef __CONFIG_H
28#define __CONFIG_H
29
30/*
31 * High Level Configuration Options
32 */
33
34#define CONFIG_MPC5200
35#define CONFIG_MPC5xxx 1 /* This is an MPC5xxx CPU */
36#define CONFIG_MPX5200 1 /* ... on MPX5200 board */
37#define CONFIG_MPC5200_DDR 1 /* ... use DDR RAM */
38#define CONFIG_IPEK01 /* Motherboard is ipek01 */
39
40#define CONFIG_SYS_MPC5XXX_CLKIN 33000000 /* ... running at 33MHz */
41
42#define CONFIG_MISC_INIT_R
43
44#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */
45#define BOOTFLAG_WARM 0x02 /* Software reboot */
46
47#define CONFIG_SYS_CACHELINE_SIZE 32 /* For MPC5xxx CPUs */
48#ifdef CONFIG_CMD_KGDB
49#define CONFIG_SYS_CACHELINE_SHIFT 5 /* log base 2 of the above value */
50#endif
51
52/*
53 * Serial console configuration
54 */
55#define CONFIG_PSC_CONSOLE 1 /* console is on PSC1 */
56#define CONFIG_BAUDRATE 115200 /* ... at 9600 bps */
57#define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200, 230400 }
58
59#define CONFIG_CMDLINE_EDITING 1 /* add command line history */
60
61/*
62 * Video configuration for LIME GDC
63 */
64#define CONFIG_VIDEO
65#ifdef CONFIG_VIDEO
66#define CONFIG_VIDEO_MB862xx
67#define CONFIG_VIDEO_MB862xx_ACCEL
68#define VIDEO_FB_16BPP_WORD_SWAP
69#define CONFIG_CFB_CONSOLE
70#define CONFIG_VIDEO_LOGO
71#define CONFIG_VIDEO_BMP_LOGO
72#define CONFIG_CONSOLE_EXTRA_INFO
73#define CONFIG_VGA_AS_SINGLE_DEVICE
74#define CONFIG_SYS_CONSOLE_IS_IN_ENV
75#define CONFIG_VIDEO_SW_CURSOR
76#define CONFIG_SPLASH_SCREEN
77#define CONFIG_VIDEO_BMP_GZIP
78#define CONFIG_SYS_VIDEO_LOGO_MAX_SIZE (2 << 20) /* decompressed img */
79/* Lime clock frequency */
80#define CONFIG_SYS_MB862xx_CCF 0x90000 /* geo 166MHz other 133MHz */
81/* SDRAM parameter */
82#define CONFIG_SYS_MB862xx_MMR 0x41c767e3
83#endif
84
85/*
86 * PCI Mapping:
87 * 0x40000000 - 0x4fffffff - PCI Memory
88 * 0x50000000 - 0x50ffffff - PCI IO Space
89 */
90#define CONFIG_PCI 1
91#define CONFIG_PCI_PNP 1
92#define CONFIG_PCI_SCAN_SHOW 1
93
94#define CONFIG_PCI_MEM_BUS 0x40000000
95#define CONFIG_PCI_MEM_PHYS CONFIG_PCI_MEM_BUS
96#define CONFIG_PCI_MEM_SIZE 0x10000000
97
98#define CONFIG_PCI_IO_BUS 0x50000000
99#define CONFIG_PCI_IO_PHYS CONFIG_PCI_IO_BUS
100#define CONFIG_PCI_IO_SIZE 0x01000000
101
102#define CONFIG_NET_MULTI 1
103#define CONFIG_MII 1
104#define CONFIG_EEPRO100 1
105#define CONFIG_SYS_RX_ETH_BUFFER 8 /* use 8 rx buffer on eepro100 */
106
107/* Partitions */
108#define CONFIG_DOS_PARTITION
109
110/* USB */
111#define CONFIG_USB_OHCI_NEW
112#define CONFIG_SYS_OHCI_BE_CONTROLLER
113#define CONFIG_USB_STORAGE
114
115#define CONFIG_SYS_USB_OHCI_CPU_INIT
116#define CONFIG_SYS_USB_OHCI_REGS_BASE MPC5XXX_USB
117#define CONFIG_SYS_USB_OHCI_SLOT_NAME "mpc5200"
118#define CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS 15
119
120/*
121 * Command line configuration.
122 */
123#include <config_cmd_default.h>
124
125#ifdef CONFIG_VIDEO
126#define CONFIG_CMD_BMP /* BMP support */
127#endif
128#define CONFIG_CMD_DATE /* support for RTC, date/time...*/
129#define CONFIG_CMD_DHCP /* DHCP Support */
130#define CONFIG_CMD_FAT /* FAT support */
131#define CONFIG_CMD_I2C /* I2C serial bus support */
132#define CONFIG_CMD_IDE /* IDE harddisk support */
133#define CONFIG_CMD_IRQ /* irqinfo */
134#define CONFIG_CMD_MII /* MII support */
135#define CONFIG_CMD_PCI /* pciinfo */
136#define CONFIG_CMD_USB /* USB Support */
137
138#define CONFIG_SYS_LOWBOOT 1
139
140/*
141 * Autobooting
142 */
143#define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */
144
145#define CONFIG_PREBOOT "echo;" \
146 "echo Type \\\"run flash_nfs\\\" to mount root filesystem over NFS;" \
147 "echo"
148
149#undef CONFIG_BOOTARGS
150
151#define CONFIG_EXTRA_ENV_SETTINGS \
152 "netdev=eth0\0" \
153 "consoledev=ttyPSC0\0" \
154 "hostname=ipek01\0" \
155 "nfsargs=setenv bootargs root=/dev/nfs rw " \
156 "nfsroot=${serverip}:${rootpath}\0" \
157 "ramargs=setenv bootargs root=/dev/ram rw\0" \
158 "addip=setenv bootargs ${bootargs} " \
159 "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}" \
160 ":${hostname}:${netdev}:off panic=1\0" \
161 "addtty=setenv bootargs ${bootargs} " \
162 "console=${consoledev},${baudrate}\0" \
163 "flash_nfs=run nfsargs addip addtty;" \
164 "bootm ${kernel_addr} - ${fdtaddr}\0" \
165 "flash_self=run ramargs addip addtty;" \
166 "bootm ${kernel_addr} ${ramdisk_addr} ${fdtaddr}\0" \
167 "net_nfs=tftp 200000 ${bootfile}; tftp ${fdtaddr} ${fdtfile};" \
168 "run nfsargs addip addtty;" \
169 "bootm ${loadaddr} - ${fdtaddr}\0" \
170 "rootpath=/opt/eldk/ppc_6xx\0" \
171 "bootfile=ipek01/uImage\0" \
172 "load=tftp 100000 ipek01/u-boot.bin\0" \
173 "update=protect off FC000000 +60000; era FC000000 +60000; " \
174 "cp.b 100000 FC000000 ${filesize}\0" \
175 "upd=run load;run update\0" \
176 "fdtaddr=800000\0" \
177 "loadaddr=400000\0" \
178 "fdtfile=ipek01/ipek01.dtb\0" \
179 ""
180
181#define CONFIG_BOOTCOMMAND "run flash_self"
182
183/*
184 * IPB Bus clocking configuration.
185 */
186#define CONFIG_SYS_IPBCLK_EQUALS_XLBCLK /* for 133MHz */
187/* PCI clock must be 33, because board will not boot */
188#undef CONFIG_SYS_PCICLK_EQUALS_IPBCLK_DIV2 /* for 66MHz */
189
190/*
191 * Open firmware flat tree support
192 */
193#define CONFIG_OF_LIBFDT 1
194#define CONFIG_OF_BOARD_SETUP 1
195
196#define OF_CPU "PowerPC,5200@0"
197#define OF_SOC "soc5200@f0000000"
198#define OF_TBCLK (bd->bi_busfreq / 4)
199
200/*
201 * I2C configuration
202 */
203#define CONFIG_HARD_I2C 1 /* I2C with hardware support */
204#define CONFIG_SYS_I2C_MODULE 2 /* Select I2C module #1 or #2 */
205
206#define CONFIG_SYS_I2C_SPEED 100000 /* 100 kHz */
207#define CONFIG_SYS_I2C_SLAVE 0x7F
208
209/*
210 * EEPROM configuration
211 */
212#define CONFIG_SYS_I2C_EEPROM_ADDR 0x53
213#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2
214#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 6
215#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 10
216
217/*
218 * RTC configuration
219 */
220#define CONFIG_RTC_PCF8563
221#define CONFIG_SYS_I2C_RTC_ADDR 0x51
222
223#define CONFIG_SYS_FLASH_BASE 0xFC000000
224#define CONFIG_SYS_FLASH_SIZE 0x01000000
225#define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + \
226 CONFIG_SYS_MONITOR_LEN)
227
228#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max num of memory banks */
229#define CONFIG_SYS_MAX_FLASH_SECT 256 /* max num of sects on one chip */
230#define CONFIG_SYS_FLASH_PROTECTION /* "Real" (hardware) sectors protection */
231
232/* use CFI flash driver */
233#define CONFIG_FLASH_CFI_DRIVER
234#define CONFIG_SYS_FLASH_CFI
235#define CONFIG_SYS_FLASH_EMPTY_INFO
236#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 1
237
238/*
239 * Environment settings
240 */
241#define CONFIG_ENV_IS_IN_FLASH 1
242#define CONFIG_ENV_SIZE 0x10000
243#define CONFIG_ENV_SECT_SIZE 0x20000
244#define CONFIG_ENV_OVERWRITE 1
245#define CONFIG_ENV_ADDR_REDUND (CONFIG_ENV_ADDR + CONFIG_ENV_SECT_SIZE)
246#define CONFIG_ENV_SIZE_REDUND CONFIG_ENV_SIZE
247
248/*
249 * Memory map
250 */
251#define CONFIG_SYS_MBAR 0xf0000000
252#define CONFIG_SYS_SDRAM_BASE 0x00000000
253#define CONFIG_SYS_DEFAULT_MBAR 0x80000000
254#define CONFIG_SYS_SRAM_BASE 0xF1000000
255#define CONFIG_SYS_SRAM_SIZE 0x00200000
256#define CONFIG_SYS_LIME_BASE 0xE4000000
257#define CONFIG_SYS_LIME_SIZE 0x04000000
258#define CONFIG_SYS_FPGA_BASE 0xC0000000
259#define CONFIG_SYS_FPGA_SIZE 0x10000000
260#define CONFIG_SYS_MPEG_BASE 0xe2000000
261#define CONFIG_SYS_MPEG_SIZE 0x01000000
262#define CONFIG_SYS_CF_BASE 0xe1000000
263#define CONFIG_SYS_CF_SIZE 0x01000000
264
265/* Use SRAM until RAM will be available */
266#define CONFIG_SYS_INIT_RAM_ADDR MPC5XXX_SRAM
267/* End of used area in DPRAM */
268#define CONFIG_SYS_INIT_RAM_END MPC5XXX_SRAM_SIZE
269
Wolfgang Grandeggercd12f612009-10-23 12:03:16 +0200270/* size in bytes reserved for initial data */
271#define CONFIG_SYS_GBL_DATA_SIZE 128
272
273#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_END - \
274 CONFIG_SYS_GBL_DATA_SIZE)
275#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
276
277#define CONFIG_SYS_MONITOR_BASE TEXT_BASE
278#if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE)
279# define CONFIG_SYS_RAMBOOT 1
280#endif
281
282#define CONFIG_SYS_MONITOR_LEN (384 << 10) /* Reserve 384 kB for Monitor */
283#define CONFIG_SYS_MALLOC_LEN (4 << 20) /* Reserve 128 kB for malloc() */
284#define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
285
286/*
287 * Ethernet configuration
288 */
289#define CONFIG_MPC5xxx_FEC 1
290#define CONFIG_MPC5xxx_FEC_MII100
291#define CONFIG_PHY_ADDR 0x00
292
293/*
294 * GPIO configuration
295 */
296#define CONFIG_SYS_GPS_PORT_CONFIG 0x1d556624
297
298/*
299 * Miscellaneous configurable options
300 */
301#define CONFIG_SYS_LONGHELP /* undef to save memory */
302#define CONFIG_SYS_PROMPT "=> " /* Monitor Command Prompt */
303#ifdef CONFIG_CMD_KGDB
304#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
305#else
306#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
307#endif
308/* Print Buffer Size */
309#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + \
310 sizeof(CONFIG_SYS_PROMPT) + 16)
311/* max number of command args */
312#define CONFIG_SYS_MAXARGS 16
313/* Boot Argument Buffer Size */
314#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE
315
Wolfgang Grandeggercd12f612009-10-23 12:03:16 +0200316#define CONFIG_SYS_MEMTEST_START 0x00100000 /* memtest works on */
317#define CONFIG_SYS_MEMTEST_END 0x00f00000 /* 1...15 MB in DRAM */
318
319#define CONFIG_SYS_LOAD_ADDR 0x100000 /* default load address */
320
321#define CONFIG_SYS_HZ 1000 /* decrementer freq: 1 ms ticks */
322#define CONFIG_LOOPW
323
324/*
325 * Various low-level settings
326 */
Wolfgang Grandeggercd12f612009-10-23 12:03:16 +0200327#define CONFIG_SYS_HID0_INIT HID0_ICE | HID0_ICFI
328#define CONFIG_SYS_HID0_FINAL HID0_ICE
Wolfgang Grandeggercd12f612009-10-23 12:03:16 +0200329
330#define CONFIG_SYS_BOOTCS_START CONFIG_SYS_FLASH_BASE
331#define CONFIG_SYS_BOOTCS_SIZE CONFIG_SYS_FLASH_SIZE
332#define CONFIG_SYS_CS0_START CONFIG_SYS_FLASH_BASE
333#define CONFIG_SYS_CS0_SIZE CONFIG_SYS_FLASH_SIZE
334#define CONFIG_SYS_CS1_START CONFIG_SYS_SRAM_BASE
335#define CONFIG_SYS_CS1_SIZE CONFIG_SYS_SRAM_SIZE
336#define CONFIG_SYS_CS3_START CONFIG_SYS_LIME_BASE
337#define CONFIG_SYS_CS3_SIZE CONFIG_SYS_LIME_SIZE
338#define CONFIG_SYS_CS6_START CONFIG_SYS_FPGA_BASE
339#define CONFIG_SYS_CS6_SIZE CONFIG_SYS_FPGA_SIZE
340#define CONFIG_SYS_CS5_START CONFIG_SYS_CF_BASE
341#define CONFIG_SYS_CS5_SIZE CONFIG_SYS_CF_SIZE
342#define CONFIG_SYS_CS7_START CONFIG_SYS_MPEG_BASE
343#define CONFIG_SYS_CS7_SIZE CONFIG_SYS_MPEG_SIZE
344
345#ifdef CONFIG_SYS_PCISPEED_66
346#define CONFIG_SYS_BOOTCS_CFG 0x0006F900
347#define CONFIG_SYS_CS1_CFG 0x0004FB00
348#define CONFIG_SYS_CS2_CFG 0x0006F900
349#else
350#define CONFIG_SYS_BOOTCS_CFG 0x0002F900
351#define CONFIG_SYS_CS1_CFG 0x0001FB00
352#define CONFIG_SYS_CS2_CFG 0x0002F90C
353#endif
354
355/*
356 * Ack active, Muxed mode, AS=24 bit address, DS=32 bit data, 0
357 * waitstates, writeswap and readswap enabled
358 */
359#define CONFIG_SYS_CS3_CFG 0x00FFFB0C
360#define CONFIG_SYS_CS6_CFG 0x00FFFB0C
361#define CONFIG_SYS_CS7_CFG 0x4040751C
362
363#define CONFIG_SYS_CS_BURST 0x00000000
364#define CONFIG_SYS_CS_DEADCYCLE 0x33330000
365
366#define CONFIG_SYS_RESET_ADDRESS 0xff000000
367
368/*-----------------------------------------------------------------------
369 * USB stuff
370 *-----------------------------------------------------------------------
371 */
372#define CONFIG_USB_CLOCK 0x0001BBBB
373#define CONFIG_USB_CONFIG 0x00005000
374
375/*-----------------------------------------------------------------------
376 * IDE/ATA stuff Supports IDE harddisk
377 *-----------------------------------------------------------------------
378 */
379#define CONFIG_IDE_PREINIT
380
381#define CONFIG_SYS_IDE_MAXBUS 1 /* max. 1 IDE bus */
382#define CONFIG_SYS_IDE_MAXDEVICE 2 /* max. 2 drives per IDE bus */
383
384#define CONFIG_SYS_ATA_IDE0_OFFSET 0x0000
385
386#define CONFIG_SYS_ATA_BASE_ADDR MPC5XXX_ATA
387
388/* Offset for data I/O */
389#define CONFIG_SYS_ATA_DATA_OFFSET (0x0060)
390
391/* Offset for normal register accesses */
392#define CONFIG_SYS_ATA_REG_OFFSET (CONFIG_SYS_ATA_DATA_OFFSET)
393
394/* Offset for alternate registers */
395#define CONFIG_SYS_ATA_ALT_OFFSET (0x005C)
396
397/* Interval between registers */
398#define CONFIG_SYS_ATA_STRIDE 4
399
400#endif /* __CONFIG_H */