blob: 9da98d0af27795e3f6c52d58eb2befbf4e3595c8 [file] [log] [blame]
Michael Trimarchicc74cab2022-09-18 17:09:53 +02001/* SPDX-License-Identifier: GPL-2.0+ */
2/*
3 * Copyright (C) 2021 Amarula Solutions B.V.
4 *
5 */
6#ifndef __IMX6ULZ_SMM_M2_CONFIG_H
7#define __IMX6ULZ_SMM_M2_CONFIG_H
8
9#include "mx6_common.h"
10
11#include <asm/arch/imx-regs.h>
12#include <linux/sizes.h>
13#include <linux/stringify.h>
14
Tom Rini4db38662022-12-04 10:04:55 -050015#define CFG_MXC_UART_BASE UART4_BASE
Michael Trimarchicc74cab2022-09-18 17:09:53 +020016
17#ifndef CONFIG_SPL_BUILD
18
19#define BOOT_TARGET_DEVICES(func) \
20 func(NAND, nand, 0) \
21
22#include <config_distro_bootcmd.h>
23
24#endif /* !CONFIG_SPL_BUILD */
25
26#define MEM_LAYOUT_ENV_SETTINGS \
27 "scriptaddr=" __stringify(CONFIG_SYS_LOAD_ADDR) "\0" \
28 "kernel_addr_r=" __stringify(CONFIG_SYS_LOAD_ADDR) "\0" \
29 "fdt_addr_r=0x81000000\0" \
30 "fdtfile=" CONFIG_DEFAULT_FDT_FILE "\0" \
31 "bootcmd_mfg=echo Running fastboot mode; fastboot usb 0\0" \
32
33#define NANDARGS \
34 "mtdids=" CONFIG_MTDIDS_DEFAULT "\0" \
35 CONFIG_MTDPARTS_DEFAULT "\0" \
36 "nandargs=setenv bootargs " \
37 "${optargs} " \
38 "mtdparts=${mtdparts} " \
39 "root=${nandroot} " \
40 "rootfstype=${nandrootfstype}\0" \
41 "nandroot=ubi0:root rw ubi.mtd=rootfs\0" \
42 "nandrootfstype=ubifs rootwait=1\0" \
43 "nandboot=echo Booting from nand ...; " \
44 "run nandargs; " \
45 "nand read ${fdt_addr_r} nanddtb; " \
46 "nand read ${loadaddr} kernel; " \
47 "bootz ${loadaddr} - ${fdt_addr_r}\0"
48
49#define BOOTENV_DEV_NAND(devtypeu, devtypel, instance) \
50 "bootcmd_" #devtypel #instance "=" \
51 "run nandboot\0"
52
53#define BOOTENV_DEV_NAME_NAND(devtypeu, devtypel, instance) \
54 #devtypel #instance " "
55
56/* Initial environment variables */
Tom Rini0613c362022-12-04 10:03:50 -050057#define CFG_EXTRA_ENV_SETTINGS \
Michael Trimarchicc74cab2022-09-18 17:09:53 +020058 MEM_LAYOUT_ENV_SETTINGS \
59 NANDARGS \
60 BOOTENV
61
62/* Physical Memory Map */
63#define PHYS_SDRAM MMDC0_ARB_BASE_ADDR
64#define PHYS_SDRAM_SIZE SZ_128M
65
Tom Riniaa6e94d2022-11-16 13:10:37 -050066#define CFG_SYS_SDRAM_BASE PHYS_SDRAM
Tom Rini65cc0e22022-11-16 13:10:41 -050067#define CFG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR
68#define CFG_SYS_INIT_RAM_SIZE IRAM_SIZE
Michael Trimarchicc74cab2022-09-18 17:09:53 +020069
70/* NAND */
Michael Trimarchicc74cab2022-09-18 17:09:53 +020071
Tom Rini4e590942022-11-12 17:36:51 -050072#define CFG_SYS_NAND_BASE 0x20000000
Michael Trimarchicc74cab2022-09-18 17:09:53 +020073
74#endif