blob: cd71ec8e1698aad0e2e010b276078ccd6584c8bb [file] [log] [blame]
York Suna4c66502012-08-17 08:22:39 +00001Table of interleaving 2-4 controllers
2=====================================
3 +--------------+-----------------------------------------------------------+
4 |Configuration | Memory Controller |
5 | | 1 2 3 4 |
6 |--------------+--------------+--------------+-----------------------------+
7 | Two memory | Not Intlv'ed | Not Intlv'ed | |
8 | complexes +--------------+--------------+ |
9 | | 2-way Intlv'ed | |
10 |--------------+--------------+--------------+--------------+ |
11 | | Not Intlv'ed | Not Intlv'ed | Not Intlv'ed | |
12 | Three memory +--------------+--------------+--------------+ |
13 | complexes | 2-way Intlv'ed | Not Intlv'ed | |
14 | +-----------------------------+--------------+ |
15 | | 3-way Intlv'ed | |
16 +--------------+--------------+--------------+--------------+--------------+
17 | | Not Intlv'ed | Not Intlv'ed | Not Intlv'ed | Not Intlv'ed |
18 | Four memory +--------------+--------------+--------------+--------------+
19 | complexes | 2-way Intlv'ed | 2-way Intlv'ed |
20 | +-----------------------------+-----------------------------+
21 | | 4-way Intlv'ed |
22 +--------------+-----------------------------------------------------------+
Haiying Wangc9ffd832008-10-03 12:37:10 -040023
York Suna4c66502012-08-17 08:22:39 +000024
25Table of 2-way interleaving modes supported in cpu/8xxx/ddr/
Haiying Wangc9ffd832008-10-03 12:37:10 -040026======================================================
27 +-------------+---------------------------------------------------------+
Wolfgang Denkd1a24f02011-02-02 22:36:10 +010028 | | Rank Interleaving |
29 | +--------+-----------+-----------+------------+-----------+
30 |Memory | | | | 2x2 | 4x1 |
31 |Controller | None | 2x1 lower | 2x1 upper | {CS0+CS1}, | {CS0+CS1+ |
32 |Interleaving | | {CS0+CS1} | {CS2+CS3} | {CS2+CS3} | CS2+CS3} |
Haiying Wangc9ffd832008-10-03 12:37:10 -040033 +-------------+--------+-----------+-----------+------------+-----------+
Wolfgang Denkd1a24f02011-02-02 22:36:10 +010034 |None | Yes | Yes | Yes | Yes | Yes |
Haiying Wangc9ffd832008-10-03 12:37:10 -040035 +-------------+--------+-----------+-----------+------------+-----------+
Wolfgang Denkd1a24f02011-02-02 22:36:10 +010036 |Cacheline | Yes | Yes | No | No, Only(*)| Yes |
37 | |CS0 Only| | | {CS0+CS1} | |
Haiying Wangc9ffd832008-10-03 12:37:10 -040038 +-------------+--------+-----------+-----------+------------+-----------+
Wolfgang Denkd1a24f02011-02-02 22:36:10 +010039 |Page | Yes | Yes | No | No, Only(*)| Yes |
40 | |CS0 Only| | | {CS0+CS1} | |
Haiying Wangc9ffd832008-10-03 12:37:10 -040041 +-------------+--------+-----------+-----------+------------+-----------+
Wolfgang Denkd1a24f02011-02-02 22:36:10 +010042 |Bank | Yes | Yes | No | No, Only(*)| Yes |
43 | |CS0 Only| | | {CS0+CS1} | |
Haiying Wangc9ffd832008-10-03 12:37:10 -040044 +-------------+--------+-----------+-----------+------------+-----------+
Wolfgang Denkd1a24f02011-02-02 22:36:10 +010045 |Superbank | No | Yes | No | No, Only(*)| Yes |
46 | | | | | {CS0+CS1} | |
Haiying Wangc9ffd832008-10-03 12:37:10 -040047 +-------------+--------+-----------+-----------+------------+-----------+
48 (*) Although the hardware can be configured with memory controller
49 interleaving using "2x2" rank interleaving, it only interleaves {CS0+CS1}
50 from each controller. {CS2+CS3} on each controller are only rank
51 interleaved on that controller.
52
york076bff82010-07-02 22:25:52 +000053 For memory controller interleaving, identical DIMMs are suggested. Software
54 doesn't check the size or organization of interleaved DIMMs.
55
Haiying Wangc9ffd832008-10-03 12:37:10 -040056The ways to configure the ddr interleaving mode
57==============================================
581. In board header file(e.g.MPC8572DS.h), add default interleaving setting
59 under "CONFIG_EXTRA_ENV_SETTINGS", like:
60 #define CONFIG_EXTRA_ENV_SETTINGS \
Kumar Gala79e4e642010-07-14 10:04:21 -050061 "hwconfig=fsl_ddr:ctlr_intlv=bank" \
Haiying Wangc9ffd832008-10-03 12:37:10 -040062 ......
63
Bin Menga1875592016-02-05 19:30:11 -0800642. Run U-Boot "setenv" command to configure the memory interleaving mode.
Haiying Wangc9ffd832008-10-03 12:37:10 -040065 Either numerical or string value is accepted.
66
67 # disable memory controller interleaving
Kumar Gala79e4e642010-07-14 10:04:21 -050068 setenv hwconfig "fsl_ddr:ctlr_intlv=null"
Haiying Wangc9ffd832008-10-03 12:37:10 -040069
70 # cacheline interleaving
Kumar Gala79e4e642010-07-14 10:04:21 -050071 setenv hwconfig "fsl_ddr:ctlr_intlv=cacheline"
Haiying Wangc9ffd832008-10-03 12:37:10 -040072
73 # page interleaving
Kumar Gala79e4e642010-07-14 10:04:21 -050074 setenv hwconfig "fsl_ddr:ctlr_intlv=page"
Haiying Wangc9ffd832008-10-03 12:37:10 -040075
76 # bank interleaving
Kumar Gala79e4e642010-07-14 10:04:21 -050077 setenv hwconfig "fsl_ddr:ctlr_intlv=bank"
Haiying Wangc9ffd832008-10-03 12:37:10 -040078
79 # superbank
Kumar Gala79e4e642010-07-14 10:04:21 -050080 setenv hwconfig "fsl_ddr:ctlr_intlv=superbank"
Haiying Wangc9ffd832008-10-03 12:37:10 -040081
York Suna4c66502012-08-17 08:22:39 +000082 # 1KB 3-way interleaving
83 setenv hwconfig "fsl_ddr:ctlr_intlv=3way_1KB"
84
85 # 4KB 3-way interleaving
86 setenv hwconfig "fsl_ddr:ctlr_intlv=3way_4KB"
87
88 # 8KB 3-way interleaving
89 setenv hwconfig "fsl_ddr:ctlr_intlv=3way_8KB"
90
Haiying Wangc9ffd832008-10-03 12:37:10 -040091 # disable bank (chip-select) interleaving
Kumar Gala79e4e642010-07-14 10:04:21 -050092 setenv hwconfig "fsl_ddr:bank_intlv=null"
Haiying Wangc9ffd832008-10-03 12:37:10 -040093
94 # bank(chip-select) interleaving cs0+cs1
Kumar Gala79e4e642010-07-14 10:04:21 -050095 setenv hwconfig "fsl_ddr:bank_intlv=cs0_cs1"
Haiying Wangc9ffd832008-10-03 12:37:10 -040096
97 # bank(chip-select) interleaving cs2+cs3
Kumar Gala79e4e642010-07-14 10:04:21 -050098 setenv hwconfig "fsl_ddr:bank_intlv=cs2_cs3"
Haiying Wangc9ffd832008-10-03 12:37:10 -040099
100 # bank(chip-select) interleaving (cs0+cs1) and (cs2+cs3) (2x2)
Kumar Gala79e4e642010-07-14 10:04:21 -0500101 setenv hwconfig "fsl_ddr:bank_intlv=cs0_cs1_and_cs2_cs3"
Haiying Wangc9ffd832008-10-03 12:37:10 -0400102
103 # bank(chip-select) interleaving (cs0+cs1+cs2+cs3) (4x1)
Kumar Gala79e4e642010-07-14 10:04:21 -0500104 setenv hwconfig "fsl_ddr:bank_intlv=cs0_cs1_cs2_cs3"
105
York Sun89b78092012-10-08 07:44:27 +0000106 # bank(chip-select) interleaving (auto)
107 setenv hwconfig "fsl_ddr:bank_intlv=auto"
108 This auto mode only select from cs0_cs1_cs2_cs3, cs0_cs1, null dependings
109 on DIMMs.
110
york7fd101c2010-07-02 22:25:54 +0000111Memory controller address hashing
112==================================
113If the DDR controller supports address hashing, it can be enabled by hwconfig.
114
115Syntax is:
116hwconfig=fsl_ddr:addr_hash=true
117
York Sun47df8f02011-01-10 12:02:57 +0000118Memory controller ECC on/off
119============================
120If ECC is enabled in board configuratoin file, i.e. #define CONFIG_DDR_ECC,
121ECC can be turned on/off by hwconfig.
122
123Syntax is
124hwconfig=fsl_ddr:ecc=off
York Sunebbe11d2010-09-28 15:20:33 -0700125
126Memory testing options for mpc85xx
127==================================
Bin Menga1875592016-02-05 19:30:11 -08001281. Memory test can be done once U-Boot prompt comes up using mtest, or
York Sunebbe11d2010-09-28 15:20:33 -07001292. Memory test can be done with Power-On-Self-Test function, activated at
130 compile time.
131
132 In order to enable the POST memory test, CONFIG_POST needs to be
133 defined in board configuraiton header file. By default, POST memory test
134 performs a fast test. A slow test can be enabled by changing the flag at
135 compiling time. To test memory bigger than 2GB, 36BIT support is needed.
136 Memory is tested within a 2GB window. TLBs are used to map the virtual 2GB
137 window to physical address so that all physical memory can be tested.
138
york7fd101c2010-07-02 22:25:54 +0000139Combination of hwconfig
140=======================
141Hwconfig can be combined with multiple parameters, for example, on a supported
142platform
143
York Sune1fd16b2011-01-10 12:03:00 +0000144hwconfig=fsl_ddr:addr_hash=true,ctlr_intlv=cacheline,bank_intlv=cs0_cs1_cs2_cs3,ecc=on
145
146Table for dynamic ODT for DDR3
147==============================
148For single-slot system with quad-rank DIMM and dual-slot system, dynamic ODT may
149be needed, depending on the configuration. The numbers in the following tables are
150in Ohms.
151
152* denotes dynamic ODT
153
154Two slots system
155+-----------------------+----------+---------------+-----------------------------+-----------------------------+
Wolfgang Denkd1a24f02011-02-02 22:36:10 +0100156| Configuration | |DRAM controller| Slot 1 | Slot 2 |
York Sune1fd16b2011-01-10 12:03:00 +0000157+-----------+-----------+----------+-------+-------+--------------+--------------+--------------+--------------+
Wolfgang Denkd1a24f02011-02-02 22:36:10 +0100158| | | | | | Rank 1 | Rank 2 | Rank 1 | Rank 2 |
159+ Slot 1 | Slot 2 |Write/Read| Write | Read |-------+------+-------+------+-------+------+-------+------+
160| | | | | | Write | Read | Write | Read | Write | Read | Write | Read |
York Sune1fd16b2011-01-10 12:03:00 +0000161+-----------+-----------+----------+-------+-------+-------+------+-------+------+-------+------+-------+------+
Wolfgang Denkd1a24f02011-02-02 22:36:10 +0100162| | | Slot 1 | off | 75 | 120 | off | off | off | off | off | 30 | 30 |
York Sune1fd16b2011-01-10 12:03:00 +0000163| Dual Rank | Dual Rank |----------+-------+-------+-------+------+-------+------+-------+------+-------+------+
Wolfgang Denkd1a24f02011-02-02 22:36:10 +0100164| | | Slot 2 | off | 75 | off | off | 30 | 30 | 120 | off | off | off |
York Sune1fd16b2011-01-10 12:03:00 +0000165+-----------+-----------+----------+-------+-------+-------+------+-------+------+-------+------+-------+------+
Wolfgang Denkd1a24f02011-02-02 22:36:10 +0100166| | | Slot 1 | off | 75 | 120 | off | off | off | 20 | 20 | | |
York Sune1fd16b2011-01-10 12:03:00 +0000167| Dual Rank |Single Rank|----------+-------+-------+-------+------+-------+------+-------+------+-------+------+
Wolfgang Denkd1a24f02011-02-02 22:36:10 +0100168| | | Slot 2 | off | 75 | off | off | 20 | 20 | 120 *| off | | |
York Sune1fd16b2011-01-10 12:03:00 +0000169+-----------+-----------+----------+-------+-------+-------+------+-------+------+-------+------+-------+------+
Wolfgang Denkd1a24f02011-02-02 22:36:10 +0100170| | | Slot 1 | off | 75 | 120 *| off | | | off | off | 20 | 20 |
York Sune1fd16b2011-01-10 12:03:00 +0000171|Single Rank| Dual Rank |----------+-------+-------+-------+------+-------+------+-------+------+-------+------+
Wolfgang Denkd1a24f02011-02-02 22:36:10 +0100172| | | Slot 2 | off | 75 | 20 | 20 | | | 120 | off | off | off |
York Sune1fd16b2011-01-10 12:03:00 +0000173+-----------+-----------+----------+-------+-------+-------+------+-------+------+-------+------+-------+------+
Wolfgang Denkd1a24f02011-02-02 22:36:10 +0100174| | | Slot 1 | off | 75 | 120 *| off | | | 30 | 30 | | |
York Sune1fd16b2011-01-10 12:03:00 +0000175|Single Rank|Single Rank|----------+-------+-------+-------+------+-------+------+-------+------+-------+------+
Wolfgang Denkd1a24f02011-02-02 22:36:10 +0100176| | | Slot 2 | off | 75 | 30 | 30 | | | 120 *| off | | |
York Sune1fd16b2011-01-10 12:03:00 +0000177+-----------+-----------+----------+-------+-------+-------+------+-------+------+-------+------+-------+------+
Wolfgang Denkd1a24f02011-02-02 22:36:10 +0100178| Dual Rank | Empty | Slot 1 | off | 75 | 40 | off | off | off | | | | |
York Sune1fd16b2011-01-10 12:03:00 +0000179+-----------+-----------+----------+-------+-------+-------+------+-------+------+-------+------+-------+------+
Wolfgang Denkd1a24f02011-02-02 22:36:10 +0100180| Empty | Dual Rank | Slot 2 | off | 75 | | | | | 40 | off | off | off |
York Sune1fd16b2011-01-10 12:03:00 +0000181+-----------+-----------+----------+-------+-------+-------+------+-------+------+-------+------+-------+------+
Wolfgang Denkd1a24f02011-02-02 22:36:10 +0100182|Single Rank| Empty | Slot 1 | off | 75 | 40 | off | | | | | | |
York Sune1fd16b2011-01-10 12:03:00 +0000183+-----------+-----------+----------+-------+-------+-------+------+-------+------+-------+------+-------+------+
Wolfgang Denkd1a24f02011-02-02 22:36:10 +0100184| Empty |Single Rank| Slot 2 | off | 75 | | | | | 40 | off | | |
York Sune1fd16b2011-01-10 12:03:00 +0000185+-----------+-----------+----------+-------+-------+-------+------+-------+------+-------+------+-------+------+
186
187Single slot system
188+-------------+------------+---------------+-----------------------------+-----------------------------+
Wolfgang Denkd1a24f02011-02-02 22:36:10 +0100189| | |DRAM controller| Rank 1 | Rank 2 | Rank 3 | Rank 4 |
York Sune1fd16b2011-01-10 12:03:00 +0000190|Configuration| Write/Read |-------+-------+-------+------+-------+------+-------+------+-------+------+
Wolfgang Denkd1a24f02011-02-02 22:36:10 +0100191| | | Write | Read | Write | Read | Write | Read | Write | Read | Write | Read |
York Sune1fd16b2011-01-10 12:03:00 +0000192+-------------+------------+-------+-------+-------+------+-------+------+-------+------+-------+------+
Wolfgang Denkd1a24f02011-02-02 22:36:10 +0100193| | R1 | off | 75 | 120 *| off | off | off | 20 | 20 | off | off |
194| |------------+-------+-------+-------+------+-------+------+-------+------+-------+------+
195| | R2 | off | 75 | off | 20 | 120 | off | 20 | 20 | off | off |
York Sune1fd16b2011-01-10 12:03:00 +0000196| Quad Rank |------------+-------+-------+-------+------+-------+------+-------+------+-------+------+
Wolfgang Denkd1a24f02011-02-02 22:36:10 +0100197| | R3 | off | 75 | 20 | 20 | off | off | 120 *| off | off | off |
198| |------------+-------+-------+-------+------+-------+------+-------+------+-------+------+
199| | R4 | off | 75 | 20 | 20 | off | off | off | 20 | 120 | off |
York Sune1fd16b2011-01-10 12:03:00 +0000200+-------------+------------+-------+-------+-------+------+-------+------+-------+------+-------+------+
Wolfgang Denkd1a24f02011-02-02 22:36:10 +0100201| | R1 | off | 75 | 40 | off | off | off |
York Sune1fd16b2011-01-10 12:03:00 +0000202| Dual Rank |------------+-------+-------+-------+------+-------+------+
Wolfgang Denkd1a24f02011-02-02 22:36:10 +0100203| | R2 | off | 75 | 40 | off | off | off |
York Sune1fd16b2011-01-10 12:03:00 +0000204+-------------+------------+-------+-------+-------+------+-------+------+
Wolfgang Denkd1a24f02011-02-02 22:36:10 +0100205| Single Rank | R1 | off | 75 | 40 | off |
York Sune1fd16b2011-01-10 12:03:00 +0000206+-------------+------------+-------+-------+-------+------+
207
208Reference http://www.xrosstalkmag.com/mag_issues/xrosstalk_oct08_final.pdf
Wolfgang Denkd1a24f02011-02-02 22:36:10 +0100209 http://download.micron.com/pdf/technotes/ddr3/tn4108_ddr3_design_guide.pdf
York Sun4e573822011-08-26 11:32:43 -0700210
211
212Table for ODT for DDR2
213======================
214Two slots system
215+-----------------------+----------+---------------+-----------------------------+-----------------------------+
216| Configuration | |DRAM controller| Slot 1 | Slot 2 |
217+-----------+-----------+----------+-------+-------+--------------+--------------+--------------+--------------+
218| | | | | | Rank 1 | Rank 2 | Rank 1 | Rank 2 |
219+ Slot 1 | Slot 2 |Write/Read| Write | Read |-------+------+-------+------+-------+------+-------+------+
220| | | | | | Write | Read | Write | Read | Write | Read | Write | Read |
221+-----------+-----------+----------+-------+-------+-------+------+-------+------+-------+------+-------+------+
222| | | Slot 1 | off | 150 | off | off | off | off | 75 | 75 | off | off |
223| Dual Rank | Dual Rank |----------+-------+-------+-------+------+-------+------+-------+------+-------+------+
224| | | Slot 2 | off | 150 | 75 | 75 | off | off | off | off | off | off |
225+-----------+-----------+----------+-------+-------+-------+------+-------+------+-------+------+-------+------+
226| | | Slot 1 | off | 150 | off | off | off | off | 75 | 75 | | |
227| Dual Rank |Single Rank|----------+-------+-------+-------+------+-------+------+-------+------+-------+------+
228| | | Slot 2 | off | 150 | 75 | 75 | off | off | off | off | | |
229+-----------+-----------+----------+-------+-------+-------+------+-------+------+-------+------+-------+------+
230| | | Slot 1 | off | 150 | off | off | | | 75 | 75 | off | off |
231|Single Rank| Dual Rank |----------+-------+-------+-------+------+-------+------+-------+------+-------+------+
232| | | Slot 2 | off | 150 | 75 | 75 | | | off | off | off | off |
233+-----------+-----------+----------+-------+-------+-------+------+-------+------+-------+------+-------+------+
234| | | Slot 1 | off | 150 | off | off | | | 75 | 75 | | |
235|Single Rank|Single Rank|----------+-------+-------+-------+------+-------+------+-------+------+-------+------+
236| | | Slot 2 | off | 150 | 75 | 75 | | | off | off | | |
237+-----------+-----------+----------+-------+-------+-------+------+-------+------+-------+------+-------+------+
238| Dual Rank | Empty | Slot 1 | off | 75 | 150 | off | off | off | | | | |
239+-----------+-----------+----------+-------+-------+-------+------+-------+------+-------+------+-------+------+
240| Empty | Dual Rank | Slot 2 | off | 75 | | | | | 150 | off | off | off |
241+-----------+-----------+----------+-------+-------+-------+------+-------+------+-------+------+-------+------+
242|Single Rank| Empty | Slot 1 | off | 75 | 150 | off | | | | | | |
243+-----------+-----------+----------+-------+-------+-------+------+-------+------+-------+------+-------+------+
244| Empty |Single Rank| Slot 2 | off | 75 | | | | | 150 | off | | |
245+-----------+-----------+----------+-------+-------+-------+------+-------+------+-------+------+-------+------+
246
247Single slot system
248+-------------+------------+---------------+-----------------------------+
249| | |DRAM controller| Rank 1 | Rank 2 |
250|Configuration| Write/Read |-------+-------+-------+------+-------+------+
251| | | Write | Read | Write | Read | Write | Read |
252+-------------+------------+-------+-------+-------+------+-------+------+
253| | R1 | off | 75 | 150 | off | off | off |
254| Dual Rank |------------+-------+-------+-------+------+-------+------+
255| | R2 | off | 75 | 150 | off | off | off |
256+-------------+------------+-------+-------+-------+------+-------+------+
257| Single Rank | R1 | off | 75 | 150 | off |
258+-------------+------------+-------+-------+-------+------+
259
260Reference http://www.samsung.com/global/business/semiconductor/products/dram/downloads/applicationnote/ddr2_odt_control_200603.pdf
261
York Sun6f5e1dc2011-09-16 13:21:35 -0700262
263Interactive DDR debugging
264===========================
265
James Yang02a9ce72013-01-04 08:14:03 +0000266For DDR parameter tuning up and debugging, the interactive DDR debugger can
267be activated by setting the environment variable "ddr_interactive" to any
268value. (The value of ddr_interactive may have a meaning in the future, but,
269for now, the presence of the variable will cause the debugger to run.) Once
Bin Menga1875592016-02-05 19:30:11 -0800270activated, U-Boot will show the prompt "FSL DDR>" before enabling the DDR
James Yang02a9ce72013-01-04 08:14:03 +0000271controller. The available commands are printed by typing "help".
York Sun6f5e1dc2011-09-16 13:21:35 -0700272
James Yang02a9ce72013-01-04 08:14:03 +0000273Another way to enter the interactive DDR debugger without setting the
274environment variable is to send the 'd' character early during the boot
275process. To save booting time, no additional delay is added, so the window
276to send the key press is very short -- basically, it is the time before the
277memory controller code starts to run. For example, when rebooting from
Bin Menga1875592016-02-05 19:30:11 -0800278within U-Boot, the user must press 'd' IMMEDIATELY after hitting enter to
James Yang02a9ce72013-01-04 08:14:03 +0000279initiate a 'reset' command. In case of power on/reset, the user can hold
280down the 'd' key while applying power or hitting the board's reset button.
York Sune750cfa2013-01-04 08:13:59 +0000281
York Sun6f5e1dc2011-09-16 13:21:35 -0700282The example flow of using interactive debugging is
283type command "compute" to calculate the parameters from the default
284type command "print" with arguments to show SPD, options, registers
285type command "edit" with arguments to change any if desired
James Yang5926ee32013-01-04 08:14:02 +0000286type command "copy" with arguments to copy controller/dimm settings
York Sun6f5e1dc2011-09-16 13:21:35 -0700287type command "go" to continue calculation and enable DDR controller
James Yang02a9ce72013-01-04 08:14:03 +0000288
289Additional commands to restart the debugging are:
York Sun6f5e1dc2011-09-16 13:21:35 -0700290type command "reset" to reset the board
291type command "recompute" to reload SPD and start over
292
293Note, check "next_step" to show the flow. For example, after edit opts, the
294next_step is STEP_ASSIGN_ADDRESSES. After editing registers, the next_step is
James Yang02a9ce72013-01-04 08:14:03 +0000295STEP_PROGRAM_REGS. Upon issuing command "go", the debugger will program the
296DDR controller with the current setting without further calculation and then
297exit to resume the booting of the machine.
York Sun6f5e1dc2011-09-16 13:21:35 -0700298
299The detail syntax for each commands are
300
301print [c<n>] [d<n>] [spd] [dimmparms] [commonparms] [opts] [addresses] [regs]
302 c<n> - the controller number, eg. c0, c1
303 d<n> - the DIMM number, eg. d0, d1
304 spd - print SPD data
Thomas Weberc46bf092012-03-24 22:44:01 +0000305 dimmparms - DIMM parameters, calculated from SPD
York Sun6f5e1dc2011-09-16 13:21:35 -0700306 commonparms - lowest common parameters for all DIMMs
307 opts - options
308 addresses - address assignment (not implemented yet)
309 regs - controller registers
310
311edit <c#> <d#> <spd|dimmparms|commonparms|opts|addresses|regs> <element> <value>
312 c<n> - the controller number, eg. c0, c1
313 d<n> - the DIMM number, eg. d0, d1
314 spd - print SPD data
Thomas Weberc46bf092012-03-24 22:44:01 +0000315 dimmparms - DIMM parameters, calculated from SPD
York Sun6f5e1dc2011-09-16 13:21:35 -0700316 commonparms - lowest common parameters for all DIMMs
317 opts - options
318 addresses - address assignment (not implemented yet)
319 regs - controller registers
320 <element> - name of the modified element
321 byte number if the object is SPD
322 <value> - decimal or heximal (prefixed with 0x) numbers
323
James Yang5926ee32013-01-04 08:14:02 +0000324copy <src c#> <src d#> <spd|dimmparms|commonparms|opts|addresses|regs> <dst c#> <dst d#>
325 same as for "edit" command
326 DIMM numbers ignored for commonparms, opts, and regs
327
York Sun6f5e1dc2011-09-16 13:21:35 -0700328reset
329 no arguement - reset the board
330
331recompute
332 no argument - reload SPD and start over
333
334compute
335 no argument - recompute from current next_step
336
337next_step
338 no argument - show current next_step
339
340help
341 no argument - print a list of all commands
342
343go
Bin Menga1875592016-02-05 19:30:11 -0800344 no argument - program memory controller(s) and continue with U-Boot
York Sun6f5e1dc2011-09-16 13:21:35 -0700345
346Examples of debugging flow
347
348 FSL DDR>compute
349 Detected UDIMM UG51U6400N8SU-ACF
James Yang02a9ce72013-01-04 08:14:03 +0000350 FSL DDR>print
York Sun6f5e1dc2011-09-16 13:21:35 -0700351 print [c<n>] [d<n>] [spd] [dimmparms] [commonparms] [opts] [addresses] [regs]
352 FSL DDR>print dimmparms
353 DIMM parameters: Controller=0 DIMM=0
354 DIMM organization parameters:
355 module part name = UG51U6400N8SU-ACF
356 rank_density = 2147483648 bytes (2048 megabytes)
357 capacity = 4294967296 bytes (4096 megabytes)
358 burst_lengths_bitmask = 0C
359 base_addresss = 0 (00000000 00000000)
360 n_ranks = 2
361 data_width = 64
362 primary_sdram_width = 64
363 ec_sdram_width = 0
364 registered_dimm = 0
365 n_row_addr = 15
366 n_col_addr = 10
367 edc_config = 0
368 n_banks_per_sdram_device = 8
369 tCKmin_X_ps = 1500
370 tCKmin_X_minus_1_ps = 0
371 tCKmin_X_minus_2_ps = 0
372 tCKmax_ps = 0
373 caslat_X = 960
374 tAA_ps = 13125
375 caslat_X_minus_1 = 0
376 caslat_X_minus_2 = 0
377 caslat_lowest_derated = 0
378 tRCD_ps = 13125
379 tRP_ps = 13125
380 tRAS_ps = 36000
381 tWR_ps = 15000
382 tWTR_ps = 7500
383 tRFC_ps = 160000
384 tRRD_ps = 6000
385 tRC_ps = 49125
386 refresh_rate_ps = 7800000
387 tIS_ps = 0
388 tIH_ps = 0
389 tDS_ps = 0
390 tDH_ps = 0
391 tRTP_ps = 7500
392 tDQSQ_max_ps = 0
393 tQHS_ps = 0
394 FSL DDR>edit c0 opts ECC_mode 0
395 FSL DDR>edit c0 regs cs0_bnds 0x000000FF
396 FSL DDR>go
397 2 GiB left unmapped
398 4 GiB (DDR3, 64-bit, CL=9, ECC off)
399 DDR Chip-Select Interleaving Mode: CS0+CS1
400 Testing 0x00000000 - 0x7fffffff
401 Testing 0x80000000 - 0xffffffff
402 Remap DDR 2 GiB left unmapped
403
404 POST memory PASSED
405 Flash: 128 MiB
406 L2: 128 KB enabled
407 Corenet Platform Cache: 1024 KB enabled
408 SERDES: timeout resetting bank 3
409 SRIO1: disabled
410 SRIO2: disabled
411 MMC: FSL_ESDHC: 0
412 EEPROM: Invalid ID (ff ff ff ff)
413 PCIe1: disabled
414 PCIe2: Root Complex, x1, regs @ 0xfe201000
415 01:00.0 - 8086:10d3 - Network controller
416 PCIe2: Bus 00 - 01
417 PCIe3: disabled
418 In: serial
419 Out: serial
420 Err: serial
421 Net: Initializing Fman
422 Fman1: Uploading microcode version 101.8.0
423 e1000: 00:1b:21:81:d2:e0
424 FM1@DTSEC1, FM1@DTSEC2, FM1@DTSEC3, FM1@DTSEC4, FM1@DTSEC5, e1000#0 [PRIME]
425 Warning: e1000#0 MAC addresses don't match:
426 Address in SROM is 00:1b:21:81:d2:e0
427 Address in environment is 00:e0:0c:00:ea:05
428
429 Hit any key to stop autoboot: 0
430 =>