| wdenk | 3a473b2 | 2004-01-03 00:43:19 +0000 | [diff] [blame] | 1 | /* |
| 2 | * (C) Copyright 2003 |
| 3 | * Ingo Assmus <ingo.assmus@keymile.com> |
| 4 | * |
| 5 | * based on - Driver for MV64360X ethernet ports |
| 6 | * Copyright (C) 2002 rabeeh@galileo.co.il |
| 7 | * |
| 8 | * See file CREDITS for list of people who contributed to this |
| 9 | * project. |
| 10 | * |
| 11 | * This program is free software; you can redistribute it and/or |
| 12 | * modify it under the terms of the GNU General Public License as |
| 13 | * published by the Free Software Foundation; either version 2 of |
| 14 | * the License, or (at your option) any later version. |
| 15 | * |
| 16 | * This program is distributed in the hope that it will be useful, |
| 17 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 18 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 19 | * GNU General Public License for more details. |
| 20 | * |
| 21 | * You should have received a copy of the GNU General Public License |
| 22 | * along with this program; if not, write to the Free Software |
| 23 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, |
| 24 | * MA 02111-1307 USA |
| 25 | */ |
| 26 | |
| 27 | /******************************************************************************** |
| 28 | * gt64360r.h - GT-64360 Internal registers definition file. |
| 29 | * |
| 30 | * DESCRIPTION: |
| 31 | * None. |
| 32 | * |
| 33 | * DEPENDENCIES: |
| 34 | * None. |
| 35 | * |
| 36 | *******************************************************************************/ |
| 37 | |
| 38 | #ifndef __INCmv_regsh |
| 39 | #define __INCmv_regsh |
| 40 | |
| 41 | #define MV64360 |
| 42 | |
| 43 | /* Supported by the Atlantis */ |
| 44 | #define MV64360_INCLUDE_PCI_1 |
| 45 | #define MV64360_INCLUDE_PCI_0_ARBITER |
| 46 | #define MV64360_INCLUDE_PCI_1_ARBITER |
| 47 | #define MV64360_INCLUDE_SNOOP_SUPPORT |
| 48 | #define MV64360_INCLUDE_P2P |
| 49 | #define MV64360_INCLUDE_ETH_PORT_2 |
| 50 | #define MV64360_INCLUDE_CPU_MAPPING |
| 51 | #define MV64360_INCLUDE_MPSC |
| 52 | |
| 53 | /* Not supported features */ |
| 54 | #undef INCLUDE_CNTMR_4_7 |
| 55 | #undef INCLUDE_DMA_4_7 |
| 56 | |
| 57 | /****************************************/ |
| 58 | /* Processor Address Space */ |
| 59 | /****************************************/ |
| 60 | |
| 61 | /* DDR SDRAM BAR and size registers */ |
| 62 | |
| 63 | #define MV64360_CS_0_BASE_ADDR 0x008 |
| 64 | #define MV64360_CS_0_SIZE 0x010 |
| 65 | #define MV64360_CS_1_BASE_ADDR 0x208 |
| 66 | #define MV64360_CS_1_SIZE 0x210 |
| 67 | #define MV64360_CS_2_BASE_ADDR 0x018 |
| 68 | #define MV64360_CS_2_SIZE 0x020 |
| 69 | #define MV64360_CS_3_BASE_ADDR 0x218 |
| 70 | #define MV64360_CS_3_SIZE 0x220 |
| 71 | |
| 72 | /* Devices BAR and size registers */ |
| 73 | |
| 74 | #define MV64360_DEV_CS0_BASE_ADDR 0x028 |
| 75 | #define MV64360_DEV_CS0_SIZE 0x030 |
| 76 | #define MV64360_DEV_CS1_BASE_ADDR 0x228 |
| 77 | #define MV64360_DEV_CS1_SIZE 0x230 |
| 78 | #define MV64360_DEV_CS2_BASE_ADDR 0x248 |
| 79 | #define MV64360_DEV_CS2_SIZE 0x250 |
| 80 | #define MV64360_DEV_CS3_BASE_ADDR 0x038 |
| 81 | #define MV64360_DEV_CS3_SIZE 0x040 |
| 82 | #define MV64360_BOOTCS_BASE_ADDR 0x238 |
| 83 | #define MV64360_BOOTCS_SIZE 0x240 |
| 84 | |
| 85 | /* PCI 0 BAR and size registers */ |
| 86 | |
| 87 | #define MV64360_PCI_0_IO_BASE_ADDR 0x048 |
| 88 | #define MV64360_PCI_0_IO_SIZE 0x050 |
| 89 | #define MV64360_PCI_0_MEMORY0_BASE_ADDR 0x058 |
| 90 | #define MV64360_PCI_0_MEMORY0_SIZE 0x060 |
| 91 | #define MV64360_PCI_0_MEMORY1_BASE_ADDR 0x080 |
| 92 | #define MV64360_PCI_0_MEMORY1_SIZE 0x088 |
| 93 | #define MV64360_PCI_0_MEMORY2_BASE_ADDR 0x258 |
| 94 | #define MV64360_PCI_0_MEMORY2_SIZE 0x260 |
| 95 | #define MV64360_PCI_0_MEMORY3_BASE_ADDR 0x280 |
| 96 | #define MV64360_PCI_0_MEMORY3_SIZE 0x288 |
| 97 | |
| 98 | /* PCI 1 BAR and size registers */ |
| 99 | #define MV64360_PCI_1_IO_BASE_ADDR 0x090 |
| 100 | #define MV64360_PCI_1_IO_SIZE 0x098 |
| 101 | #define MV64360_PCI_1_MEMORY0_BASE_ADDR 0x0a0 |
| 102 | #define MV64360_PCI_1_MEMORY0_SIZE 0x0a8 |
| 103 | #define MV64360_PCI_1_MEMORY1_BASE_ADDR 0x0b0 |
| 104 | #define MV64360_PCI_1_MEMORY1_SIZE 0x0b8 |
| 105 | #define MV64360_PCI_1_MEMORY2_BASE_ADDR 0x2a0 |
| 106 | #define MV64360_PCI_1_MEMORY2_SIZE 0x2a8 |
| 107 | #define MV64360_PCI_1_MEMORY3_BASE_ADDR 0x2b0 |
| 108 | #define MV64360_PCI_1_MEMORY3_SIZE 0x2b8 |
| 109 | |
| 110 | /* SRAM base address */ |
| 111 | #define MV64360_INTEGRATED_SRAM_BASE_ADDR 0x268 |
| 112 | |
| 113 | /* internal registers space base address */ |
| 114 | #define MV64360_INTERNAL_SPACE_BASE_ADDR 0x068 |
| 115 | |
| 116 | /* Enables the CS , DEV_CS , PCI 0 and PCI 1 |
| 117 | windows above */ |
| 118 | #define MV64360_BASE_ADDR_ENABLE 0x278 |
| 119 | |
| 120 | /****************************************/ |
| 121 | /* PCI remap registers */ |
| 122 | /****************************************/ |
| 123 | /* PCI 0 */ |
| 124 | #define MV64360_PCI_0_IO_ADDR_REMAP 0x0f0 |
| 125 | #define MV64360_PCI_0_MEMORY0_LOW_ADDR_REMAP 0x0f8 |
| 126 | #define MV64360_PCI_0_MEMORY0_HIGH_ADDR_REMAP 0x320 |
| 127 | #define MV64360_PCI_0_MEMORY1_LOW_ADDR_REMAP 0x100 |
| 128 | #define MV64360_PCI_0_MEMORY1_HIGH_ADDR_REMAP 0x328 |
| 129 | #define MV64360_PCI_0_MEMORY2_LOW_ADDR_REMAP 0x2f8 |
| 130 | #define MV64360_PCI_0_MEMORY2_HIGH_ADDR_REMAP 0x330 |
| 131 | #define MV64360_PCI_0_MEMORY3_LOW_ADDR_REMAP 0x300 |
| 132 | #define MV64360_PCI_0_MEMORY3_HIGH_ADDR_REMAP 0x338 |
| 133 | /* PCI 1 */ |
| 134 | #define MV64360_PCI_1_IO_ADDR_REMAP 0x108 |
| 135 | #define MV64360_PCI_1_MEMORY0_LOW_ADDR_REMAP 0x110 |
| 136 | #define MV64360_PCI_1_MEMORY0_HIGH_ADDR_REMAP 0x340 |
| 137 | #define MV64360_PCI_1_MEMORY1_LOW_ADDR_REMAP 0x118 |
| 138 | #define MV64360_PCI_1_MEMORY1_HIGH_ADDR_REMAP 0x348 |
| 139 | #define MV64360_PCI_1_MEMORY2_LOW_ADDR_REMAP 0x310 |
| 140 | #define MV64360_PCI_1_MEMORY2_HIGH_ADDR_REMAP 0x350 |
| 141 | #define MV64360_PCI_1_MEMORY3_LOW_ADDR_REMAP 0x318 |
| 142 | #define MV64360_PCI_1_MEMORY3_HIGH_ADDR_REMAP 0x358 |
| 143 | |
| 144 | #define MV64360_CPU_PCI_0_HEADERS_RETARGET_CONTROL 0x3b0 |
| 145 | #define MV64360_CPU_PCI_0_HEADERS_RETARGET_BASE 0x3b8 |
| 146 | #define MV64360_CPU_PCI_1_HEADERS_RETARGET_CONTROL 0x3c0 |
| 147 | #define MV64360_CPU_PCI_1_HEADERS_RETARGET_BASE 0x3c8 |
| 148 | #define MV64360_CPU_GE_HEADERS_RETARGET_CONTROL 0x3d0 |
| 149 | #define MV64360_CPU_GE_HEADERS_RETARGET_BASE 0x3d8 |
| 150 | #define MV64360_CPU_IDMA_HEADERS_RETARGET_CONTROL 0x3e0 |
| 151 | #define MV64360_CPU_IDMA_HEADERS_RETARGET_BASE 0x3e8 |
| 152 | |
| 153 | /****************************************/ |
| 154 | /* CPU Control Registers */ |
| 155 | /****************************************/ |
| 156 | |
| 157 | #define MV64360_CPU_CONFIG 0x000 |
| 158 | #define MV64360_CPU_MODE 0x120 |
| 159 | #define MV64360_CPU_MASTER_CONTROL 0x160 |
| 160 | #define MV64360_CPU_CROSS_BAR_CONTROL_LOW 0x150 |
| 161 | #define MV64360_CPU_CROSS_BAR_CONTROL_HIGH 0x158 |
| 162 | #define MV64360_CPU_CROSS_BAR_TIMEOUT 0x168 |
| 163 | |
| 164 | /****************************************/ |
| 165 | /* SMP RegisterS */ |
| 166 | /****************************************/ |
| 167 | |
| 168 | #define MV64360_SMP_WHO_AM_I 0x200 |
| 169 | #define MV64360_SMP_CPU0_DOORBELL 0x214 |
| 170 | #define MV64360_SMP_CPU0_DOORBELL_CLEAR 0x21C |
| 171 | #define MV64360_SMP_CPU1_DOORBELL 0x224 |
| 172 | #define MV64360_SMP_CPU1_DOORBELL_CLEAR 0x22C |
| 173 | #define MV64360_SMP_CPU0_DOORBELL_MASK 0x234 |
| 174 | #define MV64360_SMP_CPU1_DOORBELL_MASK 0x23C |
| 175 | #define MV64360_SMP_SEMAPHOR0 0x244 |
| 176 | #define MV64360_SMP_SEMAPHOR1 0x24c |
| 177 | #define MV64360_SMP_SEMAPHOR2 0x254 |
| 178 | #define MV64360_SMP_SEMAPHOR3 0x25c |
| 179 | #define MV64360_SMP_SEMAPHOR4 0x264 |
| 180 | #define MV64360_SMP_SEMAPHOR5 0x26c |
| 181 | #define MV64360_SMP_SEMAPHOR6 0x274 |
| 182 | #define MV64360_SMP_SEMAPHOR7 0x27c |
| 183 | |
| 184 | /****************************************/ |
| 185 | /* CPU Sync Barrier Register */ |
| 186 | /****************************************/ |
| 187 | |
| 188 | #define MV64360_CPU_0_SYNC_BARRIER_TRIGGER 0x0c0 |
| 189 | #define MV64360_CPU_0_SYNC_BARRIER_VIRTUAL 0x0c8 |
| 190 | #define MV64360_CPU_1_SYNC_BARRIER_TRIGGER 0x0d0 |
| 191 | #define MV64360_CPU_1_SYNC_BARRIER_VIRTUAL 0x0d8 |
| 192 | |
| 193 | /****************************************/ |
| 194 | /* CPU Access Protect */ |
| 195 | /****************************************/ |
| 196 | |
| 197 | #define MV64360_CPU_PROTECT_WINDOW_0_BASE_ADDR 0x180 |
| 198 | #define MV64360_CPU_PROTECT_WINDOW_0_SIZE 0x188 |
| 199 | #define MV64360_CPU_PROTECT_WINDOW_1_BASE_ADDR 0x190 |
| 200 | #define MV64360_CPU_PROTECT_WINDOW_1_SIZE 0x198 |
| 201 | #define MV64360_CPU_PROTECT_WINDOW_2_BASE_ADDR 0x1a0 |
| 202 | #define MV64360_CPU_PROTECT_WINDOW_2_SIZE 0x1a8 |
| 203 | #define MV64360_CPU_PROTECT_WINDOW_3_BASE_ADDR 0x1b0 |
| 204 | #define MV64360_CPU_PROTECT_WINDOW_3_SIZE 0x1b8 |
| 205 | |
| 206 | |
| 207 | /****************************************/ |
| 208 | /* CPU Error Report */ |
| 209 | /****************************************/ |
| 210 | |
| 211 | #define MV64360_CPU_ERROR_ADDR_LOW 0x070 |
| 212 | #define MV64360_CPU_ERROR_ADDR_HIGH 0x078 |
| 213 | #define MV64360_CPU_ERROR_DATA_LOW 0x128 |
| 214 | #define MV64360_CPU_ERROR_DATA_HIGH 0x130 |
| 215 | #define MV64360_CPU_ERROR_PARITY 0x138 |
| 216 | #define MV64360_CPU_ERROR_CAUSE 0x140 |
| 217 | #define MV64360_CPU_ERROR_MASK 0x148 |
| 218 | |
| 219 | /****************************************/ |
| 220 | /* CPU Interface Debug Registers */ |
| 221 | /****************************************/ |
| 222 | |
| 223 | #define MV64360_PUNIT_SLAVE_DEBUG_LOW 0x360 |
| 224 | #define MV64360_PUNIT_SLAVE_DEBUG_HIGH 0x368 |
| 225 | #define MV64360_PUNIT_MASTER_DEBUG_LOW 0x370 |
| 226 | #define MV64360_PUNIT_MASTER_DEBUG_HIGH 0x378 |
| 227 | #define MV64360_PUNIT_MMASK 0x3e4 |
| 228 | |
| 229 | /****************************************/ |
| 230 | /* Integrated SRAM Registers */ |
| 231 | /****************************************/ |
| 232 | |
| 233 | #define MV64360_SRAM_CONFIG 0x380 |
| 234 | #define MV64360_SRAM_TEST_MODE 0X3F4 |
| 235 | #define MV64360_SRAM_ERROR_CAUSE 0x388 |
| 236 | #define MV64360_SRAM_ERROR_ADDR 0x390 |
| 237 | #define MV64360_SRAM_ERROR_ADDR_HIGH 0X3F8 |
| 238 | #define MV64360_SRAM_ERROR_DATA_LOW 0x398 |
| 239 | #define MV64360_SRAM_ERROR_DATA_HIGH 0x3a0 |
| 240 | #define MV64360_SRAM_ERROR_DATA_PARITY 0x3a8 |
| 241 | |
| 242 | /****************************************/ |
| 243 | /* SDRAM Configuration */ |
| 244 | /****************************************/ |
| 245 | |
| 246 | #define MV64360_SDRAM_CONFIG 0x1400 |
| 247 | #define MV64360_D_UNIT_CONTROL_LOW 0x1404 |
| 248 | #define MV64360_D_UNIT_CONTROL_HIGH 0x1424 |
| 249 | #define MV64360_SDRAM_TIMING_CONTROL_LOW 0x1408 |
| 250 | #define MV64360_SDRAM_TIMING_CONTROL_HIGH 0x140c |
| 251 | #define MV64360_SDRAM_ADDR_CONTROL 0x1410 |
| 252 | #define MV64360_SDRAM_OPEN_PAGES_CONTROL 0x1414 |
| 253 | #define MV64360_SDRAM_OPERATION 0x1418 |
| 254 | #define MV64360_SDRAM_MODE 0x141c |
| 255 | #define MV64360_EXTENDED_DRAM_MODE 0x1420 |
| 256 | #define MV64360_SDRAM_CROSS_BAR_CONTROL_LOW 0x1430 |
| 257 | #define MV64360_SDRAM_CROSS_BAR_CONTROL_HIGH 0x1434 |
| 258 | #define MV64360_SDRAM_CROSS_BAR_TIMEOUT 0x1438 |
| 259 | #define MV64360_SDRAM_ADDR_CTRL_PADS_CALIBRATION 0x14c0 |
| 260 | #define MV64360_SDRAM_DATA_PADS_CALIBRATION 0x14c4 |
| 261 | |
| 262 | /****************************************/ |
| 263 | /* SDRAM Error Report */ |
| 264 | /****************************************/ |
| 265 | |
| 266 | #define MV64360_SDRAM_ERROR_DATA_LOW 0x1444 |
| 267 | #define MV64360_SDRAM_ERROR_DATA_HIGH 0x1440 |
| 268 | #define MV64360_SDRAM_ERROR_ADDR 0x1450 |
| 269 | #define MV64360_SDRAM_RECEIVED_ECC 0x1448 |
| 270 | #define MV64360_SDRAM_CALCULATED_ECC 0x144c |
| 271 | #define MV64360_SDRAM_ECC_CONTROL 0x1454 |
| 272 | #define MV64360_SDRAM_ECC_ERROR_COUNTER 0x1458 |
| 273 | |
| 274 | /******************************************/ |
| 275 | /* Controlled Delay Line (CDL) Registers */ |
| 276 | /******************************************/ |
| 277 | |
| 278 | #define MV64360_DFCDL_CONFIG0 0x1480 |
| 279 | #define MV64360_DFCDL_CONFIG1 0x1484 |
| 280 | #define MV64360_DLL_WRITE 0x1488 |
| 281 | #define MV64360_DLL_READ 0x148c |
| 282 | #define MV64360_SRAM_ADDR 0x1490 |
| 283 | #define MV64360_SRAM_DATA0 0x1494 |
| 284 | #define MV64360_SRAM_DATA1 0x1498 |
| 285 | #define MV64360_SRAM_DATA2 0x149c |
| 286 | #define MV64360_DFCL_PROBE 0x14a0 |
| 287 | |
| 288 | /******************************************/ |
| 289 | /* Debug Registers */ |
| 290 | /******************************************/ |
| 291 | |
| 292 | #define MV64360_DUNIT_DEBUG_LOW 0x1460 |
| 293 | #define MV64360_DUNIT_DEBUG_HIGH 0x1464 |
| 294 | #define MV64360_DUNIT_MMASK 0X1b40 |
| 295 | |
| 296 | /****************************************/ |
| 297 | /* Device Parameters */ |
| 298 | /****************************************/ |
| 299 | |
| 300 | #define MV64360_DEVICE_BANK0_PARAMETERS 0x45c |
| 301 | #define MV64360_DEVICE_BANK1_PARAMETERS 0x460 |
| 302 | #define MV64360_DEVICE_BANK2_PARAMETERS 0x464 |
| 303 | #define MV64360_DEVICE_BANK3_PARAMETERS 0x468 |
| 304 | #define MV64360_DEVICE_BOOT_BANK_PARAMETERS 0x46c |
| 305 | #define MV64360_DEVICE_INTERFACE_CONTROL 0x4c0 |
| 306 | #define MV64360_DEVICE_INTERFACE_CROSS_BAR_CONTROL_LOW 0x4c8 |
| 307 | #define MV64360_DEVICE_INTERFACE_CROSS_BAR_CONTROL_HIGH 0x4cc |
| 308 | #define MV64360_DEVICE_INTERFACE_CROSS_BAR_TIMEOUT 0x4c4 |
| 309 | |
| 310 | /****************************************/ |
| 311 | /* Device interrupt registers */ |
| 312 | /****************************************/ |
| 313 | |
| 314 | #define MV64360_DEVICE_INTERRUPT_CAUSE 0x4d0 |
| 315 | #define MV64360_DEVICE_INTERRUPT_MASK 0x4d4 |
| 316 | #define MV64360_DEVICE_ERROR_ADDR 0x4d8 |
| 317 | #define MV64360_DEVICE_ERROR_DATA 0x4dc |
| 318 | #define MV64360_DEVICE_ERROR_PARITY 0x4e0 |
| 319 | |
| 320 | /****************************************/ |
| 321 | /* Device debug registers */ |
| 322 | /****************************************/ |
| 323 | |
| 324 | #define MV64360_DEVICE_DEBUG_LOW 0x4e4 |
| 325 | #define MV64360_DEVICE_DEBUG_HIGH 0x4e8 |
| 326 | #define MV64360_RUNIT_MMASK 0x4f0 |
| 327 | |
| 328 | /****************************************/ |
| 329 | /* PCI Slave Address Decoding registers */ |
| 330 | /****************************************/ |
| 331 | |
| 332 | #define MV64360_PCI_0_CS_0_BANK_SIZE 0xc08 |
| 333 | #define MV64360_PCI_1_CS_0_BANK_SIZE 0xc88 |
| 334 | #define MV64360_PCI_0_CS_1_BANK_SIZE 0xd08 |
| 335 | #define MV64360_PCI_1_CS_1_BANK_SIZE 0xd88 |
| 336 | #define MV64360_PCI_0_CS_2_BANK_SIZE 0xc0c |
| 337 | #define MV64360_PCI_1_CS_2_BANK_SIZE 0xc8c |
| 338 | #define MV64360_PCI_0_CS_3_BANK_SIZE 0xd0c |
| 339 | #define MV64360_PCI_1_CS_3_BANK_SIZE 0xd8c |
| 340 | #define MV64360_PCI_0_DEVCS_0_BANK_SIZE 0xc10 |
| 341 | #define MV64360_PCI_1_DEVCS_0_BANK_SIZE 0xc90 |
| 342 | #define MV64360_PCI_0_DEVCS_1_BANK_SIZE 0xd10 |
| 343 | #define MV64360_PCI_1_DEVCS_1_BANK_SIZE 0xd90 |
| 344 | #define MV64360_PCI_0_DEVCS_2_BANK_SIZE 0xd18 |
| 345 | #define MV64360_PCI_1_DEVCS_2_BANK_SIZE 0xd98 |
| 346 | #define MV64360_PCI_0_DEVCS_3_BANK_SIZE 0xc14 |
| 347 | #define MV64360_PCI_1_DEVCS_3_BANK_SIZE 0xc94 |
| 348 | #define MV64360_PCI_0_DEVCS_BOOT_BANK_SIZE 0xd14 |
| 349 | #define MV64360_PCI_1_DEVCS_BOOT_BANK_SIZE 0xd94 |
| 350 | #define MV64360_PCI_0_P2P_MEM0_BAR_SIZE 0xd1c |
| 351 | #define MV64360_PCI_1_P2P_MEM0_BAR_SIZE 0xd9c |
| 352 | #define MV64360_PCI_0_P2P_MEM1_BAR_SIZE 0xd20 |
| 353 | #define MV64360_PCI_1_P2P_MEM1_BAR_SIZE 0xda0 |
| 354 | #define MV64360_PCI_0_P2P_I_O_BAR_SIZE 0xd24 |
| 355 | #define MV64360_PCI_1_P2P_I_O_BAR_SIZE 0xda4 |
| 356 | #define MV64360_PCI_0_CPU_BAR_SIZE 0xd28 |
| 357 | #define MV64360_PCI_1_CPU_BAR_SIZE 0xda8 |
| 358 | #define MV64360_PCI_0_INTERNAL_SRAM_BAR_SIZE 0xe00 |
| 359 | #define MV64360_PCI_1_INTERNAL_SRAM_BAR_SIZE 0xe80 |
| 360 | #define MV64360_PCI_0_EXPANSION_ROM_BAR_SIZE 0xd2c |
| 361 | #define MV64360_PCI_1_EXPANSION_ROM_BAR_SIZE 0xd9c |
| 362 | #define MV64360_PCI_0_BASE_ADDR_REG_ENABLE 0xc3c |
| 363 | #define MV64360_PCI_1_BASE_ADDR_REG_ENABLE 0xcbc |
| 364 | #define MV64360_PCI_0_CS_0_BASE_ADDR_REMAP 0xc48 |
| 365 | #define MV64360_PCI_1_CS_0_BASE_ADDR_REMAP 0xcc8 |
| 366 | #define MV64360_PCI_0_CS_1_BASE_ADDR_REMAP 0xd48 |
| 367 | #define MV64360_PCI_1_CS_1_BASE_ADDR_REMAP 0xdc8 |
| 368 | #define MV64360_PCI_0_CS_2_BASE_ADDR_REMAP 0xc4c |
| 369 | #define MV64360_PCI_1_CS_2_BASE_ADDR_REMAP 0xccc |
| 370 | #define MV64360_PCI_0_CS_3_BASE_ADDR_REMAP 0xd4c |
| 371 | #define MV64360_PCI_1_CS_3_BASE_ADDR_REMAP 0xdcc |
| 372 | #define MV64360_PCI_0_CS_0_BASE_HIGH_ADDR_REMAP 0xF04 |
| 373 | #define MV64360_PCI_1_CS_0_BASE_HIGH_ADDR_REMAP 0xF84 |
| 374 | #define MV64360_PCI_0_CS_1_BASE_HIGH_ADDR_REMAP 0xF08 |
| 375 | #define MV64360_PCI_1_CS_1_BASE_HIGH_ADDR_REMAP 0xF88 |
| 376 | #define MV64360_PCI_0_CS_2_BASE_HIGH_ADDR_REMAP 0xF0C |
| 377 | #define MV64360_PCI_1_CS_2_BASE_HIGH_ADDR_REMAP 0xF8C |
| 378 | #define MV64360_PCI_0_CS_3_BASE_HIGH_ADDR_REMAP 0xF10 |
| 379 | #define MV64360_PCI_1_CS_3_BASE_HIGH_ADDR_REMAP 0xF90 |
| 380 | #define MV64360_PCI_0_DEVCS_0_BASE_ADDR_REMAP 0xc50 |
| 381 | #define MV64360_PCI_1_DEVCS_0_BASE_ADDR_REMAP 0xcd0 |
| 382 | #define MV64360_PCI_0_DEVCS_1_BASE_ADDR_REMAP 0xd50 |
| 383 | #define MV64360_PCI_1_DEVCS_1_BASE_ADDR_REMAP 0xdd0 |
| 384 | #define MV64360_PCI_0_DEVCS_2_BASE_ADDR_REMAP 0xd58 |
| 385 | #define MV64360_PCI_1_DEVCS_2_BASE_ADDR_REMAP 0xdd8 |
| 386 | #define MV64360_PCI_0_DEVCS_3_BASE_ADDR_REMAP 0xc54 |
| 387 | #define MV64360_PCI_1_DEVCS_3_BASE_ADDR_REMAP 0xcd4 |
| 388 | #define MV64360_PCI_0_DEVCS_BOOTCS_BASE_ADDR_REMAP 0xd54 |
| 389 | #define MV64360_PCI_1_DEVCS_BOOTCS_BASE_ADDR_REMAP 0xdd4 |
| 390 | #define MV64360_PCI_0_P2P_MEM0_BASE_ADDR_REMAP_LOW 0xd5c |
| 391 | #define MV64360_PCI_1_P2P_MEM0_BASE_ADDR_REMAP_LOW 0xddc |
| 392 | #define MV64360_PCI_0_P2P_MEM0_BASE_ADDR_REMAP_HIGH 0xd60 |
| 393 | #define MV64360_PCI_1_P2P_MEM0_BASE_ADDR_REMAP_HIGH 0xde0 |
| 394 | #define MV64360_PCI_0_P2P_MEM1_BASE_ADDR_REMAP_LOW 0xd64 |
| 395 | #define MV64360_PCI_1_P2P_MEM1_BASE_ADDR_REMAP_LOW 0xde4 |
| 396 | #define MV64360_PCI_0_P2P_MEM1_BASE_ADDR_REMAP_HIGH 0xd68 |
| 397 | #define MV64360_PCI_1_P2P_MEM1_BASE_ADDR_REMAP_HIGH 0xde8 |
| 398 | #define MV64360_PCI_0_P2P_I_O_BASE_ADDR_REMAP 0xd6c |
| 399 | #define MV64360_PCI_1_P2P_I_O_BASE_ADDR_REMAP 0xdec |
| 400 | #define MV64360_PCI_0_CPU_BASE_ADDR_REMAP_LOW 0xd70 |
| 401 | #define MV64360_PCI_1_CPU_BASE_ADDR_REMAP_LOW 0xdf0 |
| 402 | #define MV64360_PCI_0_CPU_BASE_ADDR_REMAP_HIGH 0xd74 |
| 403 | #define MV64360_PCI_1_CPU_BASE_ADDR_REMAP_HIGH 0xdf4 |
| 404 | #define MV64360_PCI_0_INTEGRATED_SRAM_BASE_ADDR_REMAP 0xf00 |
| 405 | #define MV64360_PCI_1_INTEGRATED_SRAM_BASE_ADDR_REMAP 0xf80 |
| 406 | #define MV64360_PCI_0_EXPANSION_ROM_BASE_ADDR_REMAP 0xf38 |
| 407 | #define MV64360_PCI_1_EXPANSION_ROM_BASE_ADDR_REMAP 0xfb8 |
| 408 | #define MV64360_PCI_0_ADDR_DECODE_CONTROL 0xd3c |
| 409 | #define MV64360_PCI_1_ADDR_DECODE_CONTROL 0xdbc |
| 410 | #define MV64360_PCI_0_HEADERS_RETARGET_CONTROL 0xF40 |
| 411 | #define MV64360_PCI_1_HEADERS_RETARGET_CONTROL 0xFc0 |
| 412 | #define MV64360_PCI_0_HEADERS_RETARGET_BASE 0xF44 |
| 413 | #define MV64360_PCI_1_HEADERS_RETARGET_BASE 0xFc4 |
| 414 | #define MV64360_PCI_0_HEADERS_RETARGET_HIGH 0xF48 |
| 415 | #define MV64360_PCI_1_HEADERS_RETARGET_HIGH 0xFc8 |
| 416 | |
| 417 | /***********************************/ |
| 418 | /* PCI Control Register Map */ |
| 419 | /***********************************/ |
| 420 | |
| 421 | #define MV64360_PCI_0_DLL_STATUS_AND_COMMAND 0x1d20 |
| 422 | #define MV64360_PCI_1_DLL_STATUS_AND_COMMAND 0x1da0 |
| 423 | #define MV64360_PCI_0_MPP_PADS_DRIVE_CONTROL 0x1d1C |
| 424 | #define MV64360_PCI_1_MPP_PADS_DRIVE_CONTROL 0x1d9C |
| 425 | #define MV64360_PCI_0_COMMAND 0xc00 |
| 426 | #define MV64360_PCI_1_COMMAND 0xc80 |
| 427 | #define MV64360_PCI_0_MODE 0xd00 |
| 428 | #define MV64360_PCI_1_MODE 0xd80 |
| 429 | #define MV64360_PCI_0_RETRY 0xc04 |
| 430 | #define MV64360_PCI_1_RETRY 0xc84 |
| 431 | #define MV64360_PCI_0_READ_BUFFER_DISCARD_TIMER 0xd04 |
| 432 | #define MV64360_PCI_1_READ_BUFFER_DISCARD_TIMER 0xd84 |
| 433 | #define MV64360_PCI_0_MSI_TRIGGER_TIMER 0xc38 |
| 434 | #define MV64360_PCI_1_MSI_TRIGGER_TIMER 0xcb8 |
| 435 | #define MV64360_PCI_0_ARBITER_CONTROL 0x1d00 |
| 436 | #define MV64360_PCI_1_ARBITER_CONTROL 0x1d80 |
| 437 | #define MV64360_PCI_0_CROSS_BAR_CONTROL_LOW 0x1d08 |
| 438 | #define MV64360_PCI_1_CROSS_BAR_CONTROL_LOW 0x1d88 |
| 439 | #define MV64360_PCI_0_CROSS_BAR_CONTROL_HIGH 0x1d0c |
| 440 | #define MV64360_PCI_1_CROSS_BAR_CONTROL_HIGH 0x1d8c |
| 441 | #define MV64360_PCI_0_CROSS_BAR_TIMEOUT 0x1d04 |
| 442 | #define MV64360_PCI_1_CROSS_BAR_TIMEOUT 0x1d84 |
| 443 | #define MV64360_PCI_0_SYNC_BARRIER_TRIGGER_REG 0x1D18 |
| 444 | #define MV64360_PCI_1_SYNC_BARRIER_TRIGGER_REG 0x1D98 |
| 445 | #define MV64360_PCI_0_SYNC_BARRIER_VIRTUAL_REG 0x1d10 |
| 446 | #define MV64360_PCI_1_SYNC_BARRIER_VIRTUAL_REG 0x1d90 |
| 447 | #define MV64360_PCI_0_P2P_CONFIG 0x1d14 |
| 448 | #define MV64360_PCI_1_P2P_CONFIG 0x1d94 |
| 449 | |
| 450 | #define MV64360_PCI_0_ACCESS_CONTROL_BASE_0_LOW 0x1e00 |
| 451 | #define MV64360_PCI_0_ACCESS_CONTROL_BASE_0_HIGH 0x1e04 |
| 452 | #define MV64360_PCI_0_ACCESS_CONTROL_SIZE_0 0x1e08 |
| 453 | #define MV64360_PCI_0_ACCESS_CONTROL_BASE_1_LOW 0x1e10 |
| 454 | #define MV64360_PCI_0_ACCESS_CONTROL_BASE_1_HIGH 0x1e14 |
| 455 | #define MV64360_PCI_0_ACCESS_CONTROL_SIZE_1 0x1e18 |
| 456 | #define MV64360_PCI_0_ACCESS_CONTROL_BASE_2_LOW 0x1e20 |
| 457 | #define MV64360_PCI_0_ACCESS_CONTROL_BASE_2_HIGH 0x1e24 |
| 458 | #define MV64360_PCI_0_ACCESS_CONTROL_SIZE_2 0x1e28 |
| 459 | #define MV64360_PCI_0_ACCESS_CONTROL_BASE_3_LOW 0x1e30 |
| 460 | #define MV64360_PCI_0_ACCESS_CONTROL_BASE_3_HIGH 0x1e34 |
| 461 | #define MV64360_PCI_0_ACCESS_CONTROL_SIZE_3 0x1e38 |
| 462 | #define MV64360_PCI_0_ACCESS_CONTROL_BASE_4_LOW 0x1e40 |
| 463 | #define MV64360_PCI_0_ACCESS_CONTROL_BASE_4_HIGH 0x1e44 |
| 464 | #define MV64360_PCI_0_ACCESS_CONTROL_SIZE_4 0x1e48 |
| 465 | #define MV64360_PCI_0_ACCESS_CONTROL_BASE_5_LOW 0x1e50 |
| 466 | #define MV64360_PCI_0_ACCESS_CONTROL_BASE_5_HIGH 0x1e54 |
| 467 | #define MV64360_PCI_0_ACCESS_CONTROL_SIZE_5 0x1e58 |
| 468 | |
| 469 | #define MV64360_PCI_1_ACCESS_CONTROL_BASE_0_LOW 0x1e80 |
| 470 | #define MV64360_PCI_1_ACCESS_CONTROL_BASE_0_HIGH 0x1e84 |
| 471 | #define MV64360_PCI_1_ACCESS_CONTROL_SIZE_0 0x1e88 |
| 472 | #define MV64360_PCI_1_ACCESS_CONTROL_BASE_1_LOW 0x1e90 |
| 473 | #define MV64360_PCI_1_ACCESS_CONTROL_BASE_1_HIGH 0x1e94 |
| 474 | #define MV64360_PCI_1_ACCESS_CONTROL_SIZE_1 0x1e98 |
| 475 | #define MV64360_PCI_1_ACCESS_CONTROL_BASE_2_LOW 0x1ea0 |
| 476 | #define MV64360_PCI_1_ACCESS_CONTROL_BASE_2_HIGH 0x1ea4 |
| 477 | #define MV64360_PCI_1_ACCESS_CONTROL_SIZE_2 0x1ea8 |
| 478 | #define MV64360_PCI_1_ACCESS_CONTROL_BASE_3_LOW 0x1eb0 |
| 479 | #define MV64360_PCI_1_ACCESS_CONTROL_BASE_3_HIGH 0x1eb4 |
| 480 | #define MV64360_PCI_1_ACCESS_CONTROL_SIZE_3 0x1eb8 |
| 481 | #define MV64360_PCI_1_ACCESS_CONTROL_BASE_4_LOW 0x1ec0 |
| 482 | #define MV64360_PCI_1_ACCESS_CONTROL_BASE_4_HIGH 0x1ec4 |
| 483 | #define MV64360_PCI_1_ACCESS_CONTROL_SIZE_4 0x1ec8 |
| 484 | #define MV64360_PCI_1_ACCESS_CONTROL_BASE_5_LOW 0x1ed0 |
| 485 | #define MV64360_PCI_1_ACCESS_CONTROL_BASE_5_HIGH 0x1ed4 |
| 486 | #define MV64360_PCI_1_ACCESS_CONTROL_SIZE_5 0x1ed8 |
| 487 | |
| 488 | /****************************************/ |
| 489 | /* PCI Configuration Access Registers */ |
| 490 | /****************************************/ |
| 491 | |
| 492 | #define MV64360_PCI_0_CONFIG_ADDR 0xcf8 |
| 493 | #define MV64360_PCI_0_CONFIG_DATA_VIRTUAL_REG 0xcfc |
| 494 | #define MV64360_PCI_1_CONFIG_ADDR 0xc78 |
| 495 | #define MV64360_PCI_1_CONFIG_DATA_VIRTUAL_REG 0xc7c |
| 496 | #define MV64360_PCI_0_INTERRUPT_ACKNOWLEDGE_VIRTUAL_REG 0xc34 |
| 497 | #define MV64360_PCI_1_INTERRUPT_ACKNOWLEDGE_VIRTUAL_REG 0xcb4 |
| 498 | |
| 499 | /****************************************/ |
| 500 | /* PCI Error Report Registers */ |
| 501 | /****************************************/ |
| 502 | |
| 503 | #define MV64360_PCI_0_SERR_MASK 0xc28 |
| 504 | #define MV64360_PCI_1_SERR_MASK 0xca8 |
| 505 | #define MV64360_PCI_0_ERROR_ADDR_LOW 0x1d40 |
| 506 | #define MV64360_PCI_1_ERROR_ADDR_LOW 0x1dc0 |
| 507 | #define MV64360_PCI_0_ERROR_ADDR_HIGH 0x1d44 |
| 508 | #define MV64360_PCI_1_ERROR_ADDR_HIGH 0x1dc4 |
| 509 | #define MV64360_PCI_0_ERROR_ATTRIBUTE 0x1d48 |
| 510 | #define MV64360_PCI_1_ERROR_ATTRIBUTE 0x1dc8 |
| 511 | #define MV64360_PCI_0_ERROR_COMMAND 0x1d50 |
| 512 | #define MV64360_PCI_1_ERROR_COMMAND 0x1dd0 |
| 513 | #define MV64360_PCI_0_ERROR_CAUSE 0x1d58 |
| 514 | #define MV64360_PCI_1_ERROR_CAUSE 0x1dd8 |
| 515 | #define MV64360_PCI_0_ERROR_MASK 0x1d5c |
| 516 | #define MV64360_PCI_1_ERROR_MASK 0x1ddc |
| 517 | |
| 518 | /****************************************/ |
| 519 | /* PCI Debug Registers */ |
| 520 | /****************************************/ |
| 521 | |
| 522 | #define MV64360_PCI_0_MMASK 0X1D24 |
| 523 | #define MV64360_PCI_1_MMASK 0X1DA4 |
| 524 | |
| 525 | /*********************************************/ |
| 526 | /* PCI Configuration, Function 0, Registers */ |
| 527 | /*********************************************/ |
| 528 | |
| 529 | #define MV64360_PCI_DEVICE_AND_VENDOR_ID 0x000 |
| 530 | #define MV64360_PCI_STATUS_AND_COMMAND 0x004 |
| 531 | #define MV64360_PCI_CLASS_CODE_AND_REVISION_ID 0x008 |
| 532 | #define MV64360_PCI_BIST_HEADER_TYPE_LATENCY_TIMER_CACHE_LINE 0x00C |
| 533 | |
| 534 | #define MV64360_PCI_SCS_0_BASE_ADDR_LOW 0x010 |
| 535 | #define MV64360_PCI_SCS_0_BASE_ADDR_HIGH 0x014 |
| 536 | #define MV64360_PCI_SCS_1_BASE_ADDR_LOW 0x018 |
| 537 | #define MV64360_PCI_SCS_1_BASE_ADDR_HIGH 0x01C |
| 538 | #define MV64360_PCI_INTERNAL_REG_MEM_MAPPED_BASE_ADDR_LOW 0x020 |
| 539 | #define MV64360_PCI_INTERNAL_REG_MEM_MAPPED_BASE_ADDR_HIGH 0x024 |
| 540 | #define MV64360_PCI_SUBSYSTEM_ID_AND_SUBSYSTEM_VENDOR_ID 0x02c |
| 541 | #define MV64360_PCI_EXPANSION_ROM_BASE_ADDR_REG 0x030 |
| 542 | #define MV64360_PCI_CAPABILTY_LIST_POINTER 0x034 |
| 543 | #define MV64360_PCI_INTERRUPT_PIN_AND_LINE 0x03C |
| 544 | /* capability list */ |
| 545 | #define MV64360_PCI_POWER_MANAGEMENT_CAPABILITY 0x040 |
| 546 | #define MV64360_PCI_POWER_MANAGEMENT_STATUS_AND_CONTROL 0x044 |
| 547 | #define MV64360_PCI_VPD_ADDR 0x048 |
| 548 | #define MV64360_PCI_VPD_DATA 0x04c |
| 549 | #define MV64360_PCI_MSI_MESSAGE_CONTROL 0x050 |
| 550 | #define MV64360_PCI_MSI_MESSAGE_ADDR 0x054 |
| 551 | #define MV64360_PCI_MSI_MESSAGE_UPPER_ADDR 0x058 |
| 552 | #define MV64360_PCI_MSI_MESSAGE_DATA 0x05c |
| 553 | #define MV64360_PCI_X_COMMAND 0x060 |
| 554 | #define MV64360_PCI_X_STATUS 0x064 |
| 555 | #define MV64360_PCI_COMPACT_PCI_HOT_SWAP 0x068 |
| 556 | |
| 557 | /***********************************************/ |
| 558 | /* PCI Configuration, Function 1, Registers */ |
| 559 | /***********************************************/ |
| 560 | |
| 561 | #define MV64360_PCI_SCS_2_BASE_ADDR_LOW 0x110 |
| 562 | #define MV64360_PCI_SCS_2_BASE_ADDR_HIGH 0x114 |
| 563 | #define MV64360_PCI_SCS_3_BASE_ADDR_LOW 0x118 |
| 564 | #define MV64360_PCI_SCS_3_BASE_ADDR_HIGH 0x11c |
| 565 | #define MV64360_PCI_INTERNAL_SRAM_BASE_ADDR_LOW 0x120 |
| 566 | #define MV64360_PCI_INTERNAL_SRAM_BASE_ADDR_HIGH 0x124 |
| 567 | |
| 568 | /***********************************************/ |
| 569 | /* PCI Configuration, Function 2, Registers */ |
| 570 | /***********************************************/ |
| 571 | |
| 572 | #define MV64360_PCI_DEVCS_0_BASE_ADDR_LOW 0x210 |
| 573 | #define MV64360_PCI_DEVCS_0_BASE_ADDR_HIGH 0x214 |
| 574 | #define MV64360_PCI_DEVCS_1_BASE_ADDR_LOW 0x218 |
| 575 | #define MV64360_PCI_DEVCS_1_BASE_ADDR_HIGH 0x21c |
| 576 | #define MV64360_PCI_DEVCS_2_BASE_ADDR_LOW 0x220 |
| 577 | #define MV64360_PCI_DEVCS_2_BASE_ADDR_HIGH 0x224 |
| 578 | |
| 579 | /***********************************************/ |
| 580 | /* PCI Configuration, Function 3, Registers */ |
| 581 | /***********************************************/ |
| 582 | |
| 583 | #define MV64360_PCI_DEVCS_3_BASE_ADDR_LOW 0x310 |
| 584 | #define MV64360_PCI_DEVCS_3_BASE_ADDR_HIGH 0x314 |
| 585 | #define MV64360_PCI_BOOT_CS_BASE_ADDR_LOW 0x318 |
| 586 | #define MV64360_PCI_BOOT_CS_BASE_ADDR_HIGH 0x31c |
| 587 | #define MV64360_PCI_CPU_BASE_ADDR_LOW 0x220 |
| 588 | #define MV64360_PCI_CPU_BASE_ADDR_HIGH 0x224 |
| 589 | |
| 590 | /***********************************************/ |
| 591 | /* PCI Configuration, Function 4, Registers */ |
| 592 | /***********************************************/ |
| 593 | |
| 594 | #define MV64360_PCI_P2P_MEM0_BASE_ADDR_LOW 0x410 |
| 595 | #define MV64360_PCI_P2P_MEM0_BASE_ADDR_HIGH 0x414 |
| 596 | #define MV64360_PCI_P2P_MEM1_BASE_ADDR_LOW 0x418 |
| 597 | #define MV64360_PCI_P2P_MEM1_BASE_ADDR_HIGH 0x41c |
| 598 | #define MV64360_PCI_P2P_I_O_BASE_ADDR 0x420 |
| 599 | #define MV64360_PCI_INTERNAL_REGS_I_O_MAPPED_BASE_ADDR 0x424 |
| 600 | |
| 601 | /****************************************/ |
| 602 | /* Messaging Unit Registers (I20) */ |
| 603 | /****************************************/ |
| 604 | |
| 605 | #define MV64360_I2O_INBOUND_MESSAGE_REG0_PCI_0_SIDE 0x010 |
| 606 | #define MV64360_I2O_INBOUND_MESSAGE_REG1_PCI_0_SIDE 0x014 |
| 607 | #define MV64360_I2O_OUTBOUND_MESSAGE_REG0_PCI_0_SIDE 0x018 |
| 608 | #define MV64360_I2O_OUTBOUND_MESSAGE_REG1_PCI_0_SIDE 0x01C |
| 609 | #define MV64360_I2O_INBOUND_DOORBELL_REG_PCI_0_SIDE 0x020 |
| 610 | #define MV64360_I2O_INBOUND_INTERRUPT_CAUSE_REG_PCI_0_SIDE 0x024 |
| 611 | #define MV64360_I2O_INBOUND_INTERRUPT_MASK_REG_PCI_0_SIDE 0x028 |
| 612 | #define MV64360_I2O_OUTBOUND_DOORBELL_REG_PCI_0_SIDE 0x02C |
| 613 | #define MV64360_I2O_OUTBOUND_INTERRUPT_CAUSE_REG_PCI_0_SIDE 0x030 |
| 614 | #define MV64360_I2O_OUTBOUND_INTERRUPT_MASK_REG_PCI_0_SIDE 0x034 |
| 615 | #define MV64360_I2O_INBOUND_QUEUE_PORT_VIRTUAL_REG_PCI_0_SIDE 0x040 |
| 616 | #define MV64360_I2O_OUTBOUND_QUEUE_PORT_VIRTUAL_REG_PCI_0_SIDE 0x044 |
| 617 | #define MV64360_I2O_QUEUE_CONTROL_REG_PCI_0_SIDE 0x050 |
| 618 | #define MV64360_I2O_QUEUE_BASE_ADDR_REG_PCI_0_SIDE 0x054 |
| 619 | #define MV64360_I2O_INBOUND_FREE_HEAD_POINTER_REG_PCI_0_SIDE 0x060 |
| 620 | #define MV64360_I2O_INBOUND_FREE_TAIL_POINTER_REG_PCI_0_SIDE 0x064 |
| 621 | #define MV64360_I2O_INBOUND_POST_HEAD_POINTER_REG_PCI_0_SIDE 0x068 |
| 622 | #define MV64360_I2O_INBOUND_POST_TAIL_POINTER_REG_PCI_0_SIDE 0x06C |
| 623 | #define MV64360_I2O_OUTBOUND_FREE_HEAD_POINTER_REG_PCI_0_SIDE 0x070 |
| 624 | #define MV64360_I2O_OUTBOUND_FREE_TAIL_POINTER_REG_PCI_0_SIDE 0x074 |
| 625 | #define MV64360_I2O_OUTBOUND_POST_HEAD_POINTER_REG_PCI_0_SIDE 0x0F8 |
| 626 | #define MV64360_I2O_OUTBOUND_POST_TAIL_POINTER_REG_PCI_0_SIDE 0x0FC |
| 627 | |
| 628 | #define MV64360_I2O_INBOUND_MESSAGE_REG0_PCI_1_SIDE 0x090 |
| 629 | #define MV64360_I2O_INBOUND_MESSAGE_REG1_PCI_1_SIDE 0x094 |
| 630 | #define MV64360_I2O_OUTBOUND_MESSAGE_REG0_PCI_1_SIDE 0x098 |
| 631 | #define MV64360_I2O_OUTBOUND_MESSAGE_REG1_PCI_1_SIDE 0x09C |
| 632 | #define MV64360_I2O_INBOUND_DOORBELL_REG_PCI_1_SIDE 0x0A0 |
| 633 | #define MV64360_I2O_INBOUND_INTERRUPT_CAUSE_REG_PCI_1_SIDE 0x0A4 |
| 634 | #define MV64360_I2O_INBOUND_INTERRUPT_MASK_REG_PCI_1_SIDE 0x0A8 |
| 635 | #define MV64360_I2O_OUTBOUND_DOORBELL_REG_PCI_1_SIDE 0x0AC |
| 636 | #define MV64360_I2O_OUTBOUND_INTERRUPT_CAUSE_REG_PCI_1_SIDE 0x0B0 |
| 637 | #define MV64360_I2O_OUTBOUND_INTERRUPT_MASK_REG_PCI_1_SIDE 0x0B4 |
| 638 | #define MV64360_I2O_INBOUND_QUEUE_PORT_VIRTUAL_REG_PCI_1_SIDE 0x0C0 |
| 639 | #define MV64360_I2O_OUTBOUND_QUEUE_PORT_VIRTUAL_REG_PCI_1_SIDE 0x0C4 |
| 640 | #define MV64360_I2O_QUEUE_CONTROL_REG_PCI_1_SIDE 0x0D0 |
| 641 | #define MV64360_I2O_QUEUE_BASE_ADDR_REG_PCI_1_SIDE 0x0D4 |
| 642 | #define MV64360_I2O_INBOUND_FREE_HEAD_POINTER_REG_PCI_1_SIDE 0x0E0 |
| 643 | #define MV64360_I2O_INBOUND_FREE_TAIL_POINTER_REG_PCI_1_SIDE 0x0E4 |
| 644 | #define MV64360_I2O_INBOUND_POST_HEAD_POINTER_REG_PCI_1_SIDE 0x0E8 |
| 645 | #define MV64360_I2O_INBOUND_POST_TAIL_POINTER_REG_PCI_1_SIDE 0x0EC |
| 646 | #define MV64360_I2O_OUTBOUND_FREE_HEAD_POINTER_REG_PCI_1_SIDE 0x0F0 |
| 647 | #define MV64360_I2O_OUTBOUND_FREE_TAIL_POINTER_REG_PCI_1_SIDE 0x0F4 |
| 648 | #define MV64360_I2O_OUTBOUND_POST_HEAD_POINTER_REG_PCI_1_SIDE 0x078 |
| 649 | #define MV64360_I2O_OUTBOUND_POST_TAIL_POINTER_REG_PCI_1_SIDE 0x07C |
| 650 | |
| 651 | #define MV64360_I2O_INBOUND_MESSAGE_REG0_CPU0_SIDE 0x1C10 |
| 652 | #define MV64360_I2O_INBOUND_MESSAGE_REG1_CPU0_SIDE 0x1C14 |
| 653 | #define MV64360_I2O_OUTBOUND_MESSAGE_REG0_CPU0_SIDE 0x1C18 |
| 654 | #define MV64360_I2O_OUTBOUND_MESSAGE_REG1_CPU0_SIDE 0x1C1C |
| 655 | #define MV64360_I2O_INBOUND_DOORBELL_REG_CPU0_SIDE 0x1C20 |
| 656 | #define MV64360_I2O_INBOUND_INTERRUPT_CAUSE_REG_CPU0_SIDE 0x1C24 |
| 657 | #define MV64360_I2O_INBOUND_INTERRUPT_MASK_REG_CPU0_SIDE 0x1C28 |
| 658 | #define MV64360_I2O_OUTBOUND_DOORBELL_REG_CPU0_SIDE 0x1C2C |
| 659 | #define MV64360_I2O_OUTBOUND_INTERRUPT_CAUSE_REG_CPU0_SIDE 0x1C30 |
| 660 | #define MV64360_I2O_OUTBOUND_INTERRUPT_MASK_REG_CPU0_SIDE 0x1C34 |
| 661 | #define MV64360_I2O_INBOUND_QUEUE_PORT_VIRTUAL_REG_CPU0_SIDE 0x1C40 |
| 662 | #define MV64360_I2O_OUTBOUND_QUEUE_PORT_VIRTUAL_REG_CPU0_SIDE 0x1C44 |
| 663 | #define MV64360_I2O_QUEUE_CONTROL_REG_CPU0_SIDE 0x1C50 |
| 664 | #define MV64360_I2O_QUEUE_BASE_ADDR_REG_CPU0_SIDE 0x1C54 |
| 665 | #define MV64360_I2O_INBOUND_FREE_HEAD_POINTER_REG_CPU0_SIDE 0x1C60 |
| 666 | #define MV64360_I2O_INBOUND_FREE_TAIL_POINTER_REG_CPU0_SIDE 0x1C64 |
| 667 | #define MV64360_I2O_INBOUND_POST_HEAD_POINTER_REG_CPU0_SIDE 0x1C68 |
| 668 | #define MV64360_I2O_INBOUND_POST_TAIL_POINTER_REG_CPU0_SIDE 0x1C6C |
| 669 | #define MV64360_I2O_OUTBOUND_FREE_HEAD_POINTER_REG_CPU0_SIDE 0x1C70 |
| 670 | #define MV64360_I2O_OUTBOUND_FREE_TAIL_POINTER_REG_CPU0_SIDE 0x1C74 |
| 671 | #define MV64360_I2O_OUTBOUND_POST_HEAD_POINTER_REG_CPU0_SIDE 0x1CF8 |
| 672 | #define MV64360_I2O_OUTBOUND_POST_TAIL_POINTER_REG_CPU0_SIDE 0x1CFC |
| 673 | #define MV64360_I2O_INBOUND_MESSAGE_REG0_CPU1_SIDE 0x1C90 |
| 674 | #define MV64360_I2O_INBOUND_MESSAGE_REG1_CPU1_SIDE 0x1C94 |
| 675 | #define MV64360_I2O_OUTBOUND_MESSAGE_REG0_CPU1_SIDE 0x1C98 |
| 676 | #define MV64360_I2O_OUTBOUND_MESSAGE_REG1_CPU1_SIDE 0x1C9C |
| 677 | #define MV64360_I2O_INBOUND_DOORBELL_REG_CPU1_SIDE 0x1CA0 |
| 678 | #define MV64360_I2O_INBOUND_INTERRUPT_CAUSE_REG_CPU1_SIDE 0x1CA4 |
| 679 | #define MV64360_I2O_INBOUND_INTERRUPT_MASK_REG_CPU1_SIDE 0x1CA8 |
| 680 | #define MV64360_I2O_OUTBOUND_DOORBELL_REG_CPU1_SIDE 0x1CAC |
| 681 | #define MV64360_I2O_OUTBOUND_INTERRUPT_CAUSE_REG_CPU1_SIDE 0x1CB0 |
| 682 | #define MV64360_I2O_OUTBOUND_INTERRUPT_MASK_REG_CPU1_SIDE 0x1CB4 |
| 683 | #define MV64360_I2O_INBOUND_QUEUE_PORT_VIRTUAL_REG_CPU1_SIDE 0x1CC0 |
| 684 | #define MV64360_I2O_OUTBOUND_QUEUE_PORT_VIRTUAL_REG_CPU1_SIDE 0x1CC4 |
| 685 | #define MV64360_I2O_QUEUE_CONTROL_REG_CPU1_SIDE 0x1CD0 |
| 686 | #define MV64360_I2O_QUEUE_BASE_ADDR_REG_CPU1_SIDE 0x1CD4 |
| 687 | #define MV64360_I2O_INBOUND_FREE_HEAD_POINTER_REG_CPU1_SIDE 0x1CE0 |
| 688 | #define MV64360_I2O_INBOUND_FREE_TAIL_POINTER_REG_CPU1_SIDE 0x1CE4 |
| 689 | #define MV64360_I2O_INBOUND_POST_HEAD_POINTER_REG_CPU1_SIDE 0x1CE8 |
| 690 | #define MV64360_I2O_INBOUND_POST_TAIL_POINTER_REG_CPU1_SIDE 0x1CEC |
| 691 | #define MV64360_I2O_OUTBOUND_FREE_HEAD_POINTER_REG_CPU1_SIDE 0x1CF0 |
| 692 | #define MV64360_I2O_OUTBOUND_FREE_TAIL_POINTER_REG_CPU1_SIDE 0x1CF4 |
| 693 | #define MV64360_I2O_OUTBOUND_POST_HEAD_POINTER_REG_CPU1_SIDE 0x1C78 |
| 694 | #define MV64360_I2O_OUTBOUND_POST_TAIL_POINTER_REG_CPU1_SIDE 0x1C7C |
| 695 | |
| 696 | /****************************************/ |
| 697 | /* Ethernet Unit Registers */ |
| 698 | /****************************************/ |
| 699 | |
| 700 | #define MV64360_ETH_PHY_ADDR_REG 0x2000 |
| 701 | #define MV64360_ETH_SMI_REG 0x2004 |
| 702 | #define MV64360_ETH_UNIT_DEFAULT_ADDR_REG 0x2008 |
| 703 | #define MV64360_ETH_UNIT_DEFAULTID_REG 0x200c |
| 704 | #define MV64360_ETH_UNIT_INTERRUPT_CAUSE_REG 0x2080 |
| 705 | #define MV64360_ETH_UNIT_INTERRUPT_MASK_REG 0x2084 |
| 706 | #define MV64360_ETH_UNIT_INTERNAL_USE_REG 0x24fc |
| 707 | #define MV64360_ETH_UNIT_ERROR_ADDR_REG 0x2094 |
| 708 | #define MV64360_ETH_BAR_0 0x2200 |
| 709 | #define MV64360_ETH_BAR_1 0x2208 |
| 710 | #define MV64360_ETH_BAR_2 0x2210 |
| 711 | #define MV64360_ETH_BAR_3 0x2218 |
| 712 | #define MV64360_ETH_BAR_4 0x2220 |
| 713 | #define MV64360_ETH_BAR_5 0x2228 |
| 714 | #define MV64360_ETH_SIZE_REG_0 0x2204 |
| 715 | #define MV64360_ETH_SIZE_REG_1 0x220c |
| 716 | #define MV64360_ETH_SIZE_REG_2 0x2214 |
| 717 | #define MV64360_ETH_SIZE_REG_3 0x221c |
| 718 | #define MV64360_ETH_SIZE_REG_4 0x2224 |
| 719 | #define MV64360_ETH_SIZE_REG_5 0x222c |
| 720 | #define MV64360_ETH_HEADERS_RETARGET_BASE_REG 0x2230 |
| 721 | #define MV64360_ETH_HEADERS_RETARGET_CONTROL_REG 0x2234 |
| 722 | #define MV64360_ETH_HIGH_ADDR_REMAP_REG_0 0x2280 |
| 723 | #define MV64360_ETH_HIGH_ADDR_REMAP_REG_1 0x2284 |
| 724 | #define MV64360_ETH_HIGH_ADDR_REMAP_REG_2 0x2288 |
| 725 | #define MV64360_ETH_HIGH_ADDR_REMAP_REG_3 0x228c |
| 726 | #define MV64360_ETH_BASE_ADDR_ENABLE_REG 0x2290 |
| 727 | #define MV64360_ETH_ACCESS_PROTECTION_REG(port) (0x2294 + (port<<2)) |
| 728 | #define MV64360_ETH_MIB_COUNTERS_BASE(port) (0x3000 + (port<<7)) |
| 729 | #define MV64360_ETH_PORT_CONFIG_REG(port) (0x2400 + (port<<10)) |
| 730 | #define MV64360_ETH_PORT_CONFIG_EXTEND_REG(port) (0x2404 + (port<<10)) |
| 731 | #define MV64360_ETH_MII_SERIAL_PARAMETRS_REG(port) (0x2408 + (port<<10)) |
| 732 | #define MV64360_ETH_GMII_SERIAL_PARAMETRS_REG(port) (0x240c + (port<<10)) |
| 733 | #define MV64360_ETH_VLAN_ETHERTYPE_REG(port) (0x2410 + (port<<10)) |
| 734 | #define MV64360_ETH_MAC_ADDR_LOW(port) (0x2414 + (port<<10)) |
| 735 | #define MV64360_ETH_MAC_ADDR_HIGH(port) (0x2418 + (port<<10)) |
| 736 | #define MV64360_ETH_SDMA_CONFIG_REG(port) (0x241c + (port<<10)) |
| 737 | #define MV64360_ETH_DSCP_0(port) (0x2420 + (port<<10)) |
| 738 | #define MV64360_ETH_DSCP_1(port) (0x2424 + (port<<10)) |
| 739 | #define MV64360_ETH_DSCP_2(port) (0x2428 + (port<<10)) |
| 740 | #define MV64360_ETH_DSCP_3(port) (0x242c + (port<<10)) |
| 741 | #define MV64360_ETH_DSCP_4(port) (0x2430 + (port<<10)) |
| 742 | #define MV64360_ETH_DSCP_5(port) (0x2434 + (port<<10)) |
| 743 | #define MV64360_ETH_DSCP_6(port) (0x2438 + (port<<10)) |
| 744 | #define MV64360_ETH_PORT_SERIAL_CONTROL_REG(port) (0x243c + (port<<10)) |
| 745 | #define MV64360_ETH_VLAN_PRIORITY_TAG_TO_PRIORITY(port) (0x2440 + (port<<10)) |
| 746 | #define MV64360_ETH_PORT_STATUS_REG(port) (0x2444 + (port<<10)) |
| 747 | #define MV64360_ETH_TRANSMIT_QUEUE_COMMAND_REG(port) (0x2448 + (port<<10)) |
| 748 | #define MV64360_ETH_TX_QUEUE_FIXED_PRIORITY(port) (0x244c + (port<<10)) |
| 749 | #define MV64360_ETH_PORT_TX_TOKEN_BUCKET_RATE_CONFIG(port) (0x2450 + (port<<10)) |
| 750 | #define MV64360_ETH_MAXIMUM_TRANSMIT_UNIT(port) (0x2458 + (port<<10)) |
| 751 | #define MV64360_ETH_PORT_MAXIMUM_TOKEN_BUCKET_SIZE(port) (0x245c + (port<<10)) |
| 752 | #define MV64360_ETH_INTERRUPT_CAUSE_REG(port) (0x2460 + (port<<10)) |
| 753 | #define MV64360_ETH_INTERRUPT_CAUSE_EXTEND_REG(port) (0x2464 + (port<<10)) |
| 754 | #define MV64360_ETH_INTERRUPT_MASK_REG(port) (0x2468 + (port<<10)) |
| 755 | #define MV64360_ETH_INTERRUPT_EXTEND_MASK_REG(port) (0x246c + (port<<10)) |
| 756 | #define MV64360_ETH_RX_FIFO_URGENT_THRESHOLD_REG(port) (0x2470 + (port<<10)) |
| 757 | #define MV64360_ETH_TX_FIFO_URGENT_THRESHOLD_REG(port) (0x2474 + (port<<10)) |
| 758 | #define MV64360_ETH_RX_MINIMAL_FRAME_SIZE_REG(port) (0x247c + (port<<10)) |
| 759 | #define MV64360_ETH_RX_DISCARDED_FRAMES_COUNTER(port) (0x2484 + (port<<10) |
| 760 | #define MV64360_ETH_PORT_DEBUG_0_REG(port) (0x248c + (port<<10)) |
| 761 | #define MV64360_ETH_PORT_DEBUG_1_REG(port) (0x2490 + (port<<10)) |
| 762 | #define MV64360_ETH_PORT_INTERNAL_ADDR_ERROR_REG(port) (0x2494 + (port<<10)) |
| 763 | #define MV64360_ETH_INTERNAL_USE_REG(port) (0x24fc + (port<<10)) |
| 764 | #define MV64360_ETH_RECEIVE_QUEUE_COMMAND_REG(port) (0x2680 + (port<<10)) |
| 765 | #define MV64360_ETH_CURRENT_SERVED_TX_DESC_PTR(port) (0x2684 + (port<<10)) |
| 766 | #define MV64360_ETH_RX_CURRENT_QUEUE_DESC_PTR_0(port) (0x260c + (port<<10)) |
| 767 | #define MV64360_ETH_RX_CURRENT_QUEUE_DESC_PTR_1(port) (0x261c + (port<<10)) |
| 768 | #define MV64360_ETH_RX_CURRENT_QUEUE_DESC_PTR_2(port) (0x262c + (port<<10)) |
| 769 | #define MV64360_ETH_RX_CURRENT_QUEUE_DESC_PTR_3(port) (0x263c + (port<<10)) |
| 770 | #define MV64360_ETH_RX_CURRENT_QUEUE_DESC_PTR_4(port) (0x264c + (port<<10)) |
| 771 | #define MV64360_ETH_RX_CURRENT_QUEUE_DESC_PTR_5(port) (0x265c + (port<<10)) |
| 772 | #define MV64360_ETH_RX_CURRENT_QUEUE_DESC_PTR_6(port) (0x266c + (port<<10)) |
| 773 | #define MV64360_ETH_RX_CURRENT_QUEUE_DESC_PTR_7(port) (0x267c + (port<<10)) |
| 774 | #define MV64360_ETH_TX_CURRENT_QUEUE_DESC_PTR_0(port) (0x26c0 + (port<<10)) |
| 775 | #define MV64360_ETH_TX_CURRENT_QUEUE_DESC_PTR_1(port) (0x26c4 + (port<<10)) |
| 776 | #define MV64360_ETH_TX_CURRENT_QUEUE_DESC_PTR_2(port) (0x26c8 + (port<<10)) |
| 777 | #define MV64360_ETH_TX_CURRENT_QUEUE_DESC_PTR_3(port) (0x26cc + (port<<10)) |
| 778 | #define MV64360_ETH_TX_CURRENT_QUEUE_DESC_PTR_4(port) (0x26d0 + (port<<10)) |
| 779 | #define MV64360_ETH_TX_CURRENT_QUEUE_DESC_PTR_5(port) (0x26d4 + (port<<10)) |
| 780 | #define MV64360_ETH_TX_CURRENT_QUEUE_DESC_PTR_6(port) (0x26d8 + (port<<10)) |
| 781 | #define MV64360_ETH_TX_CURRENT_QUEUE_DESC_PTR_7(port) (0x26dc + (port<<10)) |
| 782 | #define MV64360_ETH_TX_QUEUE_0_TOKEN_BUCKET_COUNT(port) (0x2700 + (port<<10)) |
| 783 | #define MV64360_ETH_TX_QUEUE_1_TOKEN_BUCKET_COUNT(port) (0x2710 + (port<<10)) |
| 784 | #define MV64360_ETH_TX_QUEUE_2_TOKEN_BUCKET_COUNT(port) (0x2720 + (port<<10)) |
| 785 | #define MV64360_ETH_TX_QUEUE_3_TOKEN_BUCKET_COUNT(port) (0x2730 + (port<<10)) |
| 786 | #define MV64360_ETH_TX_QUEUE_4_TOKEN_BUCKET_COUNT(port) (0x2740 + (port<<10)) |
| 787 | #define MV64360_ETH_TX_QUEUE_5_TOKEN_BUCKET_COUNT(port) (0x2750 + (port<<10)) |
| 788 | #define MV64360_ETH_TX_QUEUE_6_TOKEN_BUCKET_COUNT(port) (0x2760 + (port<<10)) |
| 789 | #define MV64360_ETH_TX_QUEUE_7_TOKEN_BUCKET_COUNT(port) (0x2770 + (port<<10)) |
| 790 | #define MV64360_ETH_TX_QUEUE_0_TOKEN_BUCKET_CONFIG(port) (0x2704 + (port<<10)) |
| 791 | #define MV64360_ETH_TX_QUEUE_1_TOKEN_BUCKET_CONFIG(port) (0x2714 + (port<<10)) |
| 792 | #define MV64360_ETH_TX_QUEUE_2_TOKEN_BUCKET_CONFIG(port) (0x2724 + (port<<10)) |
| 793 | #define MV64360_ETH_TX_QUEUE_3_TOKEN_BUCKET_CONFIG(port) (0x2734 + (port<<10)) |
| 794 | #define MV64360_ETH_TX_QUEUE_4_TOKEN_BUCKET_CONFIG(port) (0x2744 + (port<<10)) |
| 795 | #define MV64360_ETH_TX_QUEUE_5_TOKEN_BUCKET_CONFIG(port) (0x2754 + (port<<10)) |
| 796 | #define MV64360_ETH_TX_QUEUE_6_TOKEN_BUCKET_CONFIG(port) (0x2764 + (port<<10)) |
| 797 | #define MV64360_ETH_TX_QUEUE_7_TOKEN_BUCKET_CONFIG(port) (0x2774 + (port<<10)) |
| 798 | #define MV64360_ETH_TX_QUEUE_0_ARBITER_CONFIG(port) (0x2708 + (port<<10)) |
| 799 | #define MV64360_ETH_TX_QUEUE_1_ARBITER_CONFIG(port) (0x2718 + (port<<10)) |
| 800 | #define MV64360_ETH_TX_QUEUE_2_ARBITER_CONFIG(port) (0x2728 + (port<<10)) |
| 801 | #define MV64360_ETH_TX_QUEUE_3_ARBITER_CONFIG(port) (0x2738 + (port<<10)) |
| 802 | #define MV64360_ETH_TX_QUEUE_4_ARBITER_CONFIG(port) (0x2748 + (port<<10)) |
| 803 | #define MV64360_ETH_TX_QUEUE_5_ARBITER_CONFIG(port) (0x2758 + (port<<10)) |
| 804 | #define MV64360_ETH_TX_QUEUE_6_ARBITER_CONFIG(port) (0x2768 + (port<<10)) |
| 805 | #define MV64360_ETH_TX_QUEUE_7_ARBITER_CONFIG(port) (0x2778 + (port<<10)) |
| 806 | #define MV64360_ETH_PORT_TX_TOKEN_BUCKET_COUNT(port) (0x2780 + (port<<10)) |
| 807 | #define MV64360_ETH_DA_FILTER_SPECIAL_MULTICAST_TABLE_BASE(port) (0x3400 + (port<<10)) |
| 808 | #define MV64360_ETH_DA_FILTER_OTHER_MULTICAST_TABLE_BASE(port) (0x3500 + (port<<10)) |
| 809 | #define MV64360_ETH_DA_FILTER_UNICAST_TABLE_BASE(port) (0x3600 + (port<<10)) |
| 810 | |
| 811 | /*******************************************/ |
| 812 | /* CUNIT Registers */ |
| 813 | /*******************************************/ |
| 814 | |
| 815 | /* Address Decoding Register Map */ |
| 816 | |
| 817 | #define MV64360_CUNIT_BASE_ADDR_REG0 0xf200 |
| 818 | #define MV64360_CUNIT_BASE_ADDR_REG1 0xf208 |
| 819 | #define MV64360_CUNIT_BASE_ADDR_REG2 0xf210 |
| 820 | #define MV64360_CUNIT_BASE_ADDR_REG3 0xf218 |
| 821 | #define MV64360_CUNIT_SIZE0 0xf204 |
| 822 | #define MV64360_CUNIT_SIZE1 0xf20c |
| 823 | #define MV64360_CUNIT_SIZE2 0xf214 |
| 824 | #define MV64360_CUNIT_SIZE3 0xf21c |
| 825 | #define MV64360_CUNIT_HIGH_ADDR_REMAP_REG0 0xf240 |
| 826 | #define MV64360_CUNIT_HIGH_ADDR_REMAP_REG1 0xf244 |
| 827 | #define MV64360_CUNIT_BASE_ADDR_ENABLE_REG 0xf250 |
| 828 | #define MV64360_MPSC0_ACCESS_PROTECTION_REG 0xf254 |
| 829 | #define MV64360_MPSC1_ACCESS_PROTECTION_REG 0xf258 |
| 830 | #define MV64360_CUNIT_INTERNAL_SPACE_BASE_ADDR_REG 0xf25C |
| 831 | |
| 832 | /* Error Report Registers */ |
| 833 | |
| 834 | #define MV64360_CUNIT_INTERRUPT_CAUSE_REG 0xf310 |
| 835 | #define MV64360_CUNIT_INTERRUPT_MASK_REG 0xf314 |
| 836 | #define MV64360_CUNIT_ERROR_ADDR 0xf318 |
| 837 | |
| 838 | /* Cunit Control Registers */ |
| 839 | |
| 840 | #define MV64360_CUNIT_ARBITER_CONTROL_REG 0xf300 |
| 841 | #define MV64360_CUNIT_CONFIG_REG 0xb40c |
| 842 | #define MV64360_CUNIT_CRROSBAR_TIMEOUT_REG 0xf304 |
| 843 | |
| 844 | /* Cunit Debug Registers */ |
| 845 | |
| 846 | #define MV64360_CUNIT_DEBUG_LOW 0xf340 |
| 847 | #define MV64360_CUNIT_DEBUG_HIGH 0xf344 |
| 848 | #define MV64360_CUNIT_MMASK 0xf380 |
| 849 | |
| 850 | /* Cunit Base Address Enable Window Bits*/ |
| 851 | #define MV64360_CUNIT_BASE_ADDR_WIN_0_BIT 0x0 |
| 852 | #define MV64360_CUNIT_BASE_ADDR_WIN_1_BIT 0x1 |
| 853 | #define MV64360_CUNIT_BASE_ADDR_WIN_2_BIT 0x2 |
| 854 | #define MV64360_CUNIT_BASE_ADDR_WIN_3_BIT 0x3 |
| 855 | |
| 856 | /* MPSCs Clocks Routing Registers */ |
| 857 | |
| 858 | #define MV64360_MPSC_ROUTING_REG 0xb400 |
| 859 | #define MV64360_MPSC_RX_CLOCK_ROUTING_REG 0xb404 |
| 860 | #define MV64360_MPSC_TX_CLOCK_ROUTING_REG 0xb408 |
| 861 | |
| 862 | /* MPSCs Interrupts Registers */ |
| 863 | |
| 864 | #define MV64360_MPSC_CAUSE_REG(port) (0xb804 + (port<<3)) |
| 865 | #define MV64360_MPSC_MASK_REG(port) (0xb884 + (port<<3)) |
| 866 | |
| 867 | #define MV64360_MPSC_MAIN_CONFIG_LOW(port) (0x8000 + (port<<12)) |
| 868 | #define MV64360_MPSC_MAIN_CONFIG_HIGH(port) (0x8004 + (port<<12)) |
| 869 | #define MV64360_MPSC_PROTOCOL_CONFIG(port) (0x8008 + (port<<12)) |
| 870 | #define MV64360_MPSC_CHANNEL_REG1(port) (0x800c + (port<<12)) |
| 871 | #define MV64360_MPSC_CHANNEL_REG2(port) (0x8010 + (port<<12)) |
| 872 | #define MV64360_MPSC_CHANNEL_REG3(port) (0x8014 + (port<<12)) |
| 873 | #define MV64360_MPSC_CHANNEL_REG4(port) (0x8018 + (port<<12)) |
| 874 | #define MV64360_MPSC_CHANNEL_REG5(port) (0x801c + (port<<12)) |
| 875 | #define MV64360_MPSC_CHANNEL_REG6(port) (0x8020 + (port<<12)) |
| 876 | #define MV64360_MPSC_CHANNEL_REG7(port) (0x8024 + (port<<12)) |
| 877 | #define MV64360_MPSC_CHANNEL_REG8(port) (0x8028 + (port<<12)) |
| 878 | #define MV64360_MPSC_CHANNEL_REG9(port) (0x802c + (port<<12)) |
| 879 | #define MV64360_MPSC_CHANNEL_REG10(port) (0x8030 + (port<<12)) |
| 880 | |
| 881 | /* MPSC0 Registers */ |
| 882 | |
| 883 | |
| 884 | /***************************************/ |
| 885 | /* SDMA Registers */ |
| 886 | /***************************************/ |
| 887 | |
| 888 | #define MV64360_SDMA_CONFIG_REG(channel) (0x4000 + (channel<<13)) |
| 889 | #define MV64360_SDMA_COMMAND_REG(channel) (0x4008 + (channel<<13)) |
| 890 | #define MV64360_SDMA_CURRENT_RX_DESCRIPTOR_POINTER(channel) (0x4810 + (channel<<13)) |
| 891 | #define MV64360_SDMA_CURRENT_TX_DESCRIPTOR_POINTER(channel) (0x4c10 + (channel<<13)) |
| 892 | #define MV64360_SDMA_FIRST_TX_DESCRIPTOR_POINTER(channel) (0x4c14 + (channel<<13)) |
| 893 | |
| 894 | #define MV64360_SDMA_CAUSE_REG 0xb800 |
| 895 | #define MV64360_SDMA_MASK_REG 0xb880 |
| 896 | |
| 897 | |
| 898 | /****************************************/ |
| 899 | /* SDMA Address Space Targets */ |
| 900 | /****************************************/ |
| 901 | |
| 902 | #define MV64360_SDMA_DRAM_CS_0_TARGET 0x0e00 |
| 903 | #define MV64360_SDMA_DRAM_CS_1_TARGET 0x0d00 |
| 904 | #define MV64360_SDMA_DRAM_CS_2_TARGET 0x0b00 |
| 905 | #define MV64360_SDMA_DRAM_CS_3_TARGET 0x0700 |
| 906 | |
| 907 | #define MV64360_SDMA_DEV_CS_0_TARGET 0x1e01 |
| 908 | #define MV64360_SDMA_DEV_CS_1_TARGET 0x1d01 |
| 909 | #define MV64360_SDMA_DEV_CS_2_TARGET 0x1b01 |
| 910 | #define MV64360_SDMA_DEV_CS_3_TARGET 0x1701 |
| 911 | |
| 912 | #define MV64360_SDMA_BOOT_CS_TARGET 0x0f00 |
| 913 | |
| 914 | #define MV64360_SDMA_SRAM_TARGET 0x0003 |
| 915 | #define MV64360_SDMA_60X_BUS_TARGET 0x4003 |
| 916 | |
| 917 | #define MV64360_PCI_0_TARGET 0x0003 |
| 918 | #define MV64360_PCI_1_TARGET 0x0004 |
| 919 | |
| 920 | |
| 921 | /* Devices BAR and size registers */ |
| 922 | |
| 923 | #define MV64360_DEV_CS0_BASE_ADDR 0x028 |
| 924 | #define MV64360_DEV_CS0_SIZE 0x030 |
| 925 | #define MV64360_DEV_CS1_BASE_ADDR 0x228 |
| 926 | #define MV64360_DEV_CS1_SIZE 0x230 |
| 927 | #define MV64360_DEV_CS2_BASE_ADDR 0x248 |
| 928 | #define MV64360_DEV_CS2_SIZE 0x250 |
| 929 | #define MV64360_DEV_CS3_BASE_ADDR 0x038 |
| 930 | #define MV64360_DEV_CS3_SIZE 0x040 |
| 931 | #define MV64360_BOOTCS_BASE_ADDR 0x238 |
| 932 | #define MV64360_BOOTCS_SIZE 0x240 |
| 933 | |
| 934 | /* SDMA Window access protection */ |
| 935 | #define MV64360_SDMA_WIN_ACCESS_NOT_ALLOWED 0 |
| 936 | #define MV64360_SDMA_WIN_ACCESS_READ_ONLY 1 |
| 937 | #define MV64360_SDMA_WIN_ACCESS_FULL 2 |
| 938 | |
| 939 | /* BRG Interrupts */ |
| 940 | |
| 941 | #define MV64360_BRG_CONFIG_REG(brg) (0xb200 + (brg<<3)) |
| 942 | #define MV64360_BRG_BAUDE_TUNING_REG(brg) (0xb204 + (brg<<3)) |
| 943 | #define MV64360_BRG_CAUSE_REG 0xb834 |
| 944 | #define MV64360_BRG_MASK_REG 0xb8b4 |
| 945 | |
| 946 | /****************************************/ |
| 947 | /* DMA Channel Control */ |
| 948 | /****************************************/ |
| 949 | |
| 950 | #define MV64360_DMA_CHANNEL0_CONTROL 0x840 |
| 951 | #define MV64360_DMA_CHANNEL0_CONTROL_HIGH 0x880 |
| 952 | #define MV64360_DMA_CHANNEL1_CONTROL 0x844 |
| 953 | #define MV64360_DMA_CHANNEL1_CONTROL_HIGH 0x884 |
| 954 | #define MV64360_DMA_CHANNEL2_CONTROL 0x848 |
| 955 | #define MV64360_DMA_CHANNEL2_CONTROL_HIGH 0x888 |
| 956 | #define MV64360_DMA_CHANNEL3_CONTROL 0x84C |
| 957 | #define MV64360_DMA_CHANNEL3_CONTROL_HIGH 0x88C |
| 958 | |
| 959 | |
| 960 | /****************************************/ |
| 961 | /* IDMA Registers */ |
| 962 | /****************************************/ |
| 963 | |
| 964 | #define MV64360_DMA_CHANNEL0_BYTE_COUNT 0x800 |
| 965 | #define MV64360_DMA_CHANNEL1_BYTE_COUNT 0x804 |
| 966 | #define MV64360_DMA_CHANNEL2_BYTE_COUNT 0x808 |
| 967 | #define MV64360_DMA_CHANNEL3_BYTE_COUNT 0x80C |
| 968 | #define MV64360_DMA_CHANNEL0_SOURCE_ADDR 0x810 |
| 969 | #define MV64360_DMA_CHANNEL1_SOURCE_ADDR 0x814 |
| 970 | #define MV64360_DMA_CHANNEL2_SOURCE_ADDR 0x818 |
| 971 | #define MV64360_DMA_CHANNEL3_SOURCE_ADDR 0x81c |
| 972 | #define MV64360_DMA_CHANNEL0_DESTINATION_ADDR 0x820 |
| 973 | #define MV64360_DMA_CHANNEL1_DESTINATION_ADDR 0x824 |
| 974 | #define MV64360_DMA_CHANNEL2_DESTINATION_ADDR 0x828 |
| 975 | #define MV64360_DMA_CHANNEL3_DESTINATION_ADDR 0x82C |
| 976 | #define MV64360_DMA_CHANNEL0_NEXT_DESCRIPTOR_POINTER 0x830 |
| 977 | #define MV64360_DMA_CHANNEL1_NEXT_DESCRIPTOR_POINTER 0x834 |
| 978 | #define MV64360_DMA_CHANNEL2_NEXT_DESCRIPTOR_POINTER 0x838 |
| 979 | #define MV64360_DMA_CHANNEL3_NEXT_DESCRIPTOR_POINTER 0x83C |
| 980 | #define MV64360_DMA_CHANNEL0_CURRENT_DESCRIPTOR_POINTER 0x870 |
| 981 | #define MV64360_DMA_CHANNEL1_CURRENT_DESCRIPTOR_POINTER 0x874 |
| 982 | #define MV64360_DMA_CHANNEL2_CURRENT_DESCRIPTOR_POINTER 0x878 |
| 983 | #define MV64360_DMA_CHANNEL3_CURRENT_DESCRIPTOR_POINTER 0x87C |
| 984 | |
| 985 | /* IDMA Address Decoding Base Address Registers */ |
| 986 | |
| 987 | #define MV64360_DMA_BASE_ADDR_REG0 0xa00 |
| 988 | #define MV64360_DMA_BASE_ADDR_REG1 0xa08 |
| 989 | #define MV64360_DMA_BASE_ADDR_REG2 0xa10 |
| 990 | #define MV64360_DMA_BASE_ADDR_REG3 0xa18 |
| 991 | #define MV64360_DMA_BASE_ADDR_REG4 0xa20 |
| 992 | #define MV64360_DMA_BASE_ADDR_REG5 0xa28 |
| 993 | #define MV64360_DMA_BASE_ADDR_REG6 0xa30 |
| 994 | #define MV64360_DMA_BASE_ADDR_REG7 0xa38 |
| 995 | |
| 996 | /* IDMA Address Decoding Size Address Register */ |
| 997 | |
| 998 | #define MV64360_DMA_SIZE_REG0 0xa04 |
| 999 | #define MV64360_DMA_SIZE_REG1 0xa0c |
| 1000 | #define MV64360_DMA_SIZE_REG2 0xa14 |
| 1001 | #define MV64360_DMA_SIZE_REG3 0xa1c |
| 1002 | #define MV64360_DMA_SIZE_REG4 0xa24 |
| 1003 | #define MV64360_DMA_SIZE_REG5 0xa2c |
| 1004 | #define MV64360_DMA_SIZE_REG6 0xa34 |
| 1005 | #define MV64360_DMA_SIZE_REG7 0xa3C |
| 1006 | |
| 1007 | /* IDMA Address Decoding High Address Remap and Access |
| 1008 | Protection Registers */ |
| 1009 | |
| 1010 | #define MV64360_DMA_HIGH_ADDR_REMAP_REG0 0xa60 |
| 1011 | #define MV64360_DMA_HIGH_ADDR_REMAP_REG1 0xa64 |
| 1012 | #define MV64360_DMA_HIGH_ADDR_REMAP_REG2 0xa68 |
| 1013 | #define MV64360_DMA_HIGH_ADDR_REMAP_REG3 0xa6C |
| 1014 | #define MV64360_DMA_BASE_ADDR_ENABLE_REG 0xa80 |
| 1015 | #define MV64360_DMA_CHANNEL0_ACCESS_PROTECTION_REG 0xa70 |
| 1016 | #define MV64360_DMA_CHANNEL1_ACCESS_PROTECTION_REG 0xa74 |
| 1017 | #define MV64360_DMA_CHANNEL2_ACCESS_PROTECTION_REG 0xa78 |
| 1018 | #define MV64360_DMA_CHANNEL3_ACCESS_PROTECTION_REG 0xa7c |
| 1019 | #define MV64360_DMA_ARBITER_CONTROL 0x860 |
| 1020 | #define MV64360_DMA_CROSS_BAR_TIMEOUT 0x8d0 |
| 1021 | |
| 1022 | /* IDMA Headers Retarget Registers */ |
| 1023 | |
| 1024 | #define MV64360_DMA_HEADERS_RETARGET_CONTROL 0xa84 |
| 1025 | #define MV64360_DMA_HEADERS_RETARGET_BASE 0xa88 |
| 1026 | |
| 1027 | /* IDMA Interrupt Register */ |
| 1028 | |
| 1029 | #define MV64360_DMA_INTERRUPT_CAUSE_REG 0x8c0 |
| 1030 | #define MV64360_DMA_INTERRUPT_CAUSE_MASK 0x8c4 |
| 1031 | #define MV64360_DMA_ERROR_ADDR 0x8c8 |
| 1032 | #define MV64360_DMA_ERROR_SELECT 0x8cc |
| 1033 | |
| 1034 | /* IDMA Debug Register ( for internal use ) */ |
| 1035 | |
| 1036 | #define MV64360_DMA_DEBUG_LOW 0x8e0 |
| 1037 | #define MV64360_DMA_DEBUG_HIGH 0x8e4 |
| 1038 | #define MV64360_DMA_SPARE 0xA8C |
| 1039 | |
| 1040 | /****************************************/ |
| 1041 | /* Timer_Counter */ |
| 1042 | /****************************************/ |
| 1043 | |
| 1044 | #define MV64360_TIMER_COUNTER0 0x850 |
| 1045 | #define MV64360_TIMER_COUNTER1 0x854 |
| 1046 | #define MV64360_TIMER_COUNTER2 0x858 |
| 1047 | #define MV64360_TIMER_COUNTER3 0x85C |
| 1048 | #define MV64360_TIMER_COUNTER_0_3_CONTROL 0x864 |
| 1049 | #define MV64360_TIMER_COUNTER_0_3_INTERRUPT_CAUSE 0x868 |
| 1050 | #define MV64360_TIMER_COUNTER_0_3_INTERRUPT_MASK 0x86c |
| 1051 | |
| 1052 | /****************************************/ |
| 1053 | /* Watchdog registers */ |
| 1054 | /****************************************/ |
| 1055 | |
| 1056 | #define MV64360_WATCHDOG_CONFIG_REG 0xb410 |
| 1057 | #define MV64360_WATCHDOG_VALUE_REG 0xb414 |
| 1058 | |
| 1059 | /****************************************/ |
| 1060 | /* I2C Registers */ |
| 1061 | /****************************************/ |
| 1062 | |
| 1063 | #define MV64360_I2C_SLAVE_ADDR 0xc000 |
| 1064 | #define MV64360_I2C_EXTENDED_SLAVE_ADDR 0xc010 |
| 1065 | #define MV64360_I2C_DATA 0xc004 |
| 1066 | #define MV64360_I2C_CONTROL 0xc008 |
| 1067 | #define MV64360_I2C_STATUS_BAUDE_RATE 0xc00C |
| 1068 | #define MV64360_I2C_SOFT_RESET 0xc01c |
| 1069 | |
| 1070 | /****************************************/ |
| 1071 | /* GPP Interface Registers */ |
| 1072 | /****************************************/ |
| 1073 | |
| 1074 | #define MV64360_GPP_IO_CONTROL 0xf100 |
| 1075 | #define MV64360_GPP_LEVEL_CONTROL 0xf110 |
| 1076 | #define MV64360_GPP_VALUE 0xf104 |
| 1077 | #define MV64360_GPP_INTERRUPT_CAUSE 0xf108 |
| 1078 | #define MV64360_GPP_INTERRUPT_MASK0 0xf10c |
| 1079 | #define MV64360_GPP_INTERRUPT_MASK1 0xf114 |
| 1080 | #define MV64360_GPP_VALUE_SET 0xf118 |
| 1081 | #define MV64360_GPP_VALUE_CLEAR 0xf11c |
| 1082 | |
| 1083 | /****************************************/ |
| 1084 | /* Interrupt Controller Registers */ |
| 1085 | /****************************************/ |
| 1086 | |
| 1087 | /****************************************/ |
| 1088 | /* Interrupts */ |
| 1089 | /****************************************/ |
| 1090 | |
| 1091 | #define MV64360_MAIN_INTERRUPT_CAUSE_LOW 0x004 |
| 1092 | #define MV64360_MAIN_INTERRUPT_CAUSE_HIGH 0x00c |
| 1093 | #define MV64360_CPU_INTERRUPT0_MASK_LOW 0x014 |
| 1094 | #define MV64360_CPU_INTERRUPT0_MASK_HIGH 0x01c |
| 1095 | #define MV64360_CPU_INTERRUPT0_SELECT_CAUSE 0x024 |
| 1096 | #define MV64360_CPU_INTERRUPT1_MASK_LOW 0x034 |
| 1097 | #define MV64360_CPU_INTERRUPT1_MASK_HIGH 0x03c |
| 1098 | #define MV64360_CPU_INTERRUPT1_SELECT_CAUSE 0x044 |
| 1099 | #define MV64360_INTERRUPT0_MASK_0_LOW 0x054 |
| 1100 | #define MV64360_INTERRUPT0_MASK_0_HIGH 0x05c |
| 1101 | #define MV64360_INTERRUPT0_SELECT_CAUSE 0x064 |
| 1102 | #define MV64360_INTERRUPT1_MASK_0_LOW 0x074 |
| 1103 | #define MV64360_INTERRUPT1_MASK_0_HIGH 0x07c |
| 1104 | #define MV64360_INTERRUPT1_SELECT_CAUSE 0x084 |
| 1105 | |
| 1106 | /****************************************/ |
| 1107 | /* MPP Interface Registers */ |
| 1108 | /****************************************/ |
| 1109 | |
| 1110 | #define MV64360_MPP_CONTROL0 0xf000 |
| 1111 | #define MV64360_MPP_CONTROL1 0xf004 |
| 1112 | #define MV64360_MPP_CONTROL2 0xf008 |
| 1113 | #define MV64360_MPP_CONTROL3 0xf00c |
| 1114 | |
| 1115 | /****************************************/ |
| 1116 | /* Serial Initialization registers */ |
| 1117 | /****************************************/ |
| 1118 | |
| 1119 | #define MV64360_SERIAL_INIT_LAST_DATA 0xf324 |
| 1120 | #define MV64360_SERIAL_INIT_CONTROL 0xf328 |
| 1121 | #define MV64360_SERIAL_INIT_STATUS 0xf32c |
| 1122 | |
| 1123 | |
| 1124 | #endif /* __INCgt64360rh */ |