blob: 07d14482d68c0fa6daaa996bb2e11d5a0a0ace9e [file] [log] [blame]
Philipp Tomsich1168d2d2017-07-28 17:43:19 +02001/*
2 * Copyright (C) 2017 Theobroma Systems Design und Consulting GmbH
3 *
4 * SPDX-License-Identifier: GPL-2.0+
5 */
6
7#include <common.h>
8#include <dm.h>
Philipp Tomsichcc7ce942017-09-11 22:04:16 +02009#include <dm/ofnode.h>
Philipp Tomsich1168d2d2017-07-28 17:43:19 +020010#include <mapmem.h>
11#include <asm/arch/timer.h>
12#include <dt-structs.h>
13#include <timer.h>
14#include <asm/io.h>
15
16DECLARE_GLOBAL_DATA_PTR;
17
18#if CONFIG_IS_ENABLED(OF_PLATDATA)
19struct rockchip_timer_plat {
20 struct dtd_rockchip_rk3368_timer dtd;
21};
22#endif
23
24/* Driver private data. Contains timer id. Could be either 0 or 1. */
25struct rockchip_timer_priv {
26 struct rk_timer *timer;
27};
28
Philipp Tomsichcc7ce942017-09-11 22:04:16 +020029static inline int64_t rockchip_timer_get_curr_value(struct rk_timer *timer)
Philipp Tomsich1168d2d2017-07-28 17:43:19 +020030{
Philipp Tomsich1168d2d2017-07-28 17:43:19 +020031 uint64_t timebase_h, timebase_l;
32 uint64_t cntr;
33
Philipp Tomsichcc7ce942017-09-11 22:04:16 +020034 timebase_l = readl(&timer->timer_curr_value0);
35 timebase_h = readl(&timer->timer_curr_value1);
36
37 cntr = timebase_h << 32 | timebase_l;
38 return cntr;
39}
40
41#if CONFIG_IS_ENABLED(BOOTSTAGE)
42ulong timer_get_boot_us(void)
43{
44 uint64_t ticks = 0;
45 uint32_t rate;
46 uint64_t us;
47 int ret;
48
49 ret = dm_timer_init();
50
51 if (!ret) {
52 /* The timer is available */
53 rate = timer_get_rate(gd->timer);
54 timer_get_count(gd->timer, &ticks);
55#if !CONFIG_IS_ENABLED(OF_PLATDATA)
56 } else if (ret == -EAGAIN) {
57 /* We have been called so early that the DM is not ready,... */
58 ofnode node = offset_to_ofnode(-1);
59 struct rk_timer *timer = NULL;
60
61 /*
62 * ... so we try to access the raw timer, if it is specified
63 * via the tick-timer property in /chosen.
64 */
65 node = ofnode_get_chosen_node("tick-timer");
66 if (!ofnode_valid(node)) {
67 debug("%s: no /chosen/tick-timer\n", __func__);
68 return 0;
69 }
70
71 timer = (struct rk_timer *)ofnode_get_addr(node);
72
73 /* This timer is down-counting */
74 ticks = ~0uLL - rockchip_timer_get_curr_value(timer);
75 if (ofnode_read_u32(node, "clock-frequency", &rate)) {
76 debug("%s: could not read clock-frequency\n", __func__);
77 return 0;
78 }
79#endif
80 } else {
81 return 0;
82 }
83
84 us = (ticks * 1000) / rate;
85 return us;
86}
87#endif
88
89static int rockchip_timer_get_count(struct udevice *dev, u64 *count)
90{
91 struct rockchip_timer_priv *priv = dev_get_priv(dev);
92 uint64_t cntr = rockchip_timer_get_curr_value(priv->timer);
Philipp Tomsich1168d2d2017-07-28 17:43:19 +020093
94 /* timers are down-counting */
Philipp Tomsich1168d2d2017-07-28 17:43:19 +020095 *count = ~0ull - cntr;
96 return 0;
97}
98
99static int rockchip_clk_ofdata_to_platdata(struct udevice *dev)
100{
101#if !CONFIG_IS_ENABLED(OF_PLATDATA)
102 struct rockchip_timer_priv *priv = dev_get_priv(dev);
103
Philipp Tomsich6675c952017-09-11 22:04:17 +0200104 priv->timer = dev_read_addr_ptr(dev);
105 if (!priv->timer)
106 return -ENOENT;
Philipp Tomsich1168d2d2017-07-28 17:43:19 +0200107#endif
108
109 return 0;
110}
111
112static int rockchip_timer_start(struct udevice *dev)
113{
114 struct rockchip_timer_priv *priv = dev_get_priv(dev);
115 const uint64_t reload_val = ~0uLL;
116 const uint32_t reload_val_l = reload_val & 0xffffffff;
117 const uint32_t reload_val_h = reload_val >> 32;
118
Philipp Tomsichcc7ce942017-09-11 22:04:16 +0200119 /* don't reinit, if the timer is already running and set up */
120 if ((readl(&priv->timer->timer_ctrl_reg) & 1) == 1 &&
121 (readl(&priv->timer->timer_load_count0) == reload_val_l) &&
122 (readl(&priv->timer->timer_load_count1) == reload_val_h))
123 return 0;
124
Philipp Tomsich1168d2d2017-07-28 17:43:19 +0200125 /* disable timer and reset all control */
126 writel(0, &priv->timer->timer_ctrl_reg);
127 /* write reload value */
128 writel(reload_val_l, &priv->timer->timer_load_count0);
129 writel(reload_val_h, &priv->timer->timer_load_count1);
130 /* enable timer */
131 writel(1, &priv->timer->timer_ctrl_reg);
132
133 return 0;
134}
135
136static int rockchip_timer_probe(struct udevice *dev)
137{
138#if CONFIG_IS_ENABLED(OF_PLATDATA)
139 struct timer_dev_priv *uc_priv = dev_get_uclass_priv(dev);
140 struct rockchip_timer_priv *priv = dev_get_priv(dev);
141 struct rockchip_timer_plat *plat = dev_get_platdata(dev);
142
Philipp Tomsich8158a842017-08-14 19:05:31 +0200143 priv->timer = map_sysmem(plat->dtd.reg[0], plat->dtd.reg[1]);
Philipp Tomsich1168d2d2017-07-28 17:43:19 +0200144 uc_priv->clock_rate = plat->dtd.clock_frequency;
145#endif
146
147 return rockchip_timer_start(dev);
148}
149
150static const struct timer_ops rockchip_timer_ops = {
151 .get_count = rockchip_timer_get_count,
152};
153
154static const struct udevice_id rockchip_timer_ids[] = {
155 { .compatible = "rockchip,rk3368-timer" },
156 {}
157};
158
Philipp Tomsich5798d502017-08-25 13:22:00 +0200159U_BOOT_DRIVER(rockchip_rk3368_timer) = {
Philipp Tomsich1168d2d2017-07-28 17:43:19 +0200160 .name = "rockchip_rk3368_timer",
161 .id = UCLASS_TIMER,
162 .of_match = rockchip_timer_ids,
163 .probe = rockchip_timer_probe,
164 .ops = &rockchip_timer_ops,
165 .flags = DM_FLAG_PRE_RELOC,
166 .priv_auto_alloc_size = sizeof(struct rockchip_timer_priv),
167#if CONFIG_IS_ENABLED(OF_PLATDATA)
168 .platdata_auto_alloc_size = sizeof(struct rockchip_timer_plat),
169#endif
170 .ofdata_to_platdata = rockchip_clk_ofdata_to_platdata,
171};