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wdenk42d1f032003-10-15 23:53:47 +00001/*
Ed Swarthout29372ff2007-07-27 01:50:47 -05002 * Copyright 2007 Freescale Semiconductor.
3 *
wdenk42d1f032003-10-15 23:53:47 +00004 * (C) Copyright 2003 Motorola Inc.
5 * Modified by Xianghua Xiao, X.Xiao@motorola.com
6 *
7 * (C) Copyright 2000
8 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
9 *
10 * See file CREDITS for list of people who contributed to this
11 * project.
12 *
13 * This program is free software; you can redistribute it and/or
14 * modify it under the terms of the GNU General Public License as
15 * published by the Free Software Foundation; either version 2 of
16 * the License, or (at your option) any later version.
17 *
18 * This program is distributed in the hope that it will be useful,
19 * but WITHOUT ANY WARRANTY; without even the implied warranty of
20 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
21 * GNU General Public License for more details.
22 *
23 * You should have received a copy of the GNU General Public License
24 * along with this program; if not, write to the Free Software
25 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
26 * MA 02111-1307 USA
27 */
28
29#include <common.h>
30#include <watchdog.h>
31#include <asm/processor.h>
32#include <ioports.h>
33#include <asm/io.h>
34
Wolfgang Denkd87080b2006-03-31 18:32:53 +020035DECLARE_GLOBAL_DATA_PTR;
36
Andy Flemingda9d4612007-08-14 00:14:25 -050037#ifdef CONFIG_QE
38extern qe_iop_conf_t qe_iop_conf_tab[];
39extern void qe_config_iopin(u8 port, u8 pin, int dir,
40 int open_drain, int assign);
41extern void qe_init(uint qe_base);
42extern void qe_reset(void);
43
44static void config_qe_ioports(void)
45{
46 u8 port, pin;
47 int dir, open_drain, assign;
48 int i;
49
50 for (i = 0; qe_iop_conf_tab[i].assign != QE_IOP_TAB_END; i++) {
51 port = qe_iop_conf_tab[i].port;
52 pin = qe_iop_conf_tab[i].pin;
53 dir = qe_iop_conf_tab[i].dir;
54 open_drain = qe_iop_conf_tab[i].open_drain;
55 assign = qe_iop_conf_tab[i].assign;
56 qe_config_iopin(port, pin, dir, open_drain, assign);
57 }
58}
59#endif
Matthew McClintock40d5fa32006-06-28 10:43:36 -050060
Jon Loeliger9c4c5ae2005-07-23 10:37:35 -050061#ifdef CONFIG_CPM2
Kumar Galaaafeefb2007-11-28 00:36:33 -060062void config_8560_ioports (volatile ccsr_cpm_t * cpm)
wdenk42d1f032003-10-15 23:53:47 +000063{
64 int portnum;
65
66 for (portnum = 0; portnum < 4; portnum++) {
67 uint pmsk = 0,
68 ppar = 0,
69 psor = 0,
70 pdir = 0,
71 podr = 0,
72 pdat = 0;
73 iop_conf_t *iopc = (iop_conf_t *) & iop_conf_tab[portnum][0];
74 iop_conf_t *eiopc = iopc + 32;
75 uint msk = 1;
76
77 /*
78 * NOTE:
79 * index 0 refers to pin 31,
80 * index 31 refers to pin 0
81 */
82 while (iopc < eiopc) {
83 if (iopc->conf) {
84 pmsk |= msk;
85 if (iopc->ppar)
86 ppar |= msk;
87 if (iopc->psor)
88 psor |= msk;
89 if (iopc->pdir)
90 pdir |= msk;
91 if (iopc->podr)
92 podr |= msk;
93 if (iopc->pdat)
94 pdat |= msk;
95 }
96
97 msk <<= 1;
98 iopc++;
99 }
100
101 if (pmsk != 0) {
Kumar Galaaafeefb2007-11-28 00:36:33 -0600102 volatile ioport_t *iop = ioport_addr (cpm, portnum);
wdenk42d1f032003-10-15 23:53:47 +0000103 uint tpmsk = ~pmsk;
104
105 /*
106 * the (somewhat confused) paragraph at the
107 * bottom of page 35-5 warns that there might
108 * be "unknown behaviour" when programming
109 * PSORx and PDIRx, if PPARx = 1, so I
110 * decided this meant I had to disable the
111 * dedicated function first, and enable it
112 * last.
113 */
114 iop->ppar &= tpmsk;
115 iop->psor = (iop->psor & tpmsk) | psor;
116 iop->podr = (iop->podr & tpmsk) | podr;
117 iop->pdat = (iop->pdat & tpmsk) | pdat;
118 iop->pdir = (iop->pdir & tpmsk) | pdir;
119 iop->ppar |= ppar;
120 }
121 }
122}
123#endif
124
125/*
126 * Breathe some life into the CPU...
127 *
128 * Set up the memory map
129 * initialize a bunch of registers
130 */
131
132void cpu_init_f (void)
133{
Kumar Gala04db4002007-11-29 02:10:09 -0600134 volatile ccsr_lbc_t *memctl = (void *)(CFG_MPC85xx_LBC_ADDR);
wdenk42d1f032003-10-15 23:53:47 +0000135 extern void m8560_cpm_reset (void);
136
137 /* Pointer is writable since we allocated a register for it */
138 gd = (gd_t *) (CFG_INIT_RAM_ADDR + CFG_GBL_DATA_OFFSET);
139
140 /* Clear initial global data */
141 memset ((void *) gd, 0, sizeof (gd_t));
142
143
Jon Loeliger9c4c5ae2005-07-23 10:37:35 -0500144#ifdef CONFIG_CPM2
Kumar Galaaafeefb2007-11-28 00:36:33 -0600145 config_8560_ioports((ccsr_cpm_t *)CFG_MPC85xx_CPM_ADDR);
wdenk42d1f032003-10-15 23:53:47 +0000146#endif
147
148 /* Map banks 0 and 1 to the FLASH banks 0 and 1 at preliminary
149 * addresses - these have to be modified later when FLASH size
150 * has been determined
151 */
152#if defined(CFG_OR0_REMAP)
153 memctl->or0 = CFG_OR0_REMAP;
154#endif
155#if defined(CFG_OR1_REMAP)
156 memctl->or1 = CFG_OR1_REMAP;
157#endif
158
159 /* now restrict to preliminary range */
Ed Swarthout29372ff2007-07-27 01:50:47 -0500160 /* if cs1 is already set via debugger, leave cs0/cs1 alone */
161 if (! memctl->br1 & 1) {
wdenk42d1f032003-10-15 23:53:47 +0000162#if defined(CFG_BR0_PRELIM) && defined(CFG_OR0_PRELIM)
Ed Swarthout29372ff2007-07-27 01:50:47 -0500163 memctl->br0 = CFG_BR0_PRELIM;
164 memctl->or0 = CFG_OR0_PRELIM;
wdenk42d1f032003-10-15 23:53:47 +0000165#endif
166
167#if defined(CFG_BR1_PRELIM) && defined(CFG_OR1_PRELIM)
Ed Swarthout29372ff2007-07-27 01:50:47 -0500168 memctl->or1 = CFG_OR1_PRELIM;
169 memctl->br1 = CFG_BR1_PRELIM;
wdenk42d1f032003-10-15 23:53:47 +0000170#endif
Ed Swarthout29372ff2007-07-27 01:50:47 -0500171 }
wdenk42d1f032003-10-15 23:53:47 +0000172
wdenk42d1f032003-10-15 23:53:47 +0000173#if defined(CFG_BR2_PRELIM) && defined(CFG_OR2_PRELIM)
174 memctl->or2 = CFG_OR2_PRELIM;
175 memctl->br2 = CFG_BR2_PRELIM;
176#endif
wdenk42d1f032003-10-15 23:53:47 +0000177
178#if defined(CFG_BR3_PRELIM) && defined(CFG_OR3_PRELIM)
179 memctl->or3 = CFG_OR3_PRELIM;
180 memctl->br3 = CFG_BR3_PRELIM;
181#endif
182
183#if defined(CFG_BR4_PRELIM) && defined(CFG_OR4_PRELIM)
184 memctl->or4 = CFG_OR4_PRELIM;
185 memctl->br4 = CFG_BR4_PRELIM;
186#endif
187
188#if defined(CFG_BR5_PRELIM) && defined(CFG_OR5_PRELIM)
189 memctl->or5 = CFG_OR5_PRELIM;
190 memctl->br5 = CFG_BR5_PRELIM;
191#endif
192
193#if defined(CFG_BR6_PRELIM) && defined(CFG_OR6_PRELIM)
194 memctl->or6 = CFG_OR6_PRELIM;
195 memctl->br6 = CFG_BR6_PRELIM;
196#endif
197
198#if defined(CFG_BR7_PRELIM) && defined(CFG_OR7_PRELIM)
199 memctl->or7 = CFG_OR7_PRELIM;
200 memctl->br7 = CFG_BR7_PRELIM;
201#endif
202
Jon Loeliger9c4c5ae2005-07-23 10:37:35 -0500203#if defined(CONFIG_CPM2)
wdenk42d1f032003-10-15 23:53:47 +0000204 m8560_cpm_reset();
205#endif
Andy Flemingda9d4612007-08-14 00:14:25 -0500206#ifdef CONFIG_QE
207 /* Config QE ioports */
208 config_qe_ioports();
209#endif
210
wdenk42d1f032003-10-15 23:53:47 +0000211}
212
Jon Loeligerd9b94f22005-07-25 14:05:07 -0500213
wdenk42d1f032003-10-15 23:53:47 +0000214/*
Jon Loeligerd9b94f22005-07-25 14:05:07 -0500215 * Initialize L2 as cache.
216 *
217 * The newer 8548, etc, parts have twice as much cache, but
218 * use the same bit-encoding as the older 8555, etc, parts.
219 *
wdenk42d1f032003-10-15 23:53:47 +0000220 */
Jon Loeligerd9b94f22005-07-25 14:05:07 -0500221
222int cpu_init_r(void)
wdenk42d1f032003-10-15 23:53:47 +0000223{
Andy Fleming6c543592007-08-13 14:38:06 -0500224#ifdef CONFIG_CLEAR_LAW0
Kumar Gala04db4002007-11-29 02:10:09 -0600225 volatile ccsr_local_ecm_t *ecm = (void *)(CFG_MPC85xx_ECM_ADDR);
Ed Swarthout29372ff2007-07-27 01:50:47 -0500226
Ed Swarthout29372ff2007-07-27 01:50:47 -0500227 /* clear alternate boot location LAW (used for sdram, or ddr bank) */
228 ecm->lawar0 = 0;
229#endif
230
wdenk42d1f032003-10-15 23:53:47 +0000231#if defined(CONFIG_L2_CACHE)
Kumar Gala04db4002007-11-29 02:10:09 -0600232 volatile ccsr_l2cache_t *l2cache = (void *)CFG_MPC85xx_L2_ADDR;
Jon Loeligerd9b94f22005-07-25 14:05:07 -0500233 volatile uint cache_ctl;
234 uint svr, ver;
Ed Swarthout29372ff2007-07-27 01:50:47 -0500235 uint l2srbar;
Jon Loeligerd9b94f22005-07-25 14:05:07 -0500236
237 svr = get_svr();
238 ver = SVR_VER(svr);
wdenk42d1f032003-10-15 23:53:47 +0000239
240 asm("msync;isync");
Jon Loeligerd9b94f22005-07-25 14:05:07 -0500241 cache_ctl = l2cache->l2ctl;
242
243 switch (cache_ctl & 0x30000000) {
Jon Loeligerd65cfe82005-07-25 10:58:39 -0500244 case 0x20000000:
Ed Swarthout29372ff2007-07-27 01:50:47 -0500245 if (ver == SVR_8548 || ver == SVR_8548_E ||
Haiying Wang7a1ac412007-08-23 15:20:54 -0400246 ver == SVR_8544 || ver == SVR_8568_E) {
Jon Loeligerd9b94f22005-07-25 14:05:07 -0500247 printf ("L2 cache 512KB:");
Ed Swarthout29372ff2007-07-27 01:50:47 -0500248 /* set L2E=1, L2I=1, & L2SRAM=0 */
249 cache_ctl = 0xc0000000;
Jon Loeligerd9b94f22005-07-25 14:05:07 -0500250 } else {
251 printf ("L2 cache 256KB:");
Ed Swarthout29372ff2007-07-27 01:50:47 -0500252 /* set L2E=1, L2I=1, & L2BLKSZ=2 (256 Kbyte) */
253 cache_ctl = 0xc8000000;
Jon Loeligerd9b94f22005-07-25 14:05:07 -0500254 }
Jon Loeligerd65cfe82005-07-25 10:58:39 -0500255 break;
Jon Loeligerd65cfe82005-07-25 10:58:39 -0500256 case 0x10000000:
Ed Swarthout29372ff2007-07-27 01:50:47 -0500257 printf ("L2 cache 256KB:");
258 if (ver == SVR_8544 || ver == SVR_8544_E) {
259 cache_ctl = 0xc0000000; /* set L2E=1, L2I=1, & L2SRAM=0 */
260 }
261 break;
Jon Loeligerd65cfe82005-07-25 10:58:39 -0500262 case 0x30000000:
Ed Swarthout29372ff2007-07-27 01:50:47 -0500263 case 0x00000000:
Jon Loeligerd65cfe82005-07-25 10:58:39 -0500264 default:
Jon Loeligerd9b94f22005-07-25 14:05:07 -0500265 printf ("L2 cache unknown size (0x%08x)\n", cache_ctl);
Jon Loeligerd65cfe82005-07-25 10:58:39 -0500266 return -1;
267 }
268
Ed Swarthout29372ff2007-07-27 01:50:47 -0500269 if (l2cache->l2ctl & 0x80000000) {
270 printf(" already enabled.");
271 l2srbar = l2cache->l2srbar0;
272#ifdef CFG_INIT_L2_ADDR
273 if (l2cache->l2ctl & 0x00010000 && l2srbar >= CFG_FLASH_BASE) {
274 l2srbar = CFG_INIT_L2_ADDR;
275 l2cache->l2srbar0 = l2srbar;
276 printf(" Moving to 0x%08x", CFG_INIT_L2_ADDR);
277 }
278#endif /* CFG_INIT_L2_ADDR */
279 puts("\n");
280 } else {
281 asm("msync;isync");
282 l2cache->l2ctl = cache_ctl; /* invalidate & enable */
283 asm("msync;isync");
284 printf(" enabled\n");
285 }
wdenk42d1f032003-10-15 23:53:47 +0000286#else
Jon Loeligerd9b94f22005-07-25 14:05:07 -0500287 printf("L2 cache: disabled\n");
wdenk42d1f032003-10-15 23:53:47 +0000288#endif
Andy Flemingda9d4612007-08-14 00:14:25 -0500289#ifdef CONFIG_QE
290 uint qe_base = CFG_IMMR + 0x00080000; /* QE immr base */
291 qe_init(qe_base);
292 qe_reset();
293#endif
wdenk42d1f032003-10-15 23:53:47 +0000294
295 return 0;
296}