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wdenkc1896002003-12-28 11:44:59 +00001/*
2 * (C) Copyright 2003
wdenkd4ca31c2004-01-02 14:00:00 +00003 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
4 *
5 * modified for TOP5200-series by Reinhard Meyer, www.emk-elektronik.de
6 *
7 * TOP5200 differences from IceCube:
8 * 1 FLASH Bank for one Chip only, up to 64 MB in 16 MB Banks
9 * bank switch controlled by TIMER_6(LSB) and TIMER_7(MSB) Pins
10 * 1 SDRAM/DDRAM Bank up to 256 MB
11 * local VPD I2C Bus is software driven and uses
12 * GPIO_WKUP_6 for SDA, GPIO_WKUP_7 for SCL
13 * FLASH is re-located at 0xff000000
14 * Internal regs are at 0xf0000000
wdenkc1896002003-12-28 11:44:59 +000015 * Reset jumps to 0x00000100
16 *
17 * See file CREDITS for list of people who contributed to this
18 * project.
19 *
20 * This program is free software; you can redistribute it and/or
21 * modify it under the terms of the GNU General Public License as
22 * published by the Free Software Foundation; either version 2 of
23 * the License, or (at your option) any later version.
24 *
25 * This program is distributed in the hope that it will be useful,
26 * but WITHOUT ANY WARRANTY; without even the implied warranty of
27 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
28 * GNU General Public License for more details.
29 *
30 * You should have received a copy of the GNU General Public License
31 * along with this program; if not, write to the Free Software
32 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
33 * MA 02111-1307 USA
34 */
35
36#ifndef __CONFIG_H
37#define __CONFIG_H
38
39/*
40 * High Level Configuration Options
41 * (easy to change)
42 */
43
wdenkcbd8a352004-02-24 02:00:03 +000044#define CONFIG_MPC5xxx 1 /* This is an MPC5xxx CPU */
wdenkc1896002003-12-28 11:44:59 +000045#define CONFIG_MPC5200 1 /* More exactly a MPC5200 */
46#define CONFIG_TOP5200 1 /* ... on TOP5200 board - we need this for FEC.C */
47
wdenkd4ca31c2004-01-02 14:00:00 +000048#define CFG_MPC5XXX_CLKIN 33000000 /* ... running at 33.000000MHz */
wdenkc1896002003-12-28 11:44:59 +000049
50#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */
51#define BOOTFLAG_WARM 0x02 /* Software reboot */
52
53#define CFG_CACHELINE_SIZE 32 /* For MPC5xxx CPUs */
54#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
55# define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value */
56#endif
57
58/*
59 * Serial console configuration
60 */
61#define CONFIG_PSC_CONSOLE 1 /* console is on PSC1 */
62#define CONFIG_BAUDRATE 9600 /* ... at 9600 bps */
63#define CFG_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200, 230400 }
64
65
wdenk4d13cba2004-03-14 14:09:05 +000066#if defined (CONFIG_EVAL5200) || defined (CONFIG_LITE5200)
wdenkc1896002003-12-28 11:44:59 +000067/*
68 * PCI Mapping:
69 * 0x40000000 - 0x4fffffff - PCI Memory
70 * 0x50000000 - 0x50ffffff - PCI IO Space
71 */
72# define CONFIG_PCI 1
73# define CONFIG_PCI_PNP 1
74# define CONFIG_PCI_SCAN_SHOW 1
75
76# define CONFIG_PCI_MEM_BUS 0x40000000
77# define CONFIG_PCI_MEM_PHYS CONFIG_PCI_MEM_BUS
78# define CONFIG_PCI_MEM_SIZE 0x10000000
79
80# define CONFIG_PCI_IO_BUS 0x50000000
81# define CONFIG_PCI_IO_PHYS CONFIG_PCI_IO_BUS
82# define CONFIG_PCI_IO_SIZE 0x01000000
83
84# define ADD_PCI_CMD CFG_CMD_PCI
85
86#else /* no Evaluation board */
87
88# define ADD_PCI_CMD 0 /* no CFG_CMD_PCI */
89
90#endif
91
wdenk4d13cba2004-03-14 14:09:05 +000092/* USB */
93#if defined (CONFIG_EVAL5200) || defined (CONFIG_LITE5200)
94
95# define CONFIG_USB_OHCI
96# define CONFIG_USB_CLOCK 0x0001bbbb
wdenk498b8db2004-04-18 22:26:17 +000097# if defined (CONFIG_EVAL5200)
98# define CONFIG_USB_CONFIG 0x00005100
99# else
100# define CONFIG_USB_CONFIG 0x00001000
101# endif
wdenk4d13cba2004-03-14 14:09:05 +0000102# define ADD_USB_CMD CFG_CMD_USB | CFG_CMD_FAT
103# define CONFIG_DOS_PARTITION
104# define CONFIG_USB_STORAGE
105
106#else
107
108# define ADD_USB_CMD 0
109
110#endif
111
112/* IDE */
113#if defined (CONFIG_EVAL5200) || defined (CONFIG_LITE5200)
114
115# define ADD_IDE_CMD CFG_CMD_IDE | CFG_CMD_FAT
116# define CONFIG_DOS_PARTITION
117
118#else
119
120# define ADD_IDE_CMD 0
121
122#endif
123
wdenkc1896002003-12-28 11:44:59 +0000124/*
125 * Supported commands
126 */
wdenk1c437712004-01-16 00:30:56 +0000127#define CONFIG_COMMANDS ( CONFIG_CMD_DFL | \
128 ADD_PCI_CMD | \
wdenk4d13cba2004-03-14 14:09:05 +0000129 ADD_USB_CMD | \
wdenkb79a11c2004-03-25 15:14:43 +0000130 ADD_IDE_CMD | \
wdenk1c437712004-01-16 00:30:56 +0000131 CFG_CMD_ASKENV | \
132 CFG_CMD_DATE | \
133 CFG_CMD_DHCP | \
134 CFG_CMD_I2C | \
135 CFG_CMD_EEPROM | \
136 CFG_CMD_REGINFO | \
137 CFG_CMD_IMMAP | \
138 CFG_CMD_ELF | \
139 CFG_CMD_MII | \
140 CFG_CMD_BEDBUG \
141 )
wdenkc1896002003-12-28 11:44:59 +0000142
143/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
144#include <cmd_confdefs.h>
145
146/*
wdenk4d13cba2004-03-14 14:09:05 +0000147 * MUST be low boot - HIGHBOOT is not supported anymore
wdenkd4ca31c2004-01-02 14:00:00 +0000148 */
149#if (TEXT_BASE == 0xFF000000) /* Boot low with 16 MB Flash */
150# define CFG_LOWBOOT 1
151# define CFG_LOWBOOT16 1
wdenk4d13cba2004-03-14 14:09:05 +0000152#else
153# error "TEXT_BASE must be 0xff000000"
wdenkd4ca31c2004-01-02 14:00:00 +0000154#endif
155
156/*
wdenkc1896002003-12-28 11:44:59 +0000157 * Autobooting
158 */
159#define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */
wdenkd4ca31c2004-01-02 14:00:00 +0000160
161#define CONFIG_PREBOOT "echo;" \
162 "echo Type \"run flash_nfs\" to mount root filesystem over NFS;" \
163 "echo"
164
165#undef CONFIG_BOOTARGS
166
167#define CONFIG_EXTRA_ENV_SETTINGS \
168 "netdev=eth0\0" \
169 "nfsargs=setenv bootargs root=/dev/nfs rw " \
Wolfgang Denkfe126d82005-11-20 21:40:11 +0100170 "nfsroot=${serverip}:${rootpath}\0" \
wdenkd4ca31c2004-01-02 14:00:00 +0000171 "ramargs=setenv bootargs root=/dev/ram rw\0" \
Wolfgang Denkfe126d82005-11-20 21:40:11 +0100172 "addip=setenv bootargs ${bootargs} " \
173 "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}" \
174 ":${hostname}:${netdev}:off panic=1\0" \
wdenkd4ca31c2004-01-02 14:00:00 +0000175 "flash_nfs=run nfsargs addip;" \
Wolfgang Denkfe126d82005-11-20 21:40:11 +0100176 "bootm ${kernel_addr}\0" \
wdenkd4ca31c2004-01-02 14:00:00 +0000177 "flash_self=run ramargs addip;" \
Wolfgang Denkfe126d82005-11-20 21:40:11 +0100178 "bootm ${kernel_addr} ${ramdisk_addr}\0" \
179 "net_nfs=tftp 200000 ${bootfile};run nfsargs addip;bootm\0" \
wdenkd4ca31c2004-01-02 14:00:00 +0000180 "rootpath=/opt/eldk/ppc_82xx\0" \
181 "bootfile=/tftpboot/MPC5200/uImage\0" \
182 ""
183
184#define CONFIG_BOOTCOMMAND "run flash_self"
wdenkc1896002003-12-28 11:44:59 +0000185
186/*
187 * IPB Bus clocking configuration.
188 */
Bartlomiej Siekac99512d2007-05-27 16:53:43 +0200189#undef CFG_IPBCLK_EQUALS_XLBCLK /* define for 133MHz speed */
wdenkd4ca31c2004-01-02 14:00:00 +0000190
wdenkc1896002003-12-28 11:44:59 +0000191/*
192 * I2C configuration
193 */
194/*
195 * EEPROM configuration
196 */
197#define CFG_EEPROM_PAGE_WRITE_BITS 3
198#define CFG_EEPROM_PAGE_WRITE_DELAY_MS 70
199
200#define CFG_I2C_EEPROM_ADDR_LEN 2
201#define CFG_EEPROM_SIZE 0x2000
wdenkd4ca31c2004-01-02 14:00:00 +0000202
wdenkc1896002003-12-28 11:44:59 +0000203#define CONFIG_ENV_OVERWRITE
204#define CONFIG_MISC_INIT_R
wdenkd4ca31c2004-01-02 14:00:00 +0000205
wdenkc1896002003-12-28 11:44:59 +0000206#undef CONFIG_HARD_I2C /* I2C with hardware support */
wdenk4d13cba2004-03-14 14:09:05 +0000207#define CONFIG_SOFT_I2C 1 /* I2C with softwate support */
wdenkd4ca31c2004-01-02 14:00:00 +0000208
wdenkc1896002003-12-28 11:44:59 +0000209#if defined (CONFIG_SOFT_I2C)
210# define SDA0 0x40
211# define SCL0 0x80
wdenkd4ca31c2004-01-02 14:00:00 +0000212# define GPIOE0 *((volatile uchar*)(CFG_MBAR+0x0c00))
213# define DDR0 *((volatile uchar*)(CFG_MBAR+0x0c08))
214# define DVO0 *((volatile uchar*)(CFG_MBAR+0x0c0c))
215# define DVI0 *((volatile uchar*)(CFG_MBAR+0x0c20))
216# define ODE0 *((volatile uchar*)(CFG_MBAR+0x0c04))
wdenkc1896002003-12-28 11:44:59 +0000217# define I2C_INIT {GPIOE0|=(SDA0|SCL0);ODE0|=(SDA0|SCL0);DVO0|=(SDA0|SCL0);DDR0|=(SDA0|SCL0);}
218# define I2C_READ ((DVI0&SDA0)?1:0)
219# define I2C_SDA(x) {if(x)DVO0|=SDA0;else DVO0&=~SDA0;}
220# define I2C_SCL(x) {if(x)DVO0|=SCL0;else DVO0&=~SCL0;}
221# define I2C_DELAY {udelay(5);}
222# define I2C_ACTIVE {DDR0|=SDA0;}
223# define I2C_TRISTATE {DDR0&=~SDA0;}
224# define CFG_I2C_SPEED 100000
225# define CFG_I2C_SLAVE 0x7F
wdenk4d13cba2004-03-14 14:09:05 +0000226#define CFG_I2C_EEPROM_ADDR 0x57
227#define CFG_I2C_FACT_ADDR 0x57
wdenkc1896002003-12-28 11:44:59 +0000228#endif
wdenkd4ca31c2004-01-02 14:00:00 +0000229
230#if defined (CONFIG_HARD_I2C)
wdenkc1896002003-12-28 11:44:59 +0000231# define CFG_I2C_MODULE 2 /* Select I2C module #1 or #2 */
232# define CFG_I2C_SPEED 100000 /* 100 kHz */
233# define CFG_I2C_SLAVE 0x7F
wdenk4d13cba2004-03-14 14:09:05 +0000234#define CFG_I2C_EEPROM_ADDR 0x54
235#define CFG_I2C_FACT_ADDR 0x54
wdenkd4ca31c2004-01-02 14:00:00 +0000236#endif
wdenkc1896002003-12-28 11:44:59 +0000237
238/*
239 * Flash configuration, expect one 16 Megabyte Bank at most
240 */
241#define CFG_FLASH_BASE 0xff000000
242#define CFG_FLASH_SIZE 0x01000000
243#define CFG_MAX_FLASH_BANKS 1 /* max num of memory banks */
wdenkd4ca31c2004-01-02 14:00:00 +0000244#define CFG_ENV_ADDR (CFG_FLASH_BASE + 0)
wdenkc1896002003-12-28 11:44:59 +0000245
246#define CFG_MAX_FLASH_SECT 256 /* max num of sects on one chip */
247
248#define CFG_FLASH_ERASE_TOUT 240000 /* Flash Erase Timeout (in ms) */
249#define CFG_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (in ms) */
250
251#undef CONFIG_FLASH_16BIT /* Flash is 8-bit */
252
wdenkd4ca31c2004-01-02 14:00:00 +0000253/*
254 * DRAM configuration - will be read from VPD later... TODO!
255 */
256#if 0
257/* 2x MT48LC16M16A2 - 7.0 ns SDRAMS = 64 MegaBytes Total */
258#define CFG_DRAM_DDR 0
259#define CFG_DRAM_EMODE 0
260#define CFG_DRAM_MODE 0x008D
261#define CFG_DRAM_CONTROL 0x514F0000
262#define CFG_DRAM_CONFIG1 0xC2233A00
263#define CFG_DRAM_CONFIG2 0x88B70004
264#define CFG_DRAM_TAP_DEL 0x08
265#define CFG_DRAM_RAM_SIZE 0x19
266#endif
267#if 1
268/* 2x MT48LC16M16A2 - 7.5 ns SDRAMS = 64 MegaBytes Total */
269#define CFG_DRAM_DDR 0
270#define CFG_DRAM_EMODE 0
271#define CFG_DRAM_MODE 0x00CD
272#define CFG_DRAM_CONTROL 0x514F0000
273#define CFG_DRAM_CONFIG1 0xD2333A00
274#define CFG_DRAM_CONFIG2 0x8AD70004
275#define CFG_DRAM_TAP_DEL 0x08
276#define CFG_DRAM_RAM_SIZE 0x19
277#endif
278
wdenkc1896002003-12-28 11:44:59 +0000279/*
280 * Environment settings
281 */
282#define CFG_ENV_IS_IN_EEPROM 1 /* turn on EEPROM env feature */
283#define CFG_ENV_OFFSET 0x1000
284#define CFG_ENV_SIZE 0x0700
wdenkc1896002003-12-28 11:44:59 +0000285
wdenkd4ca31c2004-01-02 14:00:00 +0000286/*
287 * VPD settings
288 */
wdenkc1896002003-12-28 11:44:59 +0000289#define CFG_FACT_OFFSET 0x1800
290#define CFG_FACT_SIZE 0x0800
wdenkd4ca31c2004-01-02 14:00:00 +0000291
wdenkc1896002003-12-28 11:44:59 +0000292/*
wdenkd4ca31c2004-01-02 14:00:00 +0000293 * Memory map
294 *
295 * Warning!!! with the current BestComm Task, MBAR MUST BE set to 0xf0000000
wdenkc1896002003-12-28 11:44:59 +0000296 */
297#define CFG_MBAR 0xf0000000 /* DO NOT CHANGE this */
298#define CFG_SDRAM_BASE 0x00000000
299#define CFG_DEFAULT_MBAR 0x80000000
300
301/* Use SRAM until RAM will be available */
302#define CFG_INIT_RAM_ADDR MPC5XXX_SRAM
303#define CFG_INIT_RAM_END MPC5XXX_SRAM_SIZE /* End of used area in DPRAM */
304
305
306#define CFG_GBL_DATA_SIZE 128 /* size in bytes reserved for initial data */
307#define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
308#define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET
309
310#define CFG_MONITOR_BASE TEXT_BASE
311#if (CFG_MONITOR_BASE < CFG_FLASH_BASE)
312# define CFG_RAMBOOT 1
313#endif
314
315#define CFG_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */
316#define CFG_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc() */
317#define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
318
319/*
320 * Ethernet configuration
321 */
wdenkcbd8a352004-02-24 02:00:03 +0000322#define CONFIG_MPC5xxx_FEC 1
wdenkc1896002003-12-28 11:44:59 +0000323#define CONFIG_FEC_10MBIT 1 /* Workaround for FEC 100Mbit problem */
wdenkd4ca31c2004-01-02 14:00:00 +0000324#define CONFIG_PHY_ADDR 0x1f
wdenkc1896002003-12-28 11:44:59 +0000325#define CONFIG_PHY_TYPE 0x79c874
326/*
wdenkd4ca31c2004-01-02 14:00:00 +0000327 * GPIO configuration:
328 * PSC1,2,3 predefined as UART
329 * PCI disabled
wdenkc1896002003-12-28 11:44:59 +0000330 * Ethernet 100 with MD
331 */
wdenk498b8db2004-04-18 22:26:17 +0000332#define CFG_GPS_PORT_CONFIG 0x00058044
wdenkc1896002003-12-28 11:44:59 +0000333
334/*
335 * Miscellaneous configurable options
336 */
337#define CFG_LONGHELP /* undef to save memory */
338#define CFG_PROMPT "=> " /* Monitor Command Prompt */
339#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
340# define CFG_CBSIZE 1024 /* Console I/O Buffer Size */
341#else
342# define CFG_CBSIZE 256 /* Console I/O Buffer Size */
343#endif
344#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
345#define CFG_MAXARGS 16 /* max number of command args */
346#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */
347
348#define CFG_MEMTEST_START 0x00100000 /* memtest works on */
349#define CFG_MEMTEST_END 0x01f00000 /* 1 ... 31 MB in DRAM */
350
wdenk4d13cba2004-03-14 14:09:05 +0000351#define CFG_LOAD_ADDR 0x200000 /* default load address */
wdenkc1896002003-12-28 11:44:59 +0000352
353#define CFG_HZ 1000 /* decrementer freq: 1 ms ticks */
354
wdenk63e73c92004-02-23 22:22:28 +0000355#ifdef CONFIG_EVAL5200 /* M48T08 is available with the Evaluation board only */
356 #define CONFIG_RTC_MK48T59 1 /* use M48T08 on EVAL5200 */
357 #define RTC(reg) (0xf0010000+reg)
358 /* setup CS2 for M48T08. Must MAP 64kB */
359 #define CFG_CS2_START RTC(0)
360 #define CFG_CS2_SIZE 0x10000
361 /* setup CS2 configuration register: */
362 /* WaitP = 0, WaitX = 4, MX=0, AL=1, AA=1, CE=1 */
363 /* AS=2, DS=0, Bank=0, WTyp=0, WS=0, RS=0, WO=0, RO=0 */
364 #define CFG_CS2_CFG 0x00047800
365#else
366 #define CONFIG_RTC_MPC5200 1 /* use internal MPC5200 RTC */
367#endif
wdenk1c437712004-01-16 00:30:56 +0000368
wdenkc1896002003-12-28 11:44:59 +0000369/*
370 * Various low-level settings
371 */
372#define CFG_HID0_INIT HID0_ICE | HID0_ICFI
373#define CFG_HID0_FINAL HID0_ICE
374
375#define CFG_BOOTCS_START CFG_FLASH_BASE
376#define CFG_BOOTCS_SIZE CFG_FLASH_SIZE
377#define CFG_BOOTCS_CFG 0x00047801
378#define CFG_CS0_START CFG_FLASH_BASE
379#define CFG_CS0_SIZE CFG_FLASH_SIZE
380
381#define CFG_CS_BURST 0x00000000
382#define CFG_CS_DEADCYCLE 0x33333333
383
384#define CFG_RESET_ADDRESS 0x7f000000
385
wdenk4d13cba2004-03-14 14:09:05 +0000386/*-----------------------------------------------------------------------
387 * IDE/ATA stuff Supports IDE harddisk
388 *-----------------------------------------------------------------------
389 */
390
391#undef CONFIG_IDE_8xx_PCCARD /* Use IDE with PC Card Adapter */
392
393#undef CONFIG_IDE_8xx_DIRECT /* Direct IDE not supported */
394#undef CONFIG_IDE_LED /* LED for ide not supported */
395
396#define CONFIG_IDE_RESET 1
397#define CONFIG_IDE_PREINIT
398
399#define CFG_IDE_MAXBUS 1 /* max. 1 IDE bus */
400#define CFG_IDE_MAXDEVICE 1 /* max. 1 drive per IDE bus */
401
402#define CFG_ATA_IDE0_OFFSET 0x0000
403
404#define CFG_ATA_BASE_ADDR MPC5XXX_ATA
405
406/* Offset for data I/O */
407#define CFG_ATA_DATA_OFFSET (0x0060)
408
409/* Offset for normal register accesses */
410#define CFG_ATA_REG_OFFSET (CFG_ATA_DATA_OFFSET)
411
412/* Offset for alternate registers */
413#define CFG_ATA_ALT_OFFSET (0x005c)
414
415/* Interval between registers */
416#define CFG_ATA_STRIDE 4
417
wdenkc1896002003-12-28 11:44:59 +0000418#endif /* __CONFIG_H */