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wdenkc6097192002-11-03 00:24:07 +00001/*
2 * (C) Copyright 2001
3 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
4 *
5 * (C) Copyright 2002
6 * Gregory E. Allen, gallen@arlut.utexas.edu
7 * Matthew E. Karger, karger@arlut.utexas.edu
8 * Applied Research Laboratories, The University of Texas at Austin
9 *
10 * See file CREDITS for list of people who contributed to this
11 * project.
12 *
13 * This program is free software; you can redistribute it and/or
14 * modify it under the terms of the GNU General Public License as
15 * published by the Free Software Foundation; either version 2 of
16 * the License, or (at your option) any later version.
17 *
18 * This program is distributed in the hope that it will be useful,
19 * but WITHOUT ANY WARRANTY; without even the implied warranty of
20 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
21 * GNU General Public License for more details.
22 *
23 * You should have received a copy of the GNU General Public License
24 * along with this program; if not, write to the Free Software
25 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
26 * MA 02111-1307 USA
27 */
28
29/*
30 *
31 * Configuration settings for the utx8245 board.
32 *
33 */
34
35/* ------------------------------------------------------------------------- */
36
37/*
38 * board/config.h - configuration options, board specific
39 */
40
41#ifndef __CONFIG_H
42#define __CONFIG_H
43
44/*
45 * High Level Configuration Options
46 * (easy to change)
47 */
48
49#define CONFIG_MPC824X 1
50#define CONFIG_MPC8245 1
51#define CONFIG_UTX8245 1
52#define DEBUG 1
53
wdenk7a8e9bed2003-05-31 18:35:21 +000054#define CONFIG_IDENT_STRING " [UTX5] "
55
wdenkc6097192002-11-03 00:24:07 +000056#define CONFIG_CONS_INDEX 1
57#define CONFIG_BAUDRATE 57600
58#define CFG_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 }
59
wdenk7a8e9bed2003-05-31 18:35:21 +000060#define CONFIG_BOOTDELAY 2
wdenkc6097192002-11-03 00:24:07 +000061#define CONFIG_AUTOBOOT_PROMPT "autoboot in %d seconds\n"
wdenk7a8e9bed2003-05-31 18:35:21 +000062#define CONFIG_BOOTCOMMAND "run nfsboot" /* autoboot command */
wdenkc6097192002-11-03 00:24:07 +000063#define CONFIG_BOOTARGS "root=/dev/ram console=ttyS0,57600" /* RAMdisk */
wdenk7a8e9bed2003-05-31 18:35:21 +000064#define CONFIG_ETHADDR 00:AA:00:14:00:05 /* UTX5 */
65#define CONFIG_SERVERIP 10.8.17.105 /* Spree */
66#define CFG_TFTP_LOADADDR 10000
67
68#define CONFIG_EXTRA_ENV_SETTINGS \
69 "kernel_addr=FFA00000\0" \
70 "ramdisk_addr=FF800000\0" \
71 "u-boot_startaddr=FFB00000\0" \
72 "u-boot_endaddr=FFB2FFFF\0" \
Wolfgang Denkfe126d82005-11-20 21:40:11 +010073 "nfsargs=setenv bootargs console=ttyS0,${baudrate} root=/dev/nfs rw \
74nfsroot=${nfsrootip}:${rootpath} ip=dhcp\0" \
75 "ramargs=setenv bootargs console=ttyS0,${baudrate} root=/dev/ram0\0" \
76 "smargs=setenv bootargs console=ttyS0,${baudrate} root=/dev/mtdblock1 ro\0" \
77 "fwargs=setenv bootargs console=ttyS0,${baudrate} root=/dev/sda2 ro\0" \
78 "nfsboot=run nfsargs;bootm ${kernel_addr}\0" \
79 "ramboot=run ramargs;bootm ${kernel_addr} ${ramdisk_addr}\0" \
80 "smboot=run smargs;bootm ${kernel_addr} ${ramdisk_addr}\0" \
81 "fwboot=run fwargs;bootm ${kernel_addr} ${ramdisk_addr}\0" \
82 "update_u-boot=tftp ${loadaddr} /bdi2000/u-boot.bin;protect off \
83${u-boot_startaddr} ${u-boot_endaddr};era ${u-boot_startaddr} \
84${u-boot_endaddr};cp.b ${loadaddr} ${u-boot_startaddr} ${filesize};\
85protect on ${u-boot_startaddr} ${u-boot_endaddr}"
wdenk7a8e9bed2003-05-31 18:35:21 +000086
wdenkc6097192002-11-03 00:24:07 +000087#define CONFIG_ENV_OVERWRITE
88
89#define CONFIG_COMMANDS (CFG_CMD_DFL | CFG_CMD_BDI | CFG_CMD_PCI \
90 | CFG_CMD_FLASH | CFG_CMD_MEMORY \
91 | CFG_CMD_ENV | CFG_CMD_CONSOLE \
92 | CFG_CMD_LOADS | CFG_CMD_LOADB \
93 | CFG_CMD_IMI | CFG_CMD_CACHE \
wdenkc6097192002-11-03 00:24:07 +000094 | CFG_CMD_REGINFO | CFG_CMD_NET\
wdenk7a8e9bed2003-05-31 18:35:21 +000095 | CFG_CMD_DHCP | CFG_CMD_I2C \
96 | CFG_CMD_DATE)
wdenkc6097192002-11-03 00:24:07 +000097
98/* This must be included AFTER the definition of CONFIG_COMMANDS (if any)
99 */
100#include <cmd_confdefs.h>
101
102
103/*
104 * Miscellaneous configurable options
105 */
wdenk7a8e9bed2003-05-31 18:35:21 +0000106#define CFG_LONGHELP /* undef to save memory */
107#define CFG_PROMPT "=> " /* Monitor Command Prompt */
108#define CFG_CBSIZE 256 /* Console I/O Buffer Size */
wdenkc6097192002-11-03 00:24:07 +0000109
110/* Print Buffer Size */
111#define CFG_PBSIZE (CFG_CBSIZE + sizeof(CFG_PROMPT) + 16)
112
113#define CFG_MAXARGS 16 /* max number of command args */
114#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */
115#define CFG_LOAD_ADDR 0x00100000 /* Default load address */
116
117
118/*-----------------------------------------------------------------------
119 * PCI configuration
120 *-----------------------------------------------------------------------
121 */
122#define CONFIG_PCI /* include pci support */
123#undef CONFIG_PCI_PNP
124#define CONFIG_PCI_SCAN_SHOW
125#define CONFIG_NET_MULTI
126#define CONFIG_EEPRO100
stroese53cf9432003-06-05 15:39:44 +0000127#define CFG_RX_ETH_BUFFER 8 /* use 8 rx buffer on eepro100 */
wdenk7a8e9bed2003-05-31 18:35:21 +0000128#define CONFIG_EEPRO100_SROM_WRITE
wdenkc6097192002-11-03 00:24:07 +0000129
wdenk7a8e9bed2003-05-31 18:35:21 +0000130#define PCI_ENET0_IOADDR 0xF0000000
131#define PCI_ENET0_MEMADDR 0xF0000000
132
133#define PCI_FIREWIRE_IOADDR 0xF1000000
134#define PCI_FIREWIRE_MEMADDR 0xF1000000
135/*
136#define PCI_ENET0_IOADDR 0xFE000000
wdenkc6097192002-11-03 00:24:07 +0000137#define PCI_ENET0_MEMADDR 0x80000000
wdenk7a8e9bed2003-05-31 18:35:21 +0000138
wdenkc6097192002-11-03 00:24:07 +0000139#define PCI_FIREWIRE_IOADDR 0x81000000
140#define PCI_FIREWIRE_MEMADDR 0x81000000
wdenk7a8e9bed2003-05-31 18:35:21 +0000141*/
wdenkc6097192002-11-03 00:24:07 +0000142
143/*-----------------------------------------------------------------------
144 * Start addresses for the final memory configuration
145 * (Set up by the startup code)
146 * Please note that CFG_SDRAM_BASE _must_ start at 0
147 */
148#define CFG_SDRAM_BASE 0x00000000
wdenk7a8e9bed2003-05-31 18:35:21 +0000149#define CFG_MAX_RAM_SIZE 0x10000000 /* 256MB */
150/*#define CFG_VERY_BIG_RAM 1 */
wdenkc6097192002-11-03 00:24:07 +0000151
wdenk7a8e9bed2003-05-31 18:35:21 +0000152/* FLASH_BASE is FF800000, with 4MB on RCS0, but the reset vector
153 * is actually located at FFF00100. Therefore, U-Boot is
154 * physically located at 0xFFB0_0000, but is also mirrored at
155 * 0xFFF0_0000.
wdenkc6097192002-11-03 00:24:07 +0000156 */
157#define CFG_RESET_ADDRESS 0xFFF00100
158
159#define CFG_EUMB_ADDR 0xFC000000
160
161#define CFG_MONITOR_BASE TEXT_BASE
162
163#define CFG_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */
164#define CFG_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc() */
165
166/*#define CFG_DRAM_TEST 1 */
167#define CFG_MEMTEST_START 0x00003000 /* memtest works on 0...256 MB */
wdenk7a8e9bed2003-05-31 18:35:21 +0000168#define CFG_MEMTEST_END 0x0ff8ffa7 /* in SDRAM, skips exception */
wdenkc6097192002-11-03 00:24:07 +0000169 /* vectors and U-Boot */
170
171
172/*--------------------------------------------------------------------
173 * Definitions for initial stack pointer and data area
174 *------------------------------------------------------------------*/
wdenk7a8e9bed2003-05-31 18:35:21 +0000175#define CFG_INIT_DATA_SIZE 128 /* Size in bytes reserved for */
wdenkc6097192002-11-03 00:24:07 +0000176 /* initial data */
177#define CFG_INIT_RAM_ADDR 0x40000000
178#define CFG_INIT_RAM_END 0x1000
wdenk7a8e9bed2003-05-31 18:35:21 +0000179#define CFG_INIT_DATA_OFFSET (CFG_INIT_RAM_END - CFG_INIT_DATA_SIZE)
180#define CFG_GBL_DATA_SIZE 128
wdenkc6097192002-11-03 00:24:07 +0000181#define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
182
183/*--------------------------------------------------------------------
184 * NS16550 Configuration
185 *------------------------------------------------------------------*/
186#define CFG_NS16550
187#define CFG_NS16550_SERIAL
188
189#define CFG_NS16550_REG_SIZE 1
190
wdenk7a8e9bed2003-05-31 18:35:21 +0000191#if (CONFIG_CONS_INDEX == 1 || CONFIG_CONS_INDEX == 2)
192# define CFG_NS16550_CLK get_bus_freq(0)
193#else
194# define CFG_NS16550_CLK 33000000
195#endif
wdenkc6097192002-11-03 00:24:07 +0000196
197#define CFG_NS16550_COM1 (CFG_EUMB_ADDR + 0x4500)
198#define CFG_NS16550_COM2 (CFG_EUMB_ADDR + 0x4600)
wdenk7a8e9bed2003-05-31 18:35:21 +0000199#define CFG_NS16550_COM3 0xFF000000
200#define CFG_NS16550_COM4 0xFF000008
wdenkc6097192002-11-03 00:24:07 +0000201
202/*--------------------------------------------------------------------
203 * Low Level Configuration Settings
204 * (address mappings, register initial values, etc.)
205 * You should know what you are doing if you make changes here.
206 * For the detail description refer to the MPC8240 user's manual.
207 *------------------------------------------------------------------*/
208
209#define CONFIG_SYS_CLK_FREQ 33000000
210#define CFG_HZ 1000
211
wdenk7a8e9bed2003-05-31 18:35:21 +0000212/*#define CFG_ETH_DEV_FN 0x7800 */
213/*#define CFG_ETH_IOBASE 0x00104000 */
wdenkc6097192002-11-03 00:24:07 +0000214
wdenk7a8e9bed2003-05-31 18:35:21 +0000215/*--------------------------------------------------------------------
216 * I2C Configuration
217 *------------------------------------------------------------------*/
218#if 1
219#define CONFIG_HARD_I2C 1 /* To enable I2C support */
220#undef CONFIG_SOFT_I2C /* I2C bit-banged */
221#define CFG_I2C_SPEED 400000 /* I2C speed and slave address */
222#define CFG_I2C_SLAVE 0x7F
223#endif
224
225#define CONFIG_RTC_PCF8563 1 /* enable I2C support for */
226 /* Philips PCF8563 RTC */
227#define CFG_I2C_RTC_ADDR 0x51 /* Philips PCF8563 RTC address */
wdenkc6097192002-11-03 00:24:07 +0000228
229/*--------------------------------------------------------------------
230 * Memory Control Configuration Register values
231 * - see sec. 4.12 of MPC8245 UM
232 *------------------------------------------------------------------*/
233
wdenk7a8e9bed2003-05-31 18:35:21 +0000234/**** MCCR1 ****/
wdenkc6097192002-11-03 00:24:07 +0000235#define CFG_ROMNAL 0
wdenk7a8e9bed2003-05-31 18:35:21 +0000236#define CFG_ROMFAL 10 /* (tacc=70ns)*mem_freq - 2,
237 mem_freq = 100MHz */
wdenkc6097192002-11-03 00:24:07 +0000238
wdenk7a8e9bed2003-05-31 18:35:21 +0000239#define CFG_BANK7_ROW 0 /* SDRAM bank 7-0 row address */
240#define CFG_BANK6_ROW 0 /* bit count */
241#define CFG_BANK5_ROW 0
242#define CFG_BANK4_ROW 0
243#define CFG_BANK3_ROW 0
244#define CFG_BANK2_ROW 0
245#define CFG_BANK1_ROW 2
246#define CFG_BANK0_ROW 2
247
248/**** MCCR2, refresh interval clock cycles ****/
wdenkc6097192002-11-03 00:24:07 +0000249#define CFG_REFINT 480 /* 33 MHz SDRAM clock was 480 */
250
wdenk7a8e9bed2003-05-31 18:35:21 +0000251/* Burst To Precharge. Bits of this value go to MCCR3 and MCCR4. */
wdenkc6097192002-11-03 00:24:07 +0000252#define CFG_BSTOPRE 1023 /* burst to precharge[0..9], */
253 /* sets open page interval */
254
wdenk7a8e9bed2003-05-31 18:35:21 +0000255/**** MCCR3 ****/
256#define CFG_REFREC 7 /* Refresh to activate interval, trc */
wdenkc6097192002-11-03 00:24:07 +0000257
wdenk7a8e9bed2003-05-31 18:35:21 +0000258/**** MCCR4 ****/
wdenkc6097192002-11-03 00:24:07 +0000259#define CFG_PRETOACT 2 /* trp */
wdenk7a8e9bed2003-05-31 18:35:21 +0000260#define CFG_ACTTOPRE 7 /* trcd + (burst length - 1) + trdl */
wdenkc6097192002-11-03 00:24:07 +0000261#define CFG_SDMODE_CAS_LAT 3 /* SDMODE CAS latancy */
262#define CFG_SDMODE_WRAP 0 /* SDMODE wrap type, sequential */
263#define CFG_ACTORW 2 /* trcd min */
264#define CFG_DBUS_SIZE2 1 /* set for 8-bit RCS1, clear for 32,64 */
265#define CFG_REGISTERD_TYPE_BUFFER 1
wdenk7a8e9bed2003-05-31 18:35:21 +0000266#define CFG_EXTROM 0 /* we don't need extended ROM space */
wdenkc6097192002-11-03 00:24:07 +0000267#define CFG_REGDIMM 0
268
269/* calculate according to formula in sec. 6-22 of 8245 UM */
270#define CFG_PGMAX 50 /* how long the 8245 retains the */
271 /* currently accessed page in memory */
272 /* was 45 */
273
274#define CFG_SDRAM_DSCD 0x20 /* SDRAM data in sample clock delay - note */
wdenk7a8e9bed2003-05-31 18:35:21 +0000275 /* bits 7,6, and 3-0 MUST be 0 */
wdenkc6097192002-11-03 00:24:07 +0000276
wdenk7a8e9bed2003-05-31 18:35:21 +0000277#if 0
wdenkc6097192002-11-03 00:24:07 +0000278#define CFG_DLL_MAX_DELAY 0x04
wdenk7a8e9bed2003-05-31 18:35:21 +0000279#else
280#define CFG_DLL_MAX_DELAY 0
281#endif
282#if 0 /* need for 33MHz SDRAM */
wdenkc6097192002-11-03 00:24:07 +0000283#define CFG_DLL_EXTEND 0x80
wdenk7a8e9bed2003-05-31 18:35:21 +0000284#else
285#define CFG_DLL_EXTEND 0
286#endif
wdenkc6097192002-11-03 00:24:07 +0000287#define CFG_PCI_HOLD_DEL 0x20
288
289
290/* Memory bank settings.
291 * Only bits 20-29 are actually used from these values to set the
292 * start/end addresses. The upper two bits will always be 0, and the lower
293 * 20 bits will be 0x00000 for a start address, or 0xfffff for an end
294 * address. Refer to the MPC8245 user manual.
295 */
296
297#define CFG_BANK0_START 0x00000000
298#define CFG_BANK0_END (CFG_MAX_RAM_SIZE/2 - 1)
299#define CFG_BANK0_ENABLE 1
300#define CFG_BANK1_START CFG_MAX_RAM_SIZE/2
301#define CFG_BANK1_END (CFG_MAX_RAM_SIZE - 1)
302#define CFG_BANK1_ENABLE 1
303#define CFG_BANK2_START 0x3ff00000 /* not available in this design */
304#define CFG_BANK2_END 0x3fffffff
305#define CFG_BANK2_ENABLE 0
306#define CFG_BANK3_START 0x3ff00000
307#define CFG_BANK3_END 0x3fffffff
308#define CFG_BANK3_ENABLE 0
309#define CFG_BANK4_START 0x3ff00000
310#define CFG_BANK4_END 0x3fffffff
311#define CFG_BANK4_ENABLE 0
312#define CFG_BANK5_START 0x3ff00000
313#define CFG_BANK5_END 0x3fffffff
314#define CFG_BANK5_ENABLE 0
315#define CFG_BANK6_START 0x3ff00000
316#define CFG_BANK6_END 0x3fffffff
317#define CFG_BANK6_ENABLE 0
318#define CFG_BANK7_START 0x3ff00000
319#define CFG_BANK7_END 0x3fffffff
320#define CFG_BANK7_ENABLE 0
321
wdenk7a8e9bed2003-05-31 18:35:21 +0000322/*--------------------------------------------------------------------*/
323/* 4.4 - Output Driver Control Register */
324/*--------------------------------------------------------------------*/
wdenkc6097192002-11-03 00:24:07 +0000325#define CFG_ODCR 0xe5
326
wdenk7a8e9bed2003-05-31 18:35:21 +0000327/*--------------------------------------------------------------------*/
328/* 4.8 - Error Handling Registers */
329/*-------------------------------CFG_SDMODE_BURSTLEN-------------------------------------*/
wdenkc6097192002-11-03 00:24:07 +0000330#define CFG_ERRENR1 0x11 /* enable SDRAM refresh overflow error */
331
332/* SDRAM 0-256 MB */
333#define CFG_IBAT0L (CFG_SDRAM_BASE | BATL_PP_10 | BATL_MEMCOHERENCE)
wdenk7a8e9bed2003-05-31 18:35:21 +0000334/*#define CFG_IBAT0L (CFG_SDRAM_BASE | BATL_PP_10 | BATL_CACHEINHIBIT) */
wdenkc6097192002-11-03 00:24:07 +0000335#define CFG_IBAT0U (CFG_SDRAM_BASE | BATU_BL_256M | BATU_VS | BATU_VP)
336
337/* stack in dcache */
338#define CFG_IBAT1L (CFG_INIT_RAM_ADDR | BATL_PP_10 | BATL_MEMCOHERENCE)
339#define CFG_IBAT1U (CFG_INIT_RAM_ADDR | BATU_BL_128K | BATU_VS | BATU_VP)
340
wdenkc6097192002-11-03 00:24:07 +0000341
wdenk7a8e9bed2003-05-31 18:35:21 +0000342#define CFG_IBAT2L (CFG_SDRAM_BASE + 0x10000000 | BATL_PP_10 | BATL_MEMCOHERENCE)
343#define CFG_IBAT2U (CFG_SDRAM_BASE + 0x10000000| BATU_BL_256M | BATU_VS | BATU_VP)
344
345/* PCI memory */
346/*#define CFG_IBAT2L (0x80000000 | BATL_PP_10 | BATL_CACHEINHIBIT) */
347/*#define CFG_IBAT2U (0x80000000 | BATU_BL_256M | BATU_VS | BATU_VP) */
348
349/*Flash, config addrs, etc. */
wdenkc6097192002-11-03 00:24:07 +0000350#define CFG_IBAT3L (0xF0000000 | BATL_PP_10 | BATL_CACHEINHIBIT)
351#define CFG_IBAT3U (0xF0000000 | BATU_BL_256M | BATU_VS | BATU_VP)
352
353#define CFG_DBAT0L CFG_IBAT0L
354#define CFG_DBAT0U CFG_IBAT0U
355#define CFG_DBAT1L CFG_IBAT1L
356#define CFG_DBAT1U CFG_IBAT1U
357#define CFG_DBAT2L CFG_IBAT2L
358#define CFG_DBAT2U CFG_IBAT2U
359#define CFG_DBAT3L CFG_IBAT3L
360#define CFG_DBAT3U CFG_IBAT3U
361
362/*
363 * For booting Linux, the board info and command line data
364 * have to be in the first 8 MB of memory, since this is
365 * the maximum mapped by the Linux kernel during initialization.
366 */
367#define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
368
369/*-----------------------------------------------------------------------
wdenk7a8e9bed2003-05-31 18:35:21 +0000370 * FLASH organization
371 *----------------------------------------------------------------------*/
wdenkc6097192002-11-03 00:24:07 +0000372#define CFG_FLASH_BASE 0xFF800000
wdenk7a8e9bed2003-05-31 18:35:21 +0000373#define CFG_MAX_FLASH_BANKS 1 /* Max number of flash banks */
wdenkc6097192002-11-03 00:24:07 +0000374
wdenk7a8e9bed2003-05-31 18:35:21 +0000375/* NOTE: environment is not EMBEDDED in the u-boot code.
376 It's stored in flash in its own separate sector. */
377#define CFG_ENV_IS_IN_FLASH 1
378
379#if 1 /* AMD AM29LV033C */
380#define CFG_MAX_FLASH_SECT 64 /* Max number of sectors in one bank */
381#define CFG_ENV_ADDR 0xFFBF0000 /* flash sector SA63 */
382#define CFG_ENV_SECT_SIZE (64*1024) /* Size of the Environment Sector */
383#else /* AMD AM29LV116D */
wdenkc6097192002-11-03 00:24:07 +0000384#define CFG_MAX_FLASH_SECT 35 /* Max number of sectors in one bank */
wdenk7a8e9bed2003-05-31 18:35:21 +0000385#define CFG_ENV_ADDR 0xFF9FA000 /* flash sector SA33 */
386#define CFG_ENV_SECT_SIZE (8*1024) /* Size of the Environment Sector */
387#endif /* #if */
388
389#define CFG_ENV_SIZE CFG_ENV_SECT_SIZE /* Size of the Environment */
390#define CFG_ENV_OFFSET 0 /* starting right at the beginning */
wdenkc6097192002-11-03 00:24:07 +0000391
392#define CFG_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */
393#define CFG_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */
394
wdenkc6097192002-11-03 00:24:07 +0000395#if CFG_MONITOR_BASE >= CFG_FLASH_BASE
396#undef CFG_RAMBOOT
397#else
398#define CFG_RAMBOOT
399#endif
400
401
402/*-----------------------------------------------------------------------
403 * Cache Configuration
404 */
405#define CFG_CACHELINE_SIZE 32
406#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
407# define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value */
408#endif
409
410/*
411 * Internal Definitions
412 *
413 * Boot Flags
414 */
415#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */
416#define BOOTFLAG_WARM 0x02 /* Software reboot */
417
418
419#endif /* __CONFIG_H */