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Sricharanbb772a52011-11-15 09:50:00 -05001/*
2 * OMAP44xx EMIF header
3 *
4 * Copyright (C) 2009-2010 Texas Instruments, Inc.
5 *
6 * Aneesh V <aneesh@ti.com>
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as
10 * published by the Free Software Foundation.
11 */
12
13#ifndef _EMIF_H_
14#define _EMIF_H_
15#include <asm/types.h>
16#include <common.h>
Lokesh Vutlad3daba12013-12-10 15:02:22 +053017#include <asm/io.h>
Sricharanbb772a52011-11-15 09:50:00 -050018
19/* Base address */
20#define EMIF1_BASE 0x4c000000
21#define EMIF2_BASE 0x4d000000
22
Lokesh Vutlad3daba12013-12-10 15:02:22 +053023#define EMIF_4D 0x4
24#define EMIF_4D5 0x5
25
Tom Rinifda35eb2012-07-03 08:51:34 -070026/* Registers shifts, masks and values */
Sricharanbb772a52011-11-15 09:50:00 -050027
28/* EMIF_MOD_ID_REV */
29#define EMIF_REG_SCHEME_SHIFT 30
30#define EMIF_REG_SCHEME_MASK (0x3 << 30)
31#define EMIF_REG_MODULE_ID_SHIFT 16
32#define EMIF_REG_MODULE_ID_MASK (0xfff << 16)
33#define EMIF_REG_RTL_VERSION_SHIFT 11
34#define EMIF_REG_RTL_VERSION_MASK (0x1f << 11)
35#define EMIF_REG_MAJOR_REVISION_SHIFT 8
36#define EMIF_REG_MAJOR_REVISION_MASK (0x7 << 8)
37#define EMIF_REG_MINOR_REVISION_SHIFT 0
38#define EMIF_REG_MINOR_REVISION_MASK (0x3f << 0)
39
40/* STATUS */
41#define EMIF_REG_BE_SHIFT 31
42#define EMIF_REG_BE_MASK (1 << 31)
43#define EMIF_REG_DUAL_CLK_MODE_SHIFT 30
44#define EMIF_REG_DUAL_CLK_MODE_MASK (1 << 30)
45#define EMIF_REG_FAST_INIT_SHIFT 29
46#define EMIF_REG_FAST_INIT_MASK (1 << 29)
47#define EMIF_REG_PHY_DLL_READY_SHIFT 2
48#define EMIF_REG_PHY_DLL_READY_MASK (1 << 2)
49
50/* SDRAM_CONFIG */
51#define EMIF_REG_SDRAM_TYPE_SHIFT 29
52#define EMIF_REG_SDRAM_TYPE_MASK (0x7 << 29)
Tom Rinifda35eb2012-07-03 08:51:34 -070053#define EMIF_REG_SDRAM_TYPE_DDR1 0
54#define EMIF_REG_SDRAM_TYPE_LPDDR1 1
55#define EMIF_REG_SDRAM_TYPE_DDR2 2
56#define EMIF_REG_SDRAM_TYPE_DDR3 3
57#define EMIF_REG_SDRAM_TYPE_LPDDR2_S4 4
58#define EMIF_REG_SDRAM_TYPE_LPDDR2_S2 5
Sricharanbb772a52011-11-15 09:50:00 -050059#define EMIF_REG_IBANK_POS_SHIFT 27
60#define EMIF_REG_IBANK_POS_MASK (0x3 << 27)
61#define EMIF_REG_DDR_TERM_SHIFT 24
62#define EMIF_REG_DDR_TERM_MASK (0x7 << 24)
63#define EMIF_REG_DDR2_DDQS_SHIFT 23
64#define EMIF_REG_DDR2_DDQS_MASK (1 << 23)
65#define EMIF_REG_DYN_ODT_SHIFT 21
66#define EMIF_REG_DYN_ODT_MASK (0x3 << 21)
67#define EMIF_REG_DDR_DISABLE_DLL_SHIFT 20
68#define EMIF_REG_DDR_DISABLE_DLL_MASK (1 << 20)
69#define EMIF_REG_SDRAM_DRIVE_SHIFT 18
70#define EMIF_REG_SDRAM_DRIVE_MASK (0x3 << 18)
71#define EMIF_REG_CWL_SHIFT 16
72#define EMIF_REG_CWL_MASK (0x3 << 16)
73#define EMIF_REG_NARROW_MODE_SHIFT 14
74#define EMIF_REG_NARROW_MODE_MASK (0x3 << 14)
75#define EMIF_REG_CL_SHIFT 10
76#define EMIF_REG_CL_MASK (0xf << 10)
77#define EMIF_REG_ROWSIZE_SHIFT 7
78#define EMIF_REG_ROWSIZE_MASK (0x7 << 7)
79#define EMIF_REG_IBANK_SHIFT 4
80#define EMIF_REG_IBANK_MASK (0x7 << 4)
81#define EMIF_REG_EBANK_SHIFT 3
82#define EMIF_REG_EBANK_MASK (1 << 3)
83#define EMIF_REG_PAGESIZE_SHIFT 0
84#define EMIF_REG_PAGESIZE_MASK (0x7 << 0)
85
86/* SDRAM_CONFIG_2 */
87#define EMIF_REG_CS1NVMEN_SHIFT 30
88#define EMIF_REG_CS1NVMEN_MASK (1 << 30)
89#define EMIF_REG_EBANK_POS_SHIFT 27
90#define EMIF_REG_EBANK_POS_MASK (1 << 27)
91#define EMIF_REG_RDBNUM_SHIFT 4
92#define EMIF_REG_RDBNUM_MASK (0x3 << 4)
93#define EMIF_REG_RDBSIZE_SHIFT 0
94#define EMIF_REG_RDBSIZE_MASK (0x7 << 0)
95
96/* SDRAM_REF_CTRL */
97#define EMIF_REG_INITREF_DIS_SHIFT 31
98#define EMIF_REG_INITREF_DIS_MASK (1 << 31)
99#define EMIF_REG_SRT_SHIFT 29
100#define EMIF_REG_SRT_MASK (1 << 29)
101#define EMIF_REG_ASR_SHIFT 28
102#define EMIF_REG_ASR_MASK (1 << 28)
103#define EMIF_REG_PASR_SHIFT 24
104#define EMIF_REG_PASR_MASK (0x7 << 24)
105#define EMIF_REG_REFRESH_RATE_SHIFT 0
106#define EMIF_REG_REFRESH_RATE_MASK (0xffff << 0)
107
108/* SDRAM_REF_CTRL_SHDW */
109#define EMIF_REG_REFRESH_RATE_SHDW_SHIFT 0
110#define EMIF_REG_REFRESH_RATE_SHDW_MASK (0xffff << 0)
111
112/* SDRAM_TIM_1 */
113#define EMIF_REG_T_RP_SHIFT 25
114#define EMIF_REG_T_RP_MASK (0xf << 25)
115#define EMIF_REG_T_RCD_SHIFT 21
116#define EMIF_REG_T_RCD_MASK (0xf << 21)
117#define EMIF_REG_T_WR_SHIFT 17
118#define EMIF_REG_T_WR_MASK (0xf << 17)
119#define EMIF_REG_T_RAS_SHIFT 12
120#define EMIF_REG_T_RAS_MASK (0x1f << 12)
121#define EMIF_REG_T_RC_SHIFT 6
122#define EMIF_REG_T_RC_MASK (0x3f << 6)
123#define EMIF_REG_T_RRD_SHIFT 3
124#define EMIF_REG_T_RRD_MASK (0x7 << 3)
125#define EMIF_REG_T_WTR_SHIFT 0
126#define EMIF_REG_T_WTR_MASK (0x7 << 0)
127
128/* SDRAM_TIM_1_SHDW */
129#define EMIF_REG_T_RP_SHDW_SHIFT 25
130#define EMIF_REG_T_RP_SHDW_MASK (0xf << 25)
131#define EMIF_REG_T_RCD_SHDW_SHIFT 21
132#define EMIF_REG_T_RCD_SHDW_MASK (0xf << 21)
133#define EMIF_REG_T_WR_SHDW_SHIFT 17
134#define EMIF_REG_T_WR_SHDW_MASK (0xf << 17)
135#define EMIF_REG_T_RAS_SHDW_SHIFT 12
136#define EMIF_REG_T_RAS_SHDW_MASK (0x1f << 12)
137#define EMIF_REG_T_RC_SHDW_SHIFT 6
138#define EMIF_REG_T_RC_SHDW_MASK (0x3f << 6)
139#define EMIF_REG_T_RRD_SHDW_SHIFT 3
140#define EMIF_REG_T_RRD_SHDW_MASK (0x7 << 3)
141#define EMIF_REG_T_WTR_SHDW_SHIFT 0
142#define EMIF_REG_T_WTR_SHDW_MASK (0x7 << 0)
143
144/* SDRAM_TIM_2 */
145#define EMIF_REG_T_XP_SHIFT 28
146#define EMIF_REG_T_XP_MASK (0x7 << 28)
147#define EMIF_REG_T_ODT_SHIFT 25
148#define EMIF_REG_T_ODT_MASK (0x7 << 25)
149#define EMIF_REG_T_XSNR_SHIFT 16
150#define EMIF_REG_T_XSNR_MASK (0x1ff << 16)
151#define EMIF_REG_T_XSRD_SHIFT 6
152#define EMIF_REG_T_XSRD_MASK (0x3ff << 6)
153#define EMIF_REG_T_RTP_SHIFT 3
154#define EMIF_REG_T_RTP_MASK (0x7 << 3)
155#define EMIF_REG_T_CKE_SHIFT 0
156#define EMIF_REG_T_CKE_MASK (0x7 << 0)
157
158/* SDRAM_TIM_2_SHDW */
159#define EMIF_REG_T_XP_SHDW_SHIFT 28
160#define EMIF_REG_T_XP_SHDW_MASK (0x7 << 28)
161#define EMIF_REG_T_ODT_SHDW_SHIFT 25
162#define EMIF_REG_T_ODT_SHDW_MASK (0x7 << 25)
163#define EMIF_REG_T_XSNR_SHDW_SHIFT 16
164#define EMIF_REG_T_XSNR_SHDW_MASK (0x1ff << 16)
165#define EMIF_REG_T_XSRD_SHDW_SHIFT 6
166#define EMIF_REG_T_XSRD_SHDW_MASK (0x3ff << 6)
167#define EMIF_REG_T_RTP_SHDW_SHIFT 3
168#define EMIF_REG_T_RTP_SHDW_MASK (0x7 << 3)
169#define EMIF_REG_T_CKE_SHDW_SHIFT 0
170#define EMIF_REG_T_CKE_SHDW_MASK (0x7 << 0)
171
172/* SDRAM_TIM_3 */
173#define EMIF_REG_T_CKESR_SHIFT 21
174#define EMIF_REG_T_CKESR_MASK (0x7 << 21)
175#define EMIF_REG_ZQ_ZQCS_SHIFT 15
176#define EMIF_REG_ZQ_ZQCS_MASK (0x3f << 15)
177#define EMIF_REG_T_TDQSCKMAX_SHIFT 13
178#define EMIF_REG_T_TDQSCKMAX_MASK (0x3 << 13)
179#define EMIF_REG_T_RFC_SHIFT 4
180#define EMIF_REG_T_RFC_MASK (0x1ff << 4)
181#define EMIF_REG_T_RAS_MAX_SHIFT 0
182#define EMIF_REG_T_RAS_MAX_MASK (0xf << 0)
183
184/* SDRAM_TIM_3_SHDW */
185#define EMIF_REG_T_CKESR_SHDW_SHIFT 21
186#define EMIF_REG_T_CKESR_SHDW_MASK (0x7 << 21)
187#define EMIF_REG_ZQ_ZQCS_SHDW_SHIFT 15
188#define EMIF_REG_ZQ_ZQCS_SHDW_MASK (0x3f << 15)
189#define EMIF_REG_T_TDQSCKMAX_SHDW_SHIFT 13
190#define EMIF_REG_T_TDQSCKMAX_SHDW_MASK (0x3 << 13)
191#define EMIF_REG_T_RFC_SHDW_SHIFT 4
192#define EMIF_REG_T_RFC_SHDW_MASK (0x1ff << 4)
193#define EMIF_REG_T_RAS_MAX_SHDW_SHIFT 0
194#define EMIF_REG_T_RAS_MAX_SHDW_MASK (0xf << 0)
195
196/* LPDDR2_NVM_TIM */
197#define EMIF_REG_NVM_T_XP_SHIFT 28
198#define EMIF_REG_NVM_T_XP_MASK (0x7 << 28)
199#define EMIF_REG_NVM_T_WTR_SHIFT 24
200#define EMIF_REG_NVM_T_WTR_MASK (0x7 << 24)
201#define EMIF_REG_NVM_T_RP_SHIFT 20
202#define EMIF_REG_NVM_T_RP_MASK (0xf << 20)
203#define EMIF_REG_NVM_T_WRA_SHIFT 16
204#define EMIF_REG_NVM_T_WRA_MASK (0xf << 16)
205#define EMIF_REG_NVM_T_RRD_SHIFT 8
206#define EMIF_REG_NVM_T_RRD_MASK (0xff << 8)
207#define EMIF_REG_NVM_T_RCDMIN_SHIFT 0
208#define EMIF_REG_NVM_T_RCDMIN_MASK (0xff << 0)
209
210/* LPDDR2_NVM_TIM_SHDW */
211#define EMIF_REG_NVM_T_XP_SHDW_SHIFT 28
212#define EMIF_REG_NVM_T_XP_SHDW_MASK (0x7 << 28)
213#define EMIF_REG_NVM_T_WTR_SHDW_SHIFT 24
214#define EMIF_REG_NVM_T_WTR_SHDW_MASK (0x7 << 24)
215#define EMIF_REG_NVM_T_RP_SHDW_SHIFT 20
216#define EMIF_REG_NVM_T_RP_SHDW_MASK (0xf << 20)
217#define EMIF_REG_NVM_T_WRA_SHDW_SHIFT 16
218#define EMIF_REG_NVM_T_WRA_SHDW_MASK (0xf << 16)
219#define EMIF_REG_NVM_T_RRD_SHDW_SHIFT 8
220#define EMIF_REG_NVM_T_RRD_SHDW_MASK (0xff << 8)
221#define EMIF_REG_NVM_T_RCDMIN_SHDW_SHIFT 0
222#define EMIF_REG_NVM_T_RCDMIN_SHDW_MASK (0xff << 0)
223
224/* PWR_MGMT_CTRL */
225#define EMIF_REG_IDLEMODE_SHIFT 30
226#define EMIF_REG_IDLEMODE_MASK (0x3 << 30)
227#define EMIF_REG_PD_TIM_SHIFT 12
228#define EMIF_REG_PD_TIM_MASK (0xf << 12)
229#define EMIF_REG_DPD_EN_SHIFT 11
230#define EMIF_REG_DPD_EN_MASK (1 << 11)
231#define EMIF_REG_LP_MODE_SHIFT 8
232#define EMIF_REG_LP_MODE_MASK (0x7 << 8)
233#define EMIF_REG_SR_TIM_SHIFT 4
234#define EMIF_REG_SR_TIM_MASK (0xf << 4)
235#define EMIF_REG_CS_TIM_SHIFT 0
236#define EMIF_REG_CS_TIM_MASK (0xf << 0)
237
238/* PWR_MGMT_CTRL_SHDW */
SRICHARAN Raaec4482012-03-12 02:25:46 +0000239#define EMIF_REG_PD_TIM_SHDW_SHIFT 12
240#define EMIF_REG_PD_TIM_SHDW_MASK (0xf << 12)
Sricharanbb772a52011-11-15 09:50:00 -0500241#define EMIF_REG_SR_TIM_SHDW_SHIFT 4
242#define EMIF_REG_SR_TIM_SHDW_MASK (0xf << 4)
243#define EMIF_REG_CS_TIM_SHDW_SHIFT 0
244#define EMIF_REG_CS_TIM_SHDW_MASK (0xf << 0)
245
246/* LPDDR2_MODE_REG_DATA */
247#define EMIF_REG_VALUE_0_SHIFT 0
248#define EMIF_REG_VALUE_0_MASK (0x7f << 0)
249
250/* LPDDR2_MODE_REG_CFG */
251#define EMIF_REG_CS_SHIFT 31
252#define EMIF_REG_CS_MASK (1 << 31)
253#define EMIF_REG_REFRESH_EN_SHIFT 30
254#define EMIF_REG_REFRESH_EN_MASK (1 << 30)
255#define EMIF_REG_ADDRESS_SHIFT 0
256#define EMIF_REG_ADDRESS_MASK (0xff << 0)
257
258/* OCP_CONFIG */
259#define EMIF_REG_SYS_THRESH_MAX_SHIFT 24
260#define EMIF_REG_SYS_THRESH_MAX_MASK (0xf << 24)
261#define EMIF_REG_MPU_THRESH_MAX_SHIFT 20
262#define EMIF_REG_MPU_THRESH_MAX_MASK (0xf << 20)
263#define EMIF_REG_LL_THRESH_MAX_SHIFT 16
264#define EMIF_REG_LL_THRESH_MAX_MASK (0xf << 16)
265#define EMIF_REG_PR_OLD_COUNT_SHIFT 0
266#define EMIF_REG_PR_OLD_COUNT_MASK (0xff << 0)
267
268/* OCP_CFG_VAL_1 */
269#define EMIF_REG_SYS_BUS_WIDTH_SHIFT 30
270#define EMIF_REG_SYS_BUS_WIDTH_MASK (0x3 << 30)
271#define EMIF_REG_LL_BUS_WIDTH_SHIFT 28
272#define EMIF_REG_LL_BUS_WIDTH_MASK (0x3 << 28)
273#define EMIF_REG_WR_FIFO_DEPTH_SHIFT 8
274#define EMIF_REG_WR_FIFO_DEPTH_MASK (0xff << 8)
275#define EMIF_REG_CMD_FIFO_DEPTH_SHIFT 0
276#define EMIF_REG_CMD_FIFO_DEPTH_MASK (0xff << 0)
277
278/* OCP_CFG_VAL_2 */
279#define EMIF_REG_RREG_FIFO_DEPTH_SHIFT 16
280#define EMIF_REG_RREG_FIFO_DEPTH_MASK (0xff << 16)
281#define EMIF_REG_RSD_FIFO_DEPTH_SHIFT 8
282#define EMIF_REG_RSD_FIFO_DEPTH_MASK (0xff << 8)
283#define EMIF_REG_RCMD_FIFO_DEPTH_SHIFT 0
284#define EMIF_REG_RCMD_FIFO_DEPTH_MASK (0xff << 0)
285
286/* IODFT_TLGC */
287#define EMIF_REG_TLEC_SHIFT 16
288#define EMIF_REG_TLEC_MASK (0xffff << 16)
289#define EMIF_REG_MT_SHIFT 14
290#define EMIF_REG_MT_MASK (1 << 14)
291#define EMIF_REG_ACT_CAP_EN_SHIFT 13
292#define EMIF_REG_ACT_CAP_EN_MASK (1 << 13)
293#define EMIF_REG_OPG_LD_SHIFT 12
294#define EMIF_REG_OPG_LD_MASK (1 << 12)
295#define EMIF_REG_RESET_PHY_SHIFT 10
296#define EMIF_REG_RESET_PHY_MASK (1 << 10)
297#define EMIF_REG_MMS_SHIFT 8
298#define EMIF_REG_MMS_MASK (1 << 8)
299#define EMIF_REG_MC_SHIFT 4
300#define EMIF_REG_MC_MASK (0x3 << 4)
301#define EMIF_REG_PC_SHIFT 1
302#define EMIF_REG_PC_MASK (0x7 << 1)
303#define EMIF_REG_TM_SHIFT 0
304#define EMIF_REG_TM_MASK (1 << 0)
305
306/* IODFT_CTRL_MISR_RSLT */
307#define EMIF_REG_DQM_TLMR_SHIFT 16
308#define EMIF_REG_DQM_TLMR_MASK (0x3ff << 16)
309#define EMIF_REG_CTL_TLMR_SHIFT 0
310#define EMIF_REG_CTL_TLMR_MASK (0x7ff << 0)
311
312/* IODFT_ADDR_MISR_RSLT */
313#define EMIF_REG_ADDR_TLMR_SHIFT 0
314#define EMIF_REG_ADDR_TLMR_MASK (0x1fffff << 0)
315
316/* IODFT_DATA_MISR_RSLT_1 */
317#define EMIF_REG_DATA_TLMR_31_0_SHIFT 0
318#define EMIF_REG_DATA_TLMR_31_0_MASK (0xffffffff << 0)
319
320/* IODFT_DATA_MISR_RSLT_2 */
321#define EMIF_REG_DATA_TLMR_63_32_SHIFT 0
322#define EMIF_REG_DATA_TLMR_63_32_MASK (0xffffffff << 0)
323
324/* IODFT_DATA_MISR_RSLT_3 */
325#define EMIF_REG_DATA_TLMR_66_64_SHIFT 0
326#define EMIF_REG_DATA_TLMR_66_64_MASK (0x7 << 0)
327
328/* PERF_CNT_1 */
329#define EMIF_REG_COUNTER1_SHIFT 0
330#define EMIF_REG_COUNTER1_MASK (0xffffffff << 0)
331
332/* PERF_CNT_2 */
333#define EMIF_REG_COUNTER2_SHIFT 0
334#define EMIF_REG_COUNTER2_MASK (0xffffffff << 0)
335
336/* PERF_CNT_CFG */
337#define EMIF_REG_CNTR2_MCONNID_EN_SHIFT 31
338#define EMIF_REG_CNTR2_MCONNID_EN_MASK (1 << 31)
339#define EMIF_REG_CNTR2_REGION_EN_SHIFT 30
340#define EMIF_REG_CNTR2_REGION_EN_MASK (1 << 30)
341#define EMIF_REG_CNTR2_CFG_SHIFT 16
342#define EMIF_REG_CNTR2_CFG_MASK (0xf << 16)
343#define EMIF_REG_CNTR1_MCONNID_EN_SHIFT 15
344#define EMIF_REG_CNTR1_MCONNID_EN_MASK (1 << 15)
345#define EMIF_REG_CNTR1_REGION_EN_SHIFT 14
346#define EMIF_REG_CNTR1_REGION_EN_MASK (1 << 14)
347#define EMIF_REG_CNTR1_CFG_SHIFT 0
348#define EMIF_REG_CNTR1_CFG_MASK (0xf << 0)
349
350/* PERF_CNT_SEL */
351#define EMIF_REG_MCONNID2_SHIFT 24
352#define EMIF_REG_MCONNID2_MASK (0xff << 24)
353#define EMIF_REG_REGION_SEL2_SHIFT 16
354#define EMIF_REG_REGION_SEL2_MASK (0x3 << 16)
355#define EMIF_REG_MCONNID1_SHIFT 8
356#define EMIF_REG_MCONNID1_MASK (0xff << 8)
357#define EMIF_REG_REGION_SEL1_SHIFT 0
358#define EMIF_REG_REGION_SEL1_MASK (0x3 << 0)
359
360/* PERF_CNT_TIM */
361#define EMIF_REG_TOTAL_TIME_SHIFT 0
362#define EMIF_REG_TOTAL_TIME_MASK (0xffffffff << 0)
363
364/* READ_IDLE_CTRL */
365#define EMIF_REG_READ_IDLE_LEN_SHIFT 16
366#define EMIF_REG_READ_IDLE_LEN_MASK (0xf << 16)
367#define EMIF_REG_READ_IDLE_INTERVAL_SHIFT 0
368#define EMIF_REG_READ_IDLE_INTERVAL_MASK (0x1ff << 0)
369
370/* READ_IDLE_CTRL_SHDW */
371#define EMIF_REG_READ_IDLE_LEN_SHDW_SHIFT 16
372#define EMIF_REG_READ_IDLE_LEN_SHDW_MASK (0xf << 16)
373#define EMIF_REG_READ_IDLE_INTERVAL_SHDW_SHIFT 0
374#define EMIF_REG_READ_IDLE_INTERVAL_SHDW_MASK (0x1ff << 0)
375
376/* IRQ_EOI */
377#define EMIF_REG_EOI_SHIFT 0
378#define EMIF_REG_EOI_MASK (1 << 0)
379
380/* IRQSTATUS_RAW_SYS */
381#define EMIF_REG_DNV_SYS_SHIFT 2
382#define EMIF_REG_DNV_SYS_MASK (1 << 2)
383#define EMIF_REG_TA_SYS_SHIFT 1
384#define EMIF_REG_TA_SYS_MASK (1 << 1)
385#define EMIF_REG_ERR_SYS_SHIFT 0
386#define EMIF_REG_ERR_SYS_MASK (1 << 0)
387
388/* IRQSTATUS_RAW_LL */
389#define EMIF_REG_DNV_LL_SHIFT 2
390#define EMIF_REG_DNV_LL_MASK (1 << 2)
391#define EMIF_REG_TA_LL_SHIFT 1
392#define EMIF_REG_TA_LL_MASK (1 << 1)
393#define EMIF_REG_ERR_LL_SHIFT 0
394#define EMIF_REG_ERR_LL_MASK (1 << 0)
395
396/* IRQSTATUS_SYS */
397
398/* IRQSTATUS_LL */
399
400/* IRQENABLE_SET_SYS */
401#define EMIF_REG_EN_DNV_SYS_SHIFT 2
402#define EMIF_REG_EN_DNV_SYS_MASK (1 << 2)
403#define EMIF_REG_EN_TA_SYS_SHIFT 1
404#define EMIF_REG_EN_TA_SYS_MASK (1 << 1)
405#define EMIF_REG_EN_ERR_SYS_SHIFT 0
406#define EMIF_REG_EN_ERR_SYS_MASK (1 << 0)
407
408/* IRQENABLE_SET_LL */
409#define EMIF_REG_EN_DNV_LL_SHIFT 2
410#define EMIF_REG_EN_DNV_LL_MASK (1 << 2)
411#define EMIF_REG_EN_TA_LL_SHIFT 1
412#define EMIF_REG_EN_TA_LL_MASK (1 << 1)
413#define EMIF_REG_EN_ERR_LL_SHIFT 0
414#define EMIF_REG_EN_ERR_LL_MASK (1 << 0)
415
416/* IRQENABLE_CLR_SYS */
417
418/* IRQENABLE_CLR_LL */
419
420/* ZQ_CONFIG */
421#define EMIF_REG_ZQ_CS1EN_SHIFT 31
422#define EMIF_REG_ZQ_CS1EN_MASK (1 << 31)
423#define EMIF_REG_ZQ_CS0EN_SHIFT 30
424#define EMIF_REG_ZQ_CS0EN_MASK (1 << 30)
425#define EMIF_REG_ZQ_DUALCALEN_SHIFT 29
426#define EMIF_REG_ZQ_DUALCALEN_MASK (1 << 29)
427#define EMIF_REG_ZQ_SFEXITEN_SHIFT 28
428#define EMIF_REG_ZQ_SFEXITEN_MASK (1 << 28)
429#define EMIF_REG_ZQ_ZQINIT_MULT_SHIFT 18
430#define EMIF_REG_ZQ_ZQINIT_MULT_MASK (0x3 << 18)
431#define EMIF_REG_ZQ_ZQCL_MULT_SHIFT 16
432#define EMIF_REG_ZQ_ZQCL_MULT_MASK (0x3 << 16)
433#define EMIF_REG_ZQ_REFINTERVAL_SHIFT 0
434#define EMIF_REG_ZQ_REFINTERVAL_MASK (0xffff << 0)
435
436/* TEMP_ALERT_CONFIG */
437#define EMIF_REG_TA_CS1EN_SHIFT 31
438#define EMIF_REG_TA_CS1EN_MASK (1 << 31)
439#define EMIF_REG_TA_CS0EN_SHIFT 30
440#define EMIF_REG_TA_CS0EN_MASK (1 << 30)
441#define EMIF_REG_TA_SFEXITEN_SHIFT 28
442#define EMIF_REG_TA_SFEXITEN_MASK (1 << 28)
443#define EMIF_REG_TA_DEVWDT_SHIFT 26
444#define EMIF_REG_TA_DEVWDT_MASK (0x3 << 26)
445#define EMIF_REG_TA_DEVCNT_SHIFT 24
446#define EMIF_REG_TA_DEVCNT_MASK (0x3 << 24)
447#define EMIF_REG_TA_REFINTERVAL_SHIFT 0
448#define EMIF_REG_TA_REFINTERVAL_MASK (0x3fffff << 0)
449
450/* OCP_ERR_LOG */
451#define EMIF_REG_MADDRSPACE_SHIFT 14
452#define EMIF_REG_MADDRSPACE_MASK (0x3 << 14)
453#define EMIF_REG_MBURSTSEQ_SHIFT 11
454#define EMIF_REG_MBURSTSEQ_MASK (0x7 << 11)
455#define EMIF_REG_MCMD_SHIFT 8
456#define EMIF_REG_MCMD_MASK (0x7 << 8)
457#define EMIF_REG_MCONNID_SHIFT 0
458#define EMIF_REG_MCONNID_MASK (0xff << 0)
459
460/* DDR_PHY_CTRL_1 */
461#define EMIF_REG_DDR_PHY_CTRL_1_SHIFT 4
462#define EMIF_REG_DDR_PHY_CTRL_1_MASK (0xfffffff << 4)
463#define EMIF_REG_READ_LATENCY_SHIFT 0
464#define EMIF_REG_READ_LATENCY_MASK (0xf << 0)
465#define EMIF_REG_DLL_SLAVE_DLY_CTRL_SHIFT 4
466#define EMIF_REG_DLL_SLAVE_DLY_CTRL_MASK (0xFF << 4)
467#define EMIF_EMIF_DDR_PHY_CTRL_1_BASE_VAL_SHIFT 12
468#define EMIF_EMIF_DDR_PHY_CTRL_1_BASE_VAL_MASK (0xFFFFF << 12)
469
470/* DDR_PHY_CTRL_1_SHDW */
471#define EMIF_REG_DDR_PHY_CTRL_1_SHDW_SHIFT 4
472#define EMIF_REG_DDR_PHY_CTRL_1_SHDW_MASK (0xfffffff << 4)
473#define EMIF_REG_READ_LATENCY_SHDW_SHIFT 0
474#define EMIF_REG_READ_LATENCY_SHDW_MASK (0xf << 0)
475#define EMIF_REG_DLL_SLAVE_DLY_CTRL_SHDW_SHIFT 4
476#define EMIF_REG_DLL_SLAVE_DLY_CTRL_SHDW_MASK (0xFF << 4)
477#define EMIF_EMIF_DDR_PHY_CTRL_1_BASE_VAL_SHDW_SHIFT 12
478#define EMIF_EMIF_DDR_PHY_CTRL_1_BASE_VAL_SHDW_MASK (0xFFFFF << 12)
479
480/* DDR_PHY_CTRL_2 */
481#define EMIF_REG_DDR_PHY_CTRL_2_SHIFT 0
482#define EMIF_REG_DDR_PHY_CTRL_2_MASK (0xffffffff << 0)
483
Lokesh Vutla784ab7c2012-05-22 00:03:25 +0000484/*EMIF_READ_WRITE_LEVELING_CONTROL*/
485#define EMIF_REG_RDWRLVLFULL_START_SHIFT 31
486#define EMIF_REG_RDWRLVLFULL_START_MASK (1 << 31)
487#define EMIF_REG_RDWRLVLINC_PRE_SHIFT 24
488#define EMIF_REG_RDWRLVLINC_PRE_MASK (0x7F << 24)
489#define EMIF_REG_RDLVLINC_INT_SHIFT 16
490#define EMIF_REG_RDLVLINC_INT_MASK (0xFF << 16)
491#define EMIF_REG_RDLVLGATEINC_INT_SHIFT 8
492#define EMIF_REG_RDLVLGATEINC_INT_MASK (0xFF << 8)
493#define EMIF_REG_WRLVLINC_INT_SHIFT 0
494#define EMIF_REG_WRLVLINC_INT_MASK (0xFF << 0)
495
496/*EMIF_READ_WRITE_LEVELING_RAMP_CONTROL*/
497#define EMIF_REG_RDWRLVL_EN_SHIFT 31
498#define EMIF_REG_RDWRLVL_EN_MASK (1 << 31)
499#define EMIF_REG_RDWRLVLINC_RMP_PRE_SHIFT 24
500#define EMIF_REG_RDWRLVLINC_RMP_PRE_MASK (0x7F << 24)
501#define EMIF_REG_RDLVLINC_RMP_INT_SHIFT 16
502#define EMIF_REG_RDLVLINC_RMP_INT_MASK (0xFF << 16)
503#define EMIF_REG_RDLVLGATEINC_RMP_INT_SHIFT 8
504#define EMIF_REG_RDLVLGATEINC_RMP_INT_MASK (0xFF << 8)
505#define EMIF_REG_WRLVLINC_RMP_INT_SHIFT 0
506#define EMIF_REG_WRLVLINC_RMP_INT_MASK (0xFF << 0)
507
508/*EMIF_READ_WRITE_LEVELING_RAMP_WINDOW*/
509#define EMIF_REG_RDWRLVLINC_RMP_WIN_SHIFT 0
510#define EMIF_REG_RDWRLVLINC_RMP_WIN_MASK (0x1FFF << 0)
511
512/*Leveling Fields */
513#define DDR3_WR_LVL_INT 0x73
514#define DDR3_RD_LVL_INT 0x33
515#define DDR3_RD_LVL_GATE_INT 0x59
516#define RD_RW_LVL_INC_PRE 0x0
517#define DDR3_FULL_LVL (1 << EMIF_REG_RDWRLVL_EN_SHIFT)
518
519#define DDR3_INC_LVL ((DDR3_WR_LVL_INT << EMIF_REG_WRLVLINC_INT_SHIFT) \
520 | (DDR3_RD_LVL_GATE_INT << EMIF_REG_RDLVLGATEINC_INT_SHIFT) \
521 | (DDR3_RD_LVL_INT << EMIF_REG_RDLVLINC_RMP_INT_SHIFT) \
522 | (RD_RW_LVL_INC_PRE << EMIF_REG_RDWRLVLINC_RMP_PRE_SHIFT))
523
524#define SDRAM_CONFIG_EXT_RD_LVL_11_SAMPLES 0x0000C1A7
525#define SDRAM_CONFIG_EXT_RD_LVL_4_SAMPLES 0x000001A7
Lokesh Vutla9100ede2013-02-12 01:33:44 +0000526#define SDRAM_CONFIG_EXT_RD_LVL_11_SAMPLES_ES2 0x0000C1C7
Lokesh Vutla784ab7c2012-05-22 00:03:25 +0000527
Sricharanbb772a52011-11-15 09:50:00 -0500528/* DMM */
529#define DMM_BASE 0x4E000040
530
531/* Memory Adapter */
532#define MA_BASE 0x482AF040
533
534/* DMM_LISA_MAP */
535#define EMIF_SYS_ADDR_SHIFT 24
536#define EMIF_SYS_ADDR_MASK (0xff << 24)
537#define EMIF_SYS_SIZE_SHIFT 20
538#define EMIF_SYS_SIZE_MASK (0x7 << 20)
539#define EMIF_SDRC_INTL_SHIFT 18
540#define EMIF_SDRC_INTL_MASK (0x3 << 18)
541#define EMIF_SDRC_ADDRSPC_SHIFT 16
542#define EMIF_SDRC_ADDRSPC_MASK (0x3 << 16)
543#define EMIF_SDRC_MAP_SHIFT 8
544#define EMIF_SDRC_MAP_MASK (0x3 << 8)
545#define EMIF_SDRC_ADDR_SHIFT 0
546#define EMIF_SDRC_ADDR_MASK (0xff << 0)
547
548/* DMM_LISA_MAP fields */
549#define DMM_SDRC_MAP_UNMAPPED 0
550#define DMM_SDRC_MAP_EMIF1_ONLY 1
551#define DMM_SDRC_MAP_EMIF2_ONLY 2
552#define DMM_SDRC_MAP_EMIF1_AND_EMIF2 3
553
554#define DMM_SDRC_INTL_NONE 0
555#define DMM_SDRC_INTL_128B 1
556#define DMM_SDRC_INTL_256B 2
557#define DMM_SDRC_INTL_512 3
558
559#define DMM_SDRC_ADDR_SPC_SDRAM 0
560#define DMM_SDRC_ADDR_SPC_NVM 1
561#define DMM_SDRC_ADDR_SPC_INVALID 2
562
563#define DMM_LISA_MAP_INTERLEAVED_BASE_VAL (\
564 (DMM_SDRC_MAP_EMIF1_AND_EMIF2 << EMIF_SDRC_MAP_SHIFT) |\
565 (DMM_SDRC_ADDR_SPC_SDRAM << EMIF_SDRC_ADDRSPC_SHIFT) |\
566 (DMM_SDRC_INTL_128B << EMIF_SDRC_INTL_SHIFT) |\
567 (CONFIG_SYS_SDRAM_BASE << EMIF_SYS_ADDR_SHIFT))
568
569#define DMM_LISA_MAP_EMIF1_ONLY_BASE_VAL (\
570 (DMM_SDRC_MAP_EMIF1_ONLY << EMIF_SDRC_MAP_SHIFT)|\
571 (DMM_SDRC_ADDR_SPC_SDRAM << EMIF_SDRC_ADDRSPC_SHIFT)|\
572 (DMM_SDRC_INTL_NONE << EMIF_SDRC_INTL_SHIFT))
573
574#define DMM_LISA_MAP_EMIF2_ONLY_BASE_VAL (\
575 (DMM_SDRC_MAP_EMIF2_ONLY << EMIF_SDRC_MAP_SHIFT)|\
576 (DMM_SDRC_ADDR_SPC_SDRAM << EMIF_SDRC_ADDRSPC_SHIFT)|\
577 (DMM_SDRC_INTL_NONE << EMIF_SDRC_INTL_SHIFT))
578
579/* Trap for invalid TILER PAT entries */
580#define DMM_LISA_MAP_0_INVAL_ADDR_TRAP (\
581 (0 << EMIF_SDRC_ADDR_SHIFT) |\
582 (DMM_SDRC_MAP_EMIF1_ONLY << EMIF_SDRC_MAP_SHIFT)|\
583 (DMM_SDRC_ADDR_SPC_INVALID << EMIF_SDRC_ADDRSPC_SHIFT)|\
584 (DMM_SDRC_INTL_NONE << EMIF_SDRC_INTL_SHIFT)|\
585 (0xFF << EMIF_SYS_ADDR_SHIFT))
586
SRICHARAN Rf4010732012-03-12 02:25:37 +0000587#define EMIF_EXT_PHY_CTRL_TIMING_REG 0x5
Sricharanbb772a52011-11-15 09:50:00 -0500588
589/* Reg mapping structure */
590struct emif_reg_struct {
591 u32 emif_mod_id_rev;
592 u32 emif_status;
593 u32 emif_sdram_config;
594 u32 emif_lpddr2_nvm_config;
595 u32 emif_sdram_ref_ctrl;
596 u32 emif_sdram_ref_ctrl_shdw;
597 u32 emif_sdram_tim_1;
598 u32 emif_sdram_tim_1_shdw;
599 u32 emif_sdram_tim_2;
600 u32 emif_sdram_tim_2_shdw;
601 u32 emif_sdram_tim_3;
602 u32 emif_sdram_tim_3_shdw;
603 u32 emif_lpddr2_nvm_tim;
604 u32 emif_lpddr2_nvm_tim_shdw;
605 u32 emif_pwr_mgmt_ctrl;
606 u32 emif_pwr_mgmt_ctrl_shdw;
607 u32 emif_lpddr2_mode_reg_data;
608 u32 padding1[1];
609 u32 emif_lpddr2_mode_reg_data_es2;
610 u32 padding11[1];
611 u32 emif_lpddr2_mode_reg_cfg;
612 u32 emif_l3_config;
613 u32 emif_l3_cfg_val_1;
614 u32 emif_l3_cfg_val_2;
615 u32 emif_iodft_tlgc;
616 u32 padding2[7];
617 u32 emif_perf_cnt_1;
618 u32 emif_perf_cnt_2;
619 u32 emif_perf_cnt_cfg;
620 u32 emif_perf_cnt_sel;
621 u32 emif_perf_cnt_tim;
622 u32 padding3;
623 u32 emif_read_idlectrl;
624 u32 emif_read_idlectrl_shdw;
625 u32 padding4;
626 u32 emif_irqstatus_raw_sys;
627 u32 emif_irqstatus_raw_ll;
628 u32 emif_irqstatus_sys;
629 u32 emif_irqstatus_ll;
630 u32 emif_irqenable_set_sys;
631 u32 emif_irqenable_set_ll;
632 u32 emif_irqenable_clr_sys;
633 u32 emif_irqenable_clr_ll;
634 u32 padding5;
635 u32 emif_zq_config;
636 u32 emif_temp_alert_config;
637 u32 emif_l3_err_log;
SRICHARAN Rf4010732012-03-12 02:25:37 +0000638 u32 emif_rd_wr_lvl_rmp_win;
639 u32 emif_rd_wr_lvl_rmp_ctl;
640 u32 emif_rd_wr_lvl_ctl;
641 u32 padding6[1];
Sricharanbb772a52011-11-15 09:50:00 -0500642 u32 emif_ddr_phy_ctrl_1;
643 u32 emif_ddr_phy_ctrl_1_shdw;
644 u32 emif_ddr_phy_ctrl_2;
SRICHARAN Rf4010732012-03-12 02:25:37 +0000645 u32 padding7[12];
646 u32 emif_rd_wr_exec_thresh;
SRICHARAN R54d022e2013-11-08 17:40:38 +0530647 u32 padding8[7];
648 u32 emif_ddr_phy_status[21];
649 u32 padding9[27];
SRICHARAN Rf4010732012-03-12 02:25:37 +0000650 u32 emif_ddr_ext_phy_ctrl_1;
651 u32 emif_ddr_ext_phy_ctrl_1_shdw;
652 u32 emif_ddr_ext_phy_ctrl_2;
653 u32 emif_ddr_ext_phy_ctrl_2_shdw;
654 u32 emif_ddr_ext_phy_ctrl_3;
655 u32 emif_ddr_ext_phy_ctrl_3_shdw;
656 u32 emif_ddr_ext_phy_ctrl_4;
657 u32 emif_ddr_ext_phy_ctrl_4_shdw;
658 u32 emif_ddr_ext_phy_ctrl_5;
659 u32 emif_ddr_ext_phy_ctrl_5_shdw;
660 u32 emif_ddr_ext_phy_ctrl_6;
661 u32 emif_ddr_ext_phy_ctrl_6_shdw;
662 u32 emif_ddr_ext_phy_ctrl_7;
663 u32 emif_ddr_ext_phy_ctrl_7_shdw;
664 u32 emif_ddr_ext_phy_ctrl_8;
665 u32 emif_ddr_ext_phy_ctrl_8_shdw;
666 u32 emif_ddr_ext_phy_ctrl_9;
667 u32 emif_ddr_ext_phy_ctrl_9_shdw;
668 u32 emif_ddr_ext_phy_ctrl_10;
669 u32 emif_ddr_ext_phy_ctrl_10_shdw;
670 u32 emif_ddr_ext_phy_ctrl_11;
671 u32 emif_ddr_ext_phy_ctrl_11_shdw;
672 u32 emif_ddr_ext_phy_ctrl_12;
673 u32 emif_ddr_ext_phy_ctrl_12_shdw;
674 u32 emif_ddr_ext_phy_ctrl_13;
675 u32 emif_ddr_ext_phy_ctrl_13_shdw;
676 u32 emif_ddr_ext_phy_ctrl_14;
677 u32 emif_ddr_ext_phy_ctrl_14_shdw;
678 u32 emif_ddr_ext_phy_ctrl_15;
679 u32 emif_ddr_ext_phy_ctrl_15_shdw;
680 u32 emif_ddr_ext_phy_ctrl_16;
681 u32 emif_ddr_ext_phy_ctrl_16_shdw;
682 u32 emif_ddr_ext_phy_ctrl_17;
683 u32 emif_ddr_ext_phy_ctrl_17_shdw;
684 u32 emif_ddr_ext_phy_ctrl_18;
685 u32 emif_ddr_ext_phy_ctrl_18_shdw;
686 u32 emif_ddr_ext_phy_ctrl_19;
687 u32 emif_ddr_ext_phy_ctrl_19_shdw;
688 u32 emif_ddr_ext_phy_ctrl_20;
689 u32 emif_ddr_ext_phy_ctrl_20_shdw;
690 u32 emif_ddr_ext_phy_ctrl_21;
691 u32 emif_ddr_ext_phy_ctrl_21_shdw;
692 u32 emif_ddr_ext_phy_ctrl_22;
693 u32 emif_ddr_ext_phy_ctrl_22_shdw;
694 u32 emif_ddr_ext_phy_ctrl_23;
695 u32 emif_ddr_ext_phy_ctrl_23_shdw;
696 u32 emif_ddr_ext_phy_ctrl_24;
697 u32 emif_ddr_ext_phy_ctrl_24_shdw;
SRICHARAN R6c709352013-11-08 17:40:37 +0530698 u32 padding[22];
699 u32 emif_ddr_fifo_misaligned_clear_1;
700 u32 emif_ddr_fifo_misaligned_clear_2;
Sricharanbb772a52011-11-15 09:50:00 -0500701};
702
703struct dmm_lisa_map_regs {
704 u32 dmm_lisa_map_0;
705 u32 dmm_lisa_map_1;
706 u32 dmm_lisa_map_2;
707 u32 dmm_lisa_map_3;
Lokesh Vutla78314192013-02-12 21:29:07 +0000708 u8 is_ma_present;
Sricharanbb772a52011-11-15 09:50:00 -0500709};
710
711#define CS0 0
712#define CS1 1
713/* The maximum frequency at which the LPDDR2 interface can operate in Hz*/
714#define MAX_LPDDR2_FREQ 400000000 /* 400 MHz */
715
716/*
717 * The period of DDR clk is represented as numerator and denominator for
718 * better accuracy in integer based calculations. However, if the numerator
719 * and denominator are very huge there may be chances of overflow in
720 * calculations. So, as a trade-off keep denominator(and consequently
721 * numerator) within a limit sacrificing some accuracy - but not much
722 * If denominator and numerator are already small (such as at 400 MHz)
723 * no adjustment is needed
724 */
725#define EMIF_PERIOD_DEN_LIMIT 1000
726/*
727 * Maximum number of different frequencies supported by EMIF driver
728 * Determines the number of entries in the pointer array for register
729 * cache
730 */
731#define EMIF_MAX_NUM_FREQUENCIES 6
732/*
733 * Indices into the Addressing Table array.
734 * One entry each for all the different types of devices with different
735 * addressing schemes
736 */
737#define ADDR_TABLE_INDEX64M 0
738#define ADDR_TABLE_INDEX128M 1
739#define ADDR_TABLE_INDEX256M 2
740#define ADDR_TABLE_INDEX512M 3
741#define ADDR_TABLE_INDEX1GS4 4
742#define ADDR_TABLE_INDEX2GS4 5
743#define ADDR_TABLE_INDEX4G 6
744#define ADDR_TABLE_INDEX8G 7
745#define ADDR_TABLE_INDEX1GS2 8
746#define ADDR_TABLE_INDEX2GS2 9
747#define ADDR_TABLE_INDEXMAX 10
748
749/* Number of Row bits */
750#define ROW_9 0
751#define ROW_10 1
752#define ROW_11 2
753#define ROW_12 3
754#define ROW_13 4
755#define ROW_14 5
756#define ROW_15 6
757#define ROW_16 7
758
759/* Number of Column bits */
760#define COL_8 0
761#define COL_9 1
762#define COL_10 2
763#define COL_11 3
764#define COL_7 4 /*Not supported by OMAP included for completeness */
765
766/* Number of Banks*/
767#define BANKS1 0
768#define BANKS2 1
769#define BANKS4 2
770#define BANKS8 3
771
772/* Refresh rate in micro seconds x 10 */
773#define T_REFI_15_6 156
774#define T_REFI_7_8 78
775#define T_REFI_3_9 39
776
777#define EBANK_CS1_DIS 0
778#define EBANK_CS1_EN 1
779
780/* Read Latency used by the device at reset */
781#define RL_BOOT 3
782/* Read Latency for the highest frequency you want to use */
783#ifdef CONFIG_OMAP54XX
784#define RL_FINAL 8
785#else
786#define RL_FINAL 6
787#endif
788
789
790/* Interleaving policies at EMIF level- between banks and Chip Selects */
791#define EMIF_INTERLEAVING_POLICY_MAX_INTERLEAVING 0
792#define EMIF_INTERLEAVING_POLICY_NO_BANK_INTERLEAVING 3
793
794/*
795 * Interleaving policy to be used
796 * Currently set to MAX interleaving for better performance
797 */
798#define EMIF_INTERLEAVING_POLICY EMIF_INTERLEAVING_POLICY_MAX_INTERLEAVING
799
800/* State of the core voltage:
801 * This is important for some parameters such as read idle control and
802 * ZQ calibration timings. Timings are much stricter when voltage ramp
803 * is happening compared to when the voltage is stable.
804 * We need to calculate two sets of values for these parameters and use
805 * them accordingly
806 */
807#define LPDDR2_VOLTAGE_STABLE 0
808#define LPDDR2_VOLTAGE_RAMPING 1
809
810/* Length of the forced read idle period in terms of cycles */
811#define EMIF_REG_READ_IDLE_LEN_VAL 5
812
813/* Interval between forced 'read idles' */
814/* To be used when voltage is changed for DPS/DVFS - 1us */
815#define READ_IDLE_INTERVAL_DVFS (1*1000)
816/*
817 * To be used when voltage is not scaled except by Smart Reflex
818 * 50us - or maximum value will do
819 */
820#define READ_IDLE_INTERVAL_NORMAL (50*1000)
821
822
823/*
824 * Unless voltage is changing due to DVFS one ZQCS command every 50ms should
825 * be enough. This shoule be enough also in the case when voltage is changing
826 * due to smart-reflex.
827 */
828#define EMIF_ZQCS_INTERVAL_NORMAL_IN_US (50*1000)
829/*
830 * If voltage is changing due to DVFS ZQCS should be performed more
831 * often(every 50us)
832 */
833#define EMIF_ZQCS_INTERVAL_DVFS_IN_US 50
834
835/* The interval between ZQCL commands as a multiple of ZQCS interval */
836#define REG_ZQ_ZQCL_MULT 4
837/* The interval between ZQINIT commands as a multiple of ZQCL interval */
838#define REG_ZQ_ZQINIT_MULT 3
839/* Enable ZQ Calibration on exiting Self-refresh */
840#define REG_ZQ_SFEXITEN_ENABLE 1
841/*
842 * ZQ Calibration simultaneously on both chip-selects:
843 * Needs one calibration resistor per CS
844 * None of the boards that we know of have this capability
845 * So disabled by default
846 */
847#define REG_ZQ_DUALCALEN_DISABLE 0
848/*
849 * Enable ZQ Calibration by default on CS0. If we are asked to program
850 * the EMIF there will be something connected to CS0 for sure
851 */
852#define REG_ZQ_CS0EN_ENABLE 1
853
854/* EMIF_PWR_MGMT_CTRL register */
855/* Low power modes */
856#define LP_MODE_DISABLE 0
857#define LP_MODE_CLOCK_STOP 1
858#define LP_MODE_SELF_REFRESH 2
859#define LP_MODE_PWR_DN 3
860
861/* REG_DPD_EN */
862#define DPD_DISABLE 0
863#define DPD_ENABLE 1
864
865/* Maximum delay before Low Power Modes */
SRICHARAN Rf4010732012-03-12 02:25:37 +0000866#define REG_CS_TIM 0x0
Sricharan R92b04822013-05-30 03:19:39 +0000867#define REG_SR_TIM 0x0
868#define REG_PD_TIM 0x0
869
Sricharanbb772a52011-11-15 09:50:00 -0500870
871/* EMIF_PWR_MGMT_CTRL register */
872#define EMIF_PWR_MGMT_CTRL (\
873 ((REG_CS_TIM << EMIF_REG_CS_TIM_SHIFT) & EMIF_REG_CS_TIM_MASK)|\
874 ((REG_SR_TIM << EMIF_REG_SR_TIM_SHIFT) & EMIF_REG_SR_TIM_MASK)|\
875 ((REG_PD_TIM << EMIF_REG_PD_TIM_SHIFT) & EMIF_REG_PD_TIM_MASK)|\
876 ((REG_PD_TIM << EMIF_REG_PD_TIM_SHIFT) & EMIF_REG_PD_TIM_MASK)|\
877 ((LP_MODE_DISABLE << EMIF_REG_LP_MODE_SHIFT)\
878 & EMIF_REG_LP_MODE_MASK) |\
879 ((DPD_DISABLE << EMIF_REG_DPD_EN_SHIFT)\
880 & EMIF_REG_DPD_EN_MASK))\
881
882#define EMIF_PWR_MGMT_CTRL_SHDW (\
883 ((REG_CS_TIM << EMIF_REG_CS_TIM_SHDW_SHIFT)\
884 & EMIF_REG_CS_TIM_SHDW_MASK) |\
885 ((REG_SR_TIM << EMIF_REG_SR_TIM_SHDW_SHIFT)\
886 & EMIF_REG_SR_TIM_SHDW_MASK) |\
887 ((REG_PD_TIM << EMIF_REG_PD_TIM_SHDW_SHIFT)\
888 & EMIF_REG_PD_TIM_SHDW_MASK) |\
889 ((REG_PD_TIM << EMIF_REG_PD_TIM_SHDW_SHIFT)\
890 & EMIF_REG_PD_TIM_SHDW_MASK))
891
892/* EMIF_L3_CONFIG register value */
893#define EMIF_L3_CONFIG_VAL_SYS_10_LL_0 0x0A0000FF
894#define EMIF_L3_CONFIG_VAL_SYS_10_MPU_3_LL_0 0x0A300000
SRICHARAN Rf4010732012-03-12 02:25:37 +0000895#define EMIF_L3_CONFIG_VAL_SYS_10_MPU_5_LL_0 0x0A500000
Sricharanbb772a52011-11-15 09:50:00 -0500896
897/*
898 * Value of bits 12:31 of DDR_PHY_CTRL_1 register:
899 * All these fields have magic values dependent on frequency and
900 * determined by PHY and DLL integration with EMIF. Setting the magic
901 * values suggested by hw team.
902 */
903#define EMIF_DDR_PHY_CTRL_1_BASE_VAL 0x049FF
904#define EMIF_DLL_SLAVE_DLY_CTRL_400_MHZ 0x41
905#define EMIF_DLL_SLAVE_DLY_CTRL_200_MHZ 0x80
906#define EMIF_DLL_SLAVE_DLY_CTRL_100_MHZ_AND_LESS 0xFF
907
908/*
909* MR1 value:
910* Burst length : 8
911* Burst type : sequential
912* Wrap : enabled
913* nWR : 3(default). EMIF does not do pre-charge.
914* : So nWR is don't care
915*/
916#define MR1_BL_8_BT_SEQ_WRAP_EN_NWR_3 0x23
SRICHARAN Rf4010732012-03-12 02:25:37 +0000917#define MR1_BL_8_BT_SEQ_WRAP_EN_NWR_8 0xc3
Sricharanbb772a52011-11-15 09:50:00 -0500918
919/* MR2 */
920#define MR2_RL3_WL1 1
921#define MR2_RL4_WL2 2
922#define MR2_RL5_WL2 3
923#define MR2_RL6_WL3 4
924
925/* MR10: ZQ calibration codes */
926#define MR10_ZQ_ZQCS 0x56
927#define MR10_ZQ_ZQCL 0xAB
928#define MR10_ZQ_ZQINIT 0xFF
929#define MR10_ZQ_ZQRESET 0xC3
930
931/* TEMP_ALERT_CONFIG */
932#define TEMP_ALERT_POLL_INTERVAL_MS 360 /* for temp gradient - 5 C/s */
933#define TEMP_ALERT_CONFIG_DEVCT_1 0
934#define TEMP_ALERT_CONFIG_DEVWDT_32 2
935
936/* MR16 value: refresh full array(no partial array self refresh) */
937#define MR16_REF_FULL_ARRAY 0
938
939/*
940 * Maximum number of entries we keep in our array of timing tables
941 * We need not keep all the speed bins supported by the device
942 * We need to keep timing tables for only the speed bins that we
943 * are interested in
944 */
945#define MAX_NUM_SPEEDBINS 4
946
947/* LPDDR2 Densities */
948#define LPDDR2_DENSITY_64Mb 0
949#define LPDDR2_DENSITY_128Mb 1
950#define LPDDR2_DENSITY_256Mb 2
951#define LPDDR2_DENSITY_512Mb 3
952#define LPDDR2_DENSITY_1Gb 4
953#define LPDDR2_DENSITY_2Gb 5
954#define LPDDR2_DENSITY_4Gb 6
955#define LPDDR2_DENSITY_8Gb 7
956#define LPDDR2_DENSITY_16Gb 8
957#define LPDDR2_DENSITY_32Gb 9
958
959/* LPDDR2 type */
960#define LPDDR2_TYPE_S4 0
961#define LPDDR2_TYPE_S2 1
962#define LPDDR2_TYPE_NVM 2
963
964/* LPDDR2 IO width */
965#define LPDDR2_IO_WIDTH_32 0
966#define LPDDR2_IO_WIDTH_16 1
967#define LPDDR2_IO_WIDTH_8 2
968
969/* Mode register numbers */
970#define LPDDR2_MR0 0
971#define LPDDR2_MR1 1
972#define LPDDR2_MR2 2
973#define LPDDR2_MR3 3
974#define LPDDR2_MR4 4
975#define LPDDR2_MR5 5
976#define LPDDR2_MR6 6
977#define LPDDR2_MR7 7
978#define LPDDR2_MR8 8
979#define LPDDR2_MR9 9
980#define LPDDR2_MR10 10
981#define LPDDR2_MR11 11
982#define LPDDR2_MR16 16
983#define LPDDR2_MR17 17
984#define LPDDR2_MR18 18
985
986/* MR0 */
987#define LPDDR2_MR0_DAI_SHIFT 0
988#define LPDDR2_MR0_DAI_MASK 1
989#define LPDDR2_MR0_DI_SHIFT 1
990#define LPDDR2_MR0_DI_MASK (1 << 1)
991#define LPDDR2_MR0_DNVI_SHIFT 2
992#define LPDDR2_MR0_DNVI_MASK (1 << 2)
993
994/* MR4 */
995#define MR4_SDRAM_REF_RATE_SHIFT 0
996#define MR4_SDRAM_REF_RATE_MASK 7
997#define MR4_TUF_SHIFT 7
998#define MR4_TUF_MASK (1 << 7)
999
1000/* MR4 SDRAM Refresh Rate field values */
1001#define SDRAM_TEMP_LESS_LOW_SHUTDOWN 0x0
1002#define SDRAM_TEMP_LESS_4X_REFRESH_AND_TIMINGS 0x1
1003#define SDRAM_TEMP_LESS_2X_REFRESH_AND_TIMINGS 0x2
1004#define SDRAM_TEMP_NOMINAL 0x3
1005#define SDRAM_TEMP_RESERVED_4 0x4
1006#define SDRAM_TEMP_HIGH_DERATE_REFRESH 0x5
1007#define SDRAM_TEMP_HIGH_DERATE_REFRESH_AND_TIMINGS 0x6
1008#define SDRAM_TEMP_VERY_HIGH_SHUTDOWN 0x7
1009
1010#define LPDDR2_MANUFACTURER_SAMSUNG 1
1011#define LPDDR2_MANUFACTURER_QIMONDA 2
1012#define LPDDR2_MANUFACTURER_ELPIDA 3
1013#define LPDDR2_MANUFACTURER_ETRON 4
1014#define LPDDR2_MANUFACTURER_NANYA 5
1015#define LPDDR2_MANUFACTURER_HYNIX 6
1016#define LPDDR2_MANUFACTURER_MOSEL 7
1017#define LPDDR2_MANUFACTURER_WINBOND 8
1018#define LPDDR2_MANUFACTURER_ESMT 9
1019#define LPDDR2_MANUFACTURER_SPANSION 11
1020#define LPDDR2_MANUFACTURER_SST 12
1021#define LPDDR2_MANUFACTURER_ZMOS 13
1022#define LPDDR2_MANUFACTURER_INTEL 14
1023#define LPDDR2_MANUFACTURER_NUMONYX 254
1024#define LPDDR2_MANUFACTURER_MICRON 255
1025
1026/* MR8 register fields */
1027#define MR8_TYPE_SHIFT 0x0
1028#define MR8_TYPE_MASK 0x3
1029#define MR8_DENSITY_SHIFT 0x2
1030#define MR8_DENSITY_MASK (0xF << 0x2)
1031#define MR8_IO_WIDTH_SHIFT 0x6
1032#define MR8_IO_WIDTH_MASK (0x3 << 0x6)
1033
Lokesh Vutla9ca8bfe2013-02-04 04:21:59 +00001034/* SDRAM TYPE */
1035#define EMIF_SDRAM_TYPE_DDR2 0x2
1036#define EMIF_SDRAM_TYPE_DDR3 0x3
1037#define EMIF_SDRAM_TYPE_LPDDR2 0x4
1038
Sricharanbb772a52011-11-15 09:50:00 -05001039struct lpddr2_addressing {
1040 u8 num_banks;
1041 u8 t_REFI_us_x10;
1042 u8 row_sz[2]; /* One entry each for x32 and x16 */
1043 u8 col_sz[2]; /* One entry each for x32 and x16 */
1044};
1045
1046/* Structure for timings from the DDR datasheet */
1047struct lpddr2_ac_timings {
1048 u32 max_freq;
1049 u8 RL;
1050 u8 tRPab;
1051 u8 tRCD;
1052 u8 tWR;
1053 u8 tRASmin;
1054 u8 tRRD;
1055 u8 tWTRx2;
1056 u8 tXSR;
1057 u8 tXPx2;
1058 u8 tRFCab;
1059 u8 tRTPx2;
1060 u8 tCKE;
1061 u8 tCKESR;
1062 u8 tZQCS;
1063 u32 tZQCL;
1064 u32 tZQINIT;
1065 u8 tDQSCKMAXx2;
1066 u8 tRASmax;
1067 u8 tFAW;
1068
1069};
1070
1071/*
1072 * Min tCK values for some of the parameters:
1073 * If the calculated clock cycles for the respective parameter is
1074 * less than the corresponding min tCK value, we need to set the min
1075 * tCK value. This may happen at lower frequencies.
1076 */
1077struct lpddr2_min_tck {
1078 u32 tRL;
1079 u32 tRP_AB;
1080 u32 tRCD;
1081 u32 tWR;
1082 u32 tRAS_MIN;
1083 u32 tRRD;
1084 u32 tWTR;
1085 u32 tXP;
1086 u32 tRTP;
1087 u8 tCKE;
1088 u32 tCKESR;
1089 u32 tFAW;
1090};
1091
1092struct lpddr2_device_details {
1093 u8 type;
1094 u8 density;
1095 u8 io_width;
1096 u8 manufacturer;
1097};
1098
1099struct lpddr2_device_timings {
1100 const struct lpddr2_ac_timings **ac_timings;
1101 const struct lpddr2_min_tck *min_tck;
1102};
1103
1104/* Details of the devices connected to each chip-select of an EMIF instance */
1105struct emif_device_details {
1106 const struct lpddr2_device_details *cs0_device_details;
1107 const struct lpddr2_device_details *cs1_device_details;
1108 const struct lpddr2_device_timings *cs0_device_timings;
1109 const struct lpddr2_device_timings *cs1_device_timings;
1110};
1111
1112/*
1113 * Structure containing shadow of important registers in EMIF
1114 * The calculation function fills in this structure to be later used for
1115 * initialization and DVFS
1116 */
1117struct emif_regs {
1118 u32 freq;
1119 u32 sdram_config_init;
1120 u32 sdram_config;
Sricharan R92b04822013-05-30 03:19:39 +00001121 u32 sdram_config2;
Sricharanbb772a52011-11-15 09:50:00 -05001122 u32 ref_ctrl;
1123 u32 sdram_tim1;
1124 u32 sdram_tim2;
1125 u32 sdram_tim3;
1126 u32 read_idle_ctrl;
1127 u32 zq_config;
1128 u32 temp_alert_config;
1129 u32 emif_ddr_phy_ctlr_1_init;
1130 u32 emif_ddr_phy_ctlr_1;
SRICHARAN Rf4010732012-03-12 02:25:37 +00001131 u32 emif_ddr_ext_phy_ctrl_1;
1132 u32 emif_ddr_ext_phy_ctrl_2;
1133 u32 emif_ddr_ext_phy_ctrl_3;
1134 u32 emif_ddr_ext_phy_ctrl_4;
1135 u32 emif_ddr_ext_phy_ctrl_5;
Lokesh Vutla43037d72012-05-22 00:03:24 +00001136 u32 emif_rd_wr_lvl_rmp_win;
1137 u32 emif_rd_wr_lvl_rmp_ctl;
1138 u32 emif_rd_wr_lvl_ctl;
1139 u32 emif_rd_wr_exec_thresh;
Sricharanbb772a52011-11-15 09:50:00 -05001140};
1141
Lokesh Vutlae05a4f12013-02-04 04:22:03 +00001142struct lpddr2_mr_regs {
1143 s8 mr1;
1144 s8 mr2;
1145 s8 mr3;
1146 s8 mr10;
1147 s8 mr16;
1148};
1149
SRICHARAN R54d022e2013-11-08 17:40:38 +05301150struct read_write_regs {
1151 u32 read_reg;
1152 u32 write_reg;
1153};
1154
Lokesh Vutlad3daba12013-12-10 15:02:22 +05301155static inline u32 get_emif_rev(u32 base)
1156{
1157 struct emif_reg_struct *emif = (struct emif_reg_struct *)base;
1158
1159 return (readl(&emif->emif_mod_id_rev) & EMIF_REG_MAJOR_REVISION_MASK)
1160 >> EMIF_REG_MAJOR_REVISION_SHIFT;
1161}
1162
Lokesh Vutlab5e01ee2013-12-10 15:02:23 +05301163/*
1164 * Get SDRAM type connected to EMIF.
1165 * Assuming similar SDRAM parts are connected to both EMIF's
1166 * which is typically the case. So it is sufficient to get
1167 * SDRAM type from EMIF1.
1168 */
1169static inline u32 emif_sdram_type(void)
1170{
1171 struct emif_reg_struct *emif = (struct emif_reg_struct *)EMIF1_BASE;
1172
1173 return (readl(&emif->emif_sdram_config) &
1174 EMIF_REG_SDRAM_TYPE_MASK) >> EMIF_REG_SDRAM_TYPE_SHIFT;
1175}
1176
Sricharanbb772a52011-11-15 09:50:00 -05001177/* assert macros */
1178#if defined(DEBUG)
1179#define emif_assert(c) ({ if (!(c)) for (;;); })
1180#else
1181#define emif_assert(c) ({ if (0) hang(); })
1182#endif
1183
1184#ifdef CONFIG_SYS_EMIF_PRECALCULATED_TIMING_REGS
1185void emif_get_reg_dump(u32 emif_nr, const struct emif_regs **regs);
1186void emif_get_dmm_regs(const struct dmm_lisa_map_regs **dmm_lisa_regs);
1187#else
1188struct lpddr2_device_details *emif_get_device_details(u32 emif_nr, u8 cs,
1189 struct lpddr2_device_details *lpddr2_dev_details);
1190void emif_get_device_timings(u32 emif_nr,
1191 const struct lpddr2_device_timings **cs0_device_timings,
1192 const struct lpddr2_device_timings **cs1_device_timings);
1193#endif
1194
SRICHARAN R25476382012-06-04 03:40:23 +00001195void do_ext_phy_settings(u32 base, const struct emif_regs *regs);
Lokesh Vutlae05a4f12013-02-04 04:22:03 +00001196void get_lpddr2_mr_regs(const struct lpddr2_mr_regs **regs);
SRICHARAN R25476382012-06-04 03:40:23 +00001197
Sricharanbb772a52011-11-15 09:50:00 -05001198#ifndef CONFIG_SYS_EMIF_PRECALCULATED_TIMING_REGS
1199extern u32 *const T_num;
1200extern u32 *const T_den;
Sricharanbb772a52011-11-15 09:50:00 -05001201#endif
1202
Lokesh Vutla784ab7c2012-05-22 00:03:25 +00001203void config_data_eye_leveling_samples(u32 emif_base);
Lokesh Vutla9ca8bfe2013-02-04 04:21:59 +00001204u32 emif_sdram_type(void);
SRICHARAN R54d022e2013-11-08 17:40:38 +05301205const struct read_write_regs *get_bug_regs(u32 *iterations);
Sricharanbb772a52011-11-15 09:50:00 -05001206#endif