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Andreas Bießmanna420dfe2012-09-04 11:33:29 +00001/*
2 * Copyright (C) 2006 Atmel Corporation
3 *
4 * Copyright (C) 2012 Andreas Bießmann <andreas.devel@googlemail.com>
5 *
6 * Configuration settings for the AVR32 Network Gateway
7 *
Wolfgang Denk1a459662013-07-08 09:37:19 +02008 * SPDX-License-Identifier: GPL-2.0+
Andreas Bießmanna420dfe2012-09-04 11:33:29 +00009 */
10#ifndef __CONFIG_H
11#define __CONFIG_H
12
13#include <asm/arch/hardware.h>
14
Andreas Bießmanna420dfe2012-09-04 11:33:29 +000015#define CONFIG_AT32AP
16#define CONFIG_AT32AP7000
17#define CONFIG_ATNGW100MKII
18
19/*
Andreas Bießmanna420dfe2012-09-04 11:33:29 +000020 * Set up the PLL to run at 140 MHz, the CPU to run at the PLL
21 * frequency, the HSB and PBB busses to run at 1/2 the PLL frequency
22 * and the PBA bus to run at 1/4 the PLL frequency.
23 */
24#define CONFIG_PLL
25#define CONFIG_SYS_POWER_MANAGER
26#define CONFIG_SYS_OSC0_HZ 20000000
27#define CONFIG_SYS_PLL0_DIV 1
28#define CONFIG_SYS_PLL0_MUL 7
29#define CONFIG_SYS_PLL0_SUPPRESS_CYCLES 16
30/*
31 * Set the CPU running at:
32 * PLL / (2^CONFIG_SYS_CLKDIV_CPU) = CPU MHz
33 */
34#define CONFIG_SYS_CLKDIV_CPU 0
35/*
36 * Set the HSB running at:
37 * PLL / (2^CONFIG_SYS_CLKDIV_HSB) = HSB MHz
38 */
39#define CONFIG_SYS_CLKDIV_HSB 1
40/*
41 * Set the PBA running at:
42 * PLL / (2^CONFIG_SYS_CLKDIV_PBA) = PBA MHz
43 */
44#define CONFIG_SYS_CLKDIV_PBA 2
45/*
46 * Set the PBB running at:
47 * PLL / (2^CONFIG_SYS_CLKDIV_PBB) = PBB MHz
48 */
49#define CONFIG_SYS_CLKDIV_PBB 1
50
51/* Reserve VM regions for NOR flash, NAND flash and SDRAM */
52#define CONFIG_SYS_NR_VM_REGIONS 3
53
54/*
55 * The PLLOPT register controls the PLL like this:
56 * icp = PLLOPT<2>
57 * ivco = PLLOPT<1:0>
58 *
59 * We want icp=1 (default) and ivco=0 (80-160 MHz) or ivco=2 (150-240MHz).
60 */
61#define CONFIG_SYS_PLL0_OPT 0x04
62
63#define CONFIG_USART_BASE ATMEL_BASE_USART1
64#define CONFIG_USART_ID 1
65
66/* User serviceable stuff */
67#define CONFIG_DOS_PARTITION
68
69#define CONFIG_CMDLINE_TAG
70#define CONFIG_SETUP_MEMORY_TAGS
71#define CONFIG_INITRD_TAG
72
73#define CONFIG_STACKSIZE (2048)
74
75#define CONFIG_BAUDRATE 115200
76#define CONFIG_BOOTARGS \
77 "root=mtd:main rootfstype=jffs2"
78#define CONFIG_BOOTCOMMAND \
79 "fsload 0x10400000 /uImage; bootm"
80
81/*
82 * Only interrupt autoboot if <space> is pressed. Otherwise, garbage
83 * data on the serial line may interrupt the boot sequence.
84 */
85#define CONFIG_BOOTDELAY 1
86#define CONFIG_AUTOBOOT
87#define CONFIG_AUTOBOOT_KEYED
88#define CONFIG_AUTOBOOT_PROMPT \
89 "Press SPACE to abort autoboot in %d seconds\n", bootdelay
90#define CONFIG_AUTOBOOT_DELAY_STR "d"
91#define CONFIG_AUTOBOOT_STOP_STR " "
92
93/*
94 * After booting the board for the first time, new ethernet addresses
95 * should be generated and assigned to the environment variables
96 * "ethaddr" and "eth1addr". This is normally done during production.
97 */
98#define CONFIG_OVERWRITE_ETHADDR_ONCE
99#define CONFIG_NET_MULTI
100
101/*
102 * BOOTP/DHCP options
103 */
104#define CONFIG_BOOTP_SUBNETMASK
105#define CONFIG_BOOTP_GATEWAY
106
107/*
108 * Command line configuration.
109 */
110#include <config_cmd_default.h>
111
112#define CONFIG_CMD_ASKENV
113#define CONFIG_CMD_DHCP
114#define CONFIG_CMD_EXT2
115#define CONFIG_CMD_FAT
116#define CONFIG_CMD_JFFS2
117#define CONFIG_CMD_MMC
118#define CONFIG_CMD_SF
119#define CONFIG_CMD_SPI
120#define CONFIG_CMD_MII
121
122#undef CONFIG_CMD_FPGA
123#undef CONFIG_CMD_SETGETDCR
124#undef CONFIG_CMD_XIMG
125
126#define CONFIG_ATMEL_USART
127#define CONFIG_MACB
128#define CONFIG_PORTMUX_PIO
129#define CONFIG_SYS_NR_PIOS 5
130#define CONFIG_SYS_HSDRAMC
131#define CONFIG_MMC
132#define CONFIG_GENERIC_ATMEL_MCI
133#define CONFIG_GENERIC_MMC
Andreas Bießmanna420dfe2012-09-04 11:33:29 +0000134#define CONFIG_ATMEL_SPI
135
136#define CONFIG_SPI_FLASH
137#define CONFIG_SPI_FLASH_ATMEL
138
139#define CONFIG_SYS_DCACHE_LINESZ 32
140#define CONFIG_SYS_ICACHE_LINESZ 32
141
142#define CONFIG_NR_DRAM_BANKS 1
143
144#define CONFIG_SYS_FLASH_CFI
145#define CONFIG_FLASH_CFI_DRIVER
146#define CONFIG_SYS_FLASH_PROTECTION
147
148#define CONFIG_SYS_FLASH_BASE 0x00000000
149#define CONFIG_SYS_FLASH_SIZE 0x800000
150#define CONFIG_SYS_MAX_FLASH_BANKS 1
151#define CONFIG_SYS_MAX_FLASH_SECT 135
152
153#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE
154
155#define CONFIG_SYS_INTRAM_BASE INTERNAL_SRAM_BASE
156#define CONFIG_SYS_INTRAM_SIZE INTERNAL_SRAM_SIZE
157#define CONFIG_SYS_SDRAM_BASE EBI_SDRAM_BASE
158
159#define CONFIG_ENV_IS_IN_FLASH
160#define CONFIG_ENV_SIZE 65536
161#define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + CONFIG_SYS_FLASH_SIZE - CONFIG_ENV_SIZE)
162
163#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_INTRAM_BASE + CONFIG_SYS_INTRAM_SIZE)
164
165#define CONFIG_SYS_MALLOC_LEN (256*1024)
166#define CONFIG_SYS_DMA_ALLOC_LEN (16384)
167
168/* Allow 4MB for the kernel run-time image */
169#define CONFIG_SYS_LOAD_ADDR (EBI_SDRAM_BASE + 0x00400000)
170#define CONFIG_SYS_BOOTPARAMS_LEN (16 * 1024)
171
172/* Other configuration settings that shouldn't have to change all that often */
173#define CONFIG_SYS_PROMPT "U-Boot> "
174#define CONFIG_SYS_CBSIZE 256
175#define CONFIG_SYS_MAXARGS 16
176#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16)
177#define CONFIG_SYS_LONGHELP
178
179#define CONFIG_SYS_MEMTEST_START CONFIG_SYS_SDRAM_BASE
180#define CONFIG_SYS_MEMTEST_END (CONFIG_SYS_MEMTEST_START + 0x1f00000)
181
182#define CONFIG_MTD_DEVICE
183#define CONFIG_MTD_PARTITIONS
184
185#endif /* __CONFIG_H */