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Dave Liu19580e62007-09-18 12:37:57 +08001/*
2 * Copyright (C) 2007 Freescale Semiconductor, Inc.
3 * Dave Liu <daveliu@freescale.com>
4 *
5 * This program is free software; you can redistribute it and/or
6 * modify it under the terms of the GNU General Public License as
7 * published by the Free Software Foundation; either version 2 of
8 * the License, or (at your option) any later version.
9 *
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
14 *
15 * You should have received a copy of the GNU General Public License
16 * along with this program; if not, write to the Free Software
17 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
18 * MA 02111-1307 USA
19 */
20
21#ifndef __CONFIG_H
22#define __CONFIG_H
23
Dave Liu19580e62007-09-18 12:37:57 +080024/*
25 * High Level Configuration Options
26 */
27#define CONFIG_E300 1 /* E300 family */
Peter Tyser0f898602009-05-22 17:23:24 -050028#define CONFIG_MPC83xx 1 /* MPC83xx family */
Peter Tyser2c7920a2009-05-22 17:23:25 -050029#define CONFIG_MPC837x 1 /* MPC837x CPU specific */
Dave Liu19580e62007-09-18 12:37:57 +080030#define CONFIG_MPC837XEMDS 1 /* MPC837XEMDS board specific */
31
32/*
33 * System Clock Setup
34 */
35#ifdef CONFIG_PCISLAVE
36#define CONFIG_83XX_PCICLK 66000000 /* in HZ */
37#else
38#define CONFIG_83XX_CLKIN 66000000 /* in Hz */
39#endif
40
41#ifndef CONFIG_SYS_CLK_FREQ
42#define CONFIG_SYS_CLK_FREQ 66000000
43#endif
44
45/*
46 * Hardware Reset Configuration Word
47 * if CLKIN is 66MHz, then
48 * CSB = 396MHz, CORE = 594MHz, DDRC = 396MHz, LBC = 396MHz
49 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020050#define CONFIG_SYS_HRCW_LOW (\
Dave Liu19580e62007-09-18 12:37:57 +080051 HRCWL_LCL_BUS_TO_SCB_CLK_1X1 |\
52 HRCWL_DDR_TO_SCB_CLK_1X1 |\
53 HRCWL_SVCOD_DIV_2 |\
54 HRCWL_CSB_TO_CLKIN_6X1 |\
55 HRCWL_CORE_TO_CSB_1_5X1)
56
57#ifdef CONFIG_PCISLAVE
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020058#define CONFIG_SYS_HRCW_HIGH (\
Dave Liu19580e62007-09-18 12:37:57 +080059 HRCWH_PCI_AGENT |\
60 HRCWH_PCI1_ARBITER_DISABLE |\
61 HRCWH_CORE_ENABLE |\
62 HRCWH_FROM_0XFFF00100 |\
63 HRCWH_BOOTSEQ_DISABLE |\
64 HRCWH_SW_WATCHDOG_DISABLE |\
65 HRCWH_ROM_LOC_LOCAL_16BIT |\
66 HRCWH_RL_EXT_LEGACY |\
67 HRCWH_TSEC1M_IN_RGMII |\
68 HRCWH_TSEC2M_IN_RGMII |\
69 HRCWH_BIG_ENDIAN |\
70 HRCWH_LDP_CLEAR)
71#else
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020072#define CONFIG_SYS_HRCW_HIGH (\
Dave Liu19580e62007-09-18 12:37:57 +080073 HRCWH_PCI_HOST |\
74 HRCWH_PCI1_ARBITER_ENABLE |\
75 HRCWH_CORE_ENABLE |\
76 HRCWH_FROM_0X00000100 |\
77 HRCWH_BOOTSEQ_DISABLE |\
78 HRCWH_SW_WATCHDOG_DISABLE |\
79 HRCWH_ROM_LOC_LOCAL_16BIT |\
80 HRCWH_RL_EXT_LEGACY |\
81 HRCWH_TSEC1M_IN_RGMII |\
82 HRCWH_TSEC2M_IN_RGMII |\
83 HRCWH_BIG_ENDIAN |\
84 HRCWH_LDP_CLEAR)
85#endif
86
Dave Liubd4458c2008-03-04 16:59:22 +080087/* Arbiter Configuration Register */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020088#define CONFIG_SYS_ACR_PIPE_DEP 3 /* Arbiter pipeline depth is 4 */
89#define CONFIG_SYS_ACR_RPTCNT 3 /* Arbiter repeat count is 4 */
Dave Liubd4458c2008-03-04 16:59:22 +080090
91/* System Priority Control Register */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020092#define CONFIG_SYS_SPCR_TSECEP 3 /* eTSEC1/2 emergency has highest priority */
Dave Liubd4458c2008-03-04 16:59:22 +080093
Dave Liu19580e62007-09-18 12:37:57 +080094/*
Dave Liubd4458c2008-03-04 16:59:22 +080095 * IP blocks clock configuration
Dave Liu19580e62007-09-18 12:37:57 +080096 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020097#define CONFIG_SYS_SCCR_TSEC1CM 1 /* CSB:eTSEC1 = 1:1 */
98#define CONFIG_SYS_SCCR_TSEC2CM 1 /* CSB:eTSEC2 = 1:1 */
99#define CONFIG_SYS_SCCR_SATACM SCCR_SATACM_2 /* CSB:SATA[0:3] = 2:1 */
Dave Liu19580e62007-09-18 12:37:57 +0800100
101/*
102 * System IO Config
103 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200104#define CONFIG_SYS_SICRH 0x00000000
105#define CONFIG_SYS_SICRL 0x00000000
Dave Liu19580e62007-09-18 12:37:57 +0800106
107/*
108 * Output Buffer Impedance
109 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200110#define CONFIG_SYS_OBIR 0x31100000
Dave Liu19580e62007-09-18 12:37:57 +0800111
112#define CONFIG_BOARD_EARLY_INIT_F /* call board_pre_init */
113#define CONFIG_BOARD_EARLY_INIT_R
Anton Vorontsovc78c6782009-06-10 00:25:31 +0400114#define CONFIG_HWCONFIG
Dave Liu19580e62007-09-18 12:37:57 +0800115
116/*
117 * IMMR new address
118 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200119#define CONFIG_SYS_IMMR 0xE0000000
Dave Liu19580e62007-09-18 12:37:57 +0800120
121/*
122 * DDR Setup
123 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200124#define CONFIG_SYS_DDR_BASE 0x00000000 /* DDR is system memory */
125#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_BASE
126#define CONFIG_SYS_DDR_SDRAM_BASE CONFIG_SYS_DDR_BASE
127#define CONFIG_SYS_DDR_SDRAM_CLK_CNTL DDR_SDRAM_CLK_CNTL_CLK_ADJUST_05
128#define CONFIG_SYS_83XX_DDR_USES_CS0
129#define CONFIG_SYS_DDRCDR_VALUE 0x80080001 /* ODT 150ohm on SoC */
Dave Liu19580e62007-09-18 12:37:57 +0800130
131#undef CONFIG_DDR_ECC /* support DDR ECC function */
132#undef CONFIG_DDR_ECC_CMD /* Use DDR ECC user commands */
133
134#define CONFIG_SPD_EEPROM /* Use SPD EEPROM for DDR setup */
135#define CONFIG_NEVER_ASSERT_ODT_TO_CPU /* Never assert ODT to internal IOs */
136
137#if defined(CONFIG_SPD_EEPROM)
138#define SPD_EEPROM_ADDRESS 0x51 /* I2C address of DDR SODIMM SPD */
139#else
140/*
141 * Manually set up DDR parameters
Dave Liu7e74d632008-01-10 23:07:23 +0800142 * WHITE ELECTRONIC DESIGNS - W3HG64M72EEU403PD4 SO-DIMM
Dave Liu19580e62007-09-18 12:37:57 +0800143 * consist of nine chips from SAMSUNG K4T51083QE-ZC(L)D5
144 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200145#define CONFIG_SYS_DDR_SIZE 512 /* MB */
146#define CONFIG_SYS_DDR_CS0_BNDS 0x0000001f
147#define CONFIG_SYS_DDR_CS0_CONFIG ( CSCONFIG_EN \
Dave Liu19580e62007-09-18 12:37:57 +0800148 | 0x00010000 /* ODT_WR to CSn */ \
149 | CSCONFIG_ROW_BIT_14 | CSCONFIG_COL_BIT_10 )
150 /* 0x80010202 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200151#define CONFIG_SYS_DDR_TIMING_3 0x00000000
152#define CONFIG_SYS_DDR_TIMING_0 ( ( 0 << TIMING_CFG0_RWT_SHIFT ) \
Dave Liu19580e62007-09-18 12:37:57 +0800153 | ( 0 << TIMING_CFG0_WRT_SHIFT ) \
154 | ( 0 << TIMING_CFG0_RRT_SHIFT ) \
155 | ( 0 << TIMING_CFG0_WWT_SHIFT ) \
156 | ( 6 << TIMING_CFG0_ACT_PD_EXIT_SHIFT ) \
157 | ( 2 << TIMING_CFG0_PRE_PD_EXIT_SHIFT ) \
158 | ( 8 << TIMING_CFG0_ODT_PD_EXIT_SHIFT ) \
159 | ( 2 << TIMING_CFG0_MRS_CYC_SHIFT ) )
160 /* 0x00620802 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200161#define CONFIG_SYS_DDR_TIMING_1 ( ( 3 << TIMING_CFG1_PRETOACT_SHIFT ) \
Dave Liu19580e62007-09-18 12:37:57 +0800162 | ( 9 << TIMING_CFG1_ACTTOPRE_SHIFT ) \
163 | ( 3 << TIMING_CFG1_ACTTORW_SHIFT ) \
164 | ( 5 << TIMING_CFG1_CASLAT_SHIFT ) \
165 | (13 << TIMING_CFG1_REFREC_SHIFT ) \
166 | ( 3 << TIMING_CFG1_WRREC_SHIFT ) \
167 | ( 2 << TIMING_CFG1_ACTTOACT_SHIFT ) \
168 | ( 2 << TIMING_CFG1_WRTORD_SHIFT ) )
169 /* 0x3935d322 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200170#define CONFIG_SYS_DDR_TIMING_2 ( ( 1 << TIMING_CFG2_ADD_LAT_SHIFT ) \
Dave Liu19580e62007-09-18 12:37:57 +0800171 | ( 6 << TIMING_CFG2_CPO_SHIFT ) \
172 | ( 2 << TIMING_CFG2_WR_LAT_DELAY_SHIFT ) \
173 | ( 4 << TIMING_CFG2_RD_TO_PRE_SHIFT ) \
174 | ( 2 << TIMING_CFG2_WR_DATA_DELAY_SHIFT ) \
175 | ( 3 << TIMING_CFG2_CKE_PLS_SHIFT ) \
176 | ( 8 << TIMING_CFG2_FOUR_ACT_SHIFT) )
Dave Liu7e74d632008-01-10 23:07:23 +0800177 /* 0x131088c8 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200178#define CONFIG_SYS_DDR_INTERVAL ( ( 0x03E0 << SDRAM_INTERVAL_REFINT_SHIFT ) \
Dave Liu19580e62007-09-18 12:37:57 +0800179 | ( 0x0100 << SDRAM_INTERVAL_BSTOPRE_SHIFT ) )
180 /* 0x03E00100 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200181#define CONFIG_SYS_DDR_SDRAM_CFG 0x43000000
182#define CONFIG_SYS_DDR_SDRAM_CFG2 0x00001000 /* 1 posted refresh */
183#define CONFIG_SYS_DDR_MODE ( ( 0x0448 << SDRAM_MODE_ESD_SHIFT ) \
Dave Liu19580e62007-09-18 12:37:57 +0800184 | ( 0x1432 << SDRAM_MODE_SD_SHIFT ) )
Dave Liu7e74d632008-01-10 23:07:23 +0800185 /* ODT 150ohm CL=3, AL=1 on SDRAM */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200186#define CONFIG_SYS_DDR_MODE2 0x00000000
Dave Liu19580e62007-09-18 12:37:57 +0800187#endif
188
189/*
190 * Memory test
191 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200192#undef CONFIG_SYS_DRAM_TEST /* memory test, takes time */
193#define CONFIG_SYS_MEMTEST_START 0x00040000 /* memtest region */
194#define CONFIG_SYS_MEMTEST_END 0x00140000
Dave Liu19580e62007-09-18 12:37:57 +0800195
196/*
197 * The reserved memory
198 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200199#define CONFIG_SYS_MONITOR_BASE TEXT_BASE /* start of monitor */
Dave Liu19580e62007-09-18 12:37:57 +0800200
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200201#if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE)
202#define CONFIG_SYS_RAMBOOT
Dave Liu19580e62007-09-18 12:37:57 +0800203#else
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200204#undef CONFIG_SYS_RAMBOOT
Dave Liu19580e62007-09-18 12:37:57 +0800205#endif
206
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200207/* CONFIG_SYS_MONITOR_LEN must be a multiple of CONFIG_ENV_SECT_SIZE */
Anton Vorontsovb3379f32008-10-08 20:52:54 +0400208#define CONFIG_SYS_MONITOR_LEN (384 * 1024) /* Reserve 384 kB for Mon */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200209#define CONFIG_SYS_MALLOC_LEN (512 * 1024) /* Reserved for malloc */
Dave Liu19580e62007-09-18 12:37:57 +0800210
211/*
212 * Initial RAM Base Address Setup
213 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200214#define CONFIG_SYS_INIT_RAM_LOCK 1
215#define CONFIG_SYS_INIT_RAM_ADDR 0xE6000000 /* Initial RAM address */
216#define CONFIG_SYS_INIT_RAM_END 0x1000 /* End of used area in RAM */
217#define CONFIG_SYS_GBL_DATA_SIZE 0x100 /* num bytes initial data */
218#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE)
Dave Liu19580e62007-09-18 12:37:57 +0800219
220/*
221 * Local Bus Configuration & Clock Setup
222 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200223#define CONFIG_SYS_LCRR (LCRR_DBYP | LCRR_CLKDIV_8)
224#define CONFIG_SYS_LBC_LBCR 0x00000000
Dave Liu19580e62007-09-18 12:37:57 +0800225
226/*
227 * FLASH on the Local Bus
228 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200229#define CONFIG_SYS_FLASH_CFI /* use the Common Flash Interface */
Jean-Christophe PLAGNIOL-VILLARD00b18832008-08-13 01:40:42 +0200230#define CONFIG_FLASH_CFI_DRIVER /* use the CFI driver */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200231#define CONFIG_SYS_FLASH_BASE 0xFE000000 /* FLASH base address */
232#define CONFIG_SYS_FLASH_SIZE 32 /* max FLASH size is 32M */
233#define CONFIG_SYS_FLASH_PROTECTION 1 /* Use h/w Flash protection. */
Dave Liu19580e62007-09-18 12:37:57 +0800234
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200235#define CONFIG_SYS_LBLAWBAR0_PRELIM CONFIG_SYS_FLASH_BASE /* Window base at flash base */
236#define CONFIG_SYS_LBLAWAR0_PRELIM 0x80000018 /* 32MB window size */
Dave Liu19580e62007-09-18 12:37:57 +0800237
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200238#define CONFIG_SYS_BR0_PRELIM ( CONFIG_SYS_FLASH_BASE /* Flash Base address */ \
Dave Liuded08312008-01-10 23:08:26 +0800239 | (2 << BR_PS_SHIFT) /* 16 bit port size */ \
240 | BR_V ) /* valid */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200241#define CONFIG_SYS_OR0_PRELIM ( (~(CONFIG_SYS_FLASH_SIZE - 1) << 20) \
Dave Liuded08312008-01-10 23:08:26 +0800242 | OR_UPM_XAM \
243 | OR_GPCM_CSNT \
Anton Vorontsovf9023af2008-05-29 18:14:56 +0400244 | OR_GPCM_ACS_DIV2 \
Dave Liuded08312008-01-10 23:08:26 +0800245 | OR_GPCM_XACS \
246 | OR_GPCM_SCY_15 \
247 | OR_GPCM_TRLX \
248 | OR_GPCM_EHTR \
249 | OR_GPCM_EAD )
250 /* 0xFE000FF7 */
Dave Liu19580e62007-09-18 12:37:57 +0800251
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200252#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* number of banks */
253#define CONFIG_SYS_MAX_FLASH_SECT 256 /* max sectors per device */
Dave Liu19580e62007-09-18 12:37:57 +0800254
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200255#undef CONFIG_SYS_FLASH_CHECKSUM
256#define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */
257#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */
Dave Liu19580e62007-09-18 12:37:57 +0800258
259/*
260 * BCSR on the Local Bus
261 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200262#define CONFIG_SYS_BCSR 0xF8000000
263#define CONFIG_SYS_LBLAWBAR1_PRELIM CONFIG_SYS_BCSR /* Access window base at BCSR base */
264#define CONFIG_SYS_LBLAWAR1_PRELIM 0x8000000E /* Access window size 32K */
Dave Liu19580e62007-09-18 12:37:57 +0800265
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200266#define CONFIG_SYS_BR1_PRELIM (CONFIG_SYS_BCSR | 0x00000801) /* Port size=8bit, MSEL=GPCM */
267#define CONFIG_SYS_OR1_PRELIM 0xFFFFE9f7 /* length 32K */
Dave Liu19580e62007-09-18 12:37:57 +0800268
269/*
270 * NAND Flash on the Local Bus
271 */
Anton Vorontsovb3379f32008-10-08 20:52:54 +0400272#define CONFIG_CMD_NAND 1
273#define CONFIG_MTD_NAND_VERIFY_WRITE 1
274#define CONFIG_SYS_MAX_NAND_DEVICE 1
Anton Vorontsovb3379f32008-10-08 20:52:54 +0400275#define CONFIG_NAND_FSL_ELBC 1
276
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200277#define CONFIG_SYS_NAND_BASE 0xE0600000 /* 0xE0600000 */
278#define CONFIG_SYS_BR3_PRELIM ( CONFIG_SYS_NAND_BASE \
Dave Liu19580e62007-09-18 12:37:57 +0800279 | (2<<BR_DECC_SHIFT) /* Use HW ECC */ \
280 | BR_PS_8 /* Port Size = 8 bit */ \
281 | BR_MS_FCM /* MSEL = FCM */ \
282 | BR_V ) /* valid */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200283#define CONFIG_SYS_OR3_PRELIM ( 0xFFFF8000 /* length 32K */ \
Anton Vorontsovb3379f32008-10-08 20:52:54 +0400284 | OR_FCM_BCTLD \
Dave Liu19580e62007-09-18 12:37:57 +0800285 | OR_FCM_CST \
286 | OR_FCM_CHT \
287 | OR_FCM_SCY_1 \
Anton Vorontsovb3379f32008-10-08 20:52:54 +0400288 | OR_FCM_RST \
Dave Liu19580e62007-09-18 12:37:57 +0800289 | OR_FCM_TRLX \
290 | OR_FCM_EHTR )
Anton Vorontsovb3379f32008-10-08 20:52:54 +0400291 /* 0xFFFF919E */
Dave Liu19580e62007-09-18 12:37:57 +0800292
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200293#define CONFIG_SYS_LBLAWBAR3_PRELIM CONFIG_SYS_NAND_BASE
294#define CONFIG_SYS_LBLAWAR3_PRELIM 0x8000000E /* 32KB */
Dave Liu19580e62007-09-18 12:37:57 +0800295
296/*
297 * Serial Port
298 */
299#define CONFIG_CONS_INDEX 1
300#undef CONFIG_SERIAL_SOFTWARE_FIFO
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200301#define CONFIG_SYS_NS16550
302#define CONFIG_SYS_NS16550_SERIAL
303#define CONFIG_SYS_NS16550_REG_SIZE 1
304#define CONFIG_SYS_NS16550_CLK get_bus_freq(0)
Dave Liu19580e62007-09-18 12:37:57 +0800305
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200306#define CONFIG_SYS_BAUDRATE_TABLE \
Dave Liu19580e62007-09-18 12:37:57 +0800307 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200}
308
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200309#define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_IMMR+0x4500)
310#define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_IMMR+0x4600)
Dave Liu19580e62007-09-18 12:37:57 +0800311
312/* Use the HUSH parser */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200313#define CONFIG_SYS_HUSH_PARSER
314#ifdef CONFIG_SYS_HUSH_PARSER
315#define CONFIG_SYS_PROMPT_HUSH_PS2 "> "
Dave Liu19580e62007-09-18 12:37:57 +0800316#endif
317
318/* Pass open firmware flat tree */
319#define CONFIG_OF_LIBFDT 1
320#define CONFIG_OF_BOARD_SETUP 1
Kim Phillips5b8bc602007-12-20 14:09:22 -0600321#define CONFIG_OF_STDOUT_VIA_ALIAS 1
Dave Liu19580e62007-09-18 12:37:57 +0800322
Andy Fleminge1ac3872008-10-30 16:50:14 -0500323#define CONFIG_SYS_64BIT_STRTOUL 1
324#define CONFIG_SYS_64BIT_VSPRINTF 1
325
Dave Liu19580e62007-09-18 12:37:57 +0800326/* I2C */
327#define CONFIG_HARD_I2C /* I2C with hardware support */
328#undef CONFIG_SOFT_I2C /* I2C bit-banged */
329#define CONFIG_FSL_I2C
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200330#define CONFIG_SYS_I2C_SPEED 400000 /* I2C speed and slave address */
331#define CONFIG_SYS_I2C_SLAVE 0x7F
332#define CONFIG_SYS_I2C_NOPROBES {0x51} /* Don't probe these addrs */
333#define CONFIG_SYS_I2C_OFFSET 0x3000
334#define CONFIG_SYS_I2C2_OFFSET 0x3100
Dave Liu19580e62007-09-18 12:37:57 +0800335
336/*
337 * Config on-board RTC
338 */
339#define CONFIG_RTC_DS1374 /* use ds1374 rtc via i2c */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200340#define CONFIG_SYS_I2C_RTC_ADDR 0x68 /* at address 0x68 */
Dave Liu19580e62007-09-18 12:37:57 +0800341
342/*
343 * General PCI
344 * Addresses are mapped 1-1.
345 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200346#define CONFIG_SYS_PCI_MEM_BASE 0x80000000
347#define CONFIG_SYS_PCI_MEM_PHYS CONFIG_SYS_PCI_MEM_BASE
348#define CONFIG_SYS_PCI_MEM_SIZE 0x10000000 /* 256M */
349#define CONFIG_SYS_PCI_MMIO_BASE 0x90000000
350#define CONFIG_SYS_PCI_MMIO_PHYS CONFIG_SYS_PCI_MMIO_BASE
351#define CONFIG_SYS_PCI_MMIO_SIZE 0x10000000 /* 256M */
352#define CONFIG_SYS_PCI_IO_BASE 0x00000000
353#define CONFIG_SYS_PCI_IO_PHYS 0xE0300000
354#define CONFIG_SYS_PCI_IO_SIZE 0x100000 /* 1M */
Dave Liu19580e62007-09-18 12:37:57 +0800355
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200356#define CONFIG_SYS_PCI_SLV_MEM_LOCAL CONFIG_SYS_SDRAM_BASE
357#define CONFIG_SYS_PCI_SLV_MEM_BUS 0x00000000
358#define CONFIG_SYS_PCI_SLV_MEM_SIZE 0x80000000
Dave Liu19580e62007-09-18 12:37:57 +0800359
Anton Vorontsov8b345572009-01-08 04:26:19 +0300360#define CONFIG_SYS_PCIE1_BASE 0xA0000000
361#define CONFIG_SYS_PCIE1_CFG_BASE 0xA0000000
362#define CONFIG_SYS_PCIE1_CFG_SIZE 0x08000000
363#define CONFIG_SYS_PCIE1_MEM_BASE 0xA8000000
364#define CONFIG_SYS_PCIE1_MEM_PHYS 0xA8000000
365#define CONFIG_SYS_PCIE1_MEM_SIZE 0x10000000
366#define CONFIG_SYS_PCIE1_IO_BASE 0x00000000
367#define CONFIG_SYS_PCIE1_IO_PHYS 0xB8000000
368#define CONFIG_SYS_PCIE1_IO_SIZE 0x00800000
369
370#define CONFIG_SYS_PCIE2_BASE 0xC0000000
371#define CONFIG_SYS_PCIE2_CFG_BASE 0xC0000000
372#define CONFIG_SYS_PCIE2_CFG_SIZE 0x08000000
373#define CONFIG_SYS_PCIE2_MEM_BASE 0xC8000000
374#define CONFIG_SYS_PCIE2_MEM_PHYS 0xC8000000
375#define CONFIG_SYS_PCIE2_MEM_SIZE 0x10000000
376#define CONFIG_SYS_PCIE2_IO_BASE 0x00000000
377#define CONFIG_SYS_PCIE2_IO_PHYS 0xD8000000
378#define CONFIG_SYS_PCIE2_IO_SIZE 0x00800000
379
Dave Liu19580e62007-09-18 12:37:57 +0800380#ifdef CONFIG_PCI
Anton Vorontsov00f7bba2008-10-02 19:17:33 +0400381#ifndef __ASSEMBLY__
382extern int board_pci_host_broken(void);
383#endif
Kim Phillipsbe9b56d2009-07-23 14:09:38 -0500384#define CONFIG_PCIE
Dave Liu19580e62007-09-18 12:37:57 +0800385#define CONFIG_PQ_MDS_PIB 1 /* PQ MDS Platform IO Board */
386
Anton Vorontsov3bf1be32008-10-14 22:58:53 +0400387#define CONFIG_HAS_FSL_DR_USB 1 /* fixup device tree for the DR USB */
388
Dave Liu19580e62007-09-18 12:37:57 +0800389#define CONFIG_NET_MULTI
390#define CONFIG_PCI_PNP /* do pci plug-and-play */
391
392#undef CONFIG_EEPRO100
393#undef CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200394#define CONFIG_SYS_PCI_SUBSYS_VENDORID 0x1957 /* Freescale */
Dave Liu19580e62007-09-18 12:37:57 +0800395#endif /* CONFIG_PCI */
396
397#ifndef CONFIG_NET_MULTI
398#define CONFIG_NET_MULTI 1
399#endif
400
401/*
402 * TSEC
403 */
404#define CONFIG_TSEC_ENET /* TSEC ethernet support */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200405#define CONFIG_SYS_TSEC1_OFFSET 0x24000
406#define CONFIG_SYS_TSEC1 (CONFIG_SYS_IMMR+CONFIG_SYS_TSEC1_OFFSET)
407#define CONFIG_SYS_TSEC2_OFFSET 0x25000
408#define CONFIG_SYS_TSEC2 (CONFIG_SYS_IMMR+CONFIG_SYS_TSEC2_OFFSET)
Dave Liu19580e62007-09-18 12:37:57 +0800409
410/*
411 * TSEC ethernet configuration
412 */
413#define CONFIG_MII 1 /* MII PHY management */
414#define CONFIG_TSEC1 1
415#define CONFIG_TSEC1_NAME "eTSEC0"
416#define CONFIG_TSEC2 1
417#define CONFIG_TSEC2_NAME "eTSEC1"
418#define TSEC1_PHY_ADDR 2
419#define TSEC2_PHY_ADDR 3
Anton Vorontsov1da83a62008-10-02 18:32:25 +0400420#define TSEC1_PHY_ADDR_SGMII 8
421#define TSEC2_PHY_ADDR_SGMII 4
Dave Liu19580e62007-09-18 12:37:57 +0800422#define TSEC1_PHYIDX 0
423#define TSEC2_PHYIDX 0
424#define TSEC1_FLAGS (TSEC_GIGABIT | TSEC_REDUCED)
425#define TSEC2_FLAGS (TSEC_GIGABIT | TSEC_REDUCED)
426
427/* Options are: TSEC[0-1] */
428#define CONFIG_ETHPRIME "eTSEC1"
429
Dave Liu6f8c85e2008-03-26 22:56:36 +0800430/* SERDES */
431#define CONFIG_FSL_SERDES
432#define CONFIG_FSL_SERDES1 0xe3000
433#define CONFIG_FSL_SERDES2 0xe3100
434
Dave Liu19580e62007-09-18 12:37:57 +0800435/*
Dave Liu2eeb3e42008-03-26 22:57:19 +0800436 * SATA
437 */
438#define CONFIG_LIBATA
439#define CONFIG_FSL_SATA
440
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200441#define CONFIG_SYS_SATA_MAX_DEVICE 2
Dave Liu2eeb3e42008-03-26 22:57:19 +0800442#define CONFIG_SATA1
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200443#define CONFIG_SYS_SATA1_OFFSET 0x18000
444#define CONFIG_SYS_SATA1 (CONFIG_SYS_IMMR + CONFIG_SYS_SATA1_OFFSET)
445#define CONFIG_SYS_SATA1_FLAGS FLAGS_DMA
Dave Liu2eeb3e42008-03-26 22:57:19 +0800446#define CONFIG_SATA2
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200447#define CONFIG_SYS_SATA2_OFFSET 0x19000
448#define CONFIG_SYS_SATA2 (CONFIG_SYS_IMMR + CONFIG_SYS_SATA2_OFFSET)
449#define CONFIG_SYS_SATA2_FLAGS FLAGS_DMA
Dave Liu2eeb3e42008-03-26 22:57:19 +0800450
451#ifdef CONFIG_FSL_SATA
452#define CONFIG_LBA48
453#define CONFIG_CMD_SATA
454#define CONFIG_DOS_PARTITION
455#define CONFIG_CMD_EXT2
456#endif
457
458/*
Dave Liu19580e62007-09-18 12:37:57 +0800459 * Environment
460 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200461#ifndef CONFIG_SYS_RAMBOOT
Jean-Christophe PLAGNIOL-VILLARD5a1aceb2008-09-10 22:48:04 +0200462 #define CONFIG_ENV_IS_IN_FLASH 1
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200463 #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE + CONFIG_SYS_MONITOR_LEN)
Jean-Christophe PLAGNIOL-VILLARD0e8d1582008-09-10 22:48:06 +0200464 #define CONFIG_ENV_SECT_SIZE 0x20000 /* 128K(one sector) for env */
465 #define CONFIG_ENV_SIZE 0x2000
Dave Liu19580e62007-09-18 12:37:57 +0800466#else
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200467 #define CONFIG_SYS_NO_FLASH 1 /* Flash is not usable now */
Jean-Christophe PLAGNIOL-VILLARD93f6d722008-09-10 22:48:00 +0200468 #define CONFIG_ENV_IS_NOWHERE 1 /* Store ENV in memory only */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200469 #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - 0x1000)
Jean-Christophe PLAGNIOL-VILLARD0e8d1582008-09-10 22:48:06 +0200470 #define CONFIG_ENV_SIZE 0x2000
Dave Liu19580e62007-09-18 12:37:57 +0800471#endif
472
473#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200474#define CONFIG_SYS_LOADS_BAUD_CHANGE 1 /* allow baudrate change */
Dave Liu19580e62007-09-18 12:37:57 +0800475
476/*
477 * BOOTP options
478 */
479#define CONFIG_BOOTP_BOOTFILESIZE
480#define CONFIG_BOOTP_BOOTPATH
481#define CONFIG_BOOTP_GATEWAY
482#define CONFIG_BOOTP_HOSTNAME
483
484
485/*
486 * Command line configuration.
487 */
488#include <config_cmd_default.h>
489
490#define CONFIG_CMD_PING
491#define CONFIG_CMD_I2C
492#define CONFIG_CMD_MII
493#define CONFIG_CMD_DATE
494
495#if defined(CONFIG_PCI)
496 #define CONFIG_CMD_PCI
497#endif
498
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200499#if defined(CONFIG_SYS_RAMBOOT)
Mike Frysingerbdab39d2009-01-28 19:08:14 -0500500 #undef CONFIG_CMD_SAVEENV
Dave Liu19580e62007-09-18 12:37:57 +0800501 #undef CONFIG_CMD_LOADS
502#endif
503
504#define CONFIG_CMDLINE_EDITING 1 /* add command line history */
505
506#undef CONFIG_WATCHDOG /* watchdog disabled */
507
Andy Fleminge1ac3872008-10-30 16:50:14 -0500508#define CONFIG_MMC 1
509
510#ifdef CONFIG_MMC
511#define CONFIG_FSL_ESDHC
512#define CONFIG_SYS_FSL_ESDHC_ADDR CONFIG_SYS_MPC83xx_ESDHC_ADDR
513#define CONFIG_CMD_MMC
514#define CONFIG_GENERIC_MMC
515#define CONFIG_CMD_EXT2
516#define CONFIG_CMD_FAT
517#define CONFIG_DOS_PARTITION
518#endif
519
Dave Liu19580e62007-09-18 12:37:57 +0800520/*
521 * Miscellaneous configurable options
522 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200523#define CONFIG_SYS_LONGHELP /* undef to save memory */
524#define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */
525#define CONFIG_SYS_PROMPT "=> " /* Monitor Command Prompt */
Dave Liu19580e62007-09-18 12:37:57 +0800526
527#if defined(CONFIG_CMD_KGDB)
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200528 #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
Dave Liu19580e62007-09-18 12:37:57 +0800529#else
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200530 #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
Dave Liu19580e62007-09-18 12:37:57 +0800531#endif
532
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200533#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
534#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
535#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */
536#define CONFIG_SYS_HZ 1000 /* decrementer freq: 1ms ticks */
Dave Liu19580e62007-09-18 12:37:57 +0800537
538/*
539 * For booting Linux, the board info and command line data
540 * have to be in the first 8 MB of memory, since this is
541 * the maximum mapped by the Linux kernel during initialization.
542 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200543#define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
Dave Liu19580e62007-09-18 12:37:57 +0800544
545/*
546 * Core HID Setup
547 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200548#define CONFIG_SYS_HID0_INIT 0x000000000
549#define CONFIG_SYS_HID0_FINAL HID0_ENABLE_MACHINE_CHECK
550#define CONFIG_SYS_HID2 HID2_HBE
Dave Liu19580e62007-09-18 12:37:57 +0800551
552/*
Dave Liu19580e62007-09-18 12:37:57 +0800553 * MMU Setup
554 */
Becky Bruce31d82672008-05-08 19:02:12 -0500555#define CONFIG_HIGH_BATS 1 /* High BATs supported */
Dave Liu19580e62007-09-18 12:37:57 +0800556
557/* DDR: cache cacheable */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200558#define CONFIG_SYS_SDRAM_LOWER CONFIG_SYS_SDRAM_BASE
559#define CONFIG_SYS_SDRAM_UPPER (CONFIG_SYS_SDRAM_BASE + 0x10000000)
Dave Liu19580e62007-09-18 12:37:57 +0800560
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200561#define CONFIG_SYS_IBAT0L (CONFIG_SYS_SDRAM_LOWER | BATL_PP_10 | BATL_MEMCOHERENCE)
562#define CONFIG_SYS_IBAT0U (CONFIG_SYS_SDRAM_LOWER | BATU_BL_256M | BATU_VS | BATU_VP)
563#define CONFIG_SYS_DBAT0L CONFIG_SYS_IBAT0L
564#define CONFIG_SYS_DBAT0U CONFIG_SYS_IBAT0U
Dave Liu19580e62007-09-18 12:37:57 +0800565
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200566#define CONFIG_SYS_IBAT1L (CONFIG_SYS_SDRAM_UPPER | BATL_PP_10 | BATL_MEMCOHERENCE)
567#define CONFIG_SYS_IBAT1U (CONFIG_SYS_SDRAM_UPPER | BATU_BL_256M | BATU_VS | BATU_VP)
568#define CONFIG_SYS_DBAT1L CONFIG_SYS_IBAT1L
569#define CONFIG_SYS_DBAT1U CONFIG_SYS_IBAT1U
Dave Liu19580e62007-09-18 12:37:57 +0800570
571/* IMMRBAR, PCI IO and NAND: cache-inhibit and guarded */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200572#define CONFIG_SYS_IBAT2L (CONFIG_SYS_IMMR | BATL_PP_10 | \
Dave Liu19580e62007-09-18 12:37:57 +0800573 BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200574#define CONFIG_SYS_IBAT2U (CONFIG_SYS_IMMR | BATU_BL_8M | BATU_VS | BATU_VP)
575#define CONFIG_SYS_DBAT2L CONFIG_SYS_IBAT2L
576#define CONFIG_SYS_DBAT2U CONFIG_SYS_IBAT2U
Dave Liu19580e62007-09-18 12:37:57 +0800577
578/* BCSR: cache-inhibit and guarded */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200579#define CONFIG_SYS_IBAT3L (CONFIG_SYS_BCSR | BATL_PP_10 | \
Dave Liu19580e62007-09-18 12:37:57 +0800580 BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200581#define CONFIG_SYS_IBAT3U (CONFIG_SYS_BCSR | BATU_BL_128K | BATU_VS | BATU_VP)
582#define CONFIG_SYS_DBAT3L CONFIG_SYS_IBAT3L
583#define CONFIG_SYS_DBAT3U CONFIG_SYS_IBAT3U
Dave Liu19580e62007-09-18 12:37:57 +0800584
585/* FLASH: icache cacheable, but dcache-inhibit and guarded */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200586#define CONFIG_SYS_IBAT4L (CONFIG_SYS_FLASH_BASE | BATL_PP_10 | BATL_MEMCOHERENCE)
587#define CONFIG_SYS_IBAT4U (CONFIG_SYS_FLASH_BASE | BATU_BL_32M | BATU_VS | BATU_VP)
588#define CONFIG_SYS_DBAT4L (CONFIG_SYS_FLASH_BASE | BATL_PP_10 | \
Dave Liu19580e62007-09-18 12:37:57 +0800589 BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200590#define CONFIG_SYS_DBAT4U CONFIG_SYS_IBAT4U
Dave Liu19580e62007-09-18 12:37:57 +0800591
592/* Stack in dcache: cacheable, no memory coherence */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200593#define CONFIG_SYS_IBAT5L (CONFIG_SYS_INIT_RAM_ADDR | BATL_PP_10)
594#define CONFIG_SYS_IBAT5U (CONFIG_SYS_INIT_RAM_ADDR | BATU_BL_128K | BATU_VS | BATU_VP)
595#define CONFIG_SYS_DBAT5L CONFIG_SYS_IBAT5L
596#define CONFIG_SYS_DBAT5U CONFIG_SYS_IBAT5U
Dave Liu19580e62007-09-18 12:37:57 +0800597
598#ifdef CONFIG_PCI
599/* PCI MEM space: cacheable */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200600#define CONFIG_SYS_IBAT6L (CONFIG_SYS_PCI_MEM_PHYS | BATL_PP_10 | BATL_MEMCOHERENCE)
601#define CONFIG_SYS_IBAT6U (CONFIG_SYS_PCI_MEM_PHYS | BATU_BL_256M | BATU_VS | BATU_VP)
602#define CONFIG_SYS_DBAT6L CONFIG_SYS_IBAT6L
603#define CONFIG_SYS_DBAT6U CONFIG_SYS_IBAT6U
Dave Liu19580e62007-09-18 12:37:57 +0800604/* PCI MMIO space: cache-inhibit and guarded */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200605#define CONFIG_SYS_IBAT7L (CONFIG_SYS_PCI_MMIO_PHYS | BATL_PP_10 | \
Dave Liu19580e62007-09-18 12:37:57 +0800606 BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200607#define CONFIG_SYS_IBAT7U (CONFIG_SYS_PCI_MMIO_PHYS | BATU_BL_256M | BATU_VS | BATU_VP)
608#define CONFIG_SYS_DBAT7L CONFIG_SYS_IBAT7L
609#define CONFIG_SYS_DBAT7U CONFIG_SYS_IBAT7U
Dave Liu19580e62007-09-18 12:37:57 +0800610#else
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200611#define CONFIG_SYS_IBAT6L (0)
612#define CONFIG_SYS_IBAT6U (0)
613#define CONFIG_SYS_IBAT7L (0)
614#define CONFIG_SYS_IBAT7U (0)
615#define CONFIG_SYS_DBAT6L CONFIG_SYS_IBAT6L
616#define CONFIG_SYS_DBAT6U CONFIG_SYS_IBAT6U
617#define CONFIG_SYS_DBAT7L CONFIG_SYS_IBAT7L
618#define CONFIG_SYS_DBAT7U CONFIG_SYS_IBAT7U
Dave Liu19580e62007-09-18 12:37:57 +0800619#endif
620
621/*
622 * Internal Definitions
623 *
624 * Boot Flags
625 */
626#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */
627#define BOOTFLAG_WARM 0x02 /* Software reboot */
628
629#if defined(CONFIG_CMD_KGDB)
630#define CONFIG_KGDB_BAUDRATE 230400 /* speed of kgdb serial port */
631#define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */
632#endif
633
634/*
635 * Environment Configuration
636 */
637
638#define CONFIG_ENV_OVERWRITE
639
640#if defined(CONFIG_TSEC_ENET)
641#define CONFIG_HAS_ETH0
642#define CONFIG_ETHADDR 00:E0:0C:00:83:79
643#define CONFIG_HAS_ETH1
644#define CONFIG_ETH1ADDR 00:E0:0C:00:83:78
645#endif
646
647#define CONFIG_BAUDRATE 115200
648
Kim Phillips79f516b2009-08-21 16:34:38 -0500649#define CONFIG_LOADADDR 800000 /* default location for tftp and bootm */
Dave Liu19580e62007-09-18 12:37:57 +0800650
651#define CONFIG_BOOTDELAY 6 /* -1 disables auto-boot */
652#undef CONFIG_BOOTARGS /* the boot command will set bootargs */
653
654#define CONFIG_EXTRA_ENV_SETTINGS \
655 "netdev=eth0\0" \
656 "consoledev=ttyS0\0" \
657 "ramdiskaddr=1000000\0" \
658 "ramdiskfile=ramfs.83xx\0" \
Kim Phillips79f516b2009-08-21 16:34:38 -0500659 "fdtaddr=780000\0" \
Kim Phillips270fe262008-03-07 12:27:31 -0600660 "fdtfile=mpc8379_mds.dtb\0" \
Dave Liu19580e62007-09-18 12:37:57 +0800661 ""
662
663#define CONFIG_NFSBOOTCOMMAND \
664 "setenv bootargs root=/dev/nfs rw " \
665 "nfsroot=$serverip:$rootpath " \
666 "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \
667 "console=$consoledev,$baudrate $othbootargs;" \
668 "tftp $loadaddr $bootfile;" \
669 "tftp $fdtaddr $fdtfile;" \
670 "bootm $loadaddr - $fdtaddr"
671
672#define CONFIG_RAMBOOTCOMMAND \
673 "setenv bootargs root=/dev/ram rw " \
674 "console=$consoledev,$baudrate $othbootargs;" \
675 "tftp $ramdiskaddr $ramdiskfile;" \
676 "tftp $loadaddr $bootfile;" \
677 "tftp $fdtaddr $fdtfile;" \
678 "bootm $loadaddr $ramdiskaddr $fdtaddr"
679
680
681#define CONFIG_BOOTCOMMAND CONFIG_NFSBOOTCOMMAND
682
683#endif /* __CONFIG_H */