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Haiying Wang765547d2009-03-27 17:02:45 -04001/*
Kumar Gala4c2e3da2009-07-28 21:49:52 -05002 * Copyright (C) 2009 Freescale Semiconductor, Inc.
Haiying Wang765547d2009-03-27 17:02:45 -04003 *
4 * See file CREDITS for list of people who contributed to this
5 * project.
6 *
7 * This program is free software; you can redistribute it and/or
8 * modify it under the terms of the GNU General Public License as
9 * published by the Free Software Foundation; either version 2 of
10 * the License, or (at your option) any later version.
11 *
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
16 *
17 * You should have received a copy of the GNU General Public License
18 * along with this program; if not, write to the Free Software
19 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
20 * MA 02111-1307 USA
21 */
22
23/*
24 * mpc8569mds board configuration file
25 */
26#ifndef __CONFIG_H
27#define __CONFIG_H
28
29/* High Level Configuration Options */
30#define CONFIG_BOOKE 1 /* BOOKE */
31#define CONFIG_E500 1 /* BOOKE e500 family */
32#define CONFIG_MPC85xx 1 /* MPC8540/60/55/41/48/68 */
33#define CONFIG_MPC8569 1 /* MPC8569 specific */
34#define CONFIG_MPC8569MDS 1 /* MPC8569MDS board specific */
35
36#define CONFIG_FSL_ELBC 1 /* Has Enhance localbus controller */
37
38#define CONFIG_PCI 1 /* Disable PCI/PCIE */
39#define CONFIG_PCIE1 1 /* PCIE controller */
40#define CONFIG_FSL_PCI_INIT 1 /* use common fsl pci init code */
41#define CONFIG_FSL_PCIE_RESET 1 /* need PCIe reset errata */
42#define CONFIG_SYS_PCI_64BIT 1 /* enable 64-bit PCI resources */
43#define CONFIG_QE /* Enable QE */
44#define CONFIG_ENV_OVERWRITE
45#define CONFIG_FSL_LAW 1 /* Use common FSL init code */
46
47/*
48 * When initializing flash, if we cannot find the manufacturer ID,
49 * assume this is the AMD flash associated with the MDS board.
50 * This allows booting from a promjet.
51 */
52#define CONFIG_ASSUME_AMD_FLASH
53
54#ifndef __ASSEMBLY__
55extern unsigned long get_clock_freq(void);
56#endif
57/* Replace a call to get_clock_freq (after it is implemented)*/
Dave Liu67351042009-05-18 17:49:23 +080058#define CONFIG_SYS_CLK_FREQ 66666666
59#define CONFIG_DDR_CLK_FREQ CONFIG_SYS_CLK_FREQ
Haiying Wang765547d2009-03-27 17:02:45 -040060
61/*
62 * These can be toggled for performance analysis, otherwise use default.
63 */
64#define CONFIG_L2_CACHE /* toggle L2 cache */
65#define CONFIG_BTB /* toggle branch predition */
66
67/*
68 * Only possible on E500 Version 2 or newer cores.
69 */
70#define CONFIG_ENABLE_36BIT_PHYS 1
71
72#define CONFIG_BOARD_EARLY_INIT_F 1 /* Call board_pre_init */
73
74#define CONFIG_SYS_MEMTEST_START 0x00200000 /* memtest works on */
75#define CONFIG_SYS_MEMTEST_END 0x00400000
76
77/*
78 * Base addresses -- Note these are effective addresses where the
79 * actual resources get mapped (not physical addresses)
80 */
81#define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000 /* CCSRBAR Default */
82#define CONFIG_SYS_CCSRBAR 0xe0000000 /* relocated CCSRBAR */
83#define CONFIG_SYS_CCSRBAR_PHYS CONFIG_SYS_CCSRBAR
84 /* physical addr of CCSRBAR */
85#define CONFIG_SYS_IMMR CONFIG_SYS_CCSRBAR
86 /* PQII uses CONFIG_SYS_IMMR */
87
88#define CONFIG_SYS_PCI1_ADDR (CONFIG_SYS_CCSRBAR+0x8000)
89#define CONFIG_SYS_PCIE1_ADDR (CONFIG_SYS_CCSRBAR+0xa000)
90
91/* DDR Setup */
92#define CONFIG_FSL_DDR3
93#undef CONFIG_FSL_DDR_INTERACTIVE
94#define CONFIG_SPD_EEPROM /* Use SPD EEPROM for DDR setup*/
95#define CONFIG_DDR_SPD
96#define CONFIG_DDR_DLL /* possible DLL fix needed */
97#define CONFIG_ECC_INIT_VIA_DDRCONTROLLER /* DDR controller or DMA? */
98
99#define CONFIG_MEM_INIT_VALUE 0xDeadBeef
100
101#define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000
102 /* DDR is system memory*/
103#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE
104
105#define CONFIG_NUM_DDR_CONTROLLERS 1
106#define CONFIG_DIMM_SLOTS_PER_CTLR 1
107#define CONFIG_CHIP_SELECTS_PER_CTRL (2 * CONFIG_DIMM_SLOTS_PER_CTLR)
108
109/* I2C addresses of SPD EEPROMs */
110#define SPD_EEPROM_ADDRESS1 0x51 /* CTLR 0 DIMM 0 */
111#define SPD_EEPROM_ADDRESS2 0x52 /* CTLR 1 DIMM 0 */
112
113/* These are used when DDR doesn't use SPD. */
114#define CONFIG_SYS_SDRAM_SIZE 1024 /* DDR is 1024MB */
115#define CONFIG_SYS_DDR_CS0_BNDS 0x0000003F
116#define CONFIG_SYS_DDR_CS0_CONFIG 0x80014202
117#define CONFIG_SYS_DDR_TIMING_3 0x00020000
118#define CONFIG_SYS_DDR_TIMING_0 0x00330004
119#define CONFIG_SYS_DDR_TIMING_1 0x6F6B4644
120#define CONFIG_SYS_DDR_TIMING_2 0x002888D0
121#define CONFIG_SYS_DDR_SDRAM_CFG 0x47000000
122#define CONFIG_SYS_DDR_SDRAM_CFG_2 0x04401040
123#define CONFIG_SYS_DDR_SDRAM_MODE 0x40401521
124#define CONFIG_SYS_DDR_SDRAM_MODE_2 0x8000C000
125#define CONFIG_SYS_DDR_SDRAM_INTERVAL 0x03E00000
126#define CONFIG_SYS_DDR_DATA_INIT 0xdeadbeef
127#define CONFIG_SYS_DDR_SDRAM_CLK_CNTL 0x01000000
128#define CONFIG_SYS_DDR_TIMING_4 0x00220001
129#define CONFIG_SYS_DDR_TIMING_5 0x03402400
130#define CONFIG_SYS_DDR_ZQ_CNTL 0x89080600
131#define CONFIG_SYS_DDR_WRLVL_CNTL 0x0655A604
132#define CONFIG_SYS_DDR_CDR_1 0x80040000
133#define CONFIG_SYS_DDR_CDR_2 0x00000000
134#define CONFIG_SYS_DDR_OCD_CTRL 0x00000000
135#define CONFIG_SYS_DDR_OCD_STATUS 0x00000000
136#define CONFIG_SYS_DDR_CONTROL 0xc7000000 /* Type = DDR3 */
137#define CONFIG_SYS_DDR_CONTROL2 0x24400000
138
139#define CONFIG_SYS_DDR_ERR_INT_EN 0x0000000d
140#define CONFIG_SYS_DDR_ERR_DIS 0x00000000
141#define CONFIG_SYS_DDR_SBE 0x00010000
142
143#undef CONFIG_CLOCKS_IN_MHZ
144
145/*
146 * Local Bus Definitions
147 */
148
149#define CONFIG_SYS_FLASH_BASE 0xfe000000 /* start of FLASH 32M */
150#define CONFIG_SYS_FLASH_BASE_PHYS CONFIG_SYS_FLASH_BASE
151
152#define CONFIG_SYS_BCSR_BASE 0xf8000000
153#define CONFIG_SYS_BCSR_BASE_PHYS CONFIG_SYS_BCSR_BASE
154
155/*Chip select 0 - Flash*/
156#define CONFIG_SYS_BR0_PRELIM 0xfe000801
157#define CONFIG_SYS_OR0_PRELIM 0xfe000ff7
158
Haiying Wang399b53c2009-05-20 12:30:32 -0400159/*Chip select 1 - BCSR*/
Haiying Wang765547d2009-03-27 17:02:45 -0400160#define CONFIG_SYS_BR1_PRELIM 0xf8000801
161#define CONFIG_SYS_OR1_PRELIM 0xffffe9f7
162
Haiying Wang399b53c2009-05-20 12:30:32 -0400163/*Chip select 4 - PIB*/
164#define CONFIG_SYS_BR4_PRELIM 0xf8008801
165#define CONFIG_SYS_OR4_PRELIM 0xffffe9f7
166
167/*Chip select 5 - PIB*/
168#define CONFIG_SYS_BR5_PRELIM 0xf8010801
169#define CONFIG_SYS_OR5_PRELIM 0xffffe9f7
170
Haiying Wang765547d2009-03-27 17:02:45 -0400171#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* number of banks */
172#define CONFIG_SYS_MAX_FLASH_SECT 512 /* sectors per device */
173#undef CONFIG_SYS_FLASH_CHECKSUM
174#define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */
175#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */
176
177#define CONFIG_SYS_MONITOR_BASE TEXT_BASE /* start of monitor */
178
179#define CONFIG_FLASH_CFI_DRIVER
180#define CONFIG_SYS_FLASH_CFI
181#define CONFIG_SYS_FLASH_EMPTY_INFO
182
183
184/*
185 * SDRAM on the LocalBus
186 */
187#define CONFIG_SYS_LBC_SDRAM_BASE 0xf0000000 /* Localbus SDRAM */
188#define CONFIG_SYS_LBC_SDRAM_SIZE 64 /* LBC SDRAM is 64MB */
189
190#define CONFIG_SYS_LBC_LCRR 0x00000004 /* LB clock ratio reg */
191#define CONFIG_SYS_LBC_LBCR 0x00040000 /* LB config reg */
192#define CONFIG_SYS_LBC_LSRT 0x20000000 /* LB sdram refresh timer */
193#define CONFIG_SYS_LBC_MRTPR 0x00000000 /* LB refresh timer prescal*/
194
195#define CONFIG_SYS_INIT_RAM_LOCK 1
196#define CONFIG_SYS_INIT_RAM_ADDR 0xe4010000 /* Initial RAM address */
197#define CONFIG_SYS_INIT_RAM_END 0x4000 /* End of used area in RAM */
198
199#define CONFIG_SYS_GBL_DATA_SIZE 128 /* num bytes initial data */
200#define CONFIG_SYS_GBL_DATA_OFFSET \
201 (CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE)
202#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
203
204#define CONFIG_SYS_MONITOR_LEN (256 * 1024) /* Reserve 256 kB for Mon */
Haiying Wangfb279492009-06-04 16:12:39 -0400205#define CONFIG_SYS_MALLOC_LEN (512 * 1024) /* Reserved for malloc */
Haiying Wang765547d2009-03-27 17:02:45 -0400206
207/* Serial Port */
208#define CONFIG_CONS_INDEX 1
209#undef CONFIG_SERIAL_SOFTWARE_FIFO
210#define CONFIG_SYS_NS16550
211#define CONFIG_SYS_NS16550_SERIAL
212#define CONFIG_SYS_NS16550_REG_SIZE 1
213#define CONFIG_SYS_NS16550_CLK get_bus_freq(0)
214
215#define CONFIG_SYS_BAUDRATE_TABLE \
216 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400,115200}
217
218#define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x4500)
219#define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x4600)
220
221/* Use the HUSH parser*/
222#define CONFIG_SYS_HUSH_PARSER
223#ifdef CONFIG_SYS_HUSH_PARSER
224#define CONFIG_SYS_PROMPT_HUSH_PS2 "> "
225#endif
226
227/* pass open firmware flat tree */
228#define CONFIG_OF_LIBFDT 1
229#define CONFIG_OF_BOARD_SETUP 1
230#define CONFIG_OF_STDOUT_VIA_ALIAS 1
231
232#define CONFIG_SYS_64BIT_VSPRINTF 1
233#define CONFIG_SYS_64BIT_STRTOUL 1
234
235/*
236 * I2C
237 */
238#define CONFIG_FSL_I2C /* Use FSL common I2C driver */
239#define CONFIG_HARD_I2C /* I2C with hardware support*/
240#undef CONFIG_SOFT_I2C /* I2C bit-banged */
241#define CONFIG_I2C_MULTI_BUS
Haiying Wang765547d2009-03-27 17:02:45 -0400242#define CONFIG_SYS_I2C_SPEED 400000 /* I2C speed and slave address */
243#define CONFIG_SYS_I2C_SLAVE 0x7F
244#define CONFIG_SYS_I2C_NOPROBES {{0,0x69}} /* Don't probe these addrs */
245#define CONFIG_SYS_I2C_OFFSET 0x3000
246#define CONFIG_SYS_I2C2_OFFSET 0x3100
247
248/*
249 * I2C2 EEPROM
250 */
251#define CONFIG_ID_EEPROM
252#ifdef CONFIG_ID_EEPROM
253#define CONFIG_SYS_I2C_EEPROM_NXID
254#endif
255#define CONFIG_SYS_I2C_EEPROM_ADDR 0x52
256#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1
257#define CONFIG_SYS_EEPROM_BUS_NUM 1
258
259#define PLPPAR1_I2C_BIT_MASK 0x0000000F
260#define PLPPAR1_I2C2_VAL 0x00000000
261#define PLPDIR1_I2C_BIT_MASK 0x0000000F
262#define PLPDIR1_I2C2_VAL 0x0000000F
263
264/*
265 * General PCI
266 * Memory Addresses are mapped 1-1. I/O is mapped from 0
267 */
268#define CONFIG_SYS_PCIE1_MEM_VIRT 0xa0000000
269#define CONFIG_SYS_PCIE1_MEM_BUS 0xa0000000
270#define CONFIG_SYS_PCIE1_MEM_PHYS 0xa0000000
271#define CONFIG_SYS_PCIE1_MEM_SIZE 0x20000000 /* 512M */
272#define CONFIG_SYS_PCIE1_IO_VIRT 0xe2800000
273#define CONFIG_SYS_PCIE1_IO_BUS 0x00000000
274#define CONFIG_SYS_PCIE1_IO_PHYS 0xe2800000
275#define CONFIG_SYS_PCIE1_IO_SIZE 0x00800000 /* 8M */
276
277#define CONFIG_SYS_SRIO_MEM_VIRT 0xc0000000
278#define CONFIG_SYS_SRIO_MEM_BUS 0xc0000000
279#define CONFIG_SYS_SRIO_MEM_PHYS 0xc0000000
280
281#ifdef CONFIG_QE
282/*
283 * QE UEC ethernet configuration
284 */
Haiying Wangf82107f2009-05-20 12:30:37 -0400285#define CONFIG_SYS_UCC_RGMII_MODE /* Set UCC work at RGMII by default */
286#undef CONFIG_SYS_UCC_RMII_MODE /* Set UCC work at RMII mode */
Haiying Wang765547d2009-03-27 17:02:45 -0400287
288#define CONFIG_MIIM_ADDRESS (CONFIG_SYS_CCSRBAR + 0x82120)
289#define CONFIG_UEC_ETH
290#define CONFIG_ETHPRIME "FSL UEC0"
291#define CONFIG_PHY_MODE_NEED_CHANGE
292
293#define CONFIG_UEC_ETH1 /* GETH1 */
294#define CONFIG_HAS_ETH0
295
296#ifdef CONFIG_UEC_ETH1
297#define CONFIG_SYS_UEC1_UCC_NUM 0 /* UCC1 */
298#define CONFIG_SYS_UEC1_RX_CLK QE_CLK_NONE
Haiying Wangf82107f2009-05-20 12:30:37 -0400299#if defined(CONFIG_SYS_UCC_RGMII_MODE)
Haiying Wang765547d2009-03-27 17:02:45 -0400300#define CONFIG_SYS_UEC1_TX_CLK QE_CLK12
301#define CONFIG_SYS_UEC1_ETH_TYPE GIGA_ETH
302#define CONFIG_SYS_UEC1_PHY_ADDR 7
303#define CONFIG_SYS_UEC1_INTERFACE_MODE ENET_1000_RGMII_ID
Haiying Wangf82107f2009-05-20 12:30:37 -0400304#elif defined(CONFIG_SYS_UCC_RMII_MODE)
305#define CONFIG_SYS_UEC1_TX_CLK QE_CLK16 /* CLK16 for RMII */
306#define CONFIG_SYS_UEC1_ETH_TYPE FAST_ETH
307#define CONFIG_SYS_UEC1_PHY_ADDR 8 /* 0x8 for RMII */
308#define CONFIG_SYS_UEC1_INTERFACE_MODE ENET_100_RMII
309#endif /* CONFIG_SYS_UCC_RGMII_MODE */
310#endif /* CONFIG_UEC_ETH1 */
Haiying Wang765547d2009-03-27 17:02:45 -0400311
312#define CONFIG_UEC_ETH2 /* GETH2 */
313#define CONFIG_HAS_ETH1
314
315#ifdef CONFIG_UEC_ETH2
316#define CONFIG_SYS_UEC2_UCC_NUM 1 /* UCC2 */
317#define CONFIG_SYS_UEC2_RX_CLK QE_CLK_NONE
Haiying Wangf82107f2009-05-20 12:30:37 -0400318#if defined(CONFIG_SYS_UCC_RGMII_MODE)
Haiying Wang765547d2009-03-27 17:02:45 -0400319#define CONFIG_SYS_UEC2_TX_CLK QE_CLK17
320#define CONFIG_SYS_UEC2_ETH_TYPE GIGA_ETH
321#define CONFIG_SYS_UEC2_PHY_ADDR 1
322#define CONFIG_SYS_UEC2_INTERFACE_MODE ENET_1000_RGMII_ID
Haiying Wangf82107f2009-05-20 12:30:37 -0400323#elif defined(CONFIG_SYS_UCC_RMII_MODE)
324#define CONFIG_SYS_UEC2_TX_CLK QE_CLK16 /* CLK 16 for RMII */
325#define CONFIG_SYS_UEC2_ETH_TYPE FAST_ETH
326#define CONFIG_SYS_UEC2_PHY_ADDR 0x9 /* 0x9 for RMII */
327#define CONFIG_SYS_UEC2_INTERFACE_MODE ENET_100_RMII
328#endif /* CONFIG_SYS_UCC_RGMII_MODE */
329#endif /* CONFIG_UEC_ETH2 */
Haiying Wang765547d2009-03-27 17:02:45 -0400330
Haiying Wang750098d2009-05-20 12:30:36 -0400331#define CONFIG_UEC_ETH3 /* GETH3 */
332#define CONFIG_HAS_ETH2
333
334#ifdef CONFIG_UEC_ETH3
335#define CONFIG_SYS_UEC3_UCC_NUM 2 /* UCC3 */
336#define CONFIG_SYS_UEC3_RX_CLK QE_CLK_NONE
Haiying Wangf82107f2009-05-20 12:30:37 -0400337#if defined(CONFIG_SYS_UCC_RGMII_MODE)
Haiying Wang750098d2009-05-20 12:30:36 -0400338#define CONFIG_SYS_UEC3_TX_CLK QE_CLK12
339#define CONFIG_SYS_UEC3_ETH_TYPE GIGA_ETH
340#define CONFIG_SYS_UEC3_PHY_ADDR 2
341#define CONFIG_SYS_UEC3_INTERFACE_MODE ENET_1000_RGMII_ID
Haiying Wangf82107f2009-05-20 12:30:37 -0400342#elif defined(CONFIG_SYS_UCC_RMII_MODE)
343#define CONFIG_SYS_UEC3_TX_CLK QE_CLK16 /* CLK_16 for RMII */
344#define CONFIG_SYS_UEC3_ETH_TYPE FAST_ETH
345#define CONFIG_SYS_UEC3_PHY_ADDR 0xA /* 0xA for RMII */
346#define CONFIG_SYS_UEC3_INTERFACE_MODE ENET_100_RMII
347#endif /* CONFIG_SYS_UCC_RGMII_MODE */
348#endif /* CONFIG_UEC_ETH3 */
Haiying Wang750098d2009-05-20 12:30:36 -0400349
350#define CONFIG_UEC_ETH4 /* GETH4 */
351#define CONFIG_HAS_ETH3
352
353#ifdef CONFIG_UEC_ETH4
354#define CONFIG_SYS_UEC4_UCC_NUM 3 /* UCC4 */
355#define CONFIG_SYS_UEC4_RX_CLK QE_CLK_NONE
Haiying Wangf82107f2009-05-20 12:30:37 -0400356#if defined(CONFIG_SYS_UCC_RGMII_MODE)
Haiying Wang750098d2009-05-20 12:30:36 -0400357#define CONFIG_SYS_UEC4_TX_CLK QE_CLK17
358#define CONFIG_SYS_UEC4_ETH_TYPE GIGA_ETH
359#define CONFIG_SYS_UEC4_PHY_ADDR 3
360#define CONFIG_SYS_UEC4_INTERFACE_MODE ENET_1000_RGMII_ID
Haiying Wangf82107f2009-05-20 12:30:37 -0400361#elif defined(CONFIG_SYS_UCC_RMII_MODE)
362#define CONFIG_SYS_UEC4_TX_CLK QE_CLK16 /* CLK16 for RMII */
363#define CONFIG_SYS_UEC4_ETH_TYPE FAST_ETH
364#define CONFIG_SYS_UEC4_PHY_ADDR 0xB /* 0xB for RMII */
365#define CONFIG_SYS_UEC4_INTERFACE_MODE ENET_100_RMII
366#endif /* CONFIG_SYS_UCC_RGMII_MODE */
367#endif /* CONFIG_UEC_ETH4 */
Haiying Wang3bd8e532009-05-20 12:30:41 -0400368
369#undef CONFIG_UEC_ETH6 /* GETH6 */
370#define CONFIG_HAS_ETH5
371
372#ifdef CONFIG_UEC_ETH6
373#define CONFIG_SYS_UEC6_UCC_NUM 5 /* UCC6 */
374#define CONFIG_SYS_UEC6_RX_CLK QE_CLK_NONE
375#define CONFIG_SYS_UEC6_TX_CLK QE_CLK_NONE
376#define CONFIG_SYS_UEC6_ETH_TYPE GIGA_ETH
377#define CONFIG_SYS_UEC6_PHY_ADDR 4
378#define CONFIG_SYS_UEC6_INTERFACE_MODE ENET_1000_SGMII
379#endif /* CONFIG_UEC_ETH6 */
380
381#undef CONFIG_UEC_ETH8 /* GETH8 */
382#define CONFIG_HAS_ETH7
383
384#ifdef CONFIG_UEC_ETH8
385#define CONFIG_SYS_UEC8_UCC_NUM 7 /* UCC8 */
386#define CONFIG_SYS_UEC8_RX_CLK QE_CLK_NONE
387#define CONFIG_SYS_UEC8_TX_CLK QE_CLK_NONE
388#define CONFIG_SYS_UEC8_ETH_TYPE GIGA_ETH
389#define CONFIG_SYS_UEC8_PHY_ADDR 6
390#define CONFIG_SYS_UEC8_INTERFACE_MODE ENET_1000_SGMII
391#endif /* CONFIG_UEC_ETH8 */
392
Haiying Wang765547d2009-03-27 17:02:45 -0400393#endif /* CONFIG_QE */
394
395#if defined(CONFIG_PCI)
396
397#define CONFIG_NET_MULTI
398#define CONFIG_PCI_PNP /* do pci plug-and-play */
399
400#undef CONFIG_EEPRO100
401#undef CONFIG_TULIP
402
403#undef CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */
404
405#endif /* CONFIG_PCI */
406
407#ifndef CONFIG_NET_MULTI
408#define CONFIG_NET_MULTI 1
409#endif
410
411/*
412 * Environment
413 */
414#define CONFIG_ENV_IS_IN_FLASH 1
Haiying Wangfb279492009-06-04 16:12:39 -0400415#define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SECT_SIZE)
Haiying Wang765547d2009-03-27 17:02:45 -0400416#define CONFIG_ENV_SECT_SIZE 0x20000 /* 256K(one sector) for env */
Haiying Wangfb279492009-06-04 16:12:39 -0400417#define CONFIG_ENV_SIZE CONFIG_ENV_SECT_SIZE
Haiying Wang765547d2009-03-27 17:02:45 -0400418
419#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
420#define CONFIG_SYS_LOADS_BAUD_CHANGE 1 /* allow baudrate change */
421
422/* QE microcode/firmware address */
423#define CONFIG_SYS_QE_FW_ADDR 0xfff00000
424
425/*
426 * BOOTP options
427 */
428#define CONFIG_BOOTP_BOOTFILESIZE
429#define CONFIG_BOOTP_BOOTPATH
430#define CONFIG_BOOTP_GATEWAY
431#define CONFIG_BOOTP_HOSTNAME
432
433
434/*
435 * Command line configuration.
436 */
437#include <config_cmd_default.h>
438
439#define CONFIG_CMD_PING
440#define CONFIG_CMD_I2C
441#define CONFIG_CMD_MII
442#define CONFIG_CMD_ELF
443#define CONFIG_CMD_IRQ
444#define CONFIG_CMD_SETEXPR
445
446#if defined(CONFIG_PCI)
447 #define CONFIG_CMD_PCI
448#endif
449
450
451#undef CONFIG_WATCHDOG /* watchdog disabled */
452
453/*
454 * Miscellaneous configurable options
455 */
456#define CONFIG_SYS_LONGHELP /* undef to save memory */
457#define CONFIG_CMDLINE_EDITING /* Command-line editing */
458#define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */
459#define CONFIG_SYS_PROMPT "=> " /* Monitor Command Prompt */
460#if defined(CONFIG_CMD_KGDB)
461#define CONFIG_SYS_CBSIZE 2048 /* Console I/O Buffer Size */
462#else
463#define CONFIG_SYS_CBSIZE 512 /* Console I/O Buffer Size */
464#endif
465#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16)
466 /* Print Buffer Size */
467#define CONFIG_SYS_MAXARGS 32 /* max number of command args */
468#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE
469 /* Boot Argument Buffer Size */
470#define CONFIG_SYS_HZ 1000 /* decrementer freq: 1ms ticks */
471
472/*
473 * For booting Linux, the board info and command line data
Kumar Gala89188a62009-07-15 08:54:50 -0500474 * have to be in the first 16 MB of memory, since this is
Haiying Wang765547d2009-03-27 17:02:45 -0400475 * the maximum mapped by the Linux kernel during initialization.
476 */
Kumar Gala89188a62009-07-15 08:54:50 -0500477#define CONFIG_SYS_BOOTMAPSZ (16 << 20)
Haiying Wang765547d2009-03-27 17:02:45 -0400478 /* Initial Memory map for Linux*/
479
480/*
481 * Internal Definitions
482 *
483 * Boot Flags
484 */
485#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */
486#define BOOTFLAG_WARM 0x02 /* Software reboot */
487
488#if defined(CONFIG_CMD_KGDB)
489#define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */
490#define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */
491#endif
492
493/*
494 * Environment Configuration
495 */
496#define CONFIG_HOSTNAME mpc8569mds
497#define CONFIG_ROOTPATH /nfsroot
498#define CONFIG_BOOTFILE your.uImage
499
500#define CONFIG_SERVERIP 192.168.1.1
501#define CONFIG_GATEWAYIP 192.168.1.1
502#define CONFIG_NETMASK 255.255.255.0
503
504#define CONFIG_LOADADDR 200000 /*default location for tftp and bootm*/
505
506#define CONFIG_BOOTDELAY 10 /* -1 disables auto-boot */
507#undef CONFIG_BOOTARGS /* the boot command will set bootargs*/
508
509#define CONFIG_BAUDRATE 115200
510
511#define CONFIG_EXTRA_ENV_SETTINGS \
512 "netdev=eth0\0" \
513 "consoledev=ttyS0\0" \
514 "ramdiskaddr=600000\0" \
515 "ramdiskfile=your.ramdisk.u-boot\0" \
516 "fdtaddr=400000\0" \
517 "fdtfile=your.fdt.dtb\0" \
518 "nfsargs=setenv bootargs root=/dev/nfs rw " \
519 "nfsroot=$serverip:$rootpath " \
520 "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \
521 "console=$consoledev,$baudrate $othbootargs\0" \
522 "ramargs=setenv bootargs root=/dev/ram rw " \
523 "console=$consoledev,$baudrate $othbootargs\0" \
524
525#define CONFIG_NFSBOOTCOMMAND \
526 "run nfsargs;" \
527 "tftp $loadaddr $bootfile;" \
528 "tftp $fdtaddr $fdtfile;" \
529 "bootm $loadaddr - $fdtaddr"
530
531#define CONFIG_RAMBOOTCOMMAND \
532 "run ramargs;" \
533 "tftp $ramdiskaddr $ramdiskfile;" \
534 "tftp $loadaddr $bootfile;" \
535 "bootm $loadaddr $ramdiskaddr"
536
537#define CONFIG_BOOTCOMMAND CONFIG_NFSBOOTCOMMAND
538
539#endif /* __CONFIG_H */