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Michal Simek38b343d2012-09-13 20:23:35 +00001/*
2 * Copyright (C) 2012 Michal Simek <monstr@monstr.eu>
3 * Copyright (C) 2012 Xilinx, Inc. All rights reserved.
4 *
Wolfgang Denk3765b3e2013-10-07 13:07:26 +02005 * SPDX-License-Identifier: GPL-2.0+
Michal Simek38b343d2012-09-13 20:23:35 +00006 */
7#include <common.h>
Michal Simek00ed3452013-02-04 12:42:25 +01008#include <asm/io.h>
Soren Brinkmann6c3e61d2013-11-21 13:38:54 -08009#include <asm/arch/clk.h>
Michal Simek59c651f2013-02-04 12:38:59 +010010#include <asm/arch/sys_proto.h>
Michal Simek00ed3452013-02-04 12:42:25 +010011#include <asm/arch/hardware.h>
Michal Simek38b343d2012-09-13 20:23:35 +000012
Siva Durga Prasad Paladugu96a28592013-11-29 19:01:25 +053013#define ZYNQ_SILICON_VER_MASK 0xF0000000
14#define ZYNQ_SILICON_VER_SHIFT 28
15
Michal Simek262f08d2013-08-22 14:52:02 +020016int arch_cpu_init(void)
17{
Michal Simek00ed3452013-02-04 12:42:25 +010018 zynq_slcr_unlock();
Michal Simekd7e269c2014-01-14 14:21:52 +010019#ifndef CONFIG_SPL_BUILD
Michal Simek00ed3452013-02-04 12:42:25 +010020 /* Device config APB, unlock the PCAP */
21 writel(0x757BDF0D, &devcfg_base->unlock);
22 writel(0xFFFFFFFF, &devcfg_base->rom_shadow);
23
Michal Simekc1824ea2013-08-28 08:26:41 +020024#if (CONFIG_SYS_SDRAM_BASE == 0)
25 /* remap DDR to zero, FILTERSTART */
26 writel(0, &scu_base->filter_start);
27
Michal Simek00ed3452013-02-04 12:42:25 +010028 /* OCM_CFG, Mask out the ROM, map ram into upper addresses */
29 writel(0x1F, &slcr_base->ocm_cfg);
30 /* FPGA_RST_CTRL, clear resets on AXI fabric ports */
31 writel(0x0, &slcr_base->fpga_rst_ctrl);
Michal Simek00ed3452013-02-04 12:42:25 +010032 /* Set urgent bits with register */
33 writel(0x0, &slcr_base->ddr_urgent_sel);
34 /* Urgent write, ports S2/S3 */
35 writel(0xC, &slcr_base->ddr_urgent);
Michal Simekc1824ea2013-08-28 08:26:41 +020036#endif
Michal Simekd7e269c2014-01-14 14:21:52 +010037#endif
Soren Brinkmann6c3e61d2013-11-21 13:38:54 -080038 zynq_clk_early_init();
Michal Simek00ed3452013-02-04 12:42:25 +010039 zynq_slcr_lock();
Michal Simek262f08d2013-08-22 14:52:02 +020040
41 return 0;
Michal Simek00ed3452013-02-04 12:42:25 +010042}
Michal Simek38b343d2012-09-13 20:23:35 +000043
Siva Durga Prasad Paladugu96a28592013-11-29 19:01:25 +053044unsigned int zynq_get_silicon_version(void)
45{
Masahiro Yamada63a75782016-09-06 22:17:38 +090046 return (readl(&devcfg_base->mctrl) & ZYNQ_SILICON_VER_MASK)
47 >> ZYNQ_SILICON_VER_SHIFT;
Siva Durga Prasad Paladugu96a28592013-11-29 19:01:25 +053048}
49
Michal Simek38b343d2012-09-13 20:23:35 +000050void reset_cpu(ulong addr)
51{
Michal Simek59c651f2013-02-04 12:38:59 +010052 zynq_slcr_cpu_reset();
Michal Simek38b343d2012-09-13 20:23:35 +000053 while (1)
54 ;
55}
Michal Simek673ba272014-01-03 09:32:35 +010056
57#ifndef CONFIG_SYS_DCACHE_OFF
58void enable_caches(void)
59{
60 /* Enable D-cache. I-cache is already enabled in start.S */
61 dcache_enable();
62}
63#endif