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wdenk16b013e2005-05-19 22:46:33 +00001/*
2 * (C) Copyright 2004
3 * Greg Ungerer <greg.ungerer@opengear.com>.
4 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
5 *
Wolfgang Denk3765b3e2013-10-07 13:07:26 +02006 * SPDX-License-Identifier: GPL-2.0+
wdenk16b013e2005-05-19 22:46:33 +00007 */
8#ifndef __CONFIG_H
9#define __CONFIG_H
10
11/*
12 * High Level Configuration Options
13 * (easy to change)
14 */
15#define CONFIG_KS8695 1 /* it is a KS8695 CPU */
16#define CONFIG_CM4008 1 /* it is an OpenGear CM4008 boad */
17
wdenk16b013e2005-05-19 22:46:33 +000018#define CONFIG_CMDLINE_TAG 1 /* enable passing of ATAGs */
19#define CONFIG_SETUP_MEMORY_TAGS 1
20#define CONFIG_INITRD_TAG 1
21
wdenk2eab48f2005-05-23 10:49:50 +000022#define CONFIG_DRIVER_KS8695ETH /* use KS8695 ethernet driver */
23
wdenk16b013e2005-05-19 22:46:33 +000024/*
25 * Size of malloc() pool
26 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020027#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + 128*1024)
wdenk16b013e2005-05-19 22:46:33 +000028
29/*
30 * Hardware drivers
31 */
32
33/*
34 * select serial console configuration
35 */
Jean-Christophe PLAGNIOL-VILLARD93f6d722008-09-10 22:48:00 +020036#define CONFIG_ENV_IS_NOWHERE
Jean-Christophe PLAGNIOL-VILLARD176a6002009-03-29 23:01:42 +020037#define CONFIG_KS8695_SERIAL
wdenk16b013e2005-05-19 22:46:33 +000038#define CONFIG_SERIAL1
39#define CONFIG_CONS_INDEX 1
40#define CONFIG_BAUDRATE 115200
Jon Loeliger37e4f242007-07-04 22:31:56 -050041
42/*
Jon Loeliger80ff4f92007-07-10 09:29:01 -050043 * BOOTP options
44 */
45#define CONFIG_BOOTP_BOOTFILESIZE
46#define CONFIG_BOOTP_BOOTPATH
47#define CONFIG_BOOTP_GATEWAY
48#define CONFIG_BOOTP_HOSTNAME
49
50
51/*
Jon Loeliger37e4f242007-07-04 22:31:56 -050052 * Command line configuration.
53 */
54#include <config_cmd_default.h>
55
Mike Frysingerbdab39d2009-01-28 19:08:14 -050056#undef CONFIG_CMD_SAVEENV
Jon Loeliger37e4f242007-07-04 22:31:56 -050057
wdenk16b013e2005-05-19 22:46:33 +000058
59#define CONFIG_BOOTDELAY 0
60#define CONFIG_BOOTARGS "mem=16M console=ttyAM0,115200"
61#define CONFIG_BOOTCOMMAND "gofsk 0x02200000"
62
63/*
64 * Miscellaneous configurable options
65 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020066#define CONFIG_SYS_LONGHELP /* undef to save memory */
67#define CONFIG_SYS_PROMPT "boot > " /* Monitor Command Prompt */
68#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
69#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
70#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
71#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */
wdenk16b013e2005-05-19 22:46:33 +000072
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020073#define CONFIG_SYS_MEMTEST_START 0x00800000 /* memtest works on */
74#define CONFIG_SYS_MEMTEST_END 0x01000000 /* 16 MB in DRAM */
wdenk16b013e2005-05-19 22:46:33 +000075
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020076#define CONFIG_SYS_LOAD_ADDR 0x00008000 /* default load address */
wdenk16b013e2005-05-19 22:46:33 +000077
wdenk16b013e2005-05-19 22:46:33 +000078/*-----------------------------------------------------------------------
wdenk16b013e2005-05-19 22:46:33 +000079 * Physical Memory Map
80 */
81#define CONFIG_NR_DRAM_BANKS 1 /* we have 1 bank of DRAM */
82#define PHYS_SDRAM_1 0x00000000 /* SDRAM Bank #1 */
83#define PHYS_SDRAM_1_SIZE 0x01000000 /* 16 MB */
Greg Ungerera34ebbd2011-09-09 22:23:18 +100084#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1
85
86#define CONFIG_SYS_INIT_SP_ADDR 0x00020000 /* lowest 128k of RAM */
wdenk16b013e2005-05-19 22:46:33 +000087
88#define PHYS_FLASH_1 0x02000000 /* Flash Bank #1 */
89#define PHYS_FLASH_SECT_SIZE 0x00020000 /* 128 KB sectors (x1) */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020090#define CONFIG_SYS_FLASH_BASE PHYS_FLASH_1
wdenk16b013e2005-05-19 22:46:33 +000091
92/*-----------------------------------------------------------------------
93 * FLASH and environment organization
94 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020095#define CONFIG_SYS_MAX_FLASH_BANKS 2 /* max number of flash banks */
96#define CONFIG_SYS_MAX_FLASH_SECT (128) /* max number of sectors on one chip */
wdenk16b013e2005-05-19 22:46:33 +000097
98/* timeout values are in ticks */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020099#define CONFIG_SYS_FLASH_ERASE_TOUT (20*CONFIG_SYS_HZ) /* Timeout for Flash Erase */
100#define CONFIG_SYS_FLASH_WRITE_TOUT (20*CONFIG_SYS_HZ) /* Timeout for Flash Write */
wdenk16b013e2005-05-19 22:46:33 +0000101
Jean-Christophe PLAGNIOL-VILLARD0e8d1582008-09-10 22:48:06 +0200102#define CONFIG_ENV_SIZE 0x20000 /* Total Size of Environment */
wdenk16b013e2005-05-19 22:46:33 +0000103
104#endif /* __CONFIG_H */