blob: f9dfcd04115a1267ac39080fddc2feea255ad5b2 [file] [log] [blame]
Tom Warrenf29f0862013-01-23 14:01:01 -07001/*
Tom Warren7aaa5a62015-03-04 16:36:00 -07002 * Copyright (c) 2010-2015, NVIDIA CORPORATION. All rights reserved.
Tom Warrenf29f0862013-01-23 14:01:01 -07003 *
4 * This program is free software; you can redistribute it and/or modify it
5 * under the terms and conditions of the GNU General Public License,
6 * version 2, as published by the Free Software Foundation.
7 *
8 * This program is distributed in the hope it will be useful, but WITHOUT
9 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
10 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
11 * more details.
12 *
13 * You should have received a copy of the GNU General Public License
14 * along with this program. If not, see <http://www.gnu.org/licenses/>.
15 */
16
17/* Tegra SoC common clock control functions */
18
19#include <common.h>
Simon Glass746dc762015-06-05 14:39:36 -060020#include <errno.h>
Tom Warrenf29f0862013-01-23 14:01:01 -070021#include <asm/io.h>
22#include <asm/arch/clock.h>
23#include <asm/arch/tegra.h>
Stephen Warren73c38932015-01-19 16:25:52 -070024#include <asm/arch-tegra/ap.h>
Tom Warrenf29f0862013-01-23 14:01:01 -070025#include <asm/arch-tegra/clk_rst.h>
Simon Glass746dc762015-06-05 14:39:36 -060026#include <asm/arch-tegra/pmc.h>
Tom Warrenf29f0862013-01-23 14:01:01 -070027#include <asm/arch-tegra/timer.h>
28#include <div64.h>
29#include <fdtdec.h>
30
31/*
32 * This is our record of the current clock rate of each clock. We don't
33 * fill all of these in since we are only really interested in clocks which
34 * we use as parents.
35 */
36static unsigned pll_rate[CLOCK_ID_COUNT];
37
38/*
39 * The oscillator frequency is fixed to one of four set values. Based on this
40 * the other clocks are set up appropriately.
41 */
42static unsigned osc_freq[CLOCK_OSC_FREQ_COUNT] = {
43 13000000,
44 19200000,
45 12000000,
46 26000000,
Tom Warren3e8650c2015-06-22 13:03:44 -070047 38400000,
48 48000000,
Tom Warrenf29f0862013-01-23 14:01:01 -070049};
50
51/* return 1 if a peripheral ID is in range */
52#define clock_type_id_isvalid(id) ((id) >= 0 && \
53 (id) < CLOCK_TYPE_COUNT)
54
55char pllp_valid = 1; /* PLLP is set up correctly */
56
57/* return 1 if a periphc_internal_id is in range */
58#define periphc_internal_id_isvalid(id) ((id) >= 0 && \
59 (id) < PERIPHC_COUNT)
60
61/* number of clock outputs of a PLL */
62static const u8 pll_num_clkouts[] = {
63 1, /* PLLC */
64 1, /* PLLM */
65 4, /* PLLP */
66 1, /* PLLA */
67 0, /* PLLU */
68 0, /* PLLD */
69};
70
71int clock_get_osc_bypass(void)
72{
73 struct clk_rst_ctlr *clkrst =
74 (struct clk_rst_ctlr *)NV_PA_CLK_RST_BASE;
75 u32 reg;
76
77 reg = readl(&clkrst->crc_osc_ctrl);
78 return (reg & OSC_XOBP_MASK) >> OSC_XOBP_SHIFT;
79}
80
81/* Returns a pointer to the registers of the given pll */
82static struct clk_pll *get_pll(enum clock_id clkid)
83{
84 struct clk_rst_ctlr *clkrst =
85 (struct clk_rst_ctlr *)NV_PA_CLK_RST_BASE;
86
87 assert(clock_id_is_pll(clkid));
Simon Glass801b05c2015-04-14 21:03:32 -060088 if (clkid >= (enum clock_id)TEGRA_CLK_PLLS) {
Simon Glasscd3c6762015-06-05 14:39:37 -060089 debug("%s: Invalid PLL %d\n", __func__, clkid);
Simon Glass801b05c2015-04-14 21:03:32 -060090 return NULL;
91 }
Tom Warrenf29f0862013-01-23 14:01:01 -070092 return &clkrst->crc_pll[clkid];
93}
94
Simon Glass801b05c2015-04-14 21:03:32 -060095__weak struct clk_pll_simple *clock_get_simple_pll(enum clock_id clkid)
96{
97 return NULL;
98}
99
Tom Warrenf29f0862013-01-23 14:01:01 -0700100int clock_ll_read_pll(enum clock_id clkid, u32 *divm, u32 *divn,
101 u32 *divp, u32 *cpcon, u32 *lfcon)
102{
103 struct clk_pll *pll = get_pll(clkid);
Tom Warren722e0002015-06-25 09:50:44 -0700104 struct clk_pll_info *pllinfo = &tegra_pll_info_table[clkid];
Tom Warrenf29f0862013-01-23 14:01:01 -0700105 u32 data;
106
107 assert(clkid != CLOCK_ID_USB);
108
109 /* Safety check, adds to code size but is small */
110 if (!clock_id_is_pll(clkid) || clkid == CLOCK_ID_USB)
111 return -1;
112 data = readl(&pll->pll_base);
Tom Warren722e0002015-06-25 09:50:44 -0700113 *divm = (data >> pllinfo->m_shift) & pllinfo->m_mask;
114 *divn = (data >> pllinfo->n_shift) & pllinfo->n_mask;
115 *divp = (data >> pllinfo->p_shift) & pllinfo->p_mask;
Tom Warrenf29f0862013-01-23 14:01:01 -0700116 data = readl(&pll->pll_misc);
Tom Warren722e0002015-06-25 09:50:44 -0700117 /* NOTE: On T210, cpcon/lfcon no longer exist, moved to KCP/KVCO */
118 *cpcon = (data >> pllinfo->kcp_shift) & pllinfo->kcp_mask;
119 *lfcon = (data >> pllinfo->kvco_shift) & pllinfo->kvco_mask;
120
Tom Warrenf29f0862013-01-23 14:01:01 -0700121 return 0;
122}
123
124unsigned long clock_start_pll(enum clock_id clkid, u32 divm, u32 divn,
125 u32 divp, u32 cpcon, u32 lfcon)
126{
Simon Glasscd3c6762015-06-05 14:39:37 -0600127 struct clk_pll *pll = NULL;
Tom Warren722e0002015-06-25 09:50:44 -0700128 struct clk_pll_info *pllinfo = &tegra_pll_info_table[clkid];
Simon Glass5a30cee2015-08-10 07:14:36 -0600129 struct clk_pll_simple *simple_pll = NULL;
Simon Glass801b05c2015-04-14 21:03:32 -0600130 u32 misc_data, data;
Tom Warrenf29f0862013-01-23 14:01:01 -0700131
Simon Glass5a30cee2015-08-10 07:14:36 -0600132 if (clkid < (enum clock_id)TEGRA_CLK_PLLS) {
Simon Glasscd3c6762015-06-05 14:39:37 -0600133 pll = get_pll(clkid);
Simon Glass5a30cee2015-08-10 07:14:36 -0600134 } else {
135 simple_pll = clock_get_simple_pll(clkid);
136 if (!simple_pll) {
137 debug("%s: Uknown simple PLL %d\n", __func__, clkid);
138 return 0;
139 }
140 }
Simon Glasscd3c6762015-06-05 14:39:37 -0600141
Tom Warrenf29f0862013-01-23 14:01:01 -0700142 /*
Tom Warren722e0002015-06-25 09:50:44 -0700143 * pllinfo has the m/n/p and kcp/kvco mask and shift
144 * values for all of the PLLs used in U-Boot, with any
145 * SoC differences accounted for.
Simon Glass5a30cee2015-08-10 07:14:36 -0600146 *
147 * Preserve EN_LOCKDET, etc.
Tom Warrenf29f0862013-01-23 14:01:01 -0700148 */
Simon Glass5a30cee2015-08-10 07:14:36 -0600149 if (pll)
150 misc_data = readl(&pll->pll_misc);
151 else
152 misc_data = readl(&simple_pll->pll_misc);
153 misc_data &= ~(pllinfo->kcp_mask << pllinfo->kcp_shift);
154 misc_data |= cpcon << pllinfo->kcp_shift;
155 misc_data &= ~(pllinfo->kvco_mask << pllinfo->kvco_shift);
156 misc_data |= lfcon << pllinfo->kvco_shift;
Tom Warrenf29f0862013-01-23 14:01:01 -0700157
Tom Warren722e0002015-06-25 09:50:44 -0700158 data = (divm << pllinfo->m_shift) | (divn << pllinfo->n_shift);
159 data |= divp << pllinfo->p_shift;
160 data |= (1 << PLL_ENABLE_SHIFT); /* BYPASS s/b 0 already */
Tom Warrenf29f0862013-01-23 14:01:01 -0700161
Simon Glass801b05c2015-04-14 21:03:32 -0600162 if (pll) {
163 writel(misc_data, &pll->pll_misc);
164 writel(data, &pll->pll_base);
165 } else {
Simon Glass5a30cee2015-08-10 07:14:36 -0600166 writel(misc_data, &simple_pll->pll_misc);
167 writel(data, &simple_pll->pll_base);
Simon Glass801b05c2015-04-14 21:03:32 -0600168 }
Tom Warrenf29f0862013-01-23 14:01:01 -0700169
170 /* calculate the stable time */
171 return timer_get_us() + CLOCK_PLL_STABLE_DELAY_US;
172}
173
174void clock_ll_set_source_divisor(enum periph_id periph_id, unsigned source,
175 unsigned divisor)
176{
177 u32 *reg = get_periph_source_reg(periph_id);
178 u32 value;
179
180 value = readl(reg);
181
Stephen Warren9cb0c6d2014-01-24 10:16:19 -0700182 value &= ~OUT_CLK_SOURCE_31_30_MASK;
183 value |= source << OUT_CLK_SOURCE_31_30_SHIFT;
Tom Warrenf29f0862013-01-23 14:01:01 -0700184
185 value &= ~OUT_CLK_DIVISOR_MASK;
186 value |= divisor << OUT_CLK_DIVISOR_SHIFT;
187
188 writel(value, reg);
189}
190
Simon Glass7bb61992015-04-14 21:03:33 -0600191int clock_ll_set_source_bits(enum periph_id periph_id, int mux_bits,
192 unsigned source)
Tom Warrenf29f0862013-01-23 14:01:01 -0700193{
194 u32 *reg = get_periph_source_reg(periph_id);
195
Simon Glass7bb61992015-04-14 21:03:33 -0600196 switch (mux_bits) {
197 case MASK_BITS_31_30:
198 clrsetbits_le32(reg, OUT_CLK_SOURCE_31_30_MASK,
199 source << OUT_CLK_SOURCE_31_30_SHIFT);
200 break;
201
202 case MASK_BITS_31_29:
203 clrsetbits_le32(reg, OUT_CLK_SOURCE_31_29_MASK,
204 source << OUT_CLK_SOURCE_31_29_SHIFT);
205 break;
206
207 case MASK_BITS_31_28:
208 clrsetbits_le32(reg, OUT_CLK_SOURCE_31_28_MASK,
209 source << OUT_CLK_SOURCE_31_28_SHIFT);
210 break;
211
212 default:
213 return -1;
214 }
215
216 return 0;
217}
218
219void clock_ll_set_source(enum periph_id periph_id, unsigned source)
220{
221 clock_ll_set_source_bits(periph_id, MASK_BITS_31_30, source);
Tom Warrenf29f0862013-01-23 14:01:01 -0700222}
223
224/**
225 * Given the parent's rate and the required rate for the children, this works
226 * out the peripheral clock divider to use, in 7.1 binary format.
227 *
228 * @param divider_bits number of divider bits (8 or 16)
229 * @param parent_rate clock rate of parent clock in Hz
230 * @param rate required clock rate for this clock
231 * @return divider which should be used
232 */
233static int clk_get_divider(unsigned divider_bits, unsigned long parent_rate,
234 unsigned long rate)
235{
236 u64 divider = parent_rate * 2;
237 unsigned max_divider = 1 << divider_bits;
238
239 divider += rate - 1;
240 do_div(divider, rate);
241
242 if ((s64)divider - 2 < 0)
243 return 0;
244
245 if ((s64)divider - 2 >= max_divider)
246 return -1;
247
248 return divider - 2;
249}
250
251int clock_set_pllout(enum clock_id clkid, enum pll_out_id pllout, unsigned rate)
252{
253 struct clk_pll *pll = get_pll(clkid);
254 int data = 0, div = 0, offset = 0;
255
256 if (!clock_id_is_pll(clkid))
257 return -1;
258
259 if (pllout + 1 > pll_num_clkouts[clkid])
260 return -1;
261
262 div = clk_get_divider(8, pll_rate[clkid], rate);
263
264 if (div < 0)
265 return -1;
266
267 /* out2 and out4 are in the high part of the register */
268 if (pllout == PLL_OUT2 || pllout == PLL_OUT4)
269 offset = 16;
270
271 data = (div << PLL_OUT_RATIO_SHIFT) |
272 PLL_OUT_OVRRIDE | PLL_OUT_CLKEN | PLL_OUT_RSTN;
273 clrsetbits_le32(&pll->pll_out[pllout >> 1],
274 PLL_OUT_RATIO_MASK << offset, data << offset);
275
276 return 0;
277}
278
279/**
280 * Given the parent's rate and the divider in 7.1 format, this works out the
281 * resulting peripheral clock rate.
282 *
283 * @param parent_rate clock rate of parent clock in Hz
284 * @param divider which should be used in 7.1 format
285 * @return effective clock rate of peripheral
286 */
287static unsigned long get_rate_from_divider(unsigned long parent_rate,
288 int divider)
289{
290 u64 rate;
291
292 rate = (u64)parent_rate * 2;
293 do_div(rate, divider + 2);
294 return rate;
295}
296
297unsigned long clock_get_periph_rate(enum periph_id periph_id,
298 enum clock_id parent)
299{
300 u32 *reg = get_periph_source_reg(periph_id);
301
302 return get_rate_from_divider(pll_rate[parent],
303 (readl(reg) & OUT_CLK_DIVISOR_MASK) >> OUT_CLK_DIVISOR_SHIFT);
304}
305
306/**
307 * Find the best available 7.1 format divisor given a parent clock rate and
308 * required child clock rate. This function assumes that a second-stage
309 * divisor is available which can divide by powers of 2 from 1 to 256.
310 *
311 * @param divider_bits number of divider bits (8 or 16)
312 * @param parent_rate clock rate of parent clock in Hz
313 * @param rate required clock rate for this clock
314 * @param extra_div value for the second-stage divisor (not set if this
315 * function returns -1.
316 * @return divider which should be used, or -1 if nothing is valid
317 *
318 */
319static int find_best_divider(unsigned divider_bits, unsigned long parent_rate,
320 unsigned long rate, int *extra_div)
321{
322 int shift;
323 int best_divider = -1;
324 int best_error = rate;
325
326 /* try dividers from 1 to 256 and find closest match */
327 for (shift = 0; shift <= 8 && best_error > 0; shift++) {
328 unsigned divided_parent = parent_rate >> shift;
329 int divider = clk_get_divider(divider_bits, divided_parent,
330 rate);
331 unsigned effective_rate = get_rate_from_divider(divided_parent,
332 divider);
333 int error = rate - effective_rate;
334
335 /* Given a valid divider, look for the lowest error */
336 if (divider != -1 && error < best_error) {
337 best_error = error;
338 *extra_div = 1 << shift;
339 best_divider = divider;
340 }
341 }
342
343 /* return what we found - *extra_div will already be set */
344 return best_divider;
345}
346
347/**
348 * Adjust peripheral PLL to use the given divider and source.
349 *
350 * @param periph_id peripheral to adjust
351 * @param source Source number (0-3 or 0-7)
352 * @param mux_bits Number of mux bits (2 or 4)
353 * @param divider Required divider in 7.1 or 15.1 format
354 * @return 0 if ok, -1 on error (requesting a parent clock which is not valid
355 * for this peripheral)
356 */
357static int adjust_periph_pll(enum periph_id periph_id, int source,
358 int mux_bits, unsigned divider)
359{
360 u32 *reg = get_periph_source_reg(periph_id);
361
362 clrsetbits_le32(reg, OUT_CLK_DIVISOR_MASK,
363 divider << OUT_CLK_DIVISOR_SHIFT);
364 udelay(1);
365
366 /* work out the source clock and set it */
367 if (source < 0)
368 return -1;
Tom Warrenc82014d2014-01-24 10:16:22 -0700369
Simon Glass7bb61992015-04-14 21:03:33 -0600370 clock_ll_set_source_bits(periph_id, mux_bits, source);
Tom Warrenc82014d2014-01-24 10:16:22 -0700371
Tom Warrenf29f0862013-01-23 14:01:01 -0700372 udelay(2);
373 return 0;
374}
375
376unsigned clock_adjust_periph_pll_div(enum periph_id periph_id,
377 enum clock_id parent, unsigned rate, int *extra_div)
378{
379 unsigned effective_rate;
380 int mux_bits, divider_bits, source;
381 int divider;
Allen Martina51f7de2013-05-10 16:56:55 +0000382 int xdiv = 0;
Tom Warrenf29f0862013-01-23 14:01:01 -0700383
384 /* work out the source clock and set it */
385 source = get_periph_clock_source(periph_id, parent, &mux_bits,
386 &divider_bits);
387
Allen Martina51f7de2013-05-10 16:56:55 +0000388 divider = find_best_divider(divider_bits, pll_rate[parent],
389 rate, &xdiv);
Tom Warrenf29f0862013-01-23 14:01:01 -0700390 if (extra_div)
Allen Martina51f7de2013-05-10 16:56:55 +0000391 *extra_div = xdiv;
392
Tom Warrenf29f0862013-01-23 14:01:01 -0700393 assert(divider >= 0);
394 if (adjust_periph_pll(periph_id, source, mux_bits, divider))
395 return -1U;
396 debug("periph %d, rate=%d, reg=%p = %x\n", periph_id, rate,
397 get_periph_source_reg(periph_id),
398 readl(get_periph_source_reg(periph_id)));
399
400 /* Check what we ended up with. This shouldn't matter though */
401 effective_rate = clock_get_periph_rate(periph_id, parent);
402 if (extra_div)
403 effective_rate /= *extra_div;
404 if (rate != effective_rate)
405 debug("Requested clock rate %u not honored (got %u)\n",
406 rate, effective_rate);
407 return effective_rate;
408}
409
410unsigned clock_start_periph_pll(enum periph_id periph_id,
411 enum clock_id parent, unsigned rate)
412{
413 unsigned effective_rate;
414
415 reset_set_enable(periph_id, 1);
416 clock_enable(periph_id);
417
418 effective_rate = clock_adjust_periph_pll_div(periph_id, parent, rate,
419 NULL);
420
421 reset_set_enable(periph_id, 0);
422 return effective_rate;
423}
424
425void clock_enable(enum periph_id clkid)
426{
427 clock_set_enable(clkid, 1);
428}
429
430void clock_disable(enum periph_id clkid)
431{
432 clock_set_enable(clkid, 0);
433}
434
435void reset_periph(enum periph_id periph_id, int us_delay)
436{
437 /* Put peripheral into reset */
438 reset_set_enable(periph_id, 1);
439 udelay(us_delay);
440
441 /* Remove reset */
442 reset_set_enable(periph_id, 0);
443
444 udelay(us_delay);
445}
446
447void reset_cmplx_set_enable(int cpu, int which, int reset)
448{
449 struct clk_rst_ctlr *clkrst =
450 (struct clk_rst_ctlr *)NV_PA_CLK_RST_BASE;
451 u32 mask;
452
453 /* Form the mask, which depends on the cpu chosen (2 or 4) */
454 assert(cpu >= 0 && cpu < MAX_NUM_CPU);
455 mask = which << cpu;
456
457 /* either enable or disable those reset for that CPU */
458 if (reset)
459 writel(mask, &clkrst->crc_cpu_cmplx_set);
460 else
461 writel(mask, &clkrst->crc_cpu_cmplx_clr);
462}
463
464unsigned clock_get_rate(enum clock_id clkid)
465{
466 struct clk_pll *pll;
Tom Warren722e0002015-06-25 09:50:44 -0700467 u32 base, divm;
468 u64 parent_rate, rate;
469 struct clk_pll_info *pllinfo = &tegra_pll_info_table[clkid];
Tom Warrenf29f0862013-01-23 14:01:01 -0700470
471 parent_rate = osc_freq[clock_get_osc_freq()];
472 if (clkid == CLOCK_ID_OSC)
473 return parent_rate;
474
475 pll = get_pll(clkid);
Simon Glass801b05c2015-04-14 21:03:32 -0600476 if (!pll)
477 return 0;
Tom Warrenf29f0862013-01-23 14:01:01 -0700478 base = readl(&pll->pll_base);
479
Tom Warren722e0002015-06-25 09:50:44 -0700480 rate = parent_rate * ((base >> pllinfo->n_shift) & pllinfo->n_mask);
481 divm = (base >> pllinfo->m_shift) & pllinfo->m_mask;
482 /*
483 * PLLU uses p_mask/p_shift for VCO on all but T210,
484 * T210 uses normal DIVP. Handled in pllinfo table.
485 */
486 divm <<= (base >> pllinfo->p_shift) & pllinfo->p_mask;
Tom Warrenf29f0862013-01-23 14:01:01 -0700487 do_div(rate, divm);
488 return rate;
489}
490
491/**
492 * Set the output frequency you want for each PLL clock.
493 * PLL output frequencies are programmed by setting their N, M and P values.
494 * The governing equations are:
495 * VCO = (Fi / m) * n, Fo = VCO / (2^p)
496 * where Fo is the output frequency from the PLL.
497 * Example: Set the output frequency to 216Mhz(Fo) with 12Mhz OSC(Fi)
498 * 216Mhz = ((12Mhz / m) * n) / (2^p) so n=432,m=12,p=1
499 * Please see Tegra TRM section 5.3 to get the detail for PLL Programming
500 *
501 * @param n PLL feedback divider(DIVN)
502 * @param m PLL input divider(DIVN)
503 * @param p post divider(DIVP)
504 * @param cpcon base PLL charge pump(CPCON)
505 * @return 0 if ok, -1 on error (the requested PLL is incorrect and cannot
506 * be overriden), 1 if PLL is already correct
507 */
508int clock_set_rate(enum clock_id clkid, u32 n, u32 m, u32 p, u32 cpcon)
509{
Tom Warren722e0002015-06-25 09:50:44 -0700510 u32 base_reg, misc_reg;
Tom Warrenf29f0862013-01-23 14:01:01 -0700511 struct clk_pll *pll;
Tom Warren722e0002015-06-25 09:50:44 -0700512 struct clk_pll_info *pllinfo = &tegra_pll_info_table[clkid];
Tom Warrenf29f0862013-01-23 14:01:01 -0700513
514 pll = get_pll(clkid);
515
516 base_reg = readl(&pll->pll_base);
517
518 /* Set BYPASS, m, n and p to PLL_BASE */
Tom Warren722e0002015-06-25 09:50:44 -0700519 base_reg &= ~(pllinfo->m_mask << pllinfo->m_shift);
520 base_reg |= m << pllinfo->m_shift;
Tom Warrenf29f0862013-01-23 14:01:01 -0700521
Tom Warren722e0002015-06-25 09:50:44 -0700522 base_reg &= ~(pllinfo->n_mask << pllinfo->n_shift);
523 base_reg |= n << pllinfo->n_shift;
Tom Warrenf29f0862013-01-23 14:01:01 -0700524
Tom Warren722e0002015-06-25 09:50:44 -0700525 base_reg &= ~(pllinfo->p_mask << pllinfo->p_shift);
526 base_reg |= p << pllinfo->p_shift;
Tom Warrenf29f0862013-01-23 14:01:01 -0700527
528 if (clkid == CLOCK_ID_PERIPH) {
529 /*
530 * If the PLL is already set up, check that it is correct
531 * and record this info for clock_verify() to check.
532 */
533 if (base_reg & PLL_BASE_OVRRIDE_MASK) {
534 base_reg |= PLL_ENABLE_MASK;
535 if (base_reg != readl(&pll->pll_base))
536 pllp_valid = 0;
537 return pllp_valid ? 1 : -1;
538 }
539 base_reg |= PLL_BASE_OVRRIDE_MASK;
540 }
541
542 base_reg |= PLL_BYPASS_MASK;
543 writel(base_reg, &pll->pll_base);
544
Tom Warren722e0002015-06-25 09:50:44 -0700545 /* Set cpcon (KCP) to PLL_MISC */
Tom Warrenf29f0862013-01-23 14:01:01 -0700546 misc_reg = readl(&pll->pll_misc);
Tom Warren722e0002015-06-25 09:50:44 -0700547 misc_reg &= ~(pllinfo->kcp_mask << pllinfo->kcp_shift);
548 misc_reg |= cpcon << pllinfo->kcp_shift;
Tom Warrenf29f0862013-01-23 14:01:01 -0700549 writel(misc_reg, &pll->pll_misc);
550
551 /* Enable PLL */
552 base_reg |= PLL_ENABLE_MASK;
553 writel(base_reg, &pll->pll_base);
554
555 /* Disable BYPASS */
556 base_reg &= ~PLL_BYPASS_MASK;
557 writel(base_reg, &pll->pll_base);
558
559 return 0;
560}
561
562void clock_ll_start_uart(enum periph_id periph_id)
563{
564 /* Assert UART reset and enable clock */
565 reset_set_enable(periph_id, 1);
566 clock_enable(periph_id);
567 clock_ll_set_source(periph_id, 0); /* UARTx_CLK_SRC = 00, PLLP_OUT0 */
568
569 /* wait for 2us */
570 udelay(2);
571
572 /* De-assert reset to UART */
573 reset_set_enable(periph_id, 0);
574}
575
Masahiro Yamada0f925822015-08-12 07:31:55 +0900576#if CONFIG_IS_ENABLED(OF_CONTROL)
Tom Warrenf29f0862013-01-23 14:01:01 -0700577int clock_decode_periph_id(const void *blob, int node)
578{
579 enum periph_id id;
580 u32 cell[2];
581 int err;
582
583 err = fdtdec_get_int_array(blob, node, "clocks", cell,
584 ARRAY_SIZE(cell));
585 if (err)
586 return -1;
587 id = clk_id_to_periph_id(cell[1]);
588 assert(clock_periph_id_isvalid(id));
589 return id;
590}
Masahiro Yamada0f925822015-08-12 07:31:55 +0900591#endif /* CONFIG_IS_ENABLED(OF_CONTROL) */
Tom Warrenf29f0862013-01-23 14:01:01 -0700592
593int clock_verify(void)
594{
595 struct clk_pll *pll = get_pll(CLOCK_ID_PERIPH);
596 u32 reg = readl(&pll->pll_base);
597
598 if (!pllp_valid) {
599 printf("Warning: PLLP %x is not correct\n", reg);
600 return -1;
601 }
602 debug("PLLP %x is correct\n", reg);
603 return 0;
604}
605
606void clock_init(void)
607{
Tom Warren3e8650c2015-06-22 13:03:44 -0700608 pll_rate[CLOCK_ID_CGENERAL] = clock_get_rate(CLOCK_ID_CGENERAL);
Tom Warrenf29f0862013-01-23 14:01:01 -0700609 pll_rate[CLOCK_ID_MEMORY] = clock_get_rate(CLOCK_ID_MEMORY);
610 pll_rate[CLOCK_ID_PERIPH] = clock_get_rate(CLOCK_ID_PERIPH);
Tom Warren3e8650c2015-06-22 13:03:44 -0700611 pll_rate[CLOCK_ID_USB] = clock_get_rate(CLOCK_ID_USB);
Simon Glass96e82a22015-04-14 21:03:34 -0600612 pll_rate[CLOCK_ID_DISPLAY] = clock_get_rate(CLOCK_ID_DISPLAY);
Tom Warrenf29f0862013-01-23 14:01:01 -0700613 pll_rate[CLOCK_ID_XCPU] = clock_get_rate(CLOCK_ID_XCPU);
Tom Warren3e8650c2015-06-22 13:03:44 -0700614 pll_rate[CLOCK_ID_SFROM32KHZ] = 32768;
615 pll_rate[CLOCK_ID_OSC] = clock_get_rate(CLOCK_ID_OSC);
616
Tom Warrenf29f0862013-01-23 14:01:01 -0700617 debug("Osc = %d\n", pll_rate[CLOCK_ID_OSC]);
Tom Warren3e8650c2015-06-22 13:03:44 -0700618 debug("PLLC = %d\n", pll_rate[CLOCK_ID_CGENERAL]);
Tom Warrenf29f0862013-01-23 14:01:01 -0700619 debug("PLLM = %d\n", pll_rate[CLOCK_ID_MEMORY]);
620 debug("PLLP = %d\n", pll_rate[CLOCK_ID_PERIPH]);
Tom Warren3e8650c2015-06-22 13:03:44 -0700621 debug("PLLU = %d\n", pll_rate[CLOCK_ID_USB]);
Simon Glass96e82a22015-04-14 21:03:34 -0600622 debug("PLLD = %d\n", pll_rate[CLOCK_ID_DISPLAY]);
Tom Warrenf29f0862013-01-23 14:01:01 -0700623 debug("PLLX = %d\n", pll_rate[CLOCK_ID_XCPU]);
Tom Warrenf29f0862013-01-23 14:01:01 -0700624}
Jimmy Zhangb9dd6212014-01-24 10:37:36 -0700625
626static void set_avp_clock_source(u32 src)
627{
628 struct clk_rst_ctlr *clkrst =
629 (struct clk_rst_ctlr *)NV_PA_CLK_RST_BASE;
630 u32 val;
631
632 val = (src << SCLK_SWAKEUP_FIQ_SOURCE_SHIFT) |
633 (src << SCLK_SWAKEUP_IRQ_SOURCE_SHIFT) |
634 (src << SCLK_SWAKEUP_RUN_SOURCE_SHIFT) |
635 (src << SCLK_SWAKEUP_IDLE_SOURCE_SHIFT) |
636 (SCLK_SYS_STATE_RUN << SCLK_SYS_STATE_SHIFT);
637 writel(val, &clkrst->crc_sclk_brst_pol);
638 udelay(3);
639}
640
641/*
642 * This function is useful on Tegra30, and any later SoCs that have compatible
643 * PLLP configuration registers.
Tom Warren7aaa5a62015-03-04 16:36:00 -0700644 * NOTE: Not used on Tegra210 - see tegra210_setup_pllp in T210 clock.c
Jimmy Zhangb9dd6212014-01-24 10:37:36 -0700645 */
646void tegra30_set_up_pllp(void)
647{
648 struct clk_rst_ctlr *clkrst = (struct clk_rst_ctlr *)NV_PA_CLK_RST_BASE;
649 u32 reg;
650
651 /*
652 * Based on the Tegra TRM, the system clock (which is the AVP clock) can
653 * run up to 275MHz. On power on, the default sytem clock source is set
654 * to PLLP_OUT0. This function sets PLLP's (hence PLLP_OUT0's) rate to
655 * 408MHz which is beyond system clock's upper limit.
656 *
657 * The fix is to set the system clock to CLK_M before initializing PLLP,
658 * and then switch back to PLLP_OUT4, which has an appropriate divider
659 * configured, after PLLP has been configured
660 */
661 set_avp_clock_source(SCLK_SOURCE_CLKM);
662
663 /*
664 * PLLP output frequency set to 408Mhz
665 * PLLC output frequency set to 228Mhz
666 */
667 switch (clock_get_osc_freq()) {
668 case CLOCK_OSC_FREQ_12_0: /* OSC is 12Mhz */
669 clock_set_rate(CLOCK_ID_PERIPH, 408, 12, 0, 8);
670 clock_set_rate(CLOCK_ID_CGENERAL, 456, 12, 1, 8);
671 break;
672
673 case CLOCK_OSC_FREQ_26_0: /* OSC is 26Mhz */
674 clock_set_rate(CLOCK_ID_PERIPH, 408, 26, 0, 8);
675 clock_set_rate(CLOCK_ID_CGENERAL, 600, 26, 0, 8);
676 break;
677
678 case CLOCK_OSC_FREQ_13_0: /* OSC is 13Mhz */
679 clock_set_rate(CLOCK_ID_PERIPH, 408, 13, 0, 8);
680 clock_set_rate(CLOCK_ID_CGENERAL, 600, 13, 0, 8);
681 break;
682 case CLOCK_OSC_FREQ_19_2:
683 default:
684 /*
685 * These are not supported. It is too early to print a
686 * message and the UART likely won't work anyway due to the
687 * oscillator being wrong.
688 */
689 break;
690 }
691
692 /* Set PLLP_OUT1, 2, 3 & 4 freqs to 9.6, 48, 102 & 204MHz */
693
694 /* OUT1, 2 */
695 /* Assert RSTN before enable */
696 reg = PLLP_OUT2_RSTN_EN | PLLP_OUT1_RSTN_EN;
697 writel(reg, &clkrst->crc_pll[CLOCK_ID_PERIPH].pll_out[0]);
698 /* Set divisor and reenable */
699 reg = (IN_408_OUT_48_DIVISOR << PLLP_OUT2_RATIO)
700 | PLLP_OUT2_OVR | PLLP_OUT2_CLKEN | PLLP_OUT2_RSTN_DIS
701 | (IN_408_OUT_9_6_DIVISOR << PLLP_OUT1_RATIO)
702 | PLLP_OUT1_OVR | PLLP_OUT1_CLKEN | PLLP_OUT1_RSTN_DIS;
703 writel(reg, &clkrst->crc_pll[CLOCK_ID_PERIPH].pll_out[0]);
704
705 /* OUT3, 4 */
706 /* Assert RSTN before enable */
707 reg = PLLP_OUT4_RSTN_EN | PLLP_OUT3_RSTN_EN;
708 writel(reg, &clkrst->crc_pll[CLOCK_ID_PERIPH].pll_out[1]);
709 /* Set divisor and reenable */
710 reg = (IN_408_OUT_204_DIVISOR << PLLP_OUT4_RATIO)
711 | PLLP_OUT4_OVR | PLLP_OUT4_CLKEN | PLLP_OUT4_RSTN_DIS
712 | (IN_408_OUT_102_DIVISOR << PLLP_OUT3_RATIO)
713 | PLLP_OUT3_OVR | PLLP_OUT3_CLKEN | PLLP_OUT3_RSTN_DIS;
714 writel(reg, &clkrst->crc_pll[CLOCK_ID_PERIPH].pll_out[1]);
715
716 set_avp_clock_source(SCLK_SOURCE_PLLP_OUT4);
717}
Simon Glass746dc762015-06-05 14:39:36 -0600718
719int clock_external_output(int clk_id)
720{
721 struct pmc_ctlr *pmc = (struct pmc_ctlr *)NV_PA_PMC_BASE;
722
723 if (clk_id >= 1 && clk_id <= 3) {
724 setbits_le32(&pmc->pmc_clk_out_cntrl,
725 1 << (2 + (clk_id - 1) * 8));
726 } else {
727 printf("%s: Unknown output clock id %d\n", __func__, clk_id);
728 return -EINVAL;
729 }
730
731 return 0;
732}